Storage device and storage method

Abstract

The invention provides a storage device and a storage method. The storage device includes a non-volatile memory device configured to provide a physical address space; and at least one processor configured to implement: a variable mapper configured to obtain a size of compressed data, the compressed data being obtained by compressing original data in a logical page of a logical address space; based on the size of the compressed data, determining the number of physical pages, used for storing the compressed data, of the physical address space; the physical page manager is configured to distribute physical pages corresponding to the number of the physical pages; and a write controller configured to write data to the physical page allocated by the physical page manager.

Description

Technical Field

[0001] The present disclosure relates to the field of data storage, and more specifically, to a storage device, a storage method, a computer-readable storage medium, and an electronic device. Background Art

[0002] Computer and network systems (such as data storage systems, server systems, cloud storage systems, personal computers and workstations) typically include data storage devices for storing and retrieving data. These data storage devices may include hard disk drives, solid-state storage drives, tape storage devices, optical storage drives, hybrid storage devices containing rotating and solid-state data storage elements, and other mass storage devices.

[0003] Computers and network systems continue to grow in number and power, but data storage devices have limited internal resources. Summary of the invention

[0004] According to one aspect of the present disclosure, a storage device is provided, comprising: a non-volatile memory device, configured to provide a physical address space; and at least one processor, configured to implement: a variable mapper, configured to: obtain the size of compressed data, wherein the compressed data is obtained by compressing original data in a logical page of a logical address space; based on the size of the compressed data, determine the number of physical pages of the physical address space for storing the compressed data; a physical page manager, configured to allocate physical pages corresponding to the number of physical pages; and a write controller, configured to write data to the physical pages allocated by the physical page manager.

[0005] Optionally, the non-volatile memory device comprises a solid-state storage device, wherein the physical page is allocated in a NAND block of the solid-state storage device.

[0006] Optionally, the allocated physical pages are continuous physical pages of the non-volatile memory device.

[0007] Optionally, the size of a logical page is different from the size of a physical page in the physical address space.

[0008] Optionally, the logical page size is M times the physical page size to the Nth power, where M is a positive integer greater than or equal to 1, and N is a positive integer greater than or equal to 0.

[0009] Optionally, the physical page manager is further configured to: provide multiple work groups, each of the multiple work groups having a preset number of NAND blocks, each of the work groups being used to perform allocation operations for different numbers of consecutive physical pages, and the multiple work groups being able to perform the allocation operations in parallel; select a target NAND block from a work group in the multiple work groups based on the number of physical pages; allocate the physical pages from the target NAND block based on the number of physical pages; and allocate a new NAND block to a NAND block in a work group in the multiple work groups based on the fact that all physical pages in the NAND block in the work group are used.

[0010] Optionally, the physical page manager is also configured to: generate a physical page number based on the allocated physical page, and the physical page number represents the location information of the physical page in the physical address space, wherein the at least one processor is also configured to implement a mapping relationship module, and is configured to: store a mapping relationship between the physical page number and the logical page number, and the logical page number represents the location of the logical page in the logical address space.

[0011] Optionally, the non-volatile memory device includes a solid-state storage device, which includes multiple NAND blocks, wherein the physical page manager is further configured to: identify the number of valid physical pages for each NAND block in the multiple NAND blocks, and the valid physical page contains valid data; for a NAND block in the multiple NAND blocks, based on the number of valid physical pages of the NAND block, identify whether the NAND block meets a recycling condition; and recycle the NAND block based on the NAND block meeting the recycling condition.

[0012] Optionally, the physical page manager is further configured to: based on the NAND block satisfying the recycling condition, copy the data in the valid physical page to the physical page in the NAND block that does not satisfy the recycling condition; based on the physical page to which the data is copied, generate a physical page number; wherein the variable mapper is further configured to: update the mapping relationship between the physical page number and the logical page number.

[0013] According to one aspect of the present disclosure, a storage method is provided, which may include: obtaining the size of compressed data, wherein the compressed data is obtained by compressing original data in a logical page of a logical address space; based on the size of the compressed data, determining the number of physical pages of a physical address space provided by a non-volatile memory device for storing the compressed data; allocating physical pages corresponding to the number of physical pages; and writing data to the allocated physical pages.

[0014] Optionally, the non-volatile memory device comprises a solid-state storage device, wherein the allocating step comprises: allocating the physical page in a NAND block of the solid-state storage device.

[0015] Optionally, the allocated physical pages are continuous physical pages of the non-volatile memory device.

[0016] Optionally, the size of a logical page is different from the size of a physical page in the physical address space.

[0017] Optionally, the logical page size is M times the physical page size to the Nth power, where M is a positive integer greater than or equal to 1, and N is a positive integer greater than or equal to 0.

[0018] Optionally, allocating physical pages corresponding to the number of physical pages includes: providing multiple work groups, each of the multiple work groups having a preset number of NAND blocks, each of the work groups being used to perform allocation operations for different numbers of consecutive physical pages, and the multiple work groups being able to perform the allocation operations in parallel; selecting a target NAND block from a work group in the multiple work groups based on the number of physical pages; allocating the physical pages from the target NAND block based on the number of physical pages; wherein the storage method further includes: allocating a new NAND block to a NAND block in a work group in the multiple work groups based on the fact that all physical pages in the NAND block are used.

[0019] Optionally, the storage method further includes: generating a physical page number based on the allocated physical page, wherein the physical page number indicates the position of the physical page in the physical address space; and storing a mapping relationship between the physical page number and the logical page number, wherein the logical page number indicates the position of the logical page in the logical address space.

[0020] Optionally, the non-volatile memory device includes a solid-state storage device, and the solid-state storage device includes multiple NAND blocks, wherein the storage method further includes: identifying the number of valid physical pages for each NAND block in the multiple NAND blocks, and the valid physical page contains valid data; for a NAND block in the multiple NAND blocks, based on the number of valid physical pages of the NAND block, identifying whether the NAND block meets a recycling condition; based on the NAND block meeting the recycling condition, recycling the NAND block.

[0021] Optionally, the storage method further includes: based on the NAND block satisfying the recycling condition, copying the data in the valid physical page to the physical page in the NAND block that does not satisfy the recycling condition; based on the physical page to which the data is copied, generating a physical page number; and updating the mapping relationship between the physical page number and the logical page number.

[0022] According to an aspect of the present disclosure, a non-transitory computer-readable storage medium storing a computer program is provided, wherein when the computer program is executed by a processor, the storage method described above is implemented.

[0023] According to one aspect of the present disclosure, an electronic device is provided, including: a processor; and a memory storing a computer program, wherein when the computer program is executed by the processor, the storage method described above is implemented.

[0024] At least one embodiment of the present disclosure more reasonably allocates physical pages required for storage to data in logical pages by considering the size of compressed data, thereby storing more data on the same physical storage medium. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0026] Figure 1 The data access process without data compression function is shown;

[0027] Figure 2 The data access process of integrating data compression function software in the host software is shown;

[0028] Figure 3 The data access process of integrating data compression function hardware in a solid-state storage device SSD is shown;

[0029] Figure 4 The data access process of integrating data compression function hardware in the SSD and adding an additional mapping management controller between the SSD and the host is shown;

[0030] Figure 5 A schematic diagram showing mapping of logical pages to physical pages according to an embodiment of the present disclosure is shown;

[0031] Figure 6 A schematic diagram of a logical address space according to an embodiment of the present disclosure is shown;

[0032] Figure 7 A schematic diagram showing an implementation process of mapping a logical page to an indefinite number of physical pages according to an embodiment of the present disclosure;

[0033] Figure 8 shows an overall architecture diagram of a storage device according to an embodiment of the present disclosure;

[0034] Fig. 9 A schematic diagram showing a workflow of a write controller according to an embodiment of the present disclosure is shown;

[0035] Fig.10 A schematic diagram showing the workflow of a variable mapper according to an embodiment of the present disclosure is shown;

[0036] Fig.11 A schematic diagram showing the workflow of a physical page manager according to an embodiment of the present disclosure;

[0037] Fig.12 A schematic diagram showing a NAND block state according to an embodiment of the present disclosure;

[0038] Fig.13 A schematic diagram of a physical page allocator according to an embodiment of the present disclosure is shown;

[0039] Fig.14 A schematic diagram of a physical page reclaimer according to an embodiment of the present disclosure is shown;

[0040] Fig.15 A schematic diagram showing a physical page data layout according to an embodiment of the present disclosure is shown;

[0041] Fig.16 A block diagram of a flash memory conversion device according to an embodiment of the present disclosure is shown;

[0042] Fig.17 A flowchart of a storage method according to an embodiment of the present disclosure is shown;

[0043] Fig.18 is a schematic diagram of a system 1000 to which a storage device is applied according to an exemplary embodiment of the present disclosure;

[0044] Fig.19 is a block diagram of a host storage system 10 according to an exemplary embodiment; and

[0045] Fig. 20 is a diagram of a data center 3000 to which a storage device is applied according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] The following will describe the exemplary embodiments in detail with reference to the accompanying drawings. Throughout the specification, the same elements are represented by the same reference numerals, and the repeated description thereof is omitted. It is understood that when an element or layer is referred to as "on" another element or layer, "connected to" or "coupled to" another element or layer, it can be directly on another element or layer, connected to or coupled to another element or layer, and there can also be intermediate elements or layers. In contrast, when an element is referred to as "directly located at", "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto and can also be implemented in various other forms. Each exemplary embodiment provided in the following description does not exclude association with one or more features of another example or another exemplary embodiment further provided herein or not provided herein but consistent with the present disclosure.

[0047] The following description with reference to the accompanying drawings is provided to facilitate a comprehensive understanding of the various embodiments of the present disclosure as defined by the claims and their equivalents. This description includes various specific details to facilitate understanding but should be considered as exemplary only. Therefore, one of ordinary skill in the art will recognize that various changes and modifications can be made to the various embodiments described herein without departing from the scope and spirit of the present disclosure. In addition, for the sake of clarity and conciseness, descriptions of well-known functions and structures may be omitted.

[0048] It should be understood that the singular forms "a", "an", and "the" may also include plural references unless the context clearly indicates otherwise. Thus, for example, reference to "a component surface" includes reference to one or more such surfaces. When we refer to an element as being "connected" or "coupled" to another element, the one element may be directly connected or coupled to the other element, or the one element and the other element may establish a connection relationship through an intermediate element. In addition, "connected" or "coupled" as used herein may include wireless connection or wireless coupling.

[0049] The term "include" or "may include" refers to the presence of the corresponding disclosed functions, operations or components that can be used in various embodiments of the present disclosure, rather than limiting the presence of one or more additional functions, operations or features. In addition, the term "include" or "have" may be interpreted as indicating certain characteristics, numbers, steps, operations, constituent elements, components or combinations thereof, but should not be interpreted as excluding the possibility of the presence of one or more other characteristics, numbers, steps, operations, constituent elements, components or combinations thereof.

[0050] The term "or" used in various embodiments of the present disclosure includes any of the listed terms and all combinations thereof. For example, "A or B" may include A, may include B, or may include both A and B. When describing multiple (two or more) items, if the relationship between the multiple items is not clearly defined, the multiple items may refer to one, multiple, or all of the multiple items. For example, the description of "parameter A includes A1, A2, A3" may be implemented as parameter A including A1 or A2 or A3, or may be implemented as parameter A including at least two of the three items A1, A2, and A3.

[0051] Embodiments of the present disclosure provide a flash memory conversion device and a storage method, wherein the flash memory conversion device can realize flexible dynamic granularity mapping between the logical space of the original data and the physical space used by the storage device, and use less storage device memory to manage the mapping table between the logical address and the physical address, so that more user data can be stored. According to an exemplary embodiment of the present disclosure, the flash memory conversion device can be implemented by a flash translation layer (FTL).

[0052] For ease of understanding, first refer to Figures 1 to 4 Describe the relevant data access scheme. Figure 1 The data access process without data compression function is shown.

[0053] Reference Figure 1 , the original data of the host application is directly stored in the SSD. This can obtain the fastest data storage performance and reading performance. However, when the data compression function is not performed, the SSD can only store the original data of the same size as the physical storage space of the SSD.

[0054] Figure 2 The data access process of integrating data compression function software in the host software is shown.

[0055] Reference Figure 2 In the case where the software data compression / decompression engine is integrated in the host / system software, the host application calls the data compression engine to compress the data before storing it in the SSD, and then stores the compressed data in the SSD. When reading data, the compressed data is first read from the SSD, and then the data decompression engine is called to decompress the compressed data, and the obtained original data is passed to the application software for use.

[0056] This solution can store more data that will be stored in the SSD, but because the solution needs to compress and decompress data, it requires additional host computing power and reduces data access performance.

[0057] Figure 3The data access process of integrating data compression function hardware in SSD is shown.

[0058] Reference Figure 3 , a data compression and decompression engine implemented in hardware is integrated inside the SSD. When the host writes data, the host directly provides the original data to the SSD. After receiving the original data, the SSD compresses the data through the hardware data compression engine. The compressed data is written to the NAND storage medium, and finally the actual storage address and compressed data size are returned to the host. When the host reads data, it first identifies the storage address and size of the corresponding compressed data on the SSD through the original data-compressed data mapping management module, and then sends a data read command indicating the storage address and size to the SSD. The SSD receives the data read command, reads the compressed data from the storage address carried by the read command, calls the data decompression engine to decompress the data, and returns the decompressed data to the host.

[0059] This solution reduces the increase in host computing power and ensures data access performance. However, because the size of the original data and the compressed data is different, the address and size of the original data are inconsistent with the address and size of the compressed data. Specifically, the address of the original data may refer to the logical address of the original data in the SSD seen by the host side. Since the amount of data becomes smaller after the original data is compressed, the required storage space is inconsistent. Because transparent compression is used, the decompressed data seen by the host side is much larger than the compressed data. For example, if the compression rate is 50%, and the logical storage space seen by the host side is 100, the actual logical space provided inside the SSD may be 50, which leads to inconsistency in the size and logical address of the original data and the compressed data. Therefore, it is necessary to perform mapping management between the two on the host side, which occupies a large amount of host memory and introduces consistency requirements for mapping management.

[0060] Figure 4 The data access process of integrating data compression function hardware in the SSD and adding an additional mapping management controller between the SSD and the host is shown.

[0061] Reference Figure 4 , except for Figure 3 In addition to integrating hardware data compression functions in the SSD, the original data-compressed data mapping management module implemented by software on the host side is delegated to a dedicated controller. This solution reduces the use of host memory, but the introduction of the controller still requires Figure 3 The solution shown in the figure uses the same memory size as the one shown in the figure, and requires the introduction of additional logic to perform persistent management of the original data-compressed data mapping data.

[0062] Based on the above description of the data access process of SSD, Figure 1The solution shown technically requires less storage of user data. Figure 2 The solution shown in the figure technically requires less host computing resources, improves poor read and write performance, and operates without modifying the host software. Figure 3 The solution shown technically requires reduced memory resources (host or additional hardware) and operates without modifying the host software. Figure 4 The solutions shown technically require reduced memory resources (host or additional hardware).

[0063] Therefore, in order to enable SSD to provide a truly fully transparent data compression function without introducing additional software and hardware resources (such as computing resources, memory resources, additional hardware resources, etc.), and to enable users to use the data compression function of SSD without adding any modifications (such as software development modifications and additional hardware on the host side) to achieve the purpose of storing more data on the same physical storage medium, the present disclosure proposes an SSD FTL implementation scheme, which simultaneously realizes original data-compressed data mapping and logical address-physical address mapping, so that users can achieve seamless switching between ordinary SSDs and SSDs with data compression characteristics; use less SSD memory to manage address mapping tables, reduce SSD complexity; and store more user data on the same size of NAND storage space. The SSD FTL scheme disclosed in the present disclosure can be called flexible FTL (F-FTL). The following is a detailed description of the workflow of F-FTL according to an example embodiment.

[0064] The example embodiments of the present disclosure implement flexible dynamic granularity mapping between the logical space of the original data and the physical space used by the SSD. The access granularity of the host-side application is the logical page (LP); the access granularity of the SSD-side NAND is the physical page (PP). According to the example embodiments of the present disclosure, the logical page size can be set to a power multiple of the physical page size. For example, the logical page size is S LP , the physical page size is S PP , the logical page size is the Nth power of 2 of the physical page size, that is:

[0065] S LP =2 N *S PP

[0066] like Figure 5As shown, when N is 2, that is, the logical page size is 4 times the physical page size, a logical page may be mapped to 1, 2, 3 or 4 consecutive physical pages by F-FTL according to the size of different compressed data. The above examples are only exemplary, and the present disclosure is not limited thereto.

[0067] There are two basic concepts in the use of SSD, namely logical page number (LPN) and physical page number (PPN).

[0068] The logical page number represents the address of the logical page. The host application sees the storage space of the SSD as a logical address space, which is evenly divided into fixed-size and continuous logical pages. The position index of a logical page in the logical address space is the logical page number, such as Figure 6 shown.

[0069] The physical page number represents the address of the physical page and can be used to find the location of a NAND physical page in the NAND storage array.

[0070] Figure 7 A schematic diagram is shown of an implementation process of mapping a logical page to an indefinite number of physical pages according to an embodiment of the present disclosure.

[0071] The F-FTL according to the present disclosure may include three functional modules:

[0072] Mapping table: manages the mapping of logical page numbers to physical page numbers. The mapping table works in the form of a table, where each logical page corresponds to a table member, and the logical page number is the position of the logical page in the table. Through this mode, the physical page number corresponding to the logical page number can be identified. For example, the PPN may include information indicating the number of channels, columns, blocks, pages, and physical pages.

[0073] Variable mapper: When writing data to the SSD, the variable mapper allocates the required number of physical pages according to the compressed data size and updates the mapping table. For example, the variable mapper can update information such as the physical page number and physical page size in the mapping table.

[0074] Physical Page Manager (Physical Page Manager): Allocates a corresponding number of consecutive physical pages in a specific NAND block according to the required number of physical pages, generates and returns the corresponding physical page number.

[0075] When an application wants to read data from a logical page, refer to Figure 7 , the reading process is as follows:

[0076] ① Identify the corresponding physical page number from the mapping table through the logical page number.

[0077] ② Identify the corresponding NAND chip through the channel information and column information in the physical page number.

[0078] ③ Identify the corresponding NAND block in the NAND chip through the block information in the physical page number.

[0079] ④ Read the data in the corresponding physical page from the corresponding NAND block using the page information and the number of physical pages in the physical page number.

[0080] Finally, the data is decompressed and passed back to the host application.

[0081] Figure 8 The architecture diagram of the storage device according to the embodiment of the present disclosure is shown. Here, the storage device can be any one of various types of storage devices. The following description is taken as an example that the storage device is an SSD including the above-mentioned F-FTL.

[0082] Reference Figure 8 The storage device may include: F-FTL, write controller, read controller, compression engine and decompression engine, flash memory (Flash) core, and NAND storage media.

[0083] F-FTL may include a flexible mapper, a physical page manager, and a mapping table. The flexible mapper may be used to update and maintain the mapping. The physical page manager may be used to allocate physical pages and generate physical page numbers; the physical page manager may provide an optimized garbage collection function (Garbage Collection, GC). The mapping table may be used to manage the mapping between logical page numbers and physical page numbers.

[0084] The write controller can control the execution of the write operation. After receiving the original data and logical address of the host application, the compression engine is first called to compress the original data of the application, and then the corresponding physical page number is obtained through the F-FTL according to the logical page number and the size of the compressed data. Finally, a NAND write request is constructed and submitted to the Flash core for NAND write operation. The write controller can identify whether the storage space saved by the compressed data is less than one physical page. If the storage space saved by the compressed data is less than one physical page, the original data can be directly stored in the NAND medium instead of storing the compressed data. If the storage space saved by the compressed data is not less than one physical page, the compressed data can be stored in the NAND medium.

[0085] The read controller controls the execution of the read operation. The physical page number corresponding to the logical page number can be obtained through the F-FTL first, and then the compressed data or the original data can be read from the NAND medium. If compressed data is read, the decompression engine is called to decompress the compressed data. Finally, the original data is returned to the host application.

[0086] The compression engine and the decompression engine can respectively control the compression and decompression of data. The compression engine and the decompression engine can be a data compression engine and a data decompression engine implemented by hardware logic (such as a circuit), providing high-performance data compression and decompression functions.

[0087] The Flash core is a computing core (CPU) in the SSD that is specifically used for NAND read and write operations. It can be used to perform NAND programming, reading, and erasing operations.

[0088] The NAND storage medium may be a NAND array for storing data.

[0089] Fig. 9 A schematic diagram showing the workflow of a write controller according to an embodiment of the present disclosure is shown.

[0090] The write controller can control the entire write process. All write operations are based on logical pages as the basic processing unit. For write operations issued by the host application, the data size must be an integer multiple of the logical page size; at the same time, the logical address to be written must also be an integer multiple of the logical page.

[0091] Reference Fig. 9 , the basic writing process of writing controller is as follows:

[0092] ①After receiving the original data and logical address sent by the host application, the write controller can identify whether the original data size or logical address is an integer multiple of the logical page size. If the original data size or logical address is not an integer multiple of the logical page size, the write operation is rejected and an error code is returned.

[0093] ② If the original data size or the logical address is an integer multiple of the logical page size, the original data is compressed by the compression engine to obtain the compressed data and the corresponding compressed data size.

[0094] ③ Calculate the logical page number from the logical address, and pass the obtained logical page number and compressed data size to F-FTL. F-FTL can apply for the required continuous physical pages, return the corresponding physical page number and update its internal mapping table.

[0095] ④ Determine whether to store compressed data or original data based on the size of the compressed data. For example, assume that the logical page size is N times the physical page size. If the compressed data needs to be stored in less than N physical pages, store the compressed data in the NAND media; otherwise, write the original data directly. For example, if the compressed data cannot save a complete physical page, do not compress the data and store the original data directly.

[0096] ⑤ Use the data to be written to the NAND medium, the logical page number, and the physical page number to construct a NAND write request, and send the newly constructed write request to the Flash core (CPU), which writes the data to the NAND medium. For example, after the Flash core receives the write request, it can record the logical page number corresponding to the physical page in each physical page to facilitate page recycling later. Fig.10 A schematic diagram showing the workflow of a variable mapper according to an embodiment of the present disclosure is shown.

[0097] The variable mapper of the present disclosure can provide two functions: allocate new physical pages for write operations and update the mapping table. If the logical page of the write operation has been allocated a physical page, the physical page manager can be notified to release the old physical page; query the physical page corresponding to the logical page for the read operation.

[0098] Reference Fig.10 , the basic workflow of the mutable mapper is as follows:

[0099] ①After receiving the physical page request from the write controller, obtain the corresponding logical page number LPN w and compressed data size.

[0100] ② Based on the compressed data size, allocate a new physical page through the physical page manager and obtain the corresponding physical page number PPN w .

[0101] ③ Update the mapping table and add the newly generated physical page number PPN w Write with logical page number LPN w The corresponding area.

[0102] ④ If the logical page number to be updated has a previously allocated physical page number, notify the physical page manager to release the previously allocated physical page (that is, the old PPN w ).

[0103] ⑤Return the new physical page number PPN w Write the controller.

[0104] ⑥After receiving the physical page number query request from the read controller, the received logical page number LPN R , identify the corresponding physical page number PPN from the mapping table RAnd return to the read controller.

[0105] Fig.11 A schematic diagram showing the workflow of a physical page manager according to an embodiment of the present disclosure is shown.

[0106] The physical page manager of the present disclosure can control the application for physical pages and the recycling of old physical pages. The physical page manager can be mainly composed of three modules:

[0107] Physical page allocator (PhysicalPageAllocator): Controls operations used to request a specified number of contiguous physical pages.

[0108] Physical Page Recycler (Physical Page Recycler): Controls the operation of recycling old physical pages that need to be released, and provides NAND blocks that can be garbage collected. For example, when a logical page is written with new data, the physical page recycler releases and recycles the physical page that originally corresponds to the logical page.

[0109] NAND block status module: controls the operation for recording the status of all NAND blocks. For example, the NAND block status module records information indicating whether there is valid data for each physical page in the NAND block and the number of physical pages with valid data. Here, valid data can be understood as the data stored in the physical page and the data in the logical page have a mapping relationship.

[0110] Reference Fig.11 , the workflow of the physical page manager is as follows:

[0111] ① Receive a physical page request from the variable mapper of F-FTL, which includes the compressed data size.

[0112] ② The physical page allocator identifies a NAND block with sufficient space (physical page), applies for a specified number of consecutive physical pages from it, and generates a physical page number PPN.

[0113] ③ Update the NAND block status and mark the physical page requested by operation ② as containing valid data.

[0114] ④ Return the newly generated physical page number PPN to the F-FTL variable mapper.

[0115] ⑤ Receive physical page release request from F-FTL mapper, which includes the PPN that needs to be released / reclaimed.

[0116] ⑥ The physical page recycler first updates the NAND block status and marks the physical page to be released as a dirty page, indicating that the physical page has no valid data and needs to be recycled. Then the physical page recycler detects whether the NAND block where the physical page to be released is located meets the conditions for garbage collection. For example, the NAND block can be used as the basic recycling unit.

[0117] Fig.12 A schematic diagram showing a NAND block state according to an embodiment of the present disclosure is shown.

[0118] The NAND block state can essentially be a large array, including members representing a state structure of a NAND block. The state structure corresponding to each NAND block can be identified through the channel, column, and block information in the physical page number.

[0119] Reference Fig.12 , each NAND block state can save two pieces of information:

[0120] Number of valid physical pages: Indicates how many physical pages in this NAND block contain valid data.

[0121] Physical page status bitmap: Each physical page can be represented by a bit. For example, if the bit is 1, it means that the physical page contains valid data; if the bit is 0, it means that the physical page is dirty, that is, it is waiting to be released.

[0122] Fig.13 A schematic diagram showing the workflow of a physical page allocator according to an embodiment of the present disclosure is shown.

[0123] The physical page allocator can control the operation for allocating a group of continuous physical pages. To ensure allocation efficiency, the physical page allocator can adopt the following operations.

[0124] The physical page allocator provides multiple workgroups, each of which can handle different numbers of consecutive physical page requests. This can avoid resource competition caused by multiple physical page request requests.

[0125] In each work group, one or a preset number of dedicated active NAND blocks are provided for each physical page application of different granularity (the number of physical pages to be applied for). For example, an active NAND block for 1 physical page allocation only serves a single physical page application; an active NAND block for 2 physical pages allocation is only used to allocate and serve 2 physical pages. The above examples are only exemplary, and the present disclosure is not limited thereto.

[0126] After the physical pages of a certain active NAND block in any working group are exhausted, the NAND block allocator can allocate a new NAND block for it. For example, the new NAND block can be a NAND block in which the physical pages are completely unused or part of the physical pages are used.

[0127] Fig.14 A schematic diagram showing the workflow of a physical page reclaimer according to an embodiment of the present disclosure is shown.

[0128] The physical page reclaimer can control the operation of marking the physical page to be reclaimed as a dirty page, updating the number of valid physical pages of the NAND block where the reclaimed physical page is located, and finally placing the NAND block into different reclaim groups according to the number of valid physical pages in the NAND block.

[0129] Reference Fig.14 When garbage collection is needed, NAND blocks are collected in the order of the number of valid physical pages in the NAND blocks from small to large. NAND blocks without valid physical pages can be collected first, and NAND blocks that meet the garbage collection conditions can be collected in turn. For example, NAND blocks with valid physical pages greater than or equal to L can be collected. m The NAND blocks are not recycled, where L m is the default value.

[0130] like Fig.14 As shown, when NAND blocks are divided into multiple groups, such as dividing NAND blocks without valid physical pages into one group, the number of valid physical pages is less than L. 1 The NAND blocks of the group are divided into a group, and then the groups are recycled in sequence. For each group, the group can be recycled in sequence according to the number of valid physical pages contained in each NAND block in the group.

[0131] Fig.15 A schematic diagram of a physical page data layout according to an embodiment of the present disclosure is shown.

[0132] When the SSD performs garbage collection operations, there may be a small number of valid physical pages in the NAND blocks to be recycled. When recycling such NAND blocks, the physical page recycler needs to copy the data in these valid physical pages to other NAND blocks (such as any NAND blocks that can be allocated). After the data is copied / moved, the logical page-physical page mapping table needs to be updated. In the metadata associated with the physical page, the logical page number corresponding to the physical page is stored. Through the logical page number, the mapping relationship between the logical page and the physical page in the F-FTL mapping table can be updated. Fig.15 In the specification, ECC represents an error correction algorithm. Fig.15 The data layout on the physical page shown is merely exemplary, and the present disclosure is not limited thereto.

[0133] According to the embodiments of the present disclosure, the innovative F-FTL enables the SSD to support a fully transparent data compression function and provide a larger storage space without introducing additional computing load (CPU) and resource requirements (memory or additional hardware). In addition, the fully transparent data compression function enables the SSD of the present disclosure to work like a related SSD, and the host application can use the SSD product of the present disclosure without any software modification or secondary development.

[0134] According to the embodiments of the present disclosure, through an asymmetric logical page-physical page mapping method (the size of the logical page and the physical page are inconsistent), the SSD of the present disclosure only needs 40% of the relevant SSD memory requirements. The reduction in memory requirements can significantly reduce the complexity of the SSD and improve product performance. For example, assuming that the logical page is 4 times the size of the physical page and the SSD provides 1.5 times the user storage space, when the NAND medium can store 4TB of data, the user can store 1.5*4TB=6TB of data.

[0135] Fig.16 A block diagram of a flash memory conversion device according to an embodiment of the present disclosure is shown.

[0136] Reference Fig.16 The flash conversion device 1900 may include a variable mapper 1910, a physical page manager 1920, and a mapping relationship module 1930. For example, the flash conversion device 1900 may be a FTL in an SSD. For example, the flash conversion device 1900 may operate independently or jointly with an external storage device.

[0137] The variable mapper 1910 can identify the size of compressed data obtained by compressing original data in a logical page of a logical address space; and determine the number of physical pages of a physical address space for storing the compressed data based on the size of the compressed data.

[0138] The physical page manager 1920 may allocate physical pages corresponding to the physical page quantity. For example, the physical pages corresponding to the physical page quantity are allocated in the target storage block.

[0139] For example, the target storage block may be a NAND block of a solid-state storage device.

[0140] For example, the allocated physical pages may be continuous physical pages corresponding to the number of physical pages in the target NAND block.

[0141] For example, a logical page may be different from a physical page size. For example, a logical page size may be a physical page size raised to the power of M, where M is a positive integer greater than or equal to 1 and N is a positive integer greater than or equal to 0, as shown in FIG. Figure 5 shown.

[0142] For example, the physical page manager 1920 may provide a plurality of work groups, each work group having a preset number of NAND blocks, each work group being respectively used to perform allocation operations for different numbers of consecutive physical pages and each group being capable of performing the allocation operations in parallel; selecting a target NAND block from a work group corresponding to the number of physical pages, and allocating physical pages corresponding to the number of physical pages from the target NAND block; when all physical pages in a NAND block in a work group are used, allocating a new NAND block to the work group, such as Fig.13 shown.

[0143] For example, the physical page manager 1920 may generate a physical page number based on the allocated physical page, and the physical page number may represent the location information of the physical page in the physical address space, such as Fig.11 shown.

[0144] For example, the mapping relationship module 1930 may store the mapping relationship between the physical page number and the logical page number, where the logical page number indicates the location information of the logical page in the logical address space, such as Fig.10 The mapping relationship may be used to determine the position of a physical page corresponding to the logical page in the physical address space based on the logical page, or to determine the position of a logical page corresponding to the physical page in the logical address space based on the physical page.

[0145] For example, the physical page manager 1920 may determine the number of valid physical pages of each NAND block in the solid-state storage device, the valid physical page containing valid data; determine whether the NAND block meets the recycling condition based on the number of valid physical pages of the NAND block; and recycle the NAND block if the NAND block meets the recycling condition, such as Fig.12 and Fig.14 shown.

[0146] For example, the physical page manager may be configured to: when there is a valid physical page in the NAND block that satisfies the recycling condition, copy the data in the valid physical page to a physical page in the NAND block that does not satisfy the recycling condition; based on the physical page to which the data is copied, generate a physical page number, such as Fig.15 shown.

[0147] For example, the variable mapper may be configured to update the mapping relationship between the physical page number and the logical page number based on the physical page number, wherein the logical page number is a logical page number previously corresponding to the physical page number generated based on the valid physical page, such as Fig.10 shown.

[0148] As an example, the flash conversion device 1900 may be a FTL in an SSD, and the flash conversion device 1900 may be configured as follows: Figures 8 to 14 The workflow shown performs the operations.

[0149] Fig.17 A flow chart of a storage method according to an embodiment of the present disclosure is shown. Fig.17 The storage method shown may be executed by any storage device, for example, by an SSD or an FTL of an SSD.

[0150] Reference Fig.17 In operation S201, the size of compressed data is obtained, where the compressed data is obtained by compressing original data in a logical page of a logical address space.

[0151] In operation S202, based on the size of the compressed data, the number of physical pages of the physical address space used to store the compressed data is determined. The physical address space is provided by a non-volatile memory device. The non-volatile memory device may include a solid-state storage device.

[0152] In operation S203 , physical pages corresponding to the number of physical pages are allocated, and data may be written to the allocated physical pages.

[0153] For example, physical pages corresponding to the number of physical pages may be allocated in the target storage block. The target storage block may be a NAND block of a solid-state storage device.

[0154] The allocated physical pages may be continuous physical pages of the nonvolatile memory device. For example, the allocated physical pages may be continuous physical pages corresponding to the number of physical pages in the target NAND block.

[0155] For example, a logical page can be a different size than a physical page.

[0156] For example, a logical page size may be M times the Nth power of a physical page size, where M is a positive integer greater than or equal to 1, and N is a positive integer greater than or equal to 0.

[0157] For example, the operation of allocating physical pages corresponding to the number of physical pages may include: providing multiple workgroups, each of the multiple workgroups having a preset number of NAND blocks, each of the workgroups being used to perform allocation operations for different numbers of consecutive physical pages, and the multiple workgroups being able to perform the allocation operations in parallel; selecting a target NAND block from a workgroup in the multiple workgroups based on the number of physical pages; and allocating the physical pages from the target NAND block based on the number of physical pages. Specifically, multiple workgroups may be provided, each of the workgroups having a preset number of NAND blocks, each of the workgroups being used to perform allocation operations for different numbers of consecutive physical pages, and each of the groups being able to perform the allocation operations in parallel; selecting the target NAND block from the workgroup corresponding to the number of physical pages, and allocating the physical pages corresponding to the number of physical pages from the target NAND block.

[0158] For example, the storage method may further include: when all physical pages in a NAND block in a work group are used, allocating a new NAND block to the work group.

[0159] For example, the storage method may further include: generating a physical page number based on the allocated physical page, the physical page number indicating the position of the physical page in the physical address space; and storing a mapping relationship between the physical page number and the logical page number, the logical page number indicating the position of the logical page in the logical address space. For example, the mapping relationship is used to determine the position of the physical page corresponding to the logical page in the physical address space based on the logical page or to determine the position of the logical page corresponding to the physical page in the logical address space based on the physical page.

[0160] For example, the storage method may further include: identifying the number of valid physical pages for each of the multiple NAND blocks, the valid physical page containing valid data; for a NAND block among the multiple NAND blocks, based on the number of valid physical pages of the NAND block, identifying whether the NAND block meets a recycling condition; and recycling the NAND block based on the NAND block meeting the recycling condition. Specifically, the number of valid physical pages for each NAND block in the solid-state storage device may be determined, the valid physical page containing valid data; based on the number of valid physical pages of the NAND block, determining whether the NAND block meets the recycling condition; and recycling the NAND block if the NAND block meets the recycling condition.

[0161] For example, the storage method may further include: based on the existence of a valid physical page in the NAND block that meets the recycling condition, copying data in the valid physical page to a physical page in the NAND block that does not meet the recycling condition, for example, copying data in the valid physical page of the NAND block that meets the recycling condition to a physical page newly allocated from an idle NAND block; based on the physical page to which the data is copied, generating a physical page number; and updating a mapping relationship between the physical page number and the logical page number. For example, the logical page number is a logical page number previously corresponding to a physical page number generated based on the valid physical page.

[0162] Fig.17 The storage method shown can refer to the above Figures 8 to 14 The workflow shown is not described in detail here.

[0163] According to an embodiment of the present disclosure, during the data storage process, a data compression function is integrated to enable users to store more data in a fixed physical storage space, so as to reduce data storage resources and complexity.

[0164] The flash memory conversion device and storage method disclosed in the present invention can be applied to smart SSD products and other computing storage devices that provide a fully transparent data compression function and / or require that a logical page is larger than a physical page.

[0165] Fig.18 A schematic diagram of a system 1000 to which a storage device is applied according to an exemplary embodiment of the present disclosure.

[0166] Fig.18 The system 1000 may basically be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device. However, Fig.18 The system 1000 is not necessarily limited to a mobile system, and may be a PC, a laptop, a server, a media player, or an automotive device (eg, a navigation device).

[0167] Reference Fig.18 , the system 1000 may include a main processor 1100, a memory (e.g., 1200a and 1200b), and a storage device (e.g., 1300a and 1300b). The storage device may be configured to execute the above storage method. In addition, the system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0168] The main processor 1100 may control all operations of the system 1000, and more specifically, may control operations of other components included in the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, an application processor, or the like.

[0169] The main processor 1100 may include at least one central processing unit (CPU) core 1110, and also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some exemplary embodiments, the main processor 1100 may further include an accelerator 1130, which is a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), etc., and is implemented as a chip physically separated from other components of the main processor 1100.

[0170] The memories 1200a and 1200b may be used as main storage devices of the system 1000. Although the memories 1200a and 1200b may respectively include volatile memories, such as static random access memory (SRAM) and / or dynamic random access memory (DRAM), etc., the memories 1200a and 1200b may respectively include non-volatile memories, such as flash memory, phase change random access memory (PRAM) and / or resistive random access memory (RRAM), etc. The memories 1200a and 1200b may be implemented in the same package as the main processor 1100.

[0171] The storage devices 1300a and 1300b may be used as non-volatile storage devices, which are configured to store data regardless of whether they are powered on and have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include memory controllers (STRG CTRL) 1310a and 1310b and non-volatile memories (NVM) 1320a and 1320b, respectively, which are configured to store data via the control of the memory controllers 1310a and 1310b. Although the NVMs 1320a and 1320b may include V-NAND flash memories having a two-dimensional (2D) or three-dimensional (3D) structure, the NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and / or RRAM, etc.

[0172] The storage devices 1300a and 1300b may be physically separated from the main processor 1100 and included in the system 1000, or may be implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may have a type of solid-state device (SSD) or memory card, and may be removably combined with other components of the system 1000 through an interface such as a connection interface 1480 to be described later. The storage devices 1300a and 1300b may be devices to which a standard protocol such as Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or NVMe is applied, but are not limited thereto.

[0173] The image capture device 1410 can capture still images or moving images. The image capture device 1410 may include a camera, a camcorder, and / or a webcam, etc.

[0174] The user input device 1420 may receive various types of data input by a user of the system 1000 and includes a touch pad, a keypad, a keyboard, a mouse, a microphone, and the like.

[0175] The sensor 1430 may detect various types of physical quantities that may be obtained from the outside of the system 1000 and convert the detected physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor, etc.

[0176] The communication device 1440 may transmit and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, a transceiver, a modem, or the like.

[0177] Display 1450 and speaker 1460 may be used as output devices configured to output visual information and auditory information, respectively, to a user of system 1000 .

[0178] The power supply device 1470 may appropriately convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000 .

[0179] The connection interface 1480 may provide a connection between the system 1000 and an external device that is connected to the system 1000 and is capable of transmitting and receiving data to and from the system 1000. The connection interface 1480 may be implemented by using various interface schemes, for example, Advanced Technology Attachment (ATA), Serial ATA (SATA), External Serial ATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, UFS interface, Embedded UFS (eUFS) interface, Compact Flash (CF) card interface, and the like.

[0180] The storage device (e.g., 1300a and 1300b) may be an SSD. According to an exemplary embodiment of the present disclosure, a system (e.g., 1000) to which a storage device is applied is provided, including: a main processor (e.g., 1100); a memory (e.g., 1200a and 1200b); and a storage device (e.g., 1300a and 1300b), wherein the storage device is configured to execute the storage method described above. For example, a storage controller (e.g., 1310a or 1310b) may include Figure 8 The F-FTL, write controller, read controller, compression engine and decompression engine, Flash core and NAND storage medium shown; and performing any of the above methods or operations.

[0181] Fig.19 is a block diagram of a host storage system 10 according to an exemplary embodiment.

[0182] The host storage system 10 may include a host 100 and a storage device 200. The storage device 200 may be configured to perform the above-mentioned storage method. In addition, the storage device 200 may include a memory controller 210 and an NVM 220. According to an exemplary embodiment of the present disclosure, the host 100 may include a host controller 110 and a host memory 120. The host memory 120 may be used as a buffer memory, which is configured to temporarily store data to be sent to the storage device 200 or data received from the storage device 200.

[0183] The storage device 200 may include a storage medium configured to store data in response to a request from the host 100. As an example, the storage device 200 may include at least one of an SSD, an embedded memory, and a removable external memory. When the storage device 200 is an SSD, the storage device 200 may be a device that complies with the NVMe standard. When the storage device 200 is an embedded memory or an external memory, the storage device 200 may be a device that complies with the UFS standard or the eMMC standard. Both the host 100 and the storage device 200 may generate a packet and send the packet according to the adopted standard protocol.

[0184] When the NVM 220 of the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may include various other types of NVM. For example, the storage device 200 may include a magnetic random access memory (MRAM), a spin transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FRAM), a PRAM, a RRAM, and various other types of memory.

[0185] According to an exemplary embodiment, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. Alternatively, in some exemplary embodiments, the host controller 110 and the host memory 120 may be integrated in the same semiconductor chip. As an example, the host controller 110 may be any one of a plurality of modules included in an application processor (AP). The AP may be implemented as a system on chip (SoC). In addition, the host memory 120 may be an embedded memory included in the AP or a memory module outside the AP.

[0186] The host controller 110 may manage an operation of storing data (eg, write data) of the buffer area of ​​the host memory 120 in the NVM 220 or an operation of storing data (eg, read data) of the NVM 220 in the buffer area.

[0187] The memory controller 210 may include a host interface 211, a memory interface 212, and a CPU 213. In addition, the memory controller 210 may further include a flash translation layer (FTL), a packet manager 215, a buffer memory 216, an error correction code (ECC) engine 217, and an advanced encryption standard (AES) engine 218. The memory controller 210 may further include a working memory (not shown) in which the FTL 214 is loaded. The CPU 213 may execute the FTL 214 to control data write and read operations on the NVM 220.

[0188] The host interface 211 may transmit and receive packets to and from the host 100. The packets transmitted from the host 100 to the host interface 211 may include commands or data to be written to the NVM 220, etc. The packets transmitted from the host interface 211 to the host 100 may include responses to commands or data read from the NVM 220, etc. The memory interface 212 may transmit data to be written to the NVM 220 to the NVM 220 or receive data read from the NVM 220. The memory interface 212 may be configured to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0189] The FTL 214 may perform various functions, such as an address mapping operation, a wear leveling operation, and a garbage collection operation. The address mapping operation may be an operation of converting a logical address received from the host 100 into a physical address for actually storing data in the NVM 220. The wear leveling operation may be a technique for preventing excessive degradation of a specific block by allowing the blocks of the NVM 220 to be used evenly. As an example, the wear leveling operation may be implemented by using a firmware technique that balances the erase counts of physical blocks. The garbage collection operation may be a technique for ensuring available capacity in the NVM 220 by erasing an existing block after copying valid data of the existing block to a new block.

[0190] The packet manager 215 may generate a packet according to a protocol agreed to an interface of the host 100, or parse various types of information from a packet received from the host 100. In addition, the buffer memory 216 may temporarily store data to be written to or read from the NVM 220. Although the buffer memory 216 may be a component included in the memory controller 210, the buffer memory 216 may be outside the memory controller 210.

[0191] The ECC engine 217 may perform error detection and correction operations on read data read from the NVM 220. More specifically, the ECC engine 217 may generate parity bits for write data to be written to the NVM 220, and the generated parity bits may be stored together with the write data in the NVM 220. During reading of data from the NVM 220, the ECC engine 217 may correct errors in the read data by using the read data and the parity bits read from the NVM 220, and output the error-corrected read data.

[0192] The AES engine 218 may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 210 by using a symmetric key algorithm.

[0193] The storage device 200 may be an SSD. According to an exemplary embodiment of the present disclosure, a host storage system (e.g., 10) is provided, comprising: a host (e.g., 100); and a storage device (200), wherein the storage device is configured to execute the storage method described above. For example, the storage controller 210 may include Figure 8 The F-FTL, write controller, read controller, compression engine and decompression engine, Flash core and NAND storage medium shown; and performing any of the above methods or operations.

[0194] Fig. 20 FIG. 3 is a diagram of a data center 3000 to which a storage device is applied according to an exemplary embodiment of the present disclosure.

[0195] Platform part - server (application / storage)

[0196] Reference Fig. 20 , the data center 3000 may be a facility that collects various types of data and provides services, and is referred to as a data storage center. The data center 3000 may be a system for operating a search engine and a database, and may be a computing system used by a company (such as a bank) or a government agency. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. According to an exemplary embodiment, the number of applications 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected differently. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be different from each other.

[0197] The application server 3100 or the storage server 3200 may include at least one of the processors 3110 and 3210 and the memories 3120 and 3220. Now, the storage server 3200 will be described as an example. The processor 3210 may control all operations of the storage server 3200, access the memory 3220, and execute instructions and / or data loaded into the memory 3220. The memory 3220 may be a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, or a non-volatile DIMM (NVMDIMM). In some exemplary embodiments, the number of processors 3210 and memories 3220 included in the storage server 3200 may be selected differently. In an exemplary embodiment, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an exemplary embodiment, the number of processors 3210 and the number of memories 3220 may be different from each other. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100. In some embodiments, the application server 3100 may not include the storage device 3150. The storage server 3200 may include at least one storage device 3250. According to the embodiment, the number of storage devices 3250 included in the storage server 3200 may be selected differently.

[0198] Platform part - Network

[0199] The application servers 3100 to 3100n can communicate with the storage servers 3200 to 3200m through the network 3300. The network 3300 can be implemented by using a fiber channel (FC) or Ethernet. In this case, FC can be a medium for relatively high-speed data transmission, and an optical switch with high performance and high availability can be used. According to the access method of the network 3300, the storage servers 3200 to 3200m can be set to file storage, block storage, or object storage.

[0200] In one embodiment, the network 3300 may be a network dedicated to storage, such as a storage area network (SAN). For example, the SAN may be an FC-SAN, which uses an FC network and is implemented according to the FC protocol (FCP). As another example, the SAN may be an Internet Protocol (IP)-SAN, which uses a transmission control protocol (TCP) / IP network and is implemented according to the SCSI or Internet SCSI (iSCSI) protocol over TCP / IP. In another embodiment, the network 3300 may be a general network, such as a TCP / IP network. For example, the network 3300 may be implemented according to protocols such as FC over Ethernet (FCoE), network attached storage (NAS), and NVMe over fabric (NVMe-oF).

[0201] Hereinafter, the application server 3100 and the storage server 3200 will be mainly described. The description of the application server 3100 may be applied to another application server 3100n, and the description of the storage server 3200 may be applied to another storage server 3200m.

[0202] The application server 3100 may store data requested to be stored by a user or client in one of the storage servers 3200 to 3200m through the network 3300. In addition, the application server 3100 may obtain data requested to be read by a user or client from one of the storage servers 3200 to 3200m through the network 3300. For example, the application server 3100 may be implemented as a network server or a database management system (DBMS).

[0203] The application server 3100 may access a memory 3120n or a storage device 3150n included in another application server 3100n through the network 3300. Alternatively, the application server 3100 may access a memory 3220 to 3220m or a storage device 3250 to 3250m included in the storage servers 3200 to 3200m through the network 3300. Therefore, the application server 3100 may perform various operations on the data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 may execute an instruction for moving or copying data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. In this case, data may be moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m through the storage 3220 to 3220m of the storage servers 3200 to 3200m or directly to the storage 3120 to 3120n of the application servers 3100 to 3100n. The data moved through the network 3300 may be data encrypted for security or privacy.

[0204] Organic Relationship-Interface Structure / Type

[0205] The storage server 3200 will now be described as an example. The interface 3254 can provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the network interface card (NIC) 3240 and the controller 3251. For example, the interface 3254 can be implemented using a direct attached storage (DAS) solution, where the storage device 3250 is directly connected to a dedicated cable. For example, the interface 3254 can be implemented using various interface solutions, such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface, and CF card interface.

[0206] The storage server 3200 may further include a switch 3230 and a network interconnect (NIC) 3240. The switch 3230 may selectively connect the processor 3210 to the storage device 3250 or selectively connect the NIC 3240 to the storage device 3250 via the control of the processor 3210.

[0207] In one embodiment, the NIC 3240 may include a network interface card and a network adapter. The NIC 3240 may be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC 3240 may include an internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to the processor 3210 and / or the switch 3230 through the host bus interface. The host bus interface may be implemented as one of the above examples of the interface 3254. In one embodiment, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0208] Organic Relationship-Interface Operation

[0209] In the storage servers 3200 to 3200m or the application servers 3100 to 3100n, the processor may send a command to the storage devices 3150 to 3150n and 3250 to 3250m or the memories 3120 to 3120n and 3220 to 3220m and program or read data. In this case, the data may be data in which an error is corrected by an ECC engine. The data may be data on which a data bus inversion (DBI) operation or a data masking (DM) operation is performed, and may include cyclic redundancy coding (CRC) information. The data may be data encrypted for security or privacy.

[0210] The storage devices 3150 to 3150n and 3250 to 3250m may send control signals and command / address signals to the NAND flash memory devices 3252 to 3252m in response to a read command received from the processor. Therefore, when data is read from the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal may be input as a data output control signal, and thus, the data may be output to the DQ bus. The data strobe signal DQS may be generated using the RE signal. Depending on the rising edge or falling edge of the write enable (WE) signal, the command and address signals may be latched in the page buffer.

[0211] Product section - Basic operation of SSD

[0212] The controller 3251 may control all operations of the storage device 3250. In one embodiment, the controller 3251 may include an SRAM. The controller 3251 may write data to the NAND flash memory device 3252 in response to a write command, or read data from the NAND flash memory device 3252 in response to a read command. For example, a write command and / or a read command may be provided from a processor 3210 of the storage server 3200, a processor 3210m of another storage server 3200m, or processors 3110 and 3110n of application servers 3100 and 3100n. The DRAM 3253 may temporarily store (or buffer) data to be written to the NAND flash memory device 3252 or data to be read from the NAND flash memory device 3252. And, the DRAM 3253 may store metadata. Here, the metadata may be user data or data generated by the controller 3251 for managing the NAND flash memory device 3252. The storage device 3250 may include a secure element (SE) for security or privacy.

[0213] The storage device 3250 may be an SSD. According to an exemplary embodiment of the present disclosure, a data center system (e.g., 3000) is provided, including: a plurality of application servers (3100 to 3100n); and a plurality of storage servers (e.g., 3200 to 3200m), wherein each storage server includes a storage device 200, wherein the storage device 200 is configured to execute the storage method described above. For example, the controller 3251 may include Figure 8 The F-FTL, write controller, read controller, compression engine and decompression engine, Flash core and NAND storage medium shown; and performing any of the above methods or operations.

[0214] According to an exemplary embodiment of the present disclosure, there is provided a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the storage method as described above is implemented.

[0215] According to an exemplary embodiment of the present disclosure, there is provided an electronic device, including: a processor; and a memory storing a computer program, wherein when the computer program is executed by the processor, the storage method described above is implemented.

[0216] According to an exemplary embodiment of the present disclosure, a computer-readable storage medium storing instructions may also be provided, wherein when the instructions are executed by at least one processor, the at least one processor is prompted to execute the storage method according to the embodiment of the present disclosure. Examples of computer-readable storage media here include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), card storage (such as, multimedia card, secure digital (SD) card or extreme digital (XD) card), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk and any other device, any other device is configured to store computer programs and any associated data, data files and data structures in a non-transitory manner and provide the computer programs and any associated data, data files and data structures to a processor or computer so that the processor or computer can execute the computer program. The computer program in the above-mentioned computer-readable storage medium can be run in an environment deployed in a computer device such as a client, a host, an agent device, a server, etc. In addition, in one example, the computer program and any associated data, data files and data structures are distributed on a networked computer system, so that the computer program and any associated data, data files and data structures are stored, accessed and executed in a distributed manner by one or more processors or computers.

[0217] The terms "first", "second", "third", "fourth", "1", "2", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than that shown or described in the text.

[0218] It should be understood that, although the flowchart of the embodiment of the present disclosure indicates each operation / step by arrows, the implementation order of these operations / steps is not limited to the order indicated by the arrows. Unless clearly stated herein, in some implementation scenarios of the embodiment of the present disclosure, the implementation steps in each flowchart can be executed in other orders according to demand. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage in these sub-steps or stages can also be executed at different times. In scenarios with different execution times, the execution order of these sub-steps or stages can be flexibly configured according to demand, and the embodiment of the present disclosure does not limit this.

[0219] The above text and drawings are provided only as examples to help readers understand the present disclosure. They are not intended and should not be interpreted as limiting the scope of the present disclosure in any way. Although certain embodiments and examples have been provided, based on the contents disclosed herein, it is obvious to those skilled in the art that the embodiments and examples shown can be changed without departing from the scope of the present disclosure, and other similar implementation means based on the technical ideas of the present disclosure are adopted, which also fall within the protection scope of the embodiments of the present disclosure.

Claims

1. A storage device, comprising: a non-volatile memory device configured to provide a physical address space; as well as At least one processor configured to implement: A mutable mapper, configured as: Acquire the size of compressed data, where the compressed data is obtained by compressing original data in a logical page of a logical address space; Based on the size of the compressed data, determining the number of physical pages of the physical address space for storing the compressed data; a physical page manager configured to allocate physical pages corresponding to the number of physical pages; A write controller is configured to write data into the physical page allocated by the physical page manager.

2. The storage device according to claim 1, characterized in that The non-volatile memory device comprises a solid-state storage device, Wherein, the physical page is allocated in a NAND block of the solid-state storage device.

3. The storage device according to claim 1, characterized in that: The allocated physical pages are contiguous physical pages of the non-volatile memory device.

4. The storage device according to claim 1, characterized in that: The size of a logical page is different from the size of a physical page in the physical address space.

5. The storage device according to claim 4, characterized in that: The logical page size is M times the physical page size to the Nth power, where M is a positive integer greater than or equal to 1, and N is a positive integer greater than or equal to 0.

6. The storage device according to claim 1, characterized in that: The physical page manager is further configured to: Providing a plurality of work groups, each of the plurality of work groups having a preset number of NAND blocks, each of the work groups being respectively used to perform allocation operations for a different number of consecutive physical pages, and the plurality of work groups being capable of performing the allocation operations in parallel; selecting a target NAND block from a work group among the plurality of work groups based on the number of physical pages; allocating the physical pages from the target NAND block based on the number of physical pages; Based on that all physical pages in a NAND block in a work group among the plurality of work groups are used, a new NAND block is allocated to the work group.

7. A storage method, characterized in that: The storage method comprises: Acquire the size of compressed data, where the compressed data is obtained by compressing original data in a logical page of a logical address space; Based on the size of the compressed data, determining the number of physical pages of the physical address space provided by the non-volatile memory device for storing the compressed data; Allocating physical pages corresponding to the number of physical pages; and Write the data to the allocated physical page.

8. The storage method according to claim 10, characterized in that: The non-volatile memory device comprises a solid-state storage device, The allocation steps include: The physical pages are allocated in NAND blocks of the solid-state storage device.

9. A non-transitory computer-readable storage medium storing a computer program, wherein: When the computer program is executed by a processor, the storage method according to any one of claims 7 to 8 is performed.

10. An electronic device comprising: processor; A memory storing a computer program, wherein when the computer program is executed by a processor, the storage method according to any one of claims 7 to 8 is executed.

Images