Method, equipment, computer equipment and system for realizing memory sharing control

Abstract

The invention discloses a method, equipment, computer equipment and a system for realizing memory sharing control, and aims to improve the utilization rate of memory resources. According to the computer equipment, memory sharing control equipment is deployed between a processor and a memory pool, and the processor accesses the memory pool through the memory sharing control equipment. Different processing units, such as a processor or a core in the processor, access at least one memory in the memory pool in different time periods, so that the memory sharing of a plurality of processing units is realized, and the utilization rate of memory resources is improved.

Description

[0001] This application is a divisional application. The application number of the original application is 202110351637.5, and the original application date is March 31, 2021. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of information technology, and in particular to a method, device and system for controlling a shared memory. Background Art

[0003] With the popularization of big data technology, the demand for computing resources in various fields is increasing day by day. Large-scale computing represented by graph computing, deep learning and other applications represents the latest application development direction. At the same time, with the slowdown of semiconductor process development, applications can no longer continue to obtain scalable performance improvements from processor upgrades, and multi-core processors are gradually becoming the mainstream.

[0004] The demand for memory capacity in multi-core processor systems is constantly increasing. As an indispensable component in servers, memory accounts for about 30%-40% of the cost of the entire server system. Improving memory utilization is an important means to reduce the total cost of operations (TCO) of the system. Summary of the invention

[0005] The present application provides a method, device, computer device and system for implementing memory sharing control to improve the utilization of memory resources.

[0006] In a first aspect, the present application provides a computer device, comprising at least two processing units, a memory sharing control device, and a memory pool, wherein the processing unit is a processor, a core in a processor, or a combination of cores in a processor, and the memory pool comprises one or more memories;

[0007] The at least two processing units are coupled to the memory sharing control device;

[0008] The memory sharing control device is used to allocate memory from the memory pool to the at least two processing units respectively, and at least one memory in the memory pool can be accessed by different processing units in different time periods;

[0009] The at least two processing units are used to access the allocated memory through the memory sharing control device.

[0010] At least two processing units in the computer device can access at least one memory in the memory pool in different time periods through the memory sharing control device, so that multiple processing units can share the memory, thereby improving the utilization rate of memory resources.

[0011] Optionally, at least one memory in the memory pool can be accessed by different processing units in different time periods, which means that any two processing units among the at least two processing units can access at least one memory in the memory pool in different time periods. For example, the at least two processing units include a first processing unit and a second processing unit. In a first time period, the first memory in the memory pool is accessed by the first processing unit, and the second processing unit cannot access the first memory; in a second time period, the first memory in the memory pool is accessed by the second processing unit, and the first processing unit cannot access the first memory. Optionally, the processor may be a central processing unit (CPU), and a CPU may include two or more cores.

[0012] Optionally, one of the at least two processing units may be a processor, a core in a processor, a combination of multiple cores in a processor, or a combination of multiple cores in different processors. Using a combination of multiple cores in a processor as a processing unit, or using a combination of multiple cores in different processors as a processing unit, can meet the need for multiple different cores to access the same block of memory when executing tasks in parallel in a parallel computing scenario, and can improve the efficiency of multiple different cores when executing parallel computing.

[0013] Optionally, the memory sharing control device may allocate memory from the memory pool to the at least two processing units respectively according to the control instructions sent by the operating system in the computer device. Specifically, the driver in the operating system may send the control instructions for allocating memory in the memory pool to the at least two processing units to the memory sharing control device through a dedicated channel. The operating system is implemented by the CPU in the computer device by executing related codes, and the CPU running the operating system has a privileged mode, in which the driver in the operating system can send control instructions to the memory sharing control device through a dedicated or specific channel.

[0014] Optionally, the memory sharing control device can be implemented by a field programmable gate array (FPGA) chip, an application-specific integrated circuit (ASIC) or other similar chip. The circuit function of the ASIC chip is defined at the beginning of the design, and it has the characteristics of high chip integration, easy mass production, low single chip cost and small size.

[0015] In some possible implementations, the at least two processing units are connected to the memory sharing control device via a serial bus;

[0016] The first processing unit among the at least two processing units is used to send a first memory access request in the form of a serial signal to the memory sharing device through the serial bus, where the first memory access request is used to access a first memory allocated to the first processing unit.

[0017] The serial bus has the characteristics of high bandwidth and low latency. The at least two processing units and the memory sharing control device are connected via the serial bus, which can ensure the efficiency of data transmission between the processing units and the memory sharing control device.

[0018] Optionally, the serial bus is a memory semantic bus. The memory semantic bus includes but is not limited to: a bus based on quick path interconnect (QPI), peripheral component interconnect express (PCIe), Huawei Cache Coherence System (HCCS) or compute express link (CXL) protocol interconnection.

[0019] Optionally, when the first processing unit generates a memory access request, it is a memory access request in the form of a parallel signal. The first processing unit can convert the memory access request in the form of a parallel signal into a first memory access request in the form of a serial signal through an interface capable of converting parallel signals into serial signals, such as a Serdes interface, and send it to the memory sharing device through a serial bus.

[0020] In some possible implementations, the memory sharing control device includes a processor interface, and the processor interface is used to:

[0021] receiving the first memory access request;

[0022] The first memory access request is converted into a second memory access request in the form of a parallel signal.

[0023] The processor interface converts the first memory access request into a second memory access request in the form of a parallel signal, so that the memory sharing control device can access the first memory and realize memory sharing without changing the framework of the existing memory access architecture.

[0024] Optionally, the processor interface is an interface capable of converting parallel signals into serial signals, for example, a Serdes interface.

[0025] In some possible implementations, the memory sharing control device includes a control unit, and the control unit is used to:

[0026] A correspondence between a memory address of the first memory in the memory pool and a first processing unit among the at least two processing units is established to allocate the first memory to the first processing unit from the memory pool.

[0027] Optionally, the correspondence between the memory address of the first memory and the first processing unit can be adjusted dynamically. For example, the correspondence between the memory address of the first memory and the first processing unit can be adjusted dynamically as needed.

[0028] Optionally, the memory address of the first memory may be a continuous physical memory address in the memory pool. A continuous physical memory address in the memory pool can simplify the management of the first memory. Of course, the memory address of the first memory may also be several discontinuous physical memory addresses in the memory pool.

[0029] Optionally, the memory address information of the first memory includes the starting address of the first memory and the size of the first memory. The first processing unit has an identifier, and the establishing of the correspondence between the memory address of the first memory and the first processing unit may be establishing a correspondence between the unique identifier of the first processing unit and the memory address information of the first memory.

[0030] In some possible implementations, the memory sharing control device includes a control unit, and the control unit is used to:

[0031] Virtualizing a plurality of virtual memory devices from the memory pool, wherein a physical memory corresponding to a first virtual memory device among the plurality of virtual memory devices is the first memory;

[0032] The first virtual memory device is allocated to the first processing unit. Optionally, the virtual memory device corresponds to a continuous segment of physical memory addresses in the memory pool. The virtual memory device corresponds to a continuous segment of physical memory addresses in the memory pool, which can simplify the management of the virtual memory device. Of course, the virtual memory device can also correspond to several discontinuous segments of physical memory addresses in the memory pool.

[0033] Optionally, the first virtual memory device can be assigned to the first processing unit by establishing an access control table. For example, the access control table may include information such as the identifier of the first processing unit, the identifier of the first virtual memory device, the starting address and size of the memory corresponding to the first virtual memory device, etc. The access control table may also include permission information for the first processing unit to access the first virtual memory device, attribute information of the memory to be accessed (including but not limited to information on whether it is persistent memory), etc.

[0034] In some possible implementations, the control unit is further configured to:

[0035] When a preset condition is met, releasing the correspondence between the first virtual memory device and the first processing unit;

[0036] A correspondence between the first virtual memory device and a second processing unit among the at least two processing units is established.

[0037] Optionally, the correspondence between the virtual memory device and the processing unit may be dynamically adjusted according to the requirements of the at least two processing units for memory resources.

[0038] By dynamically adjusting the correspondence between the virtual memory device and the processing unit, it is possible to flexibly adapt to the needs of different processing units for memory resources in different business scenarios, thereby improving the utilization rate of memory resources.

[0039] Optionally, the preset condition may be that the demand for memory access by the first processing unit decreases, while the demand for memory access by the second processing unit increases.

[0040] Optionally, the control unit is further used for:

[0041] When the preset condition is met, the correspondence between the first memory and the first virtual memory device is cancelled; the correspondence between the first memory and the second virtual memory device among the multiple virtual memory devices is established; and the second virtual memory device is allocated to the second processing unit among the at least two processing units. In this case, it is not necessary to change the correspondence between the virtual memory device and the physical memory address in the memory pool, but only to change the correspondence between the virtual memory device and different processing units, so that different processing units can access the same physical memory in different time periods.

[0042] In some possible implementations, the memory sharing control device also includes a cache unit, which is used to cache data read from the memory pool by any one of the at least two processing units, or cache data eliminated by any one of the at least two processing units.

[0043] The cache unit can further improve the efficiency of the processing unit accessing memory data.

[0044] Optionally, the cache unit may include a first-level cache and a second-level cache. The first-level cache may be small in capacity but with a higher read and write speed than the second-level cache, for example, the first-level cache may be a nanosecond-level cache of 100 megabytes (MB); the second-level cache may be large in capacity but with a lower read and write speed than the first-level cache, for example, the second-level cache may be a 1-gigabyte (GB) dynamic random access memory (DRAM). Through the first-level cache and the second-level cache, while the processor accesses data speed through the cache, the cache space can be increased, the scope of the processor's rapid access to memory through the cache can be expanded, and the rate at which the processor resource pool accesses memory can be further improved overall.

[0045] Optionally, the data in the memory can be cached in the secondary cache first, and then the data in the secondary cache can be cached in the primary cache according to the needs of the processing unit for the memory data. The data that is eliminated or temporarily not needed to be processed by the processing unit can also be cached in the primary cache. To ensure that the primary cache has enough space for other processing units to cache data, the data eliminated by the processing unit in some primary caches can be cached in the secondary cache units.

[0046] In some possible implementations, the memory sharing control device further includes a prefetch engine, which is used to prefetch data that needs to be read by any one of the at least two processing units from the memory pool, and cache it in the cache unit.

[0047] Optionally, the prefetch engine may implement intelligent data anticipation through a specific algorithm or a related artificial intelligence (AI) algorithm to further improve the efficiency of the processing unit accessing memory data.

[0048] In some possible implementations, the memory sharing control device further includes a quality of service (QoS) engine, which is used to optimize the storage of data that needs to be cached by any one of the at least two processing units in the cache unit. Through the QoS engine, it is possible to achieve different cache capabilities for data accessed by different processing units in the cache unit 304. For example, a memory access request initiated by a processing unit with a high priority has an exclusive cache space in the cache unit 304, which can ensure that the data accessed by the processing unit can be cached in time, thereby ensuring the quality of such processor business processing.

[0049] In some possible implementations, the memory sharing control device further includes a compression / decompression engine, and the compression / decompression engine is used to implement compression or decompression of the data related to memory access.

[0050] Optionally, the functionality of the compression / decompression engine may be turned off.

[0051] The compression / decompression engine can compress the data written by the processing unit into the memory with a granularity of 4 kilobits (KB) per page through a compression ratio algorithm and then write it into the memory; or when the processing unit reads the compressed data in the memory, the data to be read is decompressed and then sent to the processor. This can increase the rate of data transmission and further improve the efficiency of the processing unit accessing the memory data. Optionally, the compression / decompression engine can be turned off.

[0052] Optionally, the memory sharing control device further includes a storage unit, wherein the storage unit includes software code of at least one of the QoS engine, the prefetch engine, and the compression / decompression engine. The memory sharing control device can read the code in the storage unit to implement corresponding functions.

[0053] Optionally, at least one of the QoS engine, the prefetch engine, and the compression / decompression engine may be implemented by the control logic of the memory sharing control device.

[0054] In some possible implementations, the first processing unit further has a local memory, and the local memory is used for memory access of the first processing unit. Optionally, the first processing unit can preferentially access the local memory. The first processing unit accesses the local memory faster, which can further improve the speed of the first processing unit accessing the memory.

[0055] In some possible implementations, the multiple memories included in the memory pool belong to different media types. For example, the memory pool may include at least one of the following memory media: DRAM, phase change memory (PCM), storage class memory (SCM), static random access memory (SRAM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), NAND FLASH Memory, spin-torque transfer readonly memory (STT-RAM) or resistive memory (RRAM). The memory pool may also include a dual in-line memory module or a dual-line memory module (DIMM), or a solid state disk (SSD).

[0056] Using different memory media can meet the memory resource requirements of different processing units in different processor businesses. For example, DRAM has the characteristics of fast read and write speed and volatility, so DRAM memory can be allocated to processing units that initiate hot data access; while PCM has the characteristics of non-volatility, PCM memory can be allocated to processing units that access data that needs to be saved for a long time. In this way, the flexibility of memory access control can be improved while sharing memory resources.

[0057] Taking the memory pool including volatile DRAM storage medium and non-volatile PCM storage medium as an example, the DRAM and PCM in the memory pool can be a parallel architecture, and there is no distinction between DRAM and PCM; it can also be a non-parallel architecture with DRAM as cache and PCM as main memory, DRAM can be used as the first-level storage medium, and PCM as the second-level storage medium. For the parallel architecture of DRAM and PCM, the control unit can store hot data with high access frequency on DRAM, that is, establish a corresponding relationship between the processing unit that initiates hot data with high access frequency and the virtual memory device corresponding to the DRAM memory, which can improve the reading and writing speed of memory data and the service life of the main memory system. The control unit can also establish a corresponding relationship between the processing unit that initiates cold data with low access frequency and the virtual memory device corresponding to the PCM memory, and store the cold data with low access frequency on PCM, so that the non-volatile characteristics of PCM can be used to ensure the security of important data. For the non-parallel architecture of DRAM and PCM, the high integration of PCM and the low read and write latency of DRAM can be utilized. The control unit can use PCM as main memory to store various types of data and use DRAM as cache, which can further improve the efficiency and performance of memory access.

[0058] In a second aspect, the present application provides a system, comprising at least two computer devices described in the first aspect, wherein the at least two computer devices described in the first aspect are connected via a network.

[0059] A computer device of the system can not only access the memory pool on the computer device through the memory sharing control device to improve the memory utilization, but also access the memory pool on other computer devices through the network. Expanding the scope of the memory pool can further improve the utilization of memory resources.

[0060] Optionally, the memory sharing control device in the computer device in the system may also have the function of a network adapter, which can send the access request of the processing unit to other computer devices in the system through the network to access the memory in other computer devices.

[0061] Optionally, the computer device in the system may also include a network adapter having a serial-to-parallel conversion interface (e.g., a Serdes interface), and the memory sharing control device in the computer device may send the memory access request of the processing unit to other computer devices in the system through the network via the network adapter to access the memory in the other computer devices.

[0062] Optionally, the computer devices in the system may be connected via an Ethernet-based network or a unit-bus (U-bus)-based network.

[0063] In a third aspect, the present application provides a memory sharing control device, the memory sharing control device comprising a control unit, a processor interface and a memory interface;

[0064] The processor interface is used to receive memory access requests sent by at least two processing units; wherein the processing unit is a processor, a core in a processor, or a combination of cores in a processor;

[0065] The control unit is used to allocate memory from a memory pool to the at least two processing units respectively, and at least one memory in the memory pool can be accessed by different processing units in different time periods;

[0066] The control unit is further configured to enable the at least two processing units to access the allocated memory through the memory interface.

[0067] Through the memory sharing control device, different processing units can access at least one memory in the memory pool in different time periods, which can meet the needs of the processing units for memory resources and improve the utilization rate of memory resources.

[0068] Optionally, at least one memory in the memory pool can be accessed by different processing units in different time periods, which means that any two processing units among the at least two processing units can respectively access at least one memory in the memory pool in different time periods. For example, the at least two processing units include a first processing unit and a second processing unit, and in a first time period, the first memory in the memory pool is accessed by the first processing unit, and the second processing unit cannot access the first memory; in a second time period, the first memory in the memory pool is accessed by the second processing unit, and the first processing unit cannot access the first memory.

[0069] Optionally, the memory interface may be a double data rate (DDR) controller, or the memory interface may be a memory controller with a PCM control function.

[0070] Optionally, the memory sharing control device may allocate memory from the memory pool to the at least two processing units respectively according to the control instructions sent by the operating system in the computer device. Specifically, the driver in the operating system may send the control instructions for allocating memory in the memory pool to the at least two processing units to the memory sharing control device through a dedicated channel. The operating system is implemented by the CPU in the computer device by executing related codes, and the CPU running the operating system has a privileged mode, in which the driver in the operating system can send control instructions to the memory sharing control device through a dedicated or specific channel.

[0071] Optionally, the memory sharing control device may be implemented as an FPGA chip, an ASIC or other similar chips.

[0072] In some possible implementations, the processor interface is also used to receive a first memory access request sent by a first processing unit among the at least two processing units in the form of a serial signal through a serial bus, wherein the first memory access request is used to access a first memory allocated to the first processing unit.

[0073] The serial bus has the characteristics of high bandwidth and low latency. By receiving the first memory access request sent by the first processing unit of the at least two processing units in the form of a serial signal through the serial bus, the efficiency of data transmission between the processing unit and the memory sharing control device can be ensured.

[0074] Optionally, the serial bus is a memory semantic bus. The memory semantic bus includes but is not limited to: a bus interconnected by QPI, PCIe, HCCS or CXL protocol.

[0075] In some possible implementations, the processor interface is further used to convert the first memory access request into a second memory access request in the form of a parallel signal, and send the second memory access request to the control unit;

[0076] The control unit is further configured to implement access of the second memory access request to the first memory through the memory interface.

[0077] Optionally, the processor interface is an interface capable of converting parallel signals into serial signals, for example, a Serdes interface.

[0078] In some possible implementations, the control unit is further used to establish a correspondence between a memory address of the first memory in the memory pool and the first processing unit, so as to allocate the first memory to the first processing unit from the memory pool.

[0079] Optionally, the correspondence between the memory address of the first memory and the first processing unit is dynamically adjustable. For example, the correspondence between the memory address of the first memory and the first processing unit is dynamic and can be adjusted dynamically as needed.

[0080] Optionally, the memory address of the first memory may be a continuous physical memory address in the memory pool. A continuous physical memory address in the memory pool can simplify the management of the first memory. Of course, the memory address of the first memory may also be several discontinuous physical memory addresses in the memory pool.

[0081] Optionally, the memory address information of the first memory includes the starting address of the first memory and the size of the first memory. The first processing unit has an identifier, and establishing a correspondence between the memory address of the first memory and the first processing unit may be establishing a correspondence between a unique identifier of the first processing unit and the memory address information of the first memory. In some possible implementations, the control unit is further used to virtualize multiple virtual memory devices from the memory pool, wherein the physical memory corresponding to the first virtual memory device among the multiple virtual memory devices is the first memory;

[0082] The first virtual memory device is assigned to the first processing unit.

[0083] Optionally, the virtual memory device corresponds to a continuous segment of physical memory addresses in the memory pool. The virtual memory device corresponds to a continuous segment of physical memory addresses in the memory pool, which can simplify the management of the virtual memory device. Of course, the virtual memory device can also correspond to several discontinuous segments of physical memory addresses in the memory pool.

[0084] Optionally, the first virtual memory device can be assigned to the first processing unit by establishing an access control table. For example, the access control table may include information such as the identifier of the first processing unit, the identifier of the first virtual memory device, the starting address and size of the memory corresponding to the first virtual memory device, etc. The access control table may also include permission information for the first processing unit to access the first virtual memory device, attribute information of the memory to be accessed (including but not limited to information on whether it is persistent memory), etc.

[0085] In some possible implementations, the control unit is further used to: when a preset condition is met, release the correspondence between the first virtual memory device and the first processing unit, and establish a correspondence between the first virtual memory device and the second processing unit of the at least two processing units.

[0086] Optionally, the correspondence between the virtual memory device and the processing unit may be dynamically adjusted according to the requirements of the at least two processing units for memory resources.

[0087] By dynamically adjusting the correspondence between the virtual memory device and the processing unit, it is possible to flexibly adapt to the needs of different processing units for memory resources in different business scenarios, thereby improving the utilization rate of memory resources.

[0088] Optionally, the control unit is further used for:

[0089] When the preset conditions are met, the correspondence between the first memory and the first virtual memory device is released; a correspondence between the first memory and a second virtual memory device among the multiple virtual memory devices is established; and the second virtual memory device is allocated to the second processing unit among the at least two processing units. In this case, there is no need to change the correspondence between the virtual memory device and the physical memory address in the memory pool. Only the correspondence between the virtual memory device and different processing units needs to be changed, so that different processing units can access the same physical memory in different time periods. In some possible implementations, the memory sharing control device also includes a cache unit;

[0090] The cache unit is used to cache data read from the memory pool by any one of the at least two processing units, or to cache data eliminated by any one of the at least two processing units.

[0091] The cache unit can further improve the efficiency of the processing unit accessing memory data.

[0092] Optionally, the cache unit may include a first-level cache and a second-level cache. The first-level cache may have a small capacity but a higher read and write speed than the second-level cache, for example, the first-level cache may be a nanosecond-level, 100MB cache; the second-level cache may have a large capacity but a lower read and write speed than the first-level cache, for example, the second-level cache may be a 1GB DRAM. Through the first-level cache and the second-level cache, while the processor's access speed to data can be improved through the cache, the cache space can be increased, and the scope of the processor's rapid access to memory through the cache can be expanded, thereby further improving the rate at which the processor resource pool accesses memory as a whole.

[0093] In some possible implementations, the memory sharing control device further includes a prefetch engine, which is used to prefetch data that needs to be read by any one of the at least two processing units from the memory pool, and cache it in the cache unit.

[0094] Optionally, the prefetch engine can implement intelligent data anticipation through a specific algorithm or an AI algorithm to further improve the efficiency of the processing unit accessing memory data.

[0095] In some possible implementations, the memory sharing control device further includes a quality of service (Qos) engine;

[0096] The QoS engine is used to control and implement the optimized storage of data that needs to be cached by any one of the at least two processing units in the cache unit. Through the QoS engine, it is possible to achieve different cache capabilities for data accessed by different processing units in the cache unit 304. For example, a memory access request initiated by a processing unit with a high priority has an exclusive cache space in the cache unit 304, which can ensure that the data accessed by the processing unit can be cached in time, thereby ensuring the quality of such processor business processing.

[0097] In some possible implementations, the memory sharing control device further includes a compression / decompression engine;

[0098] The compression / decompression engine is used to implement compression or decompression of data related to memory access.

[0099] Optionally, the functionality of the compression / decompression engine may be turned off.

[0100] Optionally, the compression / decompression engine can compress the data written by the processing unit to the memory with a granularity of 4KB per page through a compression ratio algorithm and then write it to the memory; or when the processing unit reads the compressed data in the memory, the data to be read is decompressed and then sent to the processor. This can increase the rate of data transmission and further improve the efficiency of the processing unit accessing memory data. Optionally, the compression / decompression engine can be turned off.

[0101] Optionally, the memory sharing control device may further include a storage unit, wherein the storage unit includes software code of at least one of the QoS engine, the prefetch engine, and the compression / decompression engine. The memory sharing control device may read the code in the storage unit to implement corresponding functions.

[0102] Optionally, at least one of the QoS engine, the prefetch engine, and the compression / decompression engine may be implemented by the control logic of the memory sharing control device.

[0103] In a fourth aspect, the present application provides a method for memory sharing control, the method being applied to a computer device, the computer device comprising at least two processing units, a memory sharing control device and a memory pool, the memory pool comprising one or more memories, the method comprising:

[0104] The memory sharing control device receives a first memory access request sent by a first processing unit among at least two processing units; wherein the processing unit is a processor, a core in a processor, or a combination of cores in a processor;

[0105] The memory sharing control device allocates a first memory to the first processing unit from a memory pool, and the first memory can be accessed by a second processing unit of the at least two processing units in other time periods;

[0106] The first processing unit accesses the first memory through the memory sharing control device.

[0107] Through the method, different processing units can access at least one memory in the memory pool in different time periods, which can meet the needs of the processing units for memory resources and improve the utilization rate of memory resources.

[0108] In some possible implementations, the method further includes:

[0109] The memory sharing control device receives a first memory access request sent in the form of a serial signal by a first processing unit among the at least two processing units through a serial bus, where the first memory access request is used to access a first memory allocated to the first processing unit.

[0110] In some possible implementations, the method further includes:

[0111] The memory sharing control device converts the first memory access request into a second memory access request in the form of a parallel signal, and implements access to the first memory according to the second memory access request.

[0112] In some possible implementations, the method further includes:

[0113] The memory sharing control device establishes a correspondence between a memory address of the first memory in the memory pool and a first processing unit among the at least two processing units.

[0114] In some possible implementations, the method further includes:

[0115] The memory sharing control device virtualizes a plurality of virtual memory devices from the memory pool, wherein a physical memory corresponding to a first virtual memory device among the plurality of virtual memory devices is the first memory;

[0116] The memory sharing control device is further configured to allocate the first virtual memory device to the first processing unit.

[0117] In some possible implementations, the method further includes:

[0118] When a preset condition is met, the memory sharing control device cancels the correspondence between the first virtual memory device and the first processing unit, and establishes a correspondence between the first virtual memory device and a second processing unit of the at least two processing units.

[0119] In some possible implementations, the method further includes:

[0120] The memory sharing control device caches data read from the memory pool by any one of the at least two processing units, or caches data eliminated by any one of the at least two processing units.

[0121] In some possible implementations, the method further includes:

[0122] The memory sharing control device pre-takes out data that any one of the at least two processing units needs to read from the memory pool and caches the data.

[0123] In some possible implementations, the method further includes:

[0124] The memory sharing control device controls optimized storage of data that needs to be cached by any one of the at least two processing units in a cache storage medium.

[0125] In some possible implementations, the method further includes:

[0126] Compress or decompress data associated with memory access.

[0127] In a fifth aspect, an embodiment of the present application further provides a chip, which is used to implement the functions implemented by the memory sharing control device described in the third aspect.

[0128] In a sixth aspect, an embodiment of the present application further provides a computer-readable storage medium, comprising a program code, wherein the program code comprises instructions for executing part or all of the steps of any method provided in the fourth aspect.

[0129] In a seventh aspect, an embodiment of the present application further provides a computer program product, which, when executed on a computer, enables any method provided in the fourth aspect to be executed.

[0130] It can be understood that any of the memory sharing control devices, computer-readable storage media or computer program products provided above are used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0131] The following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0132] Figure 1A A schematic diagram of a centralized shared memory system architecture;

[0133] Figure 1B It is a schematic diagram of the structure of a distributed shared memory system;

[0134] Figure 2A A schematic diagram of a memory sharing control device 200 provided in an embodiment of the present application;

[0135] Figure 2B A schematic diagram of the connection relationship between the memory sharing control device 200 and the processor and memory;

[0136] Figure 3 A schematic diagram of the internal structure of an SRAM-type FPGA provided in an embodiment of the present application;

[0137] Figure 4 A schematic diagram of the specific structure of a Serdes interface provided in an embodiment of the present application;

[0138] Figure 5 A schematic diagram of the internal structure of a memory controller 500 provided in an embodiment of the present application;

[0139] Figure 6 A schematic diagram of the structure of the processor 210 provided in an embodiment of the present application;

[0140] Fig. 7A A schematic diagram of the structure of a memory sharing control device 300 provided in an embodiment of the present application;

[0141] Figure 7B A schematic diagram of the structure of another memory sharing control device 300 provided in an embodiment of the present application;

[0142] Figure 7C A schematic diagram of the structure of the memory sharing control device 300 provided in an embodiment of the present application including a cache unit;

[0143] Fig.7D A schematic diagram of the structure of the memory sharing control device 300 provided in an embodiment of the present application including a storage unit;

[0144] Fig. 7E A schematic diagram of a connection relationship structure between a memory sharing control device 300 and a memory pool provided in an embodiment of the present application;

[0145] Figure 7F A schematic diagram of another connection relationship structure between the memory sharing control device 300 and the memory pool provided in an embodiment of the present application;

[0146] Figure 8A-1 A schematic diagram of the structure of a computer device 80a provided in an embodiment of the present application;

[0147] Figure 8A-2 A schematic diagram of the structure of another computer device 80a provided in an embodiment of the present application;

[0148] Figure 8B-1 A schematic diagram of the structure of a computer device 80b provided in an embodiment of the present application;

[0149] Figure 8B-2 A schematic diagram of the structure of another computer device 80b provided in an embodiment of the present application;

[0150] Fig. 9A A schematic diagram of the structure of a system 901 provided in an embodiment of the present application;

[0151] Fig. 9B A schematic diagram of the structure of a system 902 provided in an embodiment of the present application;

[0152] Fig. 9C A schematic diagram of the structure of a system 903 provided in an embodiment of the present application;

[0153] Fig.10 A logical schematic diagram for implementing memory sharing provided in an embodiment of the present application;

[0154] Fig.11 A schematic diagram of the structure of a computer device 1100 provided in an embodiment of the present application;

[0155] Fig.12 A flowchart of a method for memory sharing control provided in an embodiment of the present application. DETAILED DESCRIPTION

[0156] The embodiments of the present invention are described below in conjunction with the accompanying drawings.

[0157] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "first" and "second" are used only for descriptive purposes and are not to be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features.

[0158] In the specification and claims of this application, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to those steps or modules that are clearly listed, but may include other steps or modules that are not clearly listed or inherent to these processes, methods, products or devices. The naming or numbering of steps in this application does not mean that the steps in the method flow must be executed in the time / logical sequence indicated by the naming or numbering. The named or numbered process steps can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved. The division of units in this application is a logical division. There may be other division methods when it is implemented in actual applications. For example, multiple units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, and the indirect coupling or communication connection between units can be electrical or other similar forms, which are not limited in this application. Furthermore, the units or sub-units described as separate components may or may not be physically separated, may or may not be physical units, or may be distributed in multiple circuit units, and some or all of the units may be selected according to actual needs to achieve the purpose of the present application.

[0159] It should be understood that the terms used in the description of various examples in the specification and claims of this application are only for describing specific examples and are not intended to be limiting. As used in the description of various examples and the appended claims, the singular forms "a", "an" and "the" are intended to include plural forms as well, unless the context clearly indicates otherwise.

[0160] It should also be understood that the term "and / or" used in the specification and claims of this application refers to and covers any and all possible combinations of one or more of the associated listed items. The term "and / or" is a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0161] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0162] It should also be understood that the term “comprise” (also known as “includes,” “including,” “comprises” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0163] It should also be understood that the term "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrase "if it is determined that ..." or "if [a stated condition or event] is detected" may be interpreted to mean "upon determining that ..." or "in response to determining that ..." or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0164] It should be understood that the references to "one embodiment", "an embodiment", or "a possible implementation" throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment", or "a possible implementation" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0165] First of all, some of the terms and related technologies involved in this application are explained to facilitate understanding:

[0166] Memory controller: It is an important component of the computer system that controls the memory and exchanges data between the memory and the processor. It is a bridge for communication between the central processing unit and the memory. The main function of the memory controller is to read and write the memory. It can be roughly divided into two types: traditional and integrated. In a traditional computer system, the memory controller is located in the north bridge chip of the motherboard chipset. Under this structure, any data transmission between the CPU and the memory must go through the path of "CPU-North Bridge-Memory-North Bridge-CPU". Because when the CPU reads and writes data from the memory, it must go through multiple levels of data transmission, and the delay is relatively large. The integrated memory controller is located inside the CPU, and any data transmission between the CPU and the memory must go through the path of "CPU-Memory-CPU". Compared with the traditional type, the delay of data transmission is greatly reduced.

[0167] DRAM: It is a widely used memory medium. Unlike the sequential access of disk media, DRAM allows the central processor to directly access any byte in it randomly. The storage structure of DRAM is relatively simple. Each storage structure mainly consists of a capacitor and a transistor. When the capacitor is charged, it represents the storage of data "1". Its state after discharge represents data "0".

[0168] PCM: A non-volatile memory that stores information based on phase change storage materials. Each storage unit in PCM is composed of a phase change material (such as chalcogenide glass) and two electrodes. By changing the voltage of the electrodes and the power-on time, the phase change material can be transformed between the crystalline and amorphous states. When the medium is in the crystalline state, the resistance is low; when it is in the amorphous state, the resistance is high. Therefore, data can be stored by changing the state of the phase change material. The most typical characteristic of PCM is non-volatility.

[0169] Serializer / deserializer (Serdes): Convert parallel data into serial data at the transmitting end, and then transmit it to the receiving end via the transmission line; convert serial data into parallel data at the receiving end, which can reduce the number of transmission lines and reduce system costs. Serdes is a time division multiplexing (TDM) and point-to-point communication technology, which converts the multiple low-speed parallel signals (i.e. parallel data) at the transmitting end into high-speed serial signals (i.e. serial data), and finally converts the high-speed serial signals back into low-speed parallel signals at the receiving end through the transmission medium. Serdes uses differential signal transmission to cancel out the interference noise loaded on the two differential transmission lines, which not only improves the transmission speed, but also improves the signal transmission quality. Since parallel interface technology refers to the parallel transmission of multi-bit data, and the synchronous clock is transmitted at the same time to divide the data bytes, this method is simple and easy, but the number of signal lines is large, and it is generally used for short-distance data transmission. Serial interface technology transmits byte data bit by bit and is widely used in long-distance data communication.

[0170] With the continuous improvement of integrated circuit process technology, especially the continuous progress in the design of processor architecture, the performance of processors has gradually improved. Compared with processors, the improvement speed of memory performance is much slower. As the gap accumulates, the consequence of this uneven cumulative growth is that the memory access speed lags far behind the processor computing speed, and the bottleneck formed by memory will make it difficult for high-performance processors to play their advantages. For example, for the growing high-performance computing (HPC), the access speed of memory has become a great constraint.

[0171] At the same time, multi-core processors are gradually replacing single-core processors, and the number of accesses to memory (such as off-chip memory, also known as main memory) by the parallel execution of multiple cores in the processor will also increase significantly, which leads to a corresponding increase in the bandwidth demand between the processor and the memory.

[0172] Improving the access speed and bandwidth between the processor and the memory is usually achieved by sharing memory resources.

[0173] According to whether there is a difference in the access from processor to memory, the architecture of multi-processor shared memory can be divided into centralized shared memory system and distributed shared memory system. Centralized shared memory system has the characteristics of small number of processors and single interconnection mode. The memory is centrally connected to all processors through a crossbar switch or a shared bus. Figure 1AIt is a typical centralized shared memory system architecture. Because all processors have equal or symmetrical access to memory, this type of architecture is also called unified memory architecture (UMA) or symmetric multiprocessing (SMP).

[0174] The centralized shared memory system faces the problem of being unable to provide the required memory access bandwidth when the number of processors reaches a certain scale due to its single memory system, which becomes a bottleneck restricting performance. The distributed shared memory system effectively solves this problem. Figure 1B Figure 1 is a schematic diagram of the structure of a distributed shared memory system. Figure 1B As shown, in this system, the memory is globally shared and uniformly addressed and distributed on each processor. The address space of the memory is divided into several parts, each managed by a processor. For example, if processor 1 wants to access the memory address space managed by this processor, there is no need to cross processors or interconnection buses. If processor 1 accesses the memory space managed by other processors, for example, to access the memory address space managed by processor N, it is necessary to go through the interconnection bus. Distributed shared memory systems are also called non-uniform memory access architecture (NUMA) systems.

[0175] In a NUMA system, the address space of shared memory is managed by each processor. Due to the lack of a unified memory management mechanism, when a processor needs to use the memory space managed by other processors, the sharing of memory resources is not flexible enough, resulting in low memory resource utilization. In addition, when a processor accesses the memory address space not managed by the processor itself, the delay is often large because it passes through the interconnect bus.

[0176] The embodiments of the present application provide a device, chip, computer device, system and method for implementing memory sharing control, and provide a new memory access architecture, which establishes an access bridge between the processor and the shared memory pool (which may also be referred to as the memory pool in this embodiment) through a memory sharing control device, thereby improving the utilization rate of memory resources.

[0177] Figure 2A FIG. 2 is a schematic diagram of a memory sharing control device 200 provided in an embodiment of the present application. Figure 2A As shown, the memory sharing control device 200 includes: a control unit 201 , a processor interface 202 and a memory interface 203 .

[0178] The memory sharing control device 200 may be a chip located between a processor (CPU or a core in a CPU) and a memory (also called main memory) in a computer device, for example, an FPGA chip.

[0179] Figure 2B FIG. 2 is a schematic diagram showing the connection relationship between the memory sharing control device 200 and the processor and memory. Figure 2B The processor 210 is connected to the memory sharing control device 200 via the processor interface 202, and the memory 220 is connected to the memory sharing control device 200 via the memory interface 203. The processor 210 may be a CPU or a CPU including multiple cores; the memory 220 includes but is not limited to DRAM, PCM, flash memory, SCM, SRAM, PROM, EPROM, STT-RAM or RRAM, etc. SCM is a composite storage technology that combines the characteristics of traditional storage devices and memory. Storage-level memory can provide faster read and write speeds than hard disks, but its computing speed is slower than DRAM and its cost is cheaper than DRAM. In the embodiment of the present application, the memory 220 may also include DIMM or SSD.

[0180] The processor interface 202 is an interface connecting the memory sharing control device 200 and the processor 210. The interface can receive a serial signal sent by the processor and convert the serial signal into a parallel signal. Based on the processor interface 202, the memory sharing control device 200 and the processor 210 can be connected via a serial bus. The serial bus has the characteristics of high bandwidth and low latency, and can ensure the efficiency of data transmission between the processor 210 and the memory sharing control device 200. Exemplarily, the processor interface 202 can be a Serdes interface based on low latency. As the Serdes interface of the processor interface 202, it is connected to the processor via a serial bus and can realize the conversion between serial signals and parallel signals based on serial-to-parallel conversion logic. The serial bus can be a bus with memory semantics. The bus with memory semantics includes, but is not limited to, a bus interconnected based on QPI, PCIe, HCCS or CXL protocols.

[0181] In a specific implementation, the processor 210 can be connected to the serial bus through a Serdes interface, and connected to the processor interface 202 (e.g., a Serdes interface) of the memory sharing control device 200 through the serial bus. The memory access request initiated by the processor 210 is a memory access request in the form of a parallel signal. Through the Serdes interface in the processor 210, the memory access request in the form of a parallel signal is converted into a memory access request in the form of a serial signal, and sent through the serial bus. After the processor interface 202 receives the memory access request in the form of a serial signal from the processor 210 through the serial bus, the memory access request in the form of a serial signal is converted into a memory access request in the form of a parallel signal, and the converted memory access request is sent to the control unit 301. The control unit 301 can access the corresponding memory based on the memory access request in the form of a parallel signal. For example, the corresponding memory can be accessed in parallel. In the embodiment of the present application, a parallel signal may refer to a signal that transmits multiple bits at a time, and a serial signal form may refer to a signal that transmits one bit at a time.

[0182] Similarly, when the memory sharing control device 200 returns a response message of the memory access request to the processor 210, the parallel signal form of the response message is converted into a serial signal form through the processor interface 202 (for example, a Serdes interface), and the serial signal form of the response message is sent to the processor 210 through the serial bus. After receiving the serial signal form of the response message, the processor 210 converts the serial signal form of the response message into a parallel signal and performs subsequent processing.

[0183] The memory sharing control device 200 can access the corresponding memory in the memory 220 through the memory interface 203 as a memory controller. For example, when the memory 220 is a shared memory pool composed of DRAM, the memory interface 203 is a DDR controller with a DRAM control function, which is used to implement the interface control of the DRAM storage medium; when the memory 220 is a shared memory pool composed of PCM, the memory interface 203 is a memory controller with a PCM control function, which is used to implement the interface control of the PCM storage medium.

[0184] It should be noted that Figure 2BThe processor 210 shown in the figure is only an example, and the processor connected to the memory sharing control device 200 may also be a multi-core processor or a processor resource pool. The processor resource pool includes at least two processing units, and each processing unit may be a processor, a core in a processor, or a combination of cores in a processor. The processing units in the processor resource pool may be a combination of different cores in the same processor, or a combination of different cores in different processors. When the processor executes different tasks, multiple cores are required to execute computing tasks in parallel, or cores in different processors are required to execute computing tasks in parallel. When these cores execute computing tasks in parallel, the combination of these cores can be used as a processing unit to access the same block of memory in the shared memory pool.

[0185] Figure 2B The memory 220 shown is only an example, and the memory 220 connected to the memory sharing control device 200 may also be a shared memory pool composed of multiple memories. At least one memory in the shared memory pool can be accessed by different processing units at different time periods. The memory in the shared memory pool includes but is not limited to DRAM, PCM, flash memory, STT-RAM or RRAM. Similarly, the memory in the shared memory pool may be memory on a computer device or memory on different computer devices. It is understandable that the computer device may be a computer (desktop computer or portable computer) or a server and other devices that require a processor to access memory, and may also include terminal devices such as mobile phone terminals. The embodiments of the present application do not limit the form of specific devices.

[0186] The control unit 201 is used to implement memory access control according to a memory access request, including but not limited to dividing the memory resources in the shared memory pool into multiple independent memory resources, and respectively allocating (for example, can be allocated on demand) to each processing unit in the processor resource pool. The independent memory resources divided by the control unit 201 can be a memory storage space corresponding to a physical address in the shared memory pool. The physical address of the memory resource can be continuous or discontinuous. Exemplarily, the memory sharing control device 200 can virtualize multiple virtual memory devices based on the shared memory pool, and each virtual memory device corresponds to or manages a part of the memory resources. The control unit 201 allocates the multiple independent memory resources divided in the shared memory pool to each processing unit in the processor resource pool by establishing a corresponding relationship between different virtual memory devices and processing units.

[0187] However, the correspondence between the processing unit and the memory resource is not fixed, and the correspondence can be adjusted when certain conditions are met. That is, the correspondence between the processing unit and the memory resource can be adjusted dynamically. The control unit 201 adjusts the correspondence between the processing unit and the memory resource by receiving a control instruction sent by a driver in the operating system and adjusting the correspondence according to the control instruction. The control instruction includes information for deleting, changing or adding the correspondence.

[0188] Exemplarily, the computer device 20 (not shown in the figure) includes Figure 2B The processor 210, memory sharing device 200 and memory 220 shown. The processor 210 runs the operating system that the computer device 20 needs to run to control the computer device 20. Assume that the computer device 20 is a server that provides cloud services, and there are 8 cores in the processor 210, where core A provides cloud service business for user A, and core B provides cloud service business for user B. Based on the business needs of user A and user B, the operating system of the computer device allocates memory resource A in memory 220 as a memory access resource to core A and allocates memory resource B in memory 220 as a memory access resource to core B. The operating system can send control instructions for establishing a corresponding relationship between core A and memory resource A and a corresponding relationship between core B and memory resource B to the memory sharing control device 200. The memory sharing control device 200 establishes a corresponding relationship between core A and memory resource A and a corresponding relationship between core B and memory resource B according to the control instructions of the operating system. In this way, when core A initiates a memory access request, the memory sharing control device 200 can determine the memory resources that core A can access (i.e., memory resource A) based on the information carried in the access request, and realize the access of core A to memory resource A. When user A needs to take a break due to business needs or time zone and no longer uses cloud services, resulting in a reduced demand for memory resources, and user B needs to use more cloud services due to business needs or time zone and needs more memory resources, the operating system of the computer device 20 can send a control instruction to release the correspondence between core A and memory resource A and allocate memory resource A to core B for use based on the changes in business needs of user A and user B. The operating system, which can specifically be a driver in the operating system, can send a control instruction to delete the correspondence between core A and memory resource A and establish the correspondence between core B and memory resource A. The memory sharing control device 200 reconfigures the correspondence between memory resource A based on the control instruction sent by the driver in the operating system, deletes the correspondence between core A and memory resource A, and establishes the correspondence between core B and memory resource A. In this way, memory resource A can be used as the memory of core A and core B in different time periods, meeting the needs of different cores for different services and improving the utilization of memory resources.

[0189] The driver of the operating system may send the control instruction to the memory sharing control device 200 through a dedicated or specific channel. Specifically, when the processor running the operating system is in a privileged mode, the driver in the operating system may send the control instruction to the memory sharing control device 200 through a dedicated or specific channel. In this way, the driver in the operating system may send the control instruction to delete, modify or add the corresponding relationship through a dedicated channel.

[0190] The above-mentioned memory sharing control device 200 can be connected to the processor 210 through an interface that supports serial-to-parallel conversion (such as a Serdes interface), and the processor 210 can communicate with the memory sharing control device 200 through a serial bus. Based on the high bandwidth and low latency characteristics of the serial bus, even if the communication distance between the processor 210 and the memory sharing control device 200 is far, the access rate of the processor 210 to the shared memory pool can be guaranteed.

[0191] Furthermore, the control unit 201 may also be used to implement data cache control, data compression control, or data priority control, etc., thereby further improving the efficiency and quality of the processor accessing the memory.

[0192] The following uses FPGA as an example of a chip for implementing the memory sharing control device 200 to exemplify the implementation method of the memory sharing control device 200 provided in the embodiment of the present application.

[0193] As a programmable logic device, FPGA can be divided into three categories according to different programming principles: SRAM type, anti-fuse type and FLASH type based on static random access memory (SRAM). Thanks to the erasability and volatility of SRAM, FPGA based on SRAM can be programmed repeatedly, but the configuration data will be lost when the power is off. Anti-fuse type FPGA can only be programmed once, and the circuit function is fixed after programming and cannot be modified again, so the circuit function will not change even when there is no power supply.

[0194] The following uses an SRAM-based FPGA as an example to illustrate the internal structure of the FPGA. Figure 3 The following is a schematic diagram of the internal structure of an SRAM-type FPGA. Figure 3 As shown in the figure, FAGA includes at least the following parts:

[0195] Configurable logic block (CLB): It mainly includes programmable resources such as lookup table (LUT), multiplexer, carry chain, D flip-flop, etc., which are used to realize different logic functions and are the core of the entire FPGA chip.

[0196] Programmable input / output block (IOB): Provides an interface between the FPGA and the external circuit. When the electrical characteristics inside and outside the FPGA are different, it provides appropriate drive for the input / output signal to achieve matching. Through electronic design automation (EDA) development software, different electrical standards and physical information can be configured as required, such as adjusting the size of the drive current and changing the resistance of the pull-up resistor and the pull-down resistor. Generally, several IOBs are divided into a group (bank). The number of IOBs contained in each group in different series of FPGA chips will vary.

[0197] Embedded block random access memory (BRAM): used to store large amounts of data. To meet different data read and write requirements, it can be configured as single-port RAM, dual-port RAM, content addressable memory (CAM), and first in first out (FIFO) and other common storage structures. The storage bit width and depth can be changed according to design requirements. BRAM can expand the application scope of FPGA and improve its flexibility.

[0198] Switch matrix (SM): It is an important part of the interconnection resource (IR) inside FPGA. It is mainly distributed on the left side of each resource module. The switch matrix on the left side of different modules is very similar but also has differences. It plays the role of connecting the resources of each module. Another part of the interconnection resource inside FPGA is the interconnection metal wire (Wire Segment). The interconnection metal wire and SM work together to connect the resources of the entire chip.

[0199] Figure 3 Only several main components in the FPGA chip related to the implementation of the memory sharing control device 200 in the embodiment of the present application are shown. Figure 3In addition to the components shown, the FPGA may also include other components or embedded functional units, for example, a digital signal processor (DSP), a phase locked loop (PLL) or a multiplier (MUL).

[0200] Above Figure 2A or Figure 2B The control unit 201 in the embodiment can be Figure 3 CLB implementation in. That is, the shared memory pool connected to the memory sharing control device 200 is controlled by CLB, for example, the memory resources in the shared memory pool are divided into multiple blocks, and one or more blocks of memory resources are allocated to a processing unit; or multiple virtual memory devices are virtualized based on the memory resources in the shared memory pool, each virtual memory device corresponds to a physical address space in the shared memory pool, and one or more virtual memory devices are allocated to a processing unit, and a corresponding relationship table between the allocated virtual memory devices and the corresponding processing units is established.

[0201] Above Figure 2A or Figure 2B The processor interface 202 can be Figure 3 The IOB in the implementation, that is, the interface with serial-to-parallel conversion function can be implemented through the above IOB, for example, the Serdes interface can be implemented through the IOB.

[0202] Figure 4 Figure 1 is a schematic diagram of the specific structure of a Serdes interface. Figure 4 As shown in the figure, the Serdes interface is mainly composed of a transmitting channel and a receiving channel. In the transmitting channel, the input parallel data is encoded by the encoder, and then converted into a serial signal by the parallel-to-serial module, and then driven by the transmitter (Tx) to output the serial data. In the receiving channel, the receiver and the clock recovery circuit recover the sampling clock and data, and then the serial-to-parallel module finds the byte boundary and converts it into parallel data, and finally the decoder completes the recovery of the final original parallel data.

[0203] The encoder and decoder complete the encoding and decoding functions of the data to ensure the DC balance of the serial data stream and as many data transitions as possible. Exemplary, the encoding and decoding schemes of 8b / 10b and scrambling / descrambling can be adopted. The parallel-to-serial module and the serial-to-parallel module are used to complete the conversion of data between parallel form and serial form. The clock generation circuit generates the conversion clock for the parallel-to-serial circuit, which is generally implemented by a phase-locked loop. The clock generation circuit and the clock recovery circuit provide conversion control signals for the serial-to-parallel circuit, which are generally implemented by a phase-locked loop, but can also be implemented by a phase interpolator, etc.

[0204] The above is just an exemplary description of a Serdes interface implementation method, that is, based on Figure 3 IOB implementation in Figure 4 Of course, the function of the Serdes interface can also be implemented based on other hardware components, such as other special hardware components in the FPGA, and the embodiment of the present application does not limit the specific implementation form of the Serdes interface.

[0205] Above Figure 2A or Figure 2B The memory interface 203 in the embodiment can be implemented based on the above IOB or other special circuits. For example, when the memory interface 203 is implemented by a DDR controller, its logical structure can be as follows: Figure 5 shown.

[0206] Figure 5 FIG. 5 is a schematic diagram of the internal structure of a memory controller 500. Figure 5 , the memory controller 500 includes:

[0207] Receiving module 501: used to record access request information. An access request mainly includes the type of request and the address of the request. Based on these two pieces of information, it can be known which memory address the access request is for and what operation it is for. The access request information recorded by the receiving module 501 may include the type of request and the address of the request. In addition, the information recorded by the receiving module 501 may also include some auxiliary information for estimating system performance, such as the arrival time and completion time of the access request.

[0208] Control module 502: used to perform memory initialization, power-off, etc. At the same time, control module 502 can also control the depth of the memory queue used to implement memory access control, determine whether the memory queue is empty or full, determine whether the memory request is completed, decide which arbitration scheme to use, which scheduling method to use, etc.

[0209] Address mapping module 503: used to implement the conversion between the address of the access request and the address recognizable by the memory. For example, for a DDR4 memory system, its memory address is divided into six parts: Channel, Rank, Bankgroup, Bank, Row, and Column. Different address mapping methods have different access efficiencies.

[0210] Refresh module 504: used to implement timed refresh of memory. DRAM is composed of many repeated units (cells), each cell consists of a transistor (Mosfet) and a capacitor. The capacitor is used to store charge and determines whether the logic state of the DRAM unit is 1 or 0. However, due to the leakage of capacitors, the charge will be lost every once in a while, resulting in data loss, so it is necessary to refresh it regularly through the refresh module 504.

[0211] Scheduling module 505: used to schedule access requests to different queues based on the type of request according to the access request sent by the address mapping module 503. For example, an access request can be scheduled to a queue with a high priority, and a request with the highest priority is selected from the queue with the highest priority according to a preset scheduling policy to complete a scheduling. The queue is a queue for implementing memory access control; the scheduling policy can be determined according to the time sequence of the arrival of the requests, and the earlier the request arrives, the higher the priority; or the scheduling policy can be determined according to which request is ready first, etc.

[0212] It should be noted that Figure 5 Only the components or functional modules of the memory controller 500 are shown. In a specific implementation, the memory controller 500 may also include other components or functional modules. For example, the memory controller 500 may also include a Vera engine for multi-threaded computing or a direct memory access (DMA) module for direct memory access, etc., which will not be described in detail.

[0213] The above is a description of an implementation of the memory sharing control device 200 using FPGA as an example. In specific implementation, the memory sharing control device 200 can also be implemented by other chips or other devices that can implement similar chip functions. For example, the memory sharing control device 200 can also be implemented by ASIC. The ASIC chip has its circuit functions defined at the beginning of the design, and has the characteristics of high chip integration, easy mass production, low single chip cost and small size. The embodiment of the present application does not limit the specific hardware implementation of the memory sharing control device 200.

[0214] In the embodiment of the present application, the processor connected to the memory sharing control device 200 can be any processor that implements the processor function. Figure 6 A schematic diagram of the structure of the processor 210 provided in the embodiment of the present application. Figure 6 As shown, the processor 210 includes a core 601, a memory 602, and peripherals and interfaces 603, etc. The core 601 may include more than one core to implement the functions of the processor 600. Figure 6Two cores (core 1 and core 2) are used as an example for explanation, but this does not limit the number of cores in the processor 600. The processor 600 may also include 4, 8 or 16 cores, etc. The memory 602 includes a cache or SRAM, which is used to implement a cache for reading and writing data by core 1 or core 2. The peripherals and interface 603 include a Serdes interface 6031, a memory controller 6032, an input and output interface, a power supply and a clock, etc. Among them, the Serdes interface 6031 is an interface connecting the processor 210 to the serial bus. The memory access request in the form of a parallel signal initiated by the processor 210 is converted into a serial signal by the Serdes interface 6031 and sent to the memory sharing control device 200 through the serial bus. The memory controller 6032 can be connected to the memory sharing control device 200. Figure 5 The memory controller shown has similar functions to a memory controller. When the processor 210 has a local memory controlled by it, the processor 210 can implement access control to the local memory through the memory controller 6031.

[0215] Understandably, Figure 6 The structural diagram only exemplarily describes one implementation method of the processor. The embodiment of the present application does not limit the specific structure or form of the processor connected to the memory sharing control device 200. As long as the processor can realize certain computing or control functions, it is within the scope disclosed in the embodiment of the present application.

[0216] The specific implementation method of the memory sharing control device provided in the embodiment of the present application is further described below.

[0217] Fig. 7A Schematic diagram of the structure of the memory sharing control device 300 provided in the embodiment of the present application. Fig. 7A As shown, the memory sharing control device 300 includes a control unit 301, a processor interface 302 and a memory interface 303. For the specific implementation of the memory sharing control device 300 shown in FIG. 7 , reference may be made to the above Figure 2A or Figure 2B The implementation method of the memory sharing control device 200 is implemented, and reference can also be made to Figure 3 Specifically, the control unit 301 can refer to the above Figure 2A or Figure 2B The control unit 201 in the embodiment can be realized by Figure 3 The processor interface 302 can refer to the above Figure 4 The Serdes interface shown in FIG. 3 is implemented, and the memory interface 303 can refer to the above Figure 5 The memory controller shown in the figure is used to implement the above-mentioned function and will not be described in detail here.

[0218] Specifically, Fig. 7AThe control unit 301 in the embodiment can be configured to realize the following functions:

[0219] 1. Based on the memory resources connected to the memory sharing control device 300, multiple virtual memory devices are virtualized;

[0220] The memory resources connected to the memory sharing control device 300 constitute a shared memory pool. The control unit 301 can uniformly address the memory resources in the shared memory pool, and divide the memory physical address space after the uniform addressing into a plurality of address segments, each address segment corresponding to a virtual memory device. The address space sizes corresponding to the divided address segments can be the same or different. That is, the size of each virtual memory device can be the same or different.

[0221] The virtual memory device is not an actual device, but a control unit 301 is used to identify a memory address space in the shared memory pool. This address space is allocated to a processing unit (which can be a processor, a core in a processor, a combination of different cores in the same processor, or a combination of cores in different processors) for memory access (such as reading and writing data), so it is called a virtual memory device. Exemplarily, each virtual memory device corresponds to a memory area with continuous physical addresses. Optionally, a virtual memory device can also correspond to a non-continuous physical address space.

[0222] The control unit 301 may allocate an identifier to each virtual memory device for identifying different virtual memory devices. Fig. 7A Two virtual memory devices are shown as an example: virtual memory device a and virtual memory device b. Virtual memory device a and virtual memory device b correspond to different memory address spaces in the shared memory pool. 2. Allocate the virtualized multiple virtual memory devices to the processing unit connected to the memory sharing control device 300;

[0223] The control unit 301 can allocate a virtual memory device to a processing unit. To avoid possible complex logic or possible traffic storms, the control unit 301 avoids allocating a virtual memory device to multiple processors, or avoids allocating a virtual memory device to multiple cores in a processor when allocating virtual memory devices. However, for some businesses that require different cores in the same processor to perform computing tasks in parallel, or that require different cores in different processors to perform computing tasks in parallel, the combination of allocating the memory corresponding to a virtual memory device to the cores through complex logic can improve the efficiency of business processing during parallel computing.

[0224] The control unit 301 may allocate the virtual memory device in a manner that establishes a correspondence between the identifier of the virtual memory device and the identifier of the processing unit. Exemplarily, the control unit 301 establishes a correspondence between the virtual memory device and different processing units based on the number of processing units connected to the memory sharing control device 300. Optionally, the control unit 301 may also establish a correspondence between the processing unit and the virtual memory device, and establish a correspondence between the virtual memory device and different memory resources, thereby establishing a correspondence between the processing unit and different memory resources.

[0225] 3. Record the correspondence between virtual memory devices and assigned processing units;

[0226] In a specific implementation, the control unit 301 may maintain an access control table (also referred to as a mapping table) for recording the correspondence between the virtual memory device and the processing unit. An implementation of the access control table may be shown in Table 1:

[0227]

[0228] Table 1

[0229] In Table 1, Device_ID represents the identifier of the virtual memory device, Address represents the starting address of the physical memory address managed or accessible by the virtual memory device, Size represents the memory size managed or accessible by the virtual memory device, Access Attribute represents the access method, whether it is a read operation or a write operation; Resource ID represents the identifier of the processing unit.

[0230] The Resource ID in Table 1 usually corresponds to a processing unit. Since a processing unit can be a processor, a core in a processor, a combination of multiple cores in a processor, or a combination of multiple cores in different processors, the control unit 301 can also maintain a correspondence table of Resource ID and core combinations to clarify the information of the core or processor corresponding to each processing unit. For example, Table 2 exemplarily shows the correspondence between Resource ID and core:

[0231]

[0232]

[0233] Table 2

[0234] Since in a computer device, the cores in different processors have a unified identification, the core IDs in Table 2 can distinguish different cores in different processors. It can be understood that Table 2 only exemplarily shows the correspondence between the Resource ID of the processing unit and the corresponding core or the corresponding processor. The embodiment of the present application does not limit the way in which the memory sharing control device 300 determines the correspondence between the Resource ID and the corresponding core or the corresponding processor.

[0235] In another implementation, if the memory connected to the memory sharing control device 300 includes DRAM and PCM, due to the non-persistent nature of the DRAM storage medium and the persistent nature of the PCM storage medium, the access control table maintained by the control unit 301 may also include whether each virtual memory device is a persistent virtual memory device or a non-persistent virtual memory device.

[0236] Table 3 is another implementation of the access control table provided in the embodiment of the present application:

[0237]

[0238] Table 3

[0239] In Table 3, Persistent Attr ibute represents the persistence attribute of the virtual memory device, that is, it represents whether the memory address space corresponding to the virtual memory device is persistent or non-persistent.

[0240] Optionally, the access control table maintained by the control unit 301 may also include other information for implementing further memory access control. Exemplarily, the access control table may also include permission information for the processing unit to access the virtual memory device, including but not limited to read-only access or write-only access.

[0241] 4. When receiving a memory access request sent by a processing unit, based on the correspondence between the virtual memory devices and the processing units recorded in the access control table, determine the virtual memory device corresponding to the processing unit that sent the memory access request, and access the corresponding memory based on the determined virtual memory device;

[0242] For example, a memory access request contains information such as the RESOURCE_ID, address information, and access attributes of the processing unit. The RESOURCE_ID is the ID of the core combination, the address information indicates the address information of the memory to be accessed, and the access attribute indicates whether the memory access request is a read request or a write request. The control unit 301 can query the access control table (such as Table 1) according to the RESOURCE_ID to determine at least one virtual memory device corresponding to the RESOURCE_ID. For example, the determined virtual memory device is Fig. 7A The virtual memory device a shown in , according to Table 2, can be determined that the core corresponding to the RESOURCE_ID can access the memory resources that the virtual memory device a can manage and access. The control unit 301 controls the memory access request to implement memory access control on the memory address space that the virtual memory device a can manage or access, in combination with the address information and access attributes in the access request. Optionally, when permission information is recorded in the access control table, the control unit 301 can also control the access of the corresponding processing unit to the memory based on the permission information recorded in the access control table.

[0243] It should be noted that the control unit 301 controls the access to the virtual memory device by implementing memory access control for the physical address space of the memory resource corresponding to the virtual memory device.

[0244] 5. Dynamically adjust the correspondence between virtual memory devices and processing units.

[0245] The control unit 301 can realize dynamic adjustment of the virtual memory device by changing the correspondence between the processing unit and the virtual memory device in the access control table based on preset conditions (e.g., different needs of different processing units for memory resources). For example, deleting the correspondence between a virtual memory device and a processing unit means releasing the memory resources corresponding to the virtual memory device, and the released memory resources can be allocated to other processing units for memory access. Figure 2B The control unit 201 dynamically adjusts the corresponding relationship to achieve deletion, modification or addition of the corresponding relationship.

[0246] In an optional implementation, the corresponding relationship between the processing unit and the memory resources in the shared memory pool can also be modulated by changing the memory resources corresponding to each virtual memory device. For example, when a service processed by a processing unit is in a dormant state and does not need to occupy too much memory, the memory resources managed by the virtual memory device corresponding to the processing unit can be allocated to the virtual memory device corresponding to another processing unit, thereby achieving the purpose of providing the same memory resources for different processing units to access in different time periods.

[0247] Exemplarily, when the memory sharing control device 300 passes Figure 3 When the FPGA chip shown is implemented, it can be configured Figure 3 The CLB in the control unit 301 is used to implement the functions of the above control unit 301.

[0248] It should be noted that the control unit 301 virtualizes multiple virtual memory devices, allocates the multiple virtual memory devices to the processing unit connected to the memory sharing control device 300, and dynamically adjusts the correspondence between the virtual memory devices and the processing unit, which can be achieved according to the control instructions sent by the driver of the operating system through a dedicated channel. That is, the driver in the operating system of the computer device where the memory sharing control device 300 is located sends instructions for virtualizing multiple virtual memory devices, allocating virtual memory devices to the processing unit, and dynamically adjusting the correspondence between the virtual memory devices and the processing unit to the memory sharing control device 300 through a dedicated channel, and the control unit 301 implements the corresponding functions according to the received control instructions.

[0249] The above-mentioned memory sharing control device 300 is connected to the processor through a serial bus based on a serial-to-parallel conversion interface (such as a Serdes interface), which can achieve long-distance transmission between the memory sharing control device 300 and the processor while ensuring the speed of the processor accessing the memory, so that the processor can quickly access the memory resources in the shared memory pool. Since the memory resources in the shared memory pool can be allocated to different processing units for memory access at different times, the utilization rate of the memory resources is improved.

[0250] For example, the control unit 301 in the memory sharing control device 300 can dynamically adjust the correspondence between the virtual memory device and the processing unit. When the demand for memory space of a certain processing unit increases, the unoccupied virtual memory device, or the virtual memory device that has been allocated to other processing units but is temporarily idle, is adjusted to the processing unit with increased memory demand, that is, the correspondence between these idle virtual memory devices and the processing unit with increased demand is established. In this way, the existing memory resources can be effectively used to meet the different business needs of the processing unit, which not only ensures the demand for memory space of the processing unit in different business scenarios, but also improves the utilization rate of memory resources.

[0251] Figure 7B A schematic diagram of the structure of another memory sharing control device 300 provided in an embodiment of the present application. Figure 7B The memory sharing control device 300 shown in FIG. Fig. 7A The invention also includes a cache unit 304.

[0252] The cache unit 304 may be a random access memory (RAM) used to cache data that the processing unit needs to access when accessing memory. For example, the data that the processing unit needs to read is pre-read from the shared memory pool and cached in the cache unit 304, so that the processing unit can quickly access the data, which can further improve the rate at which the processing unit reads data. The cache unit 304 can also cache data eliminated by the processing unit, such as cacheline data eliminated by the processing unit. Through the cache unit 304, the speed at which the processing unit accesses memory data can be further improved.

[0253] In an optional implementation, the cache unit 304 may include a first-level cache and a second-level cache. Figure 7C As shown, the cache unit 304 in the memory sharing control device 300 further includes a first-level cache 3041 and a second-level cache 3042, wherein:

[0254] The first-level cache 3041 may be a cache of small capacity (eg, 100MB level), or may be a nanosecond-level SRAM medium, which caches cacheline data eliminated from the processing unit.

[0255] The secondary cache 3042 can be a cache with a large capacity (for example, a capacity of 1GB level), and can be a DRAM medium. The secondary cache 3042 can cache the cacheline data eliminated from the primary cache at a granularity of 4KB per page, as well as the data pre-fetched from the memory 220 (for example, DDR or PCM medium). The cacheline data is the data in the cache. For example, the cache in the cache unit 304 is composed of three parts: valid bit, tag bit, and data bit. Each row contains these three types of data, and one row of data constitutes a cacheline. When the processing unit initiates a memory access request, the data in the memory access request is matched with the corresponding bit of the cache to read the cacheline data in the cache or write the data into the cache.

[0256] Exemplarily, when the memory sharing control device 300 passes Figure 3 When the FPGA chip shown is implemented, it can be configured Figure 3 The BRAM in the cache unit 304 can realize the function of the cache unit 304, or by configuring Figure 3 The BRAM in the cache is used to realize the functions of the above-mentioned first-level cache 3041 and second-level cache 3042.

[0257] The cache unit 304 further includes a first-level cache 3041 and a second-level cache 3042, which can increase the cache space while improving the processing unit's access to data through the cache, expand the scope of the processing unit's rapid access to the memory through the cache, and further improve the rate at which the processor resource pool accesses the memory as a whole.

[0258] Fig.7D is a schematic diagram of the structure of another memory sharing control device 300 provided in an embodiment of the present application. Fig.7D As shown, the memory sharing control device 300 also includes a storage unit 305. The storage unit 305 can be a volatile memory, such as a RAM; it can also include a non-volatile memory, such as a read-only memory (ROM), a flash memory, etc. The storage unit 305 stores programs or instructions readable by the control unit 301, such as a program code containing at least one process or a program code of at least one thread. The control unit 301 implements corresponding control by executing the program code in the storage unit 202.

[0259] The program code stored in the storage unit 305 may include at least one of a QoS engine 306 , a pre-fetch engine 307 , and a compression / decompression engine 308 . Fig.7D Just for the convenience of showing the functions related to the QoS engine 306, the pre-fetch engine 307, and the compression / decompression engine 308, these engines are shown outside the control unit 301 and the storage unit 305, which does not mean that these engines are located outside the control unit 301 and the storage unit 305. In specific implementation, these engines are the control unit 301 executing the corresponding code stored in the storage unit 305 to realize the corresponding functions.

[0260] The QoS engine 306 is used to control the storage area of ​​the data to be accessed by the processing unit in the cache unit 304 (the first-level cache 3041 or the second-level cache 3042) according to the RESOURCE_ID in the memory access request, so as to achieve different cache capabilities of the data accessed by different processing units in the cache unit 304. For example, the memory access request initiated by the processing unit with a high priority has an exclusive cache space in the cache unit 304, which can ensure that the data accessed by the processing unit can be cached in time, thereby ensuring the quality of business processing of such processing units.

[0261] The prefetch engine 307 is used to implement prefetching of data in the memory based on a specific algorithm, and to implement prefetching of data to be read by the processing unit. Different prefetching methods affect the accuracy of prefetching and the efficiency of memory access. By implementing higher-precision prefetching based on a specific algorithm by the prefetch engine 307, the hit rate of the processing unit when accessing memory data can be further improved. Exemplarily, the prefetching implemented by the prefetch engine 307 includes but is not limited to: prefetching cachelines from the second-level cache to the first-level cache, or prefetching data from an external DRAM or PCM to the cache, etc.

[0262] The compression / decompression engine 308 is used to implement compression or decompression of memory access data. For example, the data written to the memory by the processing unit is compressed with a granularity of 4KB per page through a compression ratio algorithm and then written to the memory; or when the processing unit reads compressed data in the memory, the data to be read is decompressed and then sent to the processing unit. Optionally, the compression / decompression engine can be turned off. In this way, the compression / decompression engine 308 is disabled, and the processing unit no longer compresses or decompresses the data when accessing the memory.

[0263] The above description is that the QoS engine 306, the pre-fetch engine 307, and the compression / decompression engine 308 are stored in the storage unit 305 as software modules, and the control unit 301 reads the corresponding code in the storage unit to implement the corresponding functions. As an optional implementation, at least one of the QoS engine 306, the pre-fetch engine 307, and the compression / decompression engine 308 can also be directly configured in the control unit 301 and implemented by the control logic of the control unit 301. In this way, the control unit 301 can implement the relevant functions by executing the relevant control logic without reading the code in the storage unit 305. Exemplarily, when the memory sharing control device 300 is implemented by Figure 3 When the FPGA chip shown is implemented, it can be configured Figure 3 The CLB in the Qos engine 306 is used to implement the functions related to the prefetch engine 307 and the compression / decompression engine 308.

[0264] It can be understood that part of the QoS engine 306, the pre-fetch engine 307, and the compression / decompression engine 308 can be directly implemented by the control unit 301, and part of them are stored in the storage unit 305, and the control unit 301 performs corresponding functions by reading the software code in the storage unit 305. For example, the QoS engine 306 and the pre-fetch engine 307 are directly implemented by the control logic of the control unit 301, and the compression / decompression engine 308 is a software code stored in the storage unit 305. The control unit 301 reads the software code of the compression / decompression engine 308 in the storage unit 305 to implement the function of the compression / decompression engine 308.

[0265] Exemplarily, when the memory sharing control device 300 passes Figure 3 When the FPGA chip shown is implemented, it can be configured Figure 3 The BRAM in the storage unit 305 is used to realize the function of the above storage unit 305.

[0266] The following takes the memory resources connected to the memory sharing control device 300 including DRAM and PCM as an example to exemplarily illustrate the implementation method of the memory sharing control device 300 during memory access.

[0267] Fig. 7E and Figure 7F Two implementations of DRAM and PCM as the storage medium for the shared memory pool are shown. Fig. 7E In the implementation shown, DRAM and PCM are different types of memory contained in the shared memory pool, and there is no distinction between upper and lower levels. Fig. 7E The shared memory pool shown does not distinguish between different types of memory. Fig. 7E In the embodiment, the DDR controller 3031 controls the storage medium of the DRAM, and the PCM controller 3032 controls the storage medium of the PCM. The control unit 301 can access the DRAM through the DDR controller 3031 and access the PCM through the PCM controller 3032. Figure 7F In the implementation shown, since DRAM is faster and has higher performance than PCM, DRAM can be used as the first-level memory, and data with high access frequency can be preferentially stored in DRAM. PCM is used as the second-level memory to store data with low access frequency or data eliminated from DRAM. Figure 7F In the embodiment, the memory controller 303 includes two parts: PCM control logic and DDR control logic. The memory access request received by the control unit 301 will access the PCM storage medium through the PCM control logic. Based on the preset algorithm or strategy, when it is predicted that the data is about to be accessed, the data can be cached in the DRAM in advance, so that the subsequent access request of the control unit 301 can hit the corresponding data from the DRAM through the DDR control logic, thereby further improving the efficiency of memory access.

[0268] As an optional implementation, Fig. 7EIn the horizontal architecture shown, DRAM and PCM correspond to different memory spaces. For this architecture, the control unit 301 can store hot data with a high access frequency on the DRAM, that is, establish a correspondence between the processing unit that initiates the hot data with a high access frequency and the virtual memory device corresponding to the DRAM memory, which can improve the reading and writing speed of the memory data and the service life of the main memory system. The control unit 301 can establish a correspondence between the processing unit that initiates the cold data with a low access frequency and the virtual memory device corresponding to the PCM memory, so as to store the cold data with a low access frequency on the PCM, so as to utilize the non-volatile characteristics of the PCM to ensure the security of important data. Figure 7F The vertical architecture shown in the figure takes advantage of the high integration of PCM and the low read and write latency of DRAM. On the one hand, the larger PCM main memory can be used to store various types of data, reducing the number of disk accesses. On the other hand, using DRAM as a cache can further improve the efficiency and performance of memory access.

[0269] It should be noted that although Fig. 7E or Figure 7F The system includes a cache (a first-level cache 3041 or a second-level cache 3042), a Qos engine 306, a pre-fetch engine 307, and a compression / decompression engine 308, but these components are optional. Fig. 7E or Figure 7F These components may not be included, or at least one of them may be included.

[0270] based on Fig. 7E and Figure 7F Based on the characteristics of different architectures, the control unit 301 in the memory sharing control device 300 can create virtual memory devices with different characteristics under different architectures and allocate them to processing units with different business needs. This can more flexibly meet the needs of processing units to access memory resources and further improve the efficiency of processing units when accessing memory.

[0271] Figure 8A-1 FIG. 8 is a schematic diagram of the structure of a computer device 80a provided in an embodiment of the present application. Figure 8A-1 As shown, the computer device 80a includes multiple processors (processor 810a to processor 810a+N), a memory sharing control device 800a, a shared memory pool composed of N memories 820a, and a bus 840a. The memory sharing control device 800a is connected to the processors (processor 810a to processor 810a+N) through the bus 840a, and the shared memory pool (memory 820a to memory 820a+N) is connected to the bus 840a. In the embodiment of the present application, N is a positive integer greater than or equal to 1.

[0272] Figure 8A-1In the embodiment, each processor 810a has its own local memory, for example, processor 810a has local memory 1. Each processor 810a can access the local memory, and when it is necessary to expand the memory resources to be accessed, the shared memory pool can be accessed through the memory sharing control device 800a. By providing a unified shared memory pool for any processor from processor 810a to processor 810a+N to share and use, not only can the utilization rate of memory resources be improved, but also the problem of excessive delay caused by cross-processor access when processor 810a accesses the local memory controlled by other processors can be avoided.

[0273] Optional, Figure 8A-1 The memory sharing control device 800a may also include the logical function of a network adapter, so that the memory sharing control device 800a can also access memory resources in other computer devices through the network, which can further expand the scope of shared memory resources and improve the utilization rate of memory resources.

[0274] Figure 8A-2 FIG. 8 is a schematic diagram of the structure of another computer device 80a provided in an embodiment of the present application. Figure 8A-2 As shown, the computer device 80a also includes a network adapter 830a, which is connected to the bus 840a via a Serdes interface. The memory sharing control device 800a can access the memory resources in other computer devices via the network adapter 830a. Figure 8A-2 In the computer device 80a shown, the memory sharing control device 800a may not have the function of a network adapter.

[0275] Figure 8B-1 FIG. 8 is a schematic diagram of the structure of a computer device 80b provided in an embodiment of the present application. Figure 8B-1 As shown, the computer device 80b includes a processor resource pool composed of multiple processors 810b (processor 810b to processor 810b+N), a memory sharing control device 800b, a shared memory pool composed of multiple memories 820b (memory 820b to memory 820b+N), and a bus 840b. The processor resource pool is connected to the bus 840b through the memory sharing control device 800b, and the shared memory pool is connected to the bus 840b. Figure 8A-1 or Figure 8A-2 different, Figure 8B-1 or Figure 8B-2 Each processor (any one of processor 810b to processor 810b+N) does not have its own local memory, and the processor's memory access request is implemented through the memory sharing control device 800b in the shared memory pool composed of memory 820b (memory 820b to memory 820b+N).

[0276] Optional, Figure 8B-1The memory sharing control device 800a may also include the logical function of a network adapter, so that the memory sharing control device 800b can also access memory resources in other computer devices through the network, which can further expand the scope of shared memory resources and improve the utilization rate of memory resources.

[0277] Figure 8B-2 FIG. 8 is a schematic diagram of the structure of another computer device 80b provided in an embodiment of the present application. Figure 8B-2 As shown, the computer device 80b also includes a network adapter 830b, which is connected to the bus 840b via a Serdes interface. The memory sharing control device 800b can access the memory resources in other computer devices via the network adapter 830b. Figure 8B-2 In the computer device 80b shown, the memory sharing control device 800b may not have the function of a network adapter.

[0278] Figure 8A-1 and Figure 8A-2 The memory sharing control device 80a in Figure 8B-1 and Figure 8B-2 The memory sharing control device 80b in the embodiment can refer to the above Figure 2A or Figure 2B The memory sharing control device 200 in the embodiment of the present invention, or the memory sharing control device 200 in the embodiment of Figure 7A-7F The processor 810a or the processor 810b may refer to the above Figure 6 The memory 820a or the memory 820b can be a memory resource such as DRAM or PCM. The network adapter 830a is connected to the bus 840a through a serial interface such as a Serdes interface; the network adapter 830b is connected to the bus 840b through a serial interface such as a Serdes interface. The bus 840a or the bus 840b can be a PCI e bus.

[0279] In the computer device 80a or the computer device 80b, multiple processors can realize fast access to the shared memory pool through the memory sharing control device, and can improve the utilization rate of the memory resources in the shared memory pool. At the same time, since the network adapter 830 is connected to the bus through the serial interface, the delay of data transmission between the processor and the network adapter will not be significantly increased due to the increase in distance. The computer device 80a or the computer device 80b can expand the memory resources accessible by the processor to other devices connected to the computer device 80a or the computer device 80b through the memory sharing control device and the network adapter, thereby further expanding the scope of the memory resources that the processor can share, realizing the sharing of memory resources in a larger scope, and further improving the utilization rate of memory resources.

[0280] It is understandable that the computer device 80a may also include processors without local memory, and these processors access the shared memory pool through the memory sharing control device 800a to achieve memory access. The computer device 80b may also include processors with local memory, and these processors can access both local memory and memory in the shared memory pool through the memory sharing control device 800b. Optionally, when some processors in the computer device 80b have local memory, most of the memory access of these processors is implemented in the local memory.

[0281] Fig. 9A Schematic diagram of the structure of a system 901 provided in an embodiment of the present application. Fig. 9A As shown, the system 901 includes M computer devices, for example, including computer devices 80a, computer devices 81a, computer devices 82a and other devices. In the embodiment of the present application, M is a positive integer greater than or equal to 3. The M computer devices are connected through a network 910a, and the network 910a can be an Ethernet-based network or a U-bus-based network. The structure of the computer device 81a is similar to that of the computer device 80a, including a processor resource pool composed of multiple processors (processor 8012a to processor 8012a+N), a memory sharing control device 8011a, a shared memory pool composed of multiple memories (memory 8013a to memory 8013a+N), a network adapter 8014a and a bus 8015a. In the computer device 81a, the processor resource pool, the memory sharing control device 8011a and the network adapter 8014a are respectively connected to the bus 8015a, and the shared memory pool (memory 8013a to memory 8013a+N) is connected to the memory sharing control device 8011a. The memory access request initiated by the processor in the processor resource pool accesses the shared memory pool through the memory sharing control device 8011a. The memory sharing control device 8011a can refer to the above Figure 2A or Figure 2B The memory sharing control device 200 in the embodiment of the present invention, or the memory sharing control device 200 in the embodiment of Figure 7A-7F The processor 8012a can refer to the above Figure 6 The memory 8013a may be a memory resource such as DRAM or PCM. The network adapter 8014a is connected to the bus 8015a via a serial interface, such as a Serdes interface. The bus 8015a may be a PCI e bus.

[0282] Fig. 9AIn the NUMA system, each processor has its own local memory, which is the main memory resource for processor memory access. Taking processor 8012a as an example, processor 8012a can directly access its local memory 1, and most of the memory access requests of processor 8012a can be implemented in its memory 1. When processor 8012a needs a larger memory to handle burst services, it can access the memory resources in the shared memory pool through the memory sharing control device 8011a to meet the memory resource needs of processor 8012a. Optionally, processor 8012a can also access the local memory of other processors, for example, it can access the local memory (memory N) of processor N, that is, processor 8012a can also access the local memory of other processors in accordance with the memory sharing method in the NUMA system.

[0283] The structures of the computer device 82a and other computer devices M may be similar to that of the computer device 80a, and will not be described in detail.

[0284] In the system 901, the processor 80a can access the shared memory pool composed of the memory 8013a through the memory sharing control device 800a, the network adapter 830a, the network 910a, the network adapter 8014a and the memory sharing control device 8011a. That is to say, the memory resources that the processor 810a can access include the memory resources in the computer device 80a and the memory resources in the computer device 81a. In a similar manner, the processor 810a can also access the memory resources in all the computer devices in the system 901. In this way, when a certain computer device, such as the processor 8012a running on the computer device 81a has a low business load and a large amount of memory 8013a is in an idle state, and the processor 810a in the computer device 80a needs a large amount of memory resources due to executing applications such as HPC, the memory resources of the computer device 81a can be allocated to the processor 810a in the computer device 80a through the memory sharing control device 800a. In this way, the memory resources in system 901 are effectively utilized, which not only meets the memory requirements of different computer devices when processing business, but also improves the memory resource utilization of the entire system, and is more effective in improving memory resource utilization to reduce TCO.

[0285] It should be noted that Fig. 9AIn the system 901 shown, the computer device 80a includes a network adapter 830a. In a specific implementation, the computer device 80a may not include the network adapter 830a, and the memory sharing control device 800a may include the control logic of the network adapter, so that the processor 810a can access other memory resources in the network through the memory sharing control device 8011a. Exemplarily, the processor 80a can access the shared memory pool composed of the memory 8013a through the memory sharing control device 800a, the network 910a, the network adapter 8014a and the memory sharing control device 8011a. When the computer device 81a also does not include the network adapter 8014a and the memory sharing control device 8011a implements the function of the network adapter, the processor 80a can access the shared memory pool composed of the memory 8013a through the memory sharing control device 800a, the network 910a and the memory sharing control device 8011a.

[0286] Fig. 9B Schematic diagram of the structure of a system 902 provided in an embodiment of the present application. Fig. 9B As shown, the system 902 includes M computer devices, such as computer device 80b, computer device 81b, computer device 82b and other devices, where M is a positive integer greater than or equal to 3. The M computer devices are connected via a network 910b, and network 910b can be an Ethernet-based network or a U-bus-based network. The structure of computer device 81b is similar to that of computer device 80b, including a processor resource pool composed of multiple processors (processor 8012b to processor 8012b+N), a memory sharing control device 8011b, a shared memory pool composed of multiple memories (memory 8013b to memory 8013b+N), a network adapter 8014b and a bus 8015b. The processor resource pool is connected to the bus 8015b via the memory sharing control device 8011b, and the shared memory pool and the network adapter 8014b are also respectively connected to the bus 8015b. The memory sharing control device 8011b can refer to the above Figure 2A or Figure 2B The memory sharing control device 200 in the embodiment of the present invention, or the memory sharing control device 200 in the embodiment of Figure 7A-7F The processor 8012b can refer to the above Figure 6 The memory 8013b can be a memory resource such as DRAM or PCM. The network adapter 8014b is connected to the bus 8015b through a serial interface, such as a Serdes interface. The bus 8015b can be a PCI e bus.

[0287] The structures of the computer device 82b and other computer devices M may be similar to that of the computer device 80b, and will not be described in detail.

[0288] In the system 902, the processor 810b can access the shared memory pool composed of the memory 8013b through the memory sharing control device 800b, the network adapter 830b, the network 910b and the network adapter 8014b. That is to say, the memory resources that the processor 810b can access include the memory resources in the computer device 80b and the memory resources in the computer device 81b. In a similar manner, the processor 810b can also access the memory resources in all the computer devices in the system 902, so as to use the memory resources in the system 902 as shared memory resources. In this way, when a certain computer device, such as the processor 8012 running on the computer device 81b, has a low business load and has more memory 8013b in an idle state, and the processor 810b in the computer device 80b needs a large amount of memory resources due to executing applications such as HPC, the memory resources of the computer device 81b can be allocated to the processor 810b in the computer device 80b through the memory sharing control device 800b. In this way, the memory resources in system 902 are effectively utilized to meet the memory requirements of different computer devices when processing business. At the same time, the utilization rate of memory resources in system 902 is improved, which will be more obvious in improving the utilization rate of memory resources to reduce TCO.

[0289] It should be noted that Fig. 9B In the system 902 shown, the computer device 80b includes a network adapter 830b. In a specific implementation, the computer device 80b may not include the network adapter 830b, and the memory sharing control device 800b may include the control logic of the network adapter, so that the processor 810b can access other memory resources in the network through the memory sharing control device 8011b. Exemplarily, the processor 80b can access the shared memory pool composed of the memory 8013b through the memory sharing control device 800b, the network 910b, the network adapter 8014b and the memory sharing control device 8011b. When the computer device 81b does not include the network adapter 8014b and the memory sharing control device 8011b implements the function of the network adapter, the processor 80b can access the shared memory pool composed of the memory 8013b through the memory sharing control device 800b, the network 910b and the memory sharing control device 8011b.

[0290] Fig. 9C Schematic diagram of the structure of a system 903 provided in an embodiment of the present application. Fig. 9CAs shown, the system 903 includes computer device 80a, computer device 81b, computer device 82c to computer device M. Among them, 80a in system 903 is implemented in the same way as 80a in system 901, 81b in system 903 is implemented in the same way as 81b in system 902, and computer device 82c to computer device M can be computer devices similar to computer device 80a, or can be computer devices similar to computer device 81b. System 903 integrates computer device 80a in system 910 and computer device 81b in system 920, and can also achieve the purpose of improving the utilization rate of memory resources in the system through memory sharing.

[0291] It should be noted that in the systems 901-903, the computer device needs to transmit the memory access request through the network. Since the network adapter 830b is connected to the memory sharing control device through the Serdes interface via the serial bus, the transmission rate and bandwidth of the serial bus can ensure the data transmission rate. Therefore, although the transmission through the network will have a certain impact on the data transmission rate, from the aspect of improving the utilization rate of memory resources, this method can improve the utilization rate of memory resources while taking into account the processor access memory rate.

[0292] Fig.10 for Figure 8A-1 or Figure 8A-2 The computer device 80a shown, or Figure 8B-1 or Figure 8B-2 The logical diagram of the computer device 80b implementing memory sharing can also be Figures 9A-9C The system 900 shown is a logical diagram of implementing memory sharing.

[0293] by Figure 8A-1 Taking the logical diagram of the computer device 80a implementing memory sharing as an example, processors 1-4 represent any four processors (or cores in the processor) in the processor resource pool composed of processor 810a, memory sharing control device 1000 represents memory sharing control device 800a, and memories 1-4 represent any four memories in the shared memory pool composed of memory 820a. Memory sharing control device 1000 virtualizes four virtual memory devices (i.e., Fig.10 The access control table 1001 records the correspondence between the virtual memory device and the processor. When the memory sharing control device 1000 receives a memory access request sent by any processor of the processors 1-4, the information of the virtual memory device corresponding to the processor sending the memory access request is obtained based on the access control table 1001, and the corresponding memory is accessed through the memory controller 1002 according to the obtained virtual memory device information.

[0294] by Fig. 9B Taking the logical diagram of the system 902 implementing memory sharing as an example, processors 1-4 represent four processors (or cores in processors) in any one or more computer devices in the system 902, memory sharing control device 1000 represents a memory sharing control device in any one computer device, and memories 1-4 represent four memories in any one or more computer devices in the system 900. The memory sharing control device 1000 virtualizes four virtual memory devices (i.e., Fig.10 The access control table 1001 records the correspondence between the virtual memory device and the processor. When the memory sharing control device 1000 receives a memory access request sent by any processor of the processors 1-4, the information of the virtual memory device corresponding to the processor sending the memory access request is obtained based on the access control table 1001, and the corresponding memory is accessed through the memory controller 1002 according to the obtained virtual memory device information.

[0295] Fig.11 FIG. 1 is a schematic diagram of a computer device 1100 provided in an embodiment of the present application. Fig.11 As shown, the computer device 1100 includes at least two processing units 1102, a memory sharing control device 1101 and a memory pool, the processing unit is a processor, a core in a processor or a combination of cores in a processor, and the memory pool includes one or more memories 1103;

[0296] The at least two processing units 1102 are coupled to the memory sharing control device 1101;

[0297] The memory sharing control device 1101 is used to allocate memory from the memory pool to the at least two processing units 1102 respectively, and at least one memory in the memory pool can be accessed by different processing units in different time periods;

[0298] The at least two processing units 1102 are used to access the allocated memory through the memory sharing control device 1101.

[0299] The coupling of the at least two processing units 1102 with the memory sharing control device 1101 means that the at least two processing units 1102 are respectively connected to the memory sharing control device 1101, and any one of the at least two processing units 1102 can be directly connected to the memory sharing control device 1101, or can be connected through other hardware components (such as other chips).

[0300] Fig.11For the specific implementation of the computer device 1100 shown in FIG. Figure 8A-1 , Figure 8A-2 , Figure 8B-1 and Figure 8B-2 The implementation method can also be implemented by referring to the above Figure 9A-9C The computer device (such as computer device 80a or computer device 80b, etc.) in the embodiment of the present invention can also be referred to. Fig.10 The memory sharing control device 1101 in the computer device 1100 can also refer to the above Figure 2A or Figure 2B The memory sharing control device 200 in the embodiment of the present invention, or the memory sharing control device 200 in the embodiment of Figure 7A-7F The implementation method of the memory sharing control device 300 is implemented and will not be repeated here.

[0301] Fig.11 At least two processing units 1102 in the computer device 1100 shown in the figure can access at least one memory in the memory pool in different time periods through the memory sharing control device 1101, thereby meeting the needs of the processing units for memory resources and improving the utilization rate of memory resources.

[0302] Fig.12 A flow chart of a method for memory sharing control provided in an embodiment of the present application. The method can be applied to the above Figure 8A-1 , Figure 8A-2 , Figure 8B-1 or Figure 8B-2 The computer device shown in the figure can also be applied to the above Figure 9A-9C A computer device (such as computer device 80a or computer device 80b, etc.) in the embodiment of the present invention comprises at least two processing units, a memory sharing control device and a memory pool, wherein the memory pool comprises one or more memories, such as Fig.12 As shown, the method includes:

[0303] Step 1200: The memory sharing control device receives a first memory access request sent by a first processing unit among at least two processing units; wherein the processing unit is a processor, a core in a processor, or a combination of cores in a processor;

[0304] Step 1202: the memory sharing control device allocates a first memory to the first processing unit from a memory pool, and the first memory can be accessed by a second processing unit of the at least two processing units in other time periods;

[0305] Step 1204: The first processing unit accesses the first memory through the memory sharing control device.

[0306] based on Fig.12The method shown enables different processing units to access at least one memory in the memory pool in different time periods, which can meet the needs of the processing units for memory resources and improve the utilization rate of memory resources.

[0307] Specifically, Fig.12 The method shown can refer to the above Figure 2A or Figure 2B The memory sharing control device 200 in the embodiment of the present invention, or the memory sharing control device 200 in the embodiment of Figure 7A-7F The implementation method of the memory sharing control device 300 is implemented and will not be repeated here.

[0308] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0309] In several embodiments provided in this application, the device embodiments described are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices or units, or may be an electrical, mechanical or other form of connection.

[0310] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.

[0311] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A computer device, characterized in that: The method comprises at least two processing units, a memory sharing control device and a memory pool, wherein the processing unit is a processor, a core in a processor or a combination of cores in a processor, and the memory pool comprises one or more memories; The at least two processing units are coupled to the memory sharing control device, and the at least two processing units are connected to the memory sharing control device via a serial bus; The memory sharing control device is used to allocate memory from the memory pool to the at least two processing units respectively, and at least one memory in the memory pool can be accessed by different processing units in different time periods; The at least two processing units are used to access the allocated memory through the memory sharing control device.

2. The computer device according to claim 1, characterized in that The first processing unit among the at least two processing units is used to send a first memory access request in the form of a serial signal to the memory sharing device through the serial bus, where the first memory access request is used to access a first memory allocated to the first processing unit.

3. The computer device according to claim 2, characterized in that The memory sharing control device includes a processor interface, and the processor interface is used for: receiving the first memory access request; The first memory access request is converted into a second memory access request in the form of a parallel signal.

4. The computer device according to claim 2 or 3, characterized in that: The memory sharing control device comprises a control unit, and the control unit is used for: A correspondence between a memory address of the first memory in the memory pool and a first processing unit among the at least two processing units is established to allocate the first memory to the first processing unit from the memory pool.

5. The computer device according to claim 2 or 3, characterized in that: The memory sharing control device comprises a control unit, and the control unit is used for: Virtualizing a plurality of virtual memory devices from the memory pool, wherein a physical memory corresponding to a first virtual memory device among the plurality of virtual memory devices is the first memory; The first virtual memory device is assigned to the first processing unit.

6. The computer device according to claim 5, characterized in that The control unit is also used for: When a preset condition is met, releasing the correspondence between the first virtual memory device and the first processing unit; A correspondence between the first virtual memory device and a second processing unit among the at least two processing units is established.

7. The computer device according to any one of claims 1 to 6, characterized in that: The memory sharing control device further includes a cache unit, which is used to cache data read from the memory pool by any one of the at least two processing units, or cache data eliminated by any one of the at least two processing units.

8. The computer device according to claim 7, characterized in that The memory sharing control device further includes a pre-fetch engine, which is used to pre-fetch data that needs to be read by any one of the at least two processing units from the memory pool, and cache the data in the cache unit.

9. The computer device according to claim 7 or 8, characterized in that: The memory sharing control device further comprises a quality of service (Qos) engine, and the Qos engine is used to realize optimized storage of data that needs to be cached by any one of the at least two processing units in the cache unit.

10. The computer device according to any one of claims 1 to 9, characterized in that: The memory sharing control device also includes a compression / decompression engine, which is used to realize compression or decompression of data related to memory access.

11. The computer device according to any one of claims 1 to 10, characterized in that: The first processing unit also has a local memory, and the local memory is used for memory access of the first processing unit.

12. The computer device according to any one of claims 1 to 11, characterized in that: The multiple memories included in the memory pool belong to different media types.

13. A system comprising at least two computer devices according to claims 1-12, wherein the at least two computer devices according to claims 1-12 are connected via a network.

14. A memory sharing control device, characterized in that: The memory sharing control device includes a control unit, a processor interface and a memory interface; The processor interface is used to receive memory access requests sent by at least two processing units; wherein the processing unit is a processor, a core in a processor, or a combination of cores in a processor, and the memory sharing control device is connected to the at least two processing units via a serial bus; The control unit is used to allocate memory from a memory pool to the at least two processing units respectively, and at least one memory in the memory pool can be accessed by different processing units in different time periods; The control unit is further configured to enable the at least two processing units to access the allocated memory through the memory interface.

15. The memory sharing control device according to claim 14, characterized in that: The processor interface is further used to receive a first memory access request sent by a first processing unit among the at least two processing units in the form of a serial signal through a serial bus, wherein the first memory access request is used to access a first memory allocated to the first processing unit.

16. The memory sharing control device according to claim 15, characterized in that: The processor interface is further used to convert the first memory access request into a second memory access request in the form of a parallel signal, and send the second memory access request to the control unit; The control unit is further configured to implement access of the second memory access request to the first memory through the memory interface.

17. The memory sharing control device according to claim 15 or 16, characterized in that: The control unit is further used to establish a corresponding relationship between a memory address of the first memory in the memory pool and the first processing unit, so as to allocate the first memory to the first processing unit from the memory pool.

18. The memory sharing control device according to claim 15 or 16, characterized in that: The control unit is further configured to virtualize a plurality of virtual memory devices from the memory pool, wherein a physical memory corresponding to a first virtual memory device among the plurality of virtual memory devices is the first memory; The first virtual memory device is assigned to the first processing unit.

19. The memory sharing control device according to claim 18, characterized in that: The control unit is further configured to: when a preset condition is met, cancel the correspondence between the first virtual memory device and the first processing unit, and establish a correspondence between the first virtual memory device and a second processing unit of the at least two processing units.

20. The memory sharing control device according to any one of claims 14 to 19, characterized in that: The memory sharing control device also includes a cache unit; The cache unit is used to cache data read from the memory pool by any one of the at least two processing units, or to cache data eliminated by any one of the at least two processing units.

21. The memory sharing control device according to claim 20, characterized in that: The memory sharing control device further includes a pre-fetch engine, which is used to pre-fetch data that needs to be read by any one of the at least two processing units from the memory pool, and cache the data in the cache unit.

22. The memory sharing control device according to claim 20 or 21, characterized in that: The memory sharing control device also includes a quality of service (Qos) engine; The QoS engine is used to achieve optimized storage of data that needs to be cached by any one of the at least two processing units in the cache unit.

23. The memory sharing control device according to any one of claims 14 to 22, characterized in that: The memory sharing control device also includes a compression / decompression engine; The compression / decompression engine is used to implement compression or decompression of data related to memory access.

24. A method for memory sharing control, characterized in that: The method is applied to a computer device, the computer device includes at least two processing units, a memory sharing control device and a memory pool, the memory pool includes one or more memories, and the method includes: The memory sharing control device receives a first memory access request sent by a first processing unit among at least two processing units; wherein the processing unit is a processor, a core in a processor, or a combination of cores in a processor, and the memory sharing control device is connected to the at least two processing units via a serial bus; The memory sharing control device allocates a first memory to the first processing unit from a memory pool, and the first memory can be accessed by a second processing unit of the at least two processing units in other time periods; The first processing unit accesses the first memory through the memory sharing control device.

25. The method according to claim 24, characterized in that The method further comprises: The memory sharing control device receives a first memory access request sent by a first processing unit of the at least two processing units in the form of a serial signal through a serial bus, where the first memory access request is used to access a first memory allocated to the first processing unit.

26. The method according to claim 25, characterized in that The method further comprises: The memory sharing control device converts the first memory access request into a second memory access request in the form of a parallel signal, and implements access to the first memory according to the second memory access request.

27. The method according to claim 25 or 26, characterized in that The method further comprises: The memory sharing control device establishes a correspondence between a memory address of the first memory in the memory pool and a first processing unit among the at least two processing units.

28. The method according to claim 25 or 26, characterized in that The method further comprises: The memory sharing control device virtualizes a plurality of virtual memory devices from the memory pool, wherein a physical memory corresponding to a first virtual memory device among the plurality of virtual memory devices is the first memory; The memory sharing control device is further configured to allocate the first virtual memory device to the first processing unit.

29. The method according to claim 28, characterized in that The method further comprises: When a preset condition is met, the memory sharing control device cancels the correspondence between the first virtual memory device and the first processing unit, and establishes a correspondence between the first virtual memory device and a second processing unit of the at least two processing units.

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