Test adapter comprehensive design method and test adapter

Abstract

The invention provides a comprehensive design method of a test adapter and the test adapter, and belongs to the technical field of helicopter airborne electronic system.The comprehensive design method of the test adapter comprises the steps that the type and the model of a test interface of the test adapter are determined firstly; then classifying test resources required by all the tested devices, and determining the maximum test requirement required by the test adapter; carrying out layout design on the test interface of the test adapter based on the maximum test requirement; then test resources are dynamically configured in the power supply test connector and the general test connector, dynamic configuration of the test resources is realized based on the interface design of test demand maximization, and the comprehensive capability of the test adapter is improved; and the development cost and the maintenance cost of the ATE are reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of helicopter airborne electronic system testing, and in particular relates to a comprehensive design method for a test adapter and a test adapter. Background Art

[0002] The test adapter is a component of the helicopter integrated testing platform ATE. Its function is to convert the dedicated signals of the device under test into public interface signals and transmit them to the ATE.

[0003] In the existing test adapter design method, the adapter test interface layout and test resource arrangement are carried out according to the communication (including power supply) interface of the device under test. The test adapter is not highly integrated, and the scale of test adapters that ATE needs to deploy is large, which increases the development cost and maintenance cost of ATE. Summary of the invention

[0004] In order to solve the technical problems in the related art that the test adapter is not highly integrated during design, and the development cost and maintenance cost of ATE are high, the present invention provides a test adapter comprehensive design method, which realizes dynamic configuration of test resources based on interface design that maximizes test requirements, improves the integration capability of the test adapter, and reduces the development cost and maintenance cost of ATE. The technical solution is as follows:

[0005] In a first aspect, a test adapter comprehensive design method is provided, the method comprising:

[0006] Step 1: Determine the type and model of the test adapter test interface;

[0007] Step 2: Categorize the test resources required for all devices under test and determine the maximum test requirements required for the test adapter;

[0008] Step 3: Based on the maximum test requirements, layout design of the test adapter test interface;

[0009] Step 4: Dynamically configure the test resources in the power test connector and the general test connector.

[0010] Wherein, step 1 comprises:

[0011] Step 11: Taking the maximum test requirement as input, the test adapter test interface is divided into a universal test connector interface and a power test connector interface of the same size and appearance;

[0012] Step 12: Determine the model of the universal test connector interface and the power test connector interface.

[0013] Wherein, step 2 comprises:

[0014] Step 21: Divide the test resources into 11 categories, including power supply, serial bus, 429 bus, AFDX bus, Ethernet, multimeter, A / D acquisition module, oscilloscope, signal generator, D / A output module, and switch. The number of pins corresponding to each category of test resources is (2, 4, 4, 4, 4, 2, 2, 2, 2, 1).

[0015] Step 22: Determine the number of test resources required for each device under test i and the number of pins of the test resource S i ;

[0016] Step 23: Summarize the test resources required for all devices under test and determine the maximum test requirements required for the test adapter.

[0017] Among them, in step 22,

[0018] s i =a i +b i +c i +d i +e i +f i +g i +h i +j i +k i +l i

[0019] S i =2a i +4b i +4c i +4d i +4e i +2f i +2g i +2h i +2j i +2k i +l i

[0020] Where i represents the i-th device under test, i is greater than 0 and less than or equal to n, and n is the total number of devices under test; a i It represents the amount of power required by the i-th device under test, b i It represents the number of serial bus required by the i-th device under test, c i It represents the number of 429 buses required by the i-th device under test, d i It represents the number of AFDX buses required by the i-th device under test, e i represents the number of Ethernets required by the i-th device under test, f i It represents the number of multimeters required for the i-th device under test, gi It represents the number of A / D acquisition modules required by the i-th device under test, h i represents the number of oscilloscopes required for the i-th device under test, j i represents the number of signal generators required for the i-th device under test, k i It represents the number of D / A output modules required by the i-th device under test, l i It represents the number of switches required for the i-th device under test;

[0021] Step 23 is specifically as follows: first determine the maximum value among the quantities of various test resources required by all devices under test, add up all the maximum values, and obtain the maximum test requirement s.

[0022] Wherein, step 3 comprises:

[0023] Step 31: Based on the maximum test requirement s, calculate the number of test pins ST required for the test adapter test interface;

[0024] Step 32: Calculate the number M of universal test connectors according to the number ST of test pins required for the test interface of the test adapter;

[0025] Step 33: Evenly arrange one power test connector and M universal test connectors in the test adapter test interface.

[0026] Among them, in step 31,

[0027] ST=2Max a +4Max b +4Max c +4Max d +4Max e +2Max f

[0028] +2Max g +2Max h +2Max j +2Max k +Max l

[0029] In step 32,

[0030]

[0031] Optionally, step 4 includes:

[0032] Step 41: S in Step 22 i Sort from small to large, and put the smallest S i The test resources required by the corresponding device under test are configured in the power test connector interface;

[0033] Step 42: construct a mathematical model of the configured test resource pins in the test adapter;

[0034] Step 43: Calculate the minimum difference SV between the test resources required by the remaining device under test and the test resources configured by the test adapter;

[0035] Step 44: configure the remaining test resources required by the device under test corresponding to the minimum difference SV in the power test connector interface. If the number of pins of the power test connector is insufficient, arrange the remaining pins in the universal test connector, in which the power supply pins are designed in the power test connector interface.

[0036] Step 45: Repeat steps 43 and 44 to configure the test resources required by all devices under test in the universal test connector interface.

[0037] Optionally, the mathematical model of the configured test resource pins in the test adapter constructed in step 42 is:

[0038] T=2a t +4b t +4c t +4d t +4e t +2f t +2g t +2h t +2j t +2k t +l t

[0039] Among them, a t ,b t ,c t ,d t ,e t ,f t ,g t ,h t ,j t ,k t ,l t They represent the configured test resources, including power supply, serial bus, 429 bus, AFDX bus, Ethernet, multimeter, A / D acquisition module, oscilloscope, signal generator, D / A output module, and the number of pins of switches. The initial values ​​are all 0.

[0040] In step 43, SV = Min(S1, S2...S x ),

[0041] S x =2Max(a i -a t ,0)+4Max(bi -b t ,0)+4Max(c i -c t ,0)+4Max(d i -d t ,0)+2Max(e i -e t ,0)+2Max(f i -f t ,0)

[0042] +2Max(g i -g t ,0)+2Max(h i -h t ,0)+2Max(j i -j t ,0)+2Max(k i -k t ,0)+Max(l i -l t ,0)

[0043] Among them, S x It represents the difference between the test resources required by the remaining devices under test and the test resources configured by the test adapter. x is greater than 0 and less than or equal to Y, and Y is the total number of remaining devices under test.

[0044] In a second aspect, a test adapter is provided, wherein the test adapter is designed using any of the methods described in the first aspect, the adapter comprising a power test connector interface and a plurality of universal test connector interfaces, the power test connector interface being connected to all devices under test;

[0045] ATE is connected to the device under test through a test adapter to test the device under test.

[0046] The present invention provides a comprehensive design method for a test adapter, which first determines the type and model of a test interface of a test adapter; then classifies the test resources required by all devices under test and determines the maximum test requirement required by the test adapter; then, based on the maximum test requirement, performs layout design on the test interface of the test adapter; then, dynamically configures the test resources in a power test connector and a universal test connector, implements dynamic configuration of the test resources based on an interface design that maximizes the test requirement, performs comprehensive design on the test interface of the test adapter, and improves the comprehensive capability of the test adapter. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A flow chart of a comprehensive design method for a test adapter provided by an embodiment of the present invention;

[0048] Figure 2 A schematic diagram of a test interface of a test adapter provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The present application is further described in detail below through specific implementation methods and drawings.

[0050] An embodiment of the present invention provides a test adapter comprehensive design method, which uses the maximum test requirement as input to perform comprehensive design on the test adapter, such as Figure 1 As shown, the method comprises the following steps:

[0051] Step 1: Determine the type and model of the test adapter test interface. Specifically include:

[0052] Step 11: According to GJB 589A-1993 "General Specification for Environmentally Resistant Quick-Disconnect Circular Electrical Connectors", with the maximum test requirements as input, the test adapter test interface is divided into a universal test connector interface and a power test connector interface with the same size and appearance, such as Figure 2 shown.

[0053] Step 12: Determine the models of the universal test connector interface and the power test connector interface, wherein the model of the universal test connector interface is JY27505E25F35SX (key position X can be N, A, B, C, D), and the model of the power test connector interface is JY27505E25F69SX (key position X can be N, A, B).

[0054] Step 2: Categorize the test resources required for all devices under test and determine the maximum test requirements for the test adapter. Specifically, it includes:

[0055] Step 21: Divide the test resources into 11 categories, including power supply (a), serial port bus (b), 429 bus (c), AFDX bus (d), Ethernet (e), multimeter (f), A / D acquisition module (g), oscilloscope (h), signal generator (j), D / A output module (k), and switch (l). The number of pins corresponding to each category of test resources is (2, 4, 4, 4, 2, 2, 2, 2, 1).

[0056] Step 22: Determine the number of test resources required for each device under test i and the number of pins of the test resource S i :

[0057] s i =a i +b i +c i +d i +e i +f i+g i +h i +j i +k i +l i

[0058] S i =2a i +4b i +4c i +4d i +4e i +2f i +2g i +2h i +2j i +2k i +l i

[0059] Where i represents the i-th device under test, i is greater than 0 and less than or equal to n, and n is the total number of devices under test; a i It represents the amount of power required by the i-th device under test, b i It represents the number of serial bus required by the i-th device under test, c i It represents the number of 429 buses required by the i-th device under test, d i It represents the number of AFDX buses required by the i-th device under test, e i represents the number of Ethernets required by the i-th device under test, f i It represents the number of multimeters required for the i-th device under test, g i It represents the number of A / D acquisition modules required by the i-th device under test, h i represents the number of oscilloscopes required for the i-th device under test, j i represents the number of signal generators required for the i-th device under test, k i It represents the number of D / A output modules required by the i-th device under test, l i It represents the number of switches required for the i-th device under test.

[0060] Step 23: Summarize the test resources required by all devices under test and determine the maximum test requirement required by the test adapter, specifically: first determine the maximum value of the number of various test resources required by all devices under test, add up all the maximum values, and obtain the maximum test requirement s. For example, n is equal to 3, the number of power supplies required by the first device under test is 10, the number of power supplies required by the second device under test is 5, and the number of power supplies required by the third device under test is 7, then the maximum value of the number of power supplies is 10, and similarly obtain the number of other types of test resources such as serial bus, 429 bus, AFDX bus, Ethernet, etc., and then obtain 10 maximum values, and finally add up these 11 maximum values ​​to obtain the maximum test requirement s.

[0061] Step 3: Based on the maximum test requirements, layout and design the test adapter test interface. Specifically include:

[0062] Step 31: Based on the maximum test requirement s determined in step 2, calculate the number of test pins ST required for the test adapter test interface:

[0063] ST=2Max(a i )+4Max(b i )+4Max(c i )+4Max(d i )+4Max(e i )+2Max(f i )

[0064] +2Max(g i )+2Max(h i )+2Max(j i )+2Max(k i )+Max(l i )

[0065] Step 32: Calculate the number M of universal test connectors determined in step 1 based on the number of test pins ST required for the test interface of the test adapter:

[0066]

[0067] Due to the layout restrictions of the test adapter panel, M≤4; the power test connector has a maximum of 69 pins and is arranged at the XS1 position; the universal test connector has a maximum of 128 pins, and each connector reserves 10% margin and is arranged at the XS2~XS(1+M) position, such as Figure 2 shown.

[0068] Step 33: Evenly arrange 1 power test connector and M universal test connectors in the test adapter.

[0069] Step 4: Dynamically configure the test resources in the power test connector and the general test connector. Specifically include:

[0070] Step 41: S in Step 22 i Sort from small to large, and put the smallest S i The test resources required by the corresponding device under test are configured in the power test connector, so that the test resources required by the corresponding device under test are configured in the power test connector (XS1 connector) with priority arrangement.

[0071] Step 42: Construct a mathematical model T of the configured test resource pins in the test adapter.

[0072] T=2a t +4b t +4c t +4d t +4e t +2f t +2g t +2h t +2j t +2k t +l t

[0073] Among them, a t ,b t ,c t ,d t ,e t ,f t ,g t ,h t ,j t ,k t ,l t They respectively represent the configured test resources including the pin numbers of power supply (a), serial bus (b), 429 bus (c), AFDX bus (d), Ethernet (e), multimeter (f), A / D acquisition module (g), oscilloscope (h), signal generator (j), D / A output module (k), and switch (l), and their initial values ​​are 0;

[0074] Step 43: Calculate the minimum difference SV between the remaining test resources required by the device under test and the configured test resources of the test adapter:

[0075] SV=Min(S1,S2…S x ),

[0076] S x =2Max(a i -a t ,0)+4Max(b i -b t ,0)+4Max(ci -c t ,0)+4Max(d i -d t ,0)+2Max(e i -e t ,0)+2Max(f i -f t ,0)

[0077] +2Max(g i -g t ,0)+2Max(h i -h t ,0)+2Max(j i -j t ,0)+2Max(k i -k t ,0)+Max(l i -l t ,0)

[0078] Among them, S x It represents the difference between the test resources required by the remaining devices under test and the test resources configured by the test adapter. x is greater than 0 and less than or equal to Y, and Y is the total number of remaining devices under test.

[0079] For example, Y is equal to 3, the test adapter has been configured with test resources (2,3,1,0,2,0,2,0,0,0,0), the test resources required for the first remaining device under test are (4,3,1,0,0,0,1,0,0,0,0), the test resources required for the second remaining device under test are (1,1,2,0,0,0,3,0,0,0,0), and the test resources required for the third remaining device under test are (3,2,2,0,3,0,0,0,0,0,0), then S1 is 4, S2 is 6, and S3 is 8. S1 to S3 are sorted and the minimum difference SV is 4, which corresponds to the first remaining device under test.

[0080] Step 44: Configure the remaining test resources required by the device under test corresponding to the minimum difference SV in the XS1 connector. For example, the first remaining device under test requires 2 power supplies and 4 pins. Arrange these 4 pins in the XS1 connector. If the number is insufficient (a 10% margin must be reserved), the remaining pins are arranged in XS2 (universal test connector). The power supply pins must be designed in XS1.

[0081] Step 45: Repeat steps 43 and 44 to configure the test resources required by all the devices under test in connectors XS1 to XS(1+M), where M is the number of universal test connector interfaces.

[0082] An embodiment of the present invention further provides a test adapter, which is designed using a test adapter comprehensive design method provided by an embodiment of the method of the present invention. The test adapter includes a power test connector interface and multiple universal test connector interfaces, the power test connector interface is connected to all devices under test, and the ATE is connected to the device under test through the test adapter to test the device under test.

[0083] The embodiment of the present invention improves the integrated design level of the test adapter through the comprehensive design of the test adapter, greatly reduces the number of test adapters, compresses the deployment scale of ATE, optimizes the wiring relationship of the test adapter, simplifies the internal structure, and reduces the development cost and maintenance cost of ATE.

[0084] The above only expresses the implementation methods of the present application, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. In addition, the parts that are not detailed in this application are all conventional technologies.

Claims

1. A test adapter comprehensive design method, characterized in that: The method comprises: Step 1: Determine the type and model of the test adapter test interface; Step 2: Categorize the test resources required for all devices under test and determine the maximum test requirements required for the test adapter; Step 3: Based on the maximum test requirements, layout design of the test adapter test interface; Step 4: Dynamically configure the test resources in the power test connector and the general test connector.

2. The method according to claim 1, characterized in that Step 1 includes: Step 11: Taking the maximum test requirement as input, the test adapter test interface is divided into a universal test connector interface and a power test connector interface of the same size and appearance; Step 12: Determine the model of the universal test connector interface and the power test connector interface.

3. The method according to claim 1, characterized in that: Step 2 includes: Step 21: Divide the test resources into 11 categories, including power supply, serial bus, 429 bus, AFDX bus, Ethernet, multimeter, A / D acquisition module, oscilloscope, signal generator, D / A output module, and switch. The number of pins corresponding to each category of test resources is (2, 4, 4, 4, 4, 2, 2, 2, 2, 1). Step 22: Determine the number of test resources required for each device under test i and the number of pins of the test resource S i ; Step 23: Summarize the test resources required for all devices under test and determine the maximum test requirements required for the test adapter.

4. The method according to claim 3, characterized in that In step 22, the number of test resources required by each device under test is determined. i The formula is: s i =a i +b i +c i +d i +e i +f i +g i +h i +j i +k i +l i , Determine the number of test resources required for each device under test i The formula is: <h2 style=";text-align:left;direction:ltr">S<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> =2a<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> +4b<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> +4c<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> +4d<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> +4e<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> +2f<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> +2g<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> +2h<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> +2j<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> +2k<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> +l<h2 style=";text-align:left;direction:ltr"> i <h2 style=";text-align:left;direction:ltr"> , Where i represents the i-th device under test, i is greater than 0 and less than or equal to n, and n is the total number of devices under test; a i It represents the amount of power required by the i-th device under test, b i It represents the number of serial bus required by the i-th device under test, c i It represents the number of 429 buses required by the i-th device under test, d i It represents the number of AFDX buses required by the i-th device under test, e i represents the number of Ethernets required by the i-th device under test, f i It represents the number of multimeters required for the i-th device under test, g i It represents the number of A / D acquisition modules required by the i-th device under test, h i represents the number of oscilloscopes required for the i-th device under test, j i represents the number of signal generators required for the i-th device under test, k i It represents the number of D / A output modules required by the i-th device under test. i It represents the number of switches required for the i-th device under test; Step 23 is specifically as follows: first determine the maximum value among the quantities of various test resources required by all devices under test, and then add up all the maximum values ​​to obtain the maximum test requirement s.

5. The method according to claim 4, characterized in that Step 3 includes: Step 31: Based on the maximum test requirement s, calculate the number of test pins ST required for the test adapter test interface; Step 32: Calculate the number M of universal test connectors according to the number ST of test pins required for the test interface of the test adapter; Step 33: Evenly arrange one power test connector and M universal test connectors in the test adapter test interface.

6. The method according to claim 5, characterized in that In step 31, the formula for calculating the number of test pins ST required for the test adapter test interface is: In step 32, the formula for calculating the number M of universal test connectors is:

7. The method according to claim 5, characterized in that Step 4 includes: Step 41: S in Step 22 i Sort from small to large, and put the smallest S i The test resources required by the corresponding device under test are configured in the power test connector interface; Step 42: construct a mathematical model of the configured test resource pins in the test adapter; Step 43: Calculate the minimum difference SV between the test resources required by the remaining device under test and the test resources configured by the test adapter; Step 44: configure the remaining test resources required by the device under test corresponding to the minimum difference SV in the power test connector interface; if the number of pins of the power test connector is insufficient, arrange the remaining pins in the universal test connector; the power supply pins are designed in the power test connector interface; Step 45: Repeat steps 43 and 44 to configure the test resources required by all devices under test in the universal test connector interface.

8. The method according to claim 7, characterized in that The mathematical model of the configured test resource pins in the test adapter constructed in step 42 is: <h2 style=";text-align:left;direction:ltr">T=2a<h2 style=";text-align:left;direction:ltr"> t <h2 style=";text-align:left;direction:ltr"> +4b<h2 style=";text-align:left;direction:ltr"> t <h2 style=";text-align:left;direction:ltr"> +4c<h2 style=";text-align:left;direction:ltr"> t <h2 style=";text-align:left;direction:ltr"> +4d<h2 style=";text-align:left;direction:ltr"> t <h2 style=";text-align:left;direction:ltr"> +4e<h2 style=";text-align:left;direction:ltr"> t <h2 style=";text-align:left;direction:ltr"> +2f<h2 style=";text-align:left;direction:ltr"> t <h2 style=";text-align:left;direction:ltr"> +2g<h2 style=";text-align:left;direction:ltr"> t <h2 style=";text-align:left;direction:ltr"> +2h<h2 style=";text-align:left;direction:ltr"> t <h2 style=";text-align:left;direction:ltr"> +2j<h2 style=";text-align:left;direction:ltr"> t <h2 style=";text-align:left;direction:ltr"> +2k<h2 style=";text-align:left;direction:ltr"> t <h2 style=";text-align:left;direction:ltr"> +l<h2 style=";text-align:left;direction:ltr"> t <h2 style=";text-align:left;direction:ltr"> , Among them, a t ,b t ,c t ,d t ,e t ,f t ,g t ,h t ,j t ,k t ,l t They represent the configured test resources, including the power supply, serial bus, 429 bus, AFDX bus, Ethernet, multimeter, A / D acquisition module, oscilloscope, signal generator, D / A output module, and the number of switch pins. The initial values ​​are all 0. In step 43, SV = Min(S1, S2...S x ), Among them, S x It represents the difference between the test resources required by the remaining devices under test and the test resources configured by the test adapter. x is greater than 0 and less than or equal to Y. Y is the total number of remaining devices under test.

9. A test adapter, characterized in that: The test adapter is designed by the method described in any one of claims 1 to 8, and the test adapter includes a power test connector interface and a plurality of universal test connector interfaces, and the power test connector interface is connected to all devices under test; ATE is connected to the device under test through a test adapter to test the device under test.

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