A test adapter comprehensive design method and test adapter

Abstract

The application provides a test adapter comprehensive design method and a test adapter, and belongs to the technical field of helicopter airborne electronic system testing. In the test adapter comprehensive design method, the type and model of a test adapter test interface are determined first. Then, all test resources required by the tested equipment are classified, and the maximum test requirement required by the test adapter is determined. Then, the test adapter test interface is laid out based on the maximum test requirement. Then, the test resources are dynamically configured in the power supply test connector and the general test connector. Based on the interface design maximizing the test requirement, the test resource dynamic configuration is realized, the comprehensive capability of the test adapter is improved, and the development cost and maintenance cost of the ATE are reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of helicopter airborne electronic system test, and particularly relates to a test adapter comprehensive design method and a test adapter. BACKGROUND

[0002] The test adapter is a component of the helicopter comprehensive test platform ATE, and its function is to convert the exclusive signals of the device under test into common interface signals and transmit them to the ATE.

[0003] In the existing test adapter design method, the test adapter test interface layout and test resource arrangement are performed according to the communication (including power supply) interface of the device under test, the comprehensive degree of the test adapter is not high, the scale of the test adapter deployed by the ATE is large, and thus the development cost and maintenance cost of the ATE are increased. SUMMARY

[0004] In order to solve the technical problems of low comprehensive degree of the test adapter in the related art, high development cost and maintenance cost of the ATE, and the like, the present application provides a test adapter comprehensive design method, which is based on the interface design of maximum test demand, realizes dynamic configuration of test resources, improves the comprehensive ability of the test adapter, and reduces the development cost and maintenance cost of the ATE.

[0005] In a first aspect, a test adapter comprehensive design method is provided, and the method comprises the following steps:

[0006] Step 1: determining the type and model of the test adapter test interface;

[0007] Step 2: classifying all the test resources required by the device under test, and determining the maximum test demand required by the test adapter;

[0008] Step 3: based on the maximum test demand, performing layout design on the test adapter test interface;

[0009] Step 4: dynamically configuring the test resources in the power supply test connector and the general test connector.

[0010] In step 1, the following steps are included:

[0011] Step 11: taking the maximum test demand as input, and dividing the test adapter test interface into general test connector interfaces and power supply test connector interfaces which are consistent in size and appearance;

[0012] Step 12: determining the model of the general test connector interface and the power supply test connector interface.

[0013] In step 2, the following steps are included:

[0014] Step 21: divide the test resources into 11 categories, namely power supply, serial bus, 429 bus, AFDX bus, Ethernet, multimeter, A / D acquisition module, oscilloscope, signal generator, D / A output module and switch, and the number of pins corresponding to each test resource is (2, 4, 4, 4, 4, 2, 2, 2, 2, 2, 1);

[0015] Step 22: determine the number of test resources required by each device under test s i and the number of pins S i of the test resources;

[0016] Step 23: aggregate the test resources required by all devices under test to determine the maximum test requirement of the test adapter.

[0017] In step 22,

[0018] s i =a i +b i +c i +d i +e i +f i +g i +h i +j i +k i +l i

[0019] S i =2a i +4b i +4c i +4d i +4e i +2f i +2g i +2h i +2j i +2k i +l i

[0020] where i represents the ith device under test, i is greater than 0 and less than or equal to n, n is the total number of devices under test; a i represents the number of power supplies required by the ith device under test, b i represents the number of serial buses required by the ith device under test, c i represents the number of 429 buses required by the ith device under test, d i represents the number of AFDX buses required by the ith device under test, e i represents the number of Ethernet required by the ith device under test, f i represents the number of multimeters required by the ith device under test, gi represents the number of A / D acquisition modules required by the ith measured device, h i represents the number of oscilloscopes required by the ith measured device, j i represents the number of signal generators required by the ith measured device, k i represents the number of D / A output modules required by the ith measured device, l i represents the number of switches required by the ith measured device;

[0021] Step 23 is specifically: first determine the maximum value in the number of various test resources required by all measured devices, add all the maximum values to obtain the maximum test demand s.

[0022] Wherein, step 3 comprises:

[0023] Step 31: based on the maximum test demand s, calculate the number of test pins ST required by the test adapter test interface;

[0024] Step 32: according to the number of test pins ST required by the test adapter test interface, calculate the number of general test connectors M;

[0025] Step 33: evenly arrange 1 power test connector and M general test connectors in the test adapter test interface.

[0026] Wherein, in step 31,

[0027] ST = 2Max a + 4Max b + 4Max c + 4Max d + 4Max e + 2Max f

[0028] + 2Max g + 2Max h + 2Max j + 2Max k + Max l

[0029] In step 32,

[0030]

[0031] Optionally, step 4 comprises:

[0032] Step 41: sort S i in step 22 from small to large, and the smallest S i The corresponding test resources required by the measured device are configured in the power test connector interface;

[0033] Step 42: constructing a mathematical model of the configured test resource pins in the test adapter;

[0034] Step 43: calculating the minimum difference SV of the required test resources of the remaining DUTs and the configured test resources of the test adapter;

[0035] Step 44: configuring the test remaining resources required by the DUT corresponding to the minimum difference SV in the power test connector interface, if the number of power test connector pins is not enough, then arranging the remaining pins in the general test connector, wherein the power supply pins are designed in the power test connector interface.

[0036] Step 45: repeating steps 43 and 44 to configure all the test resources required by the DUTs in the general test connector interface.

[0037] Optionally, the mathematical model of the configured test resource pins in the test adapter constructed in step 42 is:

[0038] T = 2a t + 4b t + 4c t + 4d t + 4e t + 2f t + 2g t + 2h t + 2j t + 2k t + l t

[0039] Wherein, a t , b t , c t , d t , e t , f t , g t , h t , j t , k t , and l t respectively represent the pin number of the configured test resources including power supply, serial bus, 429 bus, AFDX bus, Ethernet, multimeter, A / D acquisition module, oscilloscope, signal generator, D / A output module, and switch, and their initial values are all 0.

[0040] In step 43, SV = Min (S1, S2…S x ),

[0041] S x = 2Max (a i -a t , 0) + 4Max (bi -b t ,0)+4Max(c i -c t ,0)+4Max(d i -d t ,0)+2Max(e i -e t ,0)+2Max(f i -f t ,0)

[0042] +2Max(g i -g t ,0)+2Max(h i -h t ,0)+2Max(j i -j t ,0)+2Max(k i -k t ,0)+Max(l i -l t ,0)

[0043] Wherein, S x represents the difference between the required test resources of each remaining device under test and the configured test resources of the test adapter, x is greater than 0 and less than or equal to Y, Y is the total number of remaining devices under test.

[0044] In a second aspect, a test adapter is provided, which is designed by the method of any one of the first aspect, and the adapter comprises a power test connector interface and a plurality of general test connector interfaces, the power test connector interface is connected with all devices under test.

[0045] The ATE is connected with the devices under test through the test adapter, and the devices under test are tested.

[0046] The test adapter comprehensive design method provided by the application comprises the following steps: first, determining the type and model of the test interface of the test adapter; then, classifying the required test resources of all devices under test, and determining the maximum test requirement of the test adapter; then, based on the maximum test requirement, the test interface of the test adapter is laid out and designed; then, the test resources are dynamically configured in the power test connector and the general test connector, based on the interface design of the maximum test requirement, the test resources are dynamically configured, the test interface of the test adapter is comprehensively designed, and the comprehensive capability of the test adapter is improved. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 A test adapter comprehensive design method flow chart is provided for the embodiments of the application.

[0048] Figure 2 A test adapter test interface schematic diagram is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0049] The present application is further described in detail by specific embodiments and drawings.

[0050] An embodiment of the present application provides a test adapter comprehensive design method, which takes maximum test requirements as input to comprehensively design the test adapter, as shown in the figure, the method comprises the following steps: Figure 1

[0051] Step 1: Determine the type and model of the test adapter test interface. Specifically, it includes:

[0052] Step 11: According to GJB 589A-1993 "General Specification for Environmental Resistant Quick Release Circular Electrical Connectors", taking maximum test requirements as input, the test adapter test interface is divided into general test connector interfaces and power test connector interfaces with the same size and appearance, as shown in the figure. Figure 2

[0053] Step 12: Determine the model of the general test connector interface and the power test connector interface, wherein the model of the general test connector interface is JY27505E25F35SX (key X can be N, A, B, C, D), and the model of the power test connector interface is JY27505E25F69SX (key X can be N, A, B).

[0054] Step 2: Classify all the test resources required by the devices under test to determine the maximum test requirements required by the test adapter. Specifically, it includes:

[0055] Step 21: Divide the test resources into 11 categories, including power (a), serial bus (b), 429 bus (c), AFDX bus (d), Ethernet (e), multimeter (f), A / D acquisition module (g), oscilloscope (h), signal generator (j), D / A output module (k), and switch (l). The pin number corresponding to each category of test resources is (2, 4, 4, 4, 4, 2, 2, 2, 2, 2, 1).

[0056] Step 22: Determine the number of test resources required by each device under test s i and the pin number of the test resources S i :

[0057] s i = a i + b i + c i + d i + e i + f i ​​+g i +h i +j i +k i +l i

[0058] S i =2a i +4b i +4c i +4d i +4e i +2f i +2g i +2h i +2j i +2k i +l i

[0059] Wherein, i represents the i-th measured device, i is greater than 0 and less than or equal to n, n is the total number of measured devices; a i represents the number of power supplies required by the i-th measured device, b i represents the number of serial bus required by the i-th measured device, c i represents the number of 429 bus required by the i-th measured device, d i represents the number of AFDX bus required by the i-th measured device, e i represents the number of Ethernet required by the i-th measured device, f i represents the number of multimeter required by the i-th measured device, g i represents the number of A / D acquisition module required by the i-th measured device, h i represents the number of oscilloscope required by the i-th measured device, j i represents the number of signal generator required by the i-th measured device, k i represents the number of D / A output module required by the i-th measured device, l i represents the number of switches required by the i-th measured device.

[0060] Step 23: Sum up the test resources required by all the devices under test, determine the maximum test requirement of the test adapter, specifically, first determine the maximum value of the number of each type of test resource required by all the devices under test, add all the maximum values to obtain the maximum test requirement s. For example, n is equal to 3, the number of power supplies required by the first device under test is 10, the number of power supplies required by the second device under test is 5, and the number of power supplies required by the third device under test is 7, so the maximum value of the number of power supplies is 10, and similarly, the number of other types of test resources such as serial bus, 429 bus, AFDX bus, and Ethernet is obtained, and 10 maximum values are obtained, and finally, the 11 maximum values are added to obtain the maximum test requirement s.

[0061] Step 3: Based on the maximum test requirement, layout design is performed on the test interface of the test adapter. Specifically, the following steps are included:

[0062] Step 31: Based on the maximum test requirement s determined in step 2, the number of test pins ST required by the test interface of the test adapter is calculated:

[0063] ST = 2Max(a i ) + 4Max(b i ) + 4Max(c i ) + 4Max(d i ) + 4Max(e i ) + 2Max(f i )

[0064] + 2Max(g i ) + 2Max(h i ) + 2Max(j i ) + 2Max(k i ) + Max(l i )

[0065] Step 32: According to the number of test pins ST required by the test interface of the test adapter, the number M of general test connectors determined in step 1 is calculated:

[0066]

[0067] Due to the panel layout limitation of the test adapter, M≤4; the power supply test connector has a maximum of 69 pins and is arranged at the XS1 position; the general test connector has a maximum of 128 pins, and each connector reserves a 10% margin, and is arranged at the XS2~XS(1+M) position, as shown in the following table. Figure 2

[0068] Step 33: 1 power supply test connector and M general test connectors are evenly arranged in the test adapter.

[0069] ​Step 4: Dynamically configure the test resources in the power test connector and the general test connector. Specifically includes:

[0070] Step 41: Calculate S i from small to large, the smallest S i The test resources required by the corresponding DUT are configured in the power test connector, so that the test resources required by the corresponding DUT are arranged in the power test connector (XS1 connector) in priority.

[0071] Step 42: Build a mathematical model T of the test resource pins configured in the test adapter.

[0072] T = 2a t + 4b t + 4c t + 4d t + 4e t + 2f t + 2g t + 2h t + 2j t + 2k t + l t

[0073] Wherein, a t , b t , c t , d t , e t , f t , g t , h t , j t , k t , l t respectively represent the pin number of the configured test resources including power (a), serial bus (b), 429 bus (c), AFDX bus (d), Ethernet (e), multimeter (f), A / D acquisition module (g), oscilloscope (h), signal generator (j), D / A output module (k), switch (l), and their initial values are 0;

[0074] Step 43: Calculate the minimum difference SV between the test resources required by the remaining DUT and the test resources configured in the test adapter:

[0075] SV = Min (S1, S2…S x ),

[0076] S x = 2Max (a i -a t , 0) + 4Max (b i -b t , 0) + 4Max (ci - c t , 0) + 4Max(d i - d t , 0) + 2Max(e i - e t , 0) + 2Max(f i - f t , 0)

[0077] + 2Max(g i - g t , 0) + 2Max(h i - h t , 0) + 2Max(j i - j t , 0) + 2Max(k i - k t , 0) + Max(l i - l t , 0)

[0078] wherein S x represents the difference between the test resources required by each of the remaining devices under test and the test resources configured by the test adapter, x is greater than 0 and less than or equal to Y, and Y is the total number of the remaining devices under test.

[0079] For example, Y is equal to 3, the test resources configured by the test adapter are (2, 3, 1, 0, 2, 0, 2, 0, 0, 0, 0), the test resources required by the first remaining device under test are (4, 3, 1, 0, 0, 0, 1, 0, 0, 0, 0), the test resources required by the second remaining device under test are (1, 1, 2, 0, 0, 0, 3, 0, 0, 0, 0), and the test resources required by the third remaining device under test are (3, 2, 2, 0, 3, 0, 0, 0, 0, 0, 0), then S1 is 4, S2 is 6, and S3 is 8. The S1-S3 are sorted to obtain the minimum difference SV, which is 4, and the corresponding is the first remaining device under test.

[0080] Step 44: configuring the test resources required by the device corresponding to the minimum difference SV in the XS1 connector. For example, the first remaining device under test requires 2 power supplies and 4 pins. The 4 pins are arranged in the XS1 connector. If the number is insufficient (10% excess is required), the remaining pins are arranged in the XS2 (universal test connector). The power supply pins must be designed in the XS1.

[0081] Step 45: repeating steps 43 and 44 to configure all the test resources required by the devices under test in the XS1-XS(1+M) connectors. M is the number of universal test connector interfaces.

[0082] The embodiment of the present application also provides a test adapter, which is designed by using the test adapter comprehensive design method provided by the method embodiment of the present application. The test adapter comprises a power supply test connector interface and a plurality of general test connector interfaces, the power supply test connector interface is connected with all the devices under test, and the ATE is connected with the devices under test through the test adapter to test the devices under test.

[0083] The embodiment of the present application improves the comprehensive design level of the test adapter by comprehensively designing the test adapter, greatly reduces the number of test adapters, compresses the deployment scale of the ATE, optimizes the wiring relationship of the test adapter, simplifies the internal structure, and reduces the development cost and maintenance cost of the ATE.

[0084] The above only expresses the embodiments of the present application, the description is more specific and detailed, but cannot be understood as the limitation of the patent scope. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which all belong to the protection scope of the present application. In addition, the part not described in the present application is the conventional technology.

Claims

1. A test adapter synthesis design method, characterized by, The method comprises: Step 1: determining the type and model of the test adapter test interface; Step 2: classifying all the test resources required by the devices under test, and determining the maximum test requirement required by the test adapter; Step 3: based on the maximum test requirement, designing the layout of the test adapter test interface; Step 4: dynamically configuring the test resources in the power supply test connector and the general test connector; Step 2 comprises: Step 21: dividing the test resources into 11 categories, i.e. power supply, serial bus, 429 bus, AFDX bus, Ethernet, multimeter, A / D acquisition module, oscilloscope, signal generator, D / A output module, and switch, and the number of pins corresponding to each category of test resources is (2, 4, 4, 4, 4, 2, 2, 2, 2, 2, 1); Step 22: Determine the number of test resources s required for each device under test i and the number of pins s of the test resources i ; Step 23: summarizing all the test resources required by the devices under test, and determining the maximum test requirement required by the test adapter; In step 22, the number s of test resources required for each of the devices under test is determined i The formula is: , determining the number of pins S of test resources required for each device under test i The formula is: , Wherein, i represents the i-th measured device, i is greater than 0 and less than or equal to n, n is the total number of measured devices; a i represents the number of power supplies required by the i-th measured device, b i represents the number of serial bus required by the i-th measured device, c i represents the number of 429 bus required by the i-th measured device, d i represents the number of AFDX bus required by the i-th measured device, e i represents the number of Ethernet required by the i-th measured device, f i represents the number of multimeter required by the i-th measured device, g i represents the number of A / D acquisition module required by the i-th measured device, h i represents the number of oscilloscope required by the i-th measured device, j i represents the number of signal generator required by the i-th measured device, k i represents the number of D / A output module required by the i-th measured device, l i represents the number of switches required by the i-th measured device; Step 23 specifically comprises: first determining the maximum value in the number of each category of test resources required by all the devices under test, and then adding all the maximum values to obtain the maximum test requirement s.

2. The method of claim 1, wherein, Step 1 comprises: Step 11: dividing the test adapter test interface into the general test connector interface and the power supply test connector interface which are uniform in size and appearance, with the maximum test requirement as the input; Step 12: determining the model of the general test connector interface and the power supply test connector interface.

3. The method of claim 1, wherein, Step 3 comprises: Step 31: based on the maximum test requirement s, calculating the number ST of test pins required by the test adapter test interface; Step 32: according to the number ST of test pins required by the test adapter test interface, calculating the number M of general test connectors; Step 33: evenly arranging 1 power supply test connector and M general test connectors in the test adapter test interface.

4. The method of claim 3, wherein, In step 31, the formula for calculating the number ST of test pins required by the test adapter test interface is: ， In step 32, the formula for calculating the number M of general test connectors is: 。 5. The method of claim 3, wherein, Step 4 comprises: Step 41 : S i From small to large order, the smallest S i The corresponding test resource configuration required by the device under test is configured in the power test connector interface; Step 42: constructing a mathematical model of the configured test resource pins in the test adapter; Step 43: calculating the minimum difference SV between the test resources required by the remaining devices under test and the configured test resources of the test adapter; Step 44: configuring the remaining test resources required by the devices under test corresponding to the minimum difference SV in the power supply test connector interface; if the number of pins of the power supply test connector is insufficient, the remaining pins are arranged in the general test connector; the power supply pin is designed in the power supply test connector interface; Step 45: repeating steps 43 and 44 to configure all the test resources required by the devices under test in the general test connector interface.

6. The method of claim 5, wherein, The mathematical model T of the configured test resource pins in the test adapter constructed in step 42 is: ， Wherein, Respectively, the configured test resources, including power, serial bus, 429 bus, AFDX bus, Ethernet, multimeter, A / D acquisition module, oscilloscope, signal generator, D / A output module, the pin number of switch, the initial value of which is 0; In step 43, , where S x represents the difference between the test resources required by the remaining devices under test and the test resources configured by the test adapter, x is greater than 0 and less than or equal to Y, Y is the total number of devices under test remaining, 。 7. A test adapter, characterized by The test adapter is designed by the method of any one of claims 1 to 6, and comprises one power supply test connector interface and a plurality of general test connector interfaces, wherein the power supply test connector interface is connected with all the devices under test; The ATE is connected with the devices under test through the test adapter to test the devices under test.

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