Used for satellite-borne multi-channel electromagnetic signal pre-detection recording system

Abstract

The embodiment of this specification provides a satellite-borne multi-channel electromagnetic signal pre-detection recording system, which includes: a channel management module for acquiring payload electromagnetic signals, and allocating channel units and AD conversion parameters to electromagnetic signals through FPGA; a data cache module for collecting electromagnetic signals according to AD conversion parameters through FPGA to determine initial data, and cache the initial data for the first time to determine primary cache data, and cache the primary cache data for the second time according to the data type to determine secondary cache data; a data storage module for storing secondary cache data to a hard disk through FPGA, and sending data information of the secondary cache data to MCU to establish a data index. By using a single-chip FPGA as the core chip and integrating all functional units of the pre-detection equipment on a circuit board, the pre-detection equipment is lightweight and miniaturized, and can be easily installed on satellite equipment.

Description

Technical Field

[0001] The embodiments of this specification relate to the field of satellite communication technology, and in particular to a satellite-borne multi-channel electromagnetic signal pre-detection recording system. Background Art

[0002] With the development of satellite technology, a large number of satellites have been launched and put into use. These satellites are equipped with various electronic devices. These electronic devices will send various forms of electromagnetic signals. Some of these signals are actively sent, such as communication signals, and some are electromagnetic signal leakage. All of these signals constitute the electromagnetic characteristics of the satellite. Recording these electromagnetic characteristics and analyzing and studying them is of great value to the application of satellite technology.

[0003] The pre-test recording device is used to record the intermediate frequency signal after the original electromagnetic signal is down-converted. It directly samples the intermediate frequency signal, stores it directly into the hard disk after simple processing, and provides the most original data for subsequent research and analysis. The pre-test recording device does not process the data in any way, and the original data retains all information features during the recording process. By analyzing these data, researchers can extract various information features according to their needs, and provide specific and accurate suggestions for problem analysis, design improvement or confrontation of electronic load equipment.

[0004] The core technology of pre-inspection recording equipment lies in the sampling and storage of high-speed data. The intermediate frequency of high-speed data is mostly 1.2G. The pre-inspection recording equipment directly samples the intermediate frequency signal, has a fast sampling speed, and the sampling speed is usually between 200MHz~10GHz, and the sampling resolution is between 8~16Bit. After sampling, the recorded data flow speed is 4Gbps~60Gbps, and the amount of recorded data is between 500GB~8TB. In order to solve the problem of high data flow speed and large data volume of pre-inspection recording equipment, traditional pre-inspection recording equipment adopts a chassis plug-in card architecture, inserting the data acquisition card, hard disk storage card, and host card into an industrial control chassis, and the host performs data scheduling and management. Equipment with such an architecture is heavy, large in size, high in power consumption, low in earthquake resistance, and cannot be loaded on satellites.

[0005] Therefore, a better solution is urgently needed. Summary of the invention

[0006] In view of this, the embodiments of this specification provide a satellite-borne multi-channel electromagnetic signal pre-detection recording system to solve the technical defects existing in the prior art.

[0007] According to a first aspect of an embodiment of this specification, a system for pre-detection recording of satellite-borne multi-channel electromagnetic signals is provided, comprising:

[0008] The channel management module is used to obtain the electromagnetic signal of the payload and allocate channel units and AD conversion parameters to the electromagnetic signal through FPGA;

[0009] A data cache module is used to collect data of electromagnetic signals according to AD conversion parameters through FPGA to determine initial data, cache the initial data for the first time to determine primary cache data, and cache the primary cache data for the second time according to the data type to determine secondary cache data;

[0010] The data storage module stores the secondary cache data to the hard disk through the FPGA, and sends the data information of the secondary cache data to the MCU to establish a data index.

[0011] In a possible implementation, it also includes a data playback module;

[0012] The data playback module is used to receive the data return instruction from the satellite computer through the MCU, determine the data location through the data index based on the data return instruction, and send the data location to the FPGA; the FPGA determines the target data according to the data location and returns the target data.

[0013] In a possible implementation, the data cache module includes a decision unit and a transmission control unit;

[0014] A decision unit, used for receiving the application information cached for the second time, determining a decision result of the application information according to the priority, and sending the decision result to the transmission control unit;

[0015] The transmission control unit is used to determine the target primary cache data according to the decision result, and perform secondary cache on the target primary cache data to determine the secondary cache data.

[0016] In a possible implementation, the data cache module includes a secondary cache area;

[0017] A secondary cache area, used for storing secondary cache data;

[0018] The secondary buffer area includes at least two data type buffer areas, and any data type buffer area of ​​the at least two data type buffer areas is used to store data of the same type.

[0019] In one possible implementation, the data storage module includes a storage controller;

[0020] The storage controller is used to number the hard disks and hard disk stripes.

[0021] In a possible implementation, the storage controller includes a data write control interface; the data write control interface is an AXIS interface;

[0022] The data write control interface is used to obtain the data addressing number of the data to be written, store the target secondary cache data from the secondary cache area to the current storage position of the hard disk based on the data addressing number, and change the storage position indication value of the hard disk.

[0023] In a possible implementation, after writing the target data block to the first hard disk, the storage controller changes the current storage location to the second hard disk, so that the next data block of the target data block is written to the second hard disk.

[0024] In a possible implementation, the storage controller includes a data readout control interface; the data readout control interface is an AXIS interface;

[0025] The data read control interface is used to determine the read stripe number of the data to be read, and read the target hard disk data into the secondary cache area based on the read stripe number.

[0026] In a possible implementation, the method further includes:

[0027] The decision unit is used to receive a data storage request from the secondary cache area, determine a decision result of the data storage request according to a priority, and send the decision result to the storage controller through a data write control interface.

[0028] In a possible implementation, the data storage module includes a FLASH module;

[0029] FLASH module, used to store data index.

[0030] The embodiment of this specification provides a satellite-borne multi-channel electromagnetic signal pre-detection recording system, which includes: a channel management module for acquiring payload electromagnetic signals, and allocating channel units and AD conversion parameters to electromagnetic signals through FPGA; a data cache module for collecting electromagnetic signals according to AD conversion parameters through FPGA to determine initial data, and cache the initial data for the first time to determine primary cache data, and cache the primary cache data for the second time according to the data type to determine secondary cache data; a data storage module for storing secondary cache data to a hard disk through FPGA, and sending data information of the secondary cache data to MCU to establish a data index. By using a single-chip FPGA as the core chip and integrating all functional units of the pre-detection equipment on a circuit board, the pre-detection equipment is lightweight and miniaturized, and can be easily installed on satellite equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is an architecture diagram of a satellite-borne multi-channel electromagnetic signal pre-detection recording system provided by an embodiment of this specification;

[0032] Figure 2 This is a hardware structure diagram of a satellite-borne multi-channel electromagnetic signal pre-detection recording system provided by an embodiment of this specification;

[0033] Figure 3 It is a data decision diagram for a satellite-borne multi-channel electromagnetic signal pre-detection recording system provided by an embodiment of the present specification;

[0034] Figure 4 It is a schematic diagram of a secondary buffer area for a satellite-borne multi-channel electromagnetic signal pre-detection recording system provided by an embodiment of the present specification;

[0035] Figure 5 It is a schematic diagram of a circular queue for a satellite-borne multi-channel electromagnetic signal pre-detection recording system provided by an embodiment of the present specification;

[0036] Figure 6 It is a schematic diagram of a storage controller for a satellite-borne multi-channel electromagnetic signal pre-detection recording system provided by an embodiment of the present specification;

[0037] Figure 7 It is a schematic diagram of a primary data cache for a satellite-borne multi-channel electromagnetic signal pre-detection recording system provided by an embodiment of this specification;

[0038] Figure 8 It is a schematic diagram of a secondary cache for a satellite-borne multi-channel electromagnetic signal pre-detection recording system provided by an embodiment of the present specification. DETAILED DESCRIPTION

[0039] Many specific details are described in the following description to facilitate a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of this specification, so this specification is not limited to the specific implementation disclosed below.

[0040] The terms used in one or more embodiments of this specification are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of this specification. The singular forms of "a" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0041] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of this specification, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0042] In this specification, a satellite-borne multi-channel electromagnetic signal pre-detection recording system is provided, which is described in detail one by one in the following embodiments.

[0043] See also Figure 1 , Figure 1 The following is an architecture diagram of a satellite-borne multi-channel electromagnetic signal pre-detection recording system provided according to an embodiment of the present specification, which specifically includes the following modules.

[0044] The channel management module is used to obtain the electromagnetic signal of the load and allocate channel units and AD conversion parameters to the electromagnetic signal through FPGA; the data cache module is used to collect data of the electromagnetic signal according to the AD conversion parameters through FPGA to determine the initial data, and cache the initial data for the first time to determine the primary cache data, and cache the primary cache data for the second time according to the data type to determine the secondary cache data; the data storage module stores the secondary cache data to the hard disk through FPGA, and sends the data information of the secondary cache data to the MCU to establish a data index.

[0045] Among them, FPGA is a programmable logic array that can process multiple functional modules in parallel. High-performance FPGA chips also integrate multiple functional high-speed data interfaces. These high-speed interfaces are packaged into multiple high-speed data transmission functional modules, such as GTX, PCIE, etc., with Serdes as the core module. With this type of FPGA as the core chip, the high-speed data interface resources of FPGA are fully utilized to realize the physical interface of high-speed data acquisition and the physical interface of high-speed data transmission. At the same time, the general logic resources of FPGA are used to realize the scheduling and management of high-speed data flow and the establishment of indexes. The index data is transmitted to the FLASH MCU through the EMIF interface. System management and process control, as well as the sending and receiving of measurement and control data are completed by the FLASH MCU. All devices can be arranged on a very small circuit board to realize the lightweight and miniaturized design of pre-inspection equipment.

[0046] The embodiments of this specification support the input of multiple data payloads and the output of multiple data channels. And support multiple modes of data transmission. The payload data can be saved first, and then read out from the hard disk and transmitted back when conditions permit, or it can be directly transmitted without going through the storage process. When there are multiple transmission requirements, the actual transmission process is executed according to the priority rules specified by the user. To achieve these complex user requirements, the scheduling function of the device must be able to reasonably schedule and allocate system resources according to user requirements. The embodiments of this specification use FPGA general logic and design a resource allocation module with a multi-priority allocation / rotation mechanism to balance the allocation between user requirements and system resources. The priority of each requirement can be dynamically allocated by the MCU in order to meet the various needs of users with maximum flexibility.

[0047] Furthermore, satellite payloads are used in outer space. Electronic components are irradiated by high-energy particle flows in outer space. Irradiation by these particle flows may cause failure or damage of electronic components. In order to adapt to this use environment, the satellite management chip adopts a FLASH-type MCU and an automotive-grade chip. The program memory, data memory, and internal bus of the automotive-grade MCU chip are reinforced with ECC error control, which can effectively resist errors caused by single-particle flips and improve the reliability of the equipment under outer space conditions. The information exchange between the MCU and the FPGA uses the EMIF interface. The embodiment of this specification has made some improvements to the EMIF data access process and increased the data access speed. The embodiment of this specification adopts a cooling structure, and the housing of the heat-generating component is directly connected to the device housing through a thermally conductive material, and the housing is directly mounted on the satellite structure. In this way, the heat emitted by the pre-inspection equipment can be radiated through the satellite housing. Effective heat dissipation has been achieved, and the temperature of the core components has been kept within the operating temperature range.

[0048] In practical applications, see Figure 1 , this architecture can run on FPGA and MCU. The FPGA firmware completes the underlying functions such as channel management, ADC configuration and management, data cache, NVMe read and write protocol implementation, data flow transmission process control and arbitration, data transmission control, etc. The MCU firmware completes the reception, storage, data retrieval, read and write process control, telemetry, remote control data processing and distribution, and general platform management functions of index data. Specifically, it includes the following functions:

[0049] Channel management: FPGA configures the parameters of each channel unit and AD conversion chip according to the characteristics of the electromagnetic signal to meet the needs of data acquisition.

[0050] Data acquisition and caching: FPGA starts AD data acquisition, and the acquired data is transmitted to FPGA for the first framing and caching, and then stored in the corresponding secondary cache (DDR4) area according to different data types.

[0051] Data storage: When the amount of a certain type of data is larger than the size of an SSD stripe (chunk), the storage management module sends a storage request to the storage function module, and the storage function module stores the corresponding data in the hard disk (SSD). The data type, storage location, and storage time are sent to the MCU through EMIF. After receiving this data, the MCU stores it in FLASH as index data for data retrieval. The data storage operation is completed.

[0052] For further information, see Figure 2 The hardware architecture of the embodiment of this specification includes an FPGA, a Flash MCU, 2 groups of DDR4, and a group of AD conversion chips.

[0053] Specifically, high-speed analog-to-digital conversion is performed through an AD conversion chip, and electromagnetic signals are converted to high-speed AD, with a sampling rate of 1G to tens of G. The interfaces include LVDS, 204B, and 204C, which are directly connected to the FPGA, and the sampled data is directly sent to the FPGA for processing.

[0054] FPGA: FPGA is the core chip of the onboard pre-inspection equipment and provides hardware support for the physical layer of the onboard pre-inspection equipment. FPGA is composed of programmable logic devices and is configured with some high-speed data interfaces with specific functions. The high-speed interfaces configured by FPGA are divided into two types according to their functions: general GTX and PCIE, which are responsible for receiving and sending high-speed data streams between FPGA and external functional components. An FPGA is equipped with multiple groups of GTX and PCIE interfaces, which can be configured into different modes and perform different functions as needed in the onboard storage equipment.

[0055] General GTX can be used for the physical layer of JESD204 protocol IP and complete high-speed data physical layer communication with high-speed AD devices. JESD204 high-speed AD devices are common data output protocols, and their physical layer electrical interface adopts the GTX standard. High-speed AD sends sampled data to FPGA through the GTX interface. The maximum speed of GTX is determined by the type of GTX. The commonly used GTH can reach up to 16.5GHz per channel.

[0056] GTX can also be used as the physical layer of multiple common data transmission equipment communication protocols to complete the data transmission of readback data / real-time data to the transmitter.

[0057] The storage medium of the onboard pre-inspection equipment uses a solid-state drive (SSD) based on the NVMe protocol. NVMe is a high-speed data communication protocol for solid-state drives, and the physical layer of NVMe is the PCIE interface. Considering the universality of the chip, the pre-inspection equipment uses PCIE3.0 as the physical interface of the solid-state drive. 4 channels of PCIE3.0 (4×PCIE) can connect a hard drive.

[0058] The peak access speed of a single hard disk does not exceed 2.8GB / s, which cannot meet the needs of pre-inspection records. Satellite pre-inspection records use multiple hard disks to form RAID to solve this problem. Generally, there are multiple groups of PCIE QUAD on the FPGA, which consists of 4 channels of PCIE (4×PCIE), and one hard disk can be connected. Through reasonable options, one FPGA can connect 3~5 hard disks. Combining these hard disks into a RAID can not only improve the access speed of the hard disk, but also expand the capacity of the hard disk. The working access speed of the hard disk with 4 disks can reliably reach 5GB / s, which meets the requirements of pre-inspection records.

[0059] The onboard pre-inspection equipment uses a FLASH MCU as the management unit of the onboard pre-inspection equipment. The FLASH MCU has a relatively good radiation resistance. The onboard FLASH MCU uses dual-core comparison operation, and its program storage area, data storage area, memory, and internal bus are all ECC reinforced. The MCU and FPGA use an EMIF interface, which is simple and efficient. These measures can effectively improve the reliability of onboard storage equipment under outer space conditions.

[0060] In a possible implementation, it also includes a data playback module; the data playback module is used to receive the data return instruction of the star service computer through the MCU, determine the data position through the data index based on the data return instruction, and send the data position to the FPGA; the FPGA determines the target data according to the data position, and returns the target data.

[0061] In practical applications, see Figure 1 The data playback function of this architecture is as follows: the MCU receives the instruction from the satellite computer, reads out the specified data and transmits it back as required. The MCU first retrieves the index data, selects the storage location of the data that meets the requirements, transmits the address to the FPGA in sequence through the EMIF interface, and issues a read instruction. After receiving the address and instruction, the FPGA reads out the data according to the address and stores it in the buffer. Then it is sent to the data using device, such as a transmitter.

[0062] In one possible implementation, the data cache module includes a decision unit and a transmission control unit; the decision unit is used to receive application information for the second cache, determine a decision result of the application information according to a priority, and send the decision result to the transmission control unit; the transmission control unit is used to determine the target primary cache data according to the decision result, and perform secondary caching on the target primary cache data to determine the secondary cache data.

[0063] In practical applications, see Figure 3 , Level 1 cache: The high-speed collected data is input into the FPGA in the form of data stream, and the level 1 cache unit performs preliminary sorting and framing of the data to normalize the data. The main functions are:

[0064] Data stream bit width management converts the ADC signal input data stream into a common bit width for FPGA firmware transmission after splicing, folding, etc., which is generally 2^n bit width. After bit width processing, the sampled data stream structure is compact, which improves transmission and storage efficiency.

[0065] Insert additional data information: insert frame header flag, frame tail flag, data type flag, timestamp, frame sequence number, file number and other storage feature flags. Inserting these flags increases the reliability of data storage. Once the index file is damaged, the data index can be restored by storing additional data flags. Including frame header and frame tail, the data frame length is 2^n Byte (usually 1024 Byte).

[0066] The cache area is constructed with block RAM, and its length is generally 2^m (m>n). The first-level cache adopts a circular queue data structure, and uses a head pointer (bit width of m bits) and a tail pointer (bit width of m bits) to indicate the state of the buffer. Whenever a data is stored in the cache area, the tail pointer increases by 1, and when the effective length in the frame is greater than the frame length, the cache area applies to the first-level transmission arbitration module. After permission, a frame of data is transmitted to a specific location in the second-level cache area, and the frame head pointer increases by a frame length. The entire buffer area works in Producer-Consumer mode. Compared with the traditional ping-pong structure, the utilization granularity of the cache area is finer and more efficient.

[0067] Arbiter architecture: Before onboard inspection, the device can record multiple electromagnetic signals at the same time, and each electromagnetic signal has its own independent first-level cache unit. When the effective data length of multiple first-level caches is greater than the frame length at the same time, the conditions for transmitting the second-level cache are met, and an arbiter is needed to decide which first-level cache to perform the transmission operation. The arbiter classifies the application signals according to priority and sub-priority. Applications with high priority will be given priority; applications with higher sub-priority among the same priority will be given priority; applications with the same sub-priority will be allowed in a round-robin manner (round robin). Figure 3This is a schematic diagram of the principle of first-level cache and data transmission. In the figure, each first-level cache has an application signal line connected to the arbiter. When the data in the cache exceeds one frame, the cache sends a transmission request to the arbiter. When the arbiter receives one or more requests, it decides which signal to perform the transmission operation according to the user-specified arbitration rule. The permission signal answers the relevant application unit through the Ack signal. The arbitration result is sent to the transmission control unit at the same time. The transmission control unit controls the DataMover to transfer the data in the relevant first-level cache to the second-level cache area. The arbiter unit is directly constructed with combinational logic circuits, and the arbitration result can be obtained in just one clock cycle, reducing the time overhead of the arbitration. This is particularly important in high-speed transmission. The arbiter unit completes the complex and highly customized arbitration rules with an independent module programming, which is independent of the specific business, and realizes the decoupling of arbitration and business processes, making the firmware programming structure clear and well-organized, and improving the reliability of the firmware.

[0068] For further information, see Figure 4 , Secondary cache: The secondary cache is mainly set up to meet the requirements of high-speed data access of onboard pre-inspection equipment. The minimum data granularity managed by the solid-state hard disk is a stripe (chunk), and the size of the stripe is determined by the model of the hard disk. The stripe size of commonly used hard disks is between 128K and 1024K. Data is cached before storage. When the secondary cache data of a certain data type is greater than or equal to the stripe size, the storage control unit performs a physical storage operation. Reading the disk is the same principle. Each read operation reads a stripe of data into the read-out cache area, and then the application layer reads it out from the cache area.

[0069] Data storage and retrieval operations must go through the secondary data buffer, and data access at the application layer must also read data through the secondary cache area. The secondary data cache area must have a large enough capacity and a high enough speed to meet the requirements. The capacity and speed of the secondary cache area are one of the key factors that restrict the performance of pre-inspection equipment. The embodiment of this specification uses 2 groups of 64-bit DDR4 as the physical devices of the secondary cache area. The peak access speed of DDR reaches 38.4GB / s, which meets the performance requirements of high-bandwidth pre-inspection equipment.

[0070] See also Figure 1 , the connection between the secondary cache area and its access device includes the following:

[0071] Hard disk: connected through NVMe / AXI bridge, the access speed depends on the hard disk model. For NVMe hard disk based on PCIE3.0, the one-way access speed is about 2.5GB / s. Each hard disk is bidirectionally accessed, corresponding to the read and write operations of the hard disk. The overall access speed is positively correlated with the number of hard disks.

[0072] Data migration module (DataMover): accesses the secondary cache in bidirectional mode. The write operation corresponds to moving data from the primary cache to the secondary buffer area. The maximum unidirectional access speed is determined by the clock speed and bit width of the DataMover, which is usually around 4GB / s. In actual applications, due to protocol overhead, it can only reach around 3.2GB / s. In order to achieve higher storage speed, a dual DataMover architecture and a higher frequency clock are generally used. The read operation corresponds to the application layer (App) moving data from the read cache area to the data terminal device (such as a transmitter). In theory, the read speed is the same as the write speed, and in actual use it is related to the bandwidth of the data terminal device.

[0073] DDR4 works in single-port mode. When multiple modules require access to DDR at the same time, the firmware management uses time-division to allocate access to DDR for each module. The specific allocation of DDR resources is completed by the arbitration-allocation module. The arbitration allocation module is embedded in the switch module of the AXI bus. The design of the arbiter is basically the same as the unit mentioned above.

[0074] In one possible implementation, the data cache module includes a secondary cache area; the secondary cache area is used to store secondary cache data; the secondary cache area includes at least two data type cache areas, and any data type cache area of ​​the at least two data type cache areas is used to store data of the same type.

[0075] In practical applications, see Figure 5 The secondary cache uses a multi-type circular queue data structure. Each application functional unit has its own independent buffer, and each type of buffer is managed using a circular queue data structure. The depth of these data structures is the size of a stripe. times, to facilitate the hard disk read and write operations. Such a data structure allows all data of the same type to be recorded in one stripe, facilitating data retrieval and improving storage efficiency. All secondary cache areas are uniformly numbered according to the stripe granularity. As shown in the figure, each buffer has 8 stripes (it can also be 16, 32, 64... can be reasonably set as needed). The buffers for data 0 are numbered 0, 1, 2~7, the buffers for data 1 are 8, 9, 10~15, and so on. This addressing method is to facilitate data addressing of the storage control unit.

[0076] In a possible implementation, the data storage module includes a storage controller; the storage controller is used to number the hard disks and the hard disk stripes. The storage controller includes a data write control interface; the data write control interface is an AXIS interface; the data write control interface is used to obtain the data addressing number of the data to be written, store the target secondary cache data from the secondary cache area to the current storage location of the hard disk based on the data addressing number, and change the storage location indication value of the hard disk. After writing the target data block into the first hard disk, the storage controller changes the current storage location to the second hard disk so that the next data block of the target data block is written into the second hard disk. The storage controller includes a data read control interface; the data read control interface is an AXIS interface; the data read control interface is used to determine the read stripe number of the data to be read and read the target hard disk data into the secondary cache area based on the read stripe number. The arbitration unit is used to receive the data storage request in the secondary cache area, determine the arbitration result of the data storage request according to the priority, and send the arbitration result to the storage controller through the data write control interface. The data storage module includes a FLASH module; the FLASH module is used to store data indexes.

[0077] In practical applications, refer to Figure 6 , storage controller: The hard disk controller adopted in the embodiments of this specification implements data access based on the NVMe protocol. The NVMe protocol is the latest hard disk access control protocol. The physical layer of NVMe uses a PCIe interface and utilizes the high-speed data transmission capability of PCIe to achieve high-speed data storage. The NVMe protocol is implemented using an FPGA and further encapsulated. The encapsulated control interface is simple and easy to use and is seamlessly connected to the data circular queue structure in the secondary cache area.

[0078] Among them, the red arrow (AXIS WRITE) is the disk write control protocol interface, the green arrow (AXIS READ) is the disk read control protocol interface, the yellow arrow is the index data interface, PCIe is the hard disk physical interface, and AXIMM is the data access interface. The detailed functions of the storage controller are as follows:

[0079] Organization of hard disk storage locations: The basic unit of hard disk storage locations is a stripe (chunk), and the size of the stripe is determined by the specific model of the hard disk. In the embodiments of this specification, all hard disks have unified stripe numbering. If there are a total of n hard disks in the pre-examination recording device, numbered 0, 1, 2,..., n - 1, then the stripe numbers are 0, 1,..., n - 1, n, n + 1,.... Among them, the 0th, nth, 2*nth, 3*nth... stripes belong to the 0th hard disk; the 1st, n + 1st, 2*n + 1st, 3*n + 1st... belong to the 1st hard disk; the mth (m < n), n + mth, 2*n + mth, 3*n + mth... stripes belong to the mth hard disk; and so on, all hard disk storage locations are uniformly numbered.

[0080] Each time a storage process is initialized, the storage management unit sets the location stripe number for the next data storage through the configuration interface.

[0081] Data write control interface: In the embodiment of this specification, the write control interface is encapsulated into an AXIS data interface, which consists of four lines, AXIS_TVALID, AXIS_TREADY, AXIS_TDATA, and AXIS_TLAST (optional). AXIS_TDATA is the data address number of the secondary cache area, and AXIS_TVALID and AXIS_TREADY are the handshake signals for flow control. When AXIS_TVALID and AXIS_TREADY are both high, it means that a write instruction is successfully transmitted. The storage controller writes the data block in the secondary cache area specified by AXIS_TDATA to the current storage location of the SSD, and the current storage location of the SSD is incremented by 1.

[0082] Data write control process: When the amount of data in one or more cache data areas of the secondary data cache unit is greater than one stripe, the cache unit sends a storage request to the arbitrator, and the arbitrator decides which specific request is allowed to perform the storage operation. The arbitrator sends the storage instruction to the storage controller through the write control interface (AXIS WRITE). When the data is transferred from the secondary cache area to the hard disk cache area (on the actual hard disk), the hard disk controller generates index data, executes the next storage operation, and releases the secondary cache area where the data block has been written to the hard disk.

[0083] Parallel sequential storage: The data writing process only writes the stored data to the hard disk cache (on the actual hard disk). After the hard disk receives the data to the hard disk cache, it takes some time to write the data in the cache to the actual physical medium. In actual operation, the data transmission time is very short, and the time to write the physical medium (flash) is relatively long. In the storage process of the embodiment of this specification, after writing a data block (actually just the transmission is completed), the write position stripe number is increased by 1, and the write position is set on another hard disk (see the hard disk addressing rules), so that there is no need to wait for the previous hard disk to write the medium to complete and directly execute the data write instruction (actually data transmission), and so on to execute the write operation instructions of the 2nd to n-1th hard disks. In the process of hard disk storage in the embodiment of this specification, the data transmission process and the process of storing data in the physical medium are parallel, which greatly improves the storage speed of the hard disk. The organizational structure of the hard disk in the embodiment of this specification enables the multi-hard disk configuration to not only expand the storage capacity, but also improve the storage speed, meeting the functional requirements of high-speed storage of pre-onboard inspection equipment.

[0084] Circular storage: When the storage location reaches the stripe number with maximum capacity, storage automatically starts from the beginning to achieve first-in, first-out data storage.

[0085] Generation and storage of index data: When a storage process is completed, the storage management unit will notify the storage management unit of the current write position. The storage management unit combines the storage position and other management parameters, generates index data, and stores the index data in the index storage device. In the embodiment of this specification, the index storage device uses an independent flash device. The index data is stored and read in a three-mode manner. This design ensures that the hard disk operation is not affected by the reading and writing of the index data, and ensures the reliability of the index data.

[0086] Data read control interface: In the embodiment of this specification, the read control interface is encapsulated into an AXIS data interface, which consists of four lines, AXIS_TVALID, AXIS_TREADY, AXIS_TDATA, and AXIS_TLAST (optional). AXIS_TDATA reads the stripe number of the hard disk location, and AXIS_TVALID and AXIS_TREADY are handshake signals for flow control. When AXIS_TVALID and AXIS_TREADY are both high, it means that a read instruction is successfully transmitted. The storage controller reads the data at the hard disk storage location specified by AXIS_TDATA into the secondary cache area.

[0087] Data readout process: the satellite computer gives the conditions for reading data, the storage management unit retrieves the index according to the conditions, combines the stripe numbers of the storage data that meet the conditions into one data, and reads the data in these stripe numbers into the readout data cache area in the secondary cache unit in sequence through the data readout interface. Wait for the app to read the data from the secondary cache as needed.

[0088] Data management interface unit: In the embodiments of this specification, an automotive-grade MCU is used as the core component of the management unit of the satellite-borne pre-inspection equipment. The automotive-grade MCU operates in a dual-core comparison mode. Both the peripheral unit and the internal bus are equipped with an ECC error correction unit, which has a high degree of operational reliability.

[0089] The MCU and FPGA use the EMIF interface to exchange data. The FPGA firmware converts the data of the EMIF interface into the interface signal of the FPGA, and realizes the instruction transmission and status reporting between the MCU and FPGA.

[0090] In the embodiments of this specification, the communication between the FPGA firmware and the MCU is performed in a double buffer mode. When performing multi-cycle read and write operations, the double buffer architecture can ensure the integrity of multi-byte data access and the correctness of data transmission.

[0091] For further information, see Figure 7 ,From the first-level data flow diagram, we can see that the main function of the first-level cache is to sort the data bit width, group the frames, and store the grouped frames in the designated second-level cache area in sequence. Data transmission is achieved by DataMover. The allocation of transmission resources is completed by the arbitrator.

[0092] For further information, see Figure 8 ,The flow chart of the secondary cache and storage process,The function of the secondary cache is to classify and centralize data types,and store the same data types in a continuous memory block to prepare for data storage.,When the disk writing conditions are met, the data is written to the hard disk and an index is created,,and the written memory is released. The index includes file number, timestamp, and other content for data retrieval.

[0093] In summary, the embodiments of this specification include multi-level multi-way data caches, and each level of cache uses a data structure of a circular queue, which is finer in granularity and has a higher utilization rate of data cache units compared to the traditional ping-pong architecture. When multiple cache areas compete for the same resource, a data arbitration architecture is used to allocate resources, so that the entire firmware programming function is clear and the structure is clear. It realizes the simultaneous programming of multiple hard disks using FPGA, and at the same time encapsulates its control interface into a simple AXIS interface, and establishes a seamless connection with the address of the secondary cache area, so that the interface of the pre-inspection record and the storage module is clear and programming is simple and easy. All stripes in the embodiments of this specification are uniformly addressed, and the stored data is written in stripe order. This writing method allows the stored data to be written sequentially on each hard disk in time-sharing, realizes parallel processing of data transmission and writing physical media, and makes the multi-disk configuration not only expand the data capacity, but also improve the storage speed. The establishment and storage of index data use independent flash chips separately, and the access speed of normal business data is not affected by reading and writing index data, which improves the throughput of business data. Index data can work in a mature three-mode storage / reading method, which improves the reliability of index data.

[0094] The embodiment of this specification provides a satellite-borne multi-channel electromagnetic signal pre-detection recording system, which includes: a channel management module for acquiring payload electromagnetic signals, and allocating channel units and AD conversion parameters to electromagnetic signals through FPGA; a data cache module for collecting electromagnetic signals according to AD conversion parameters through FPGA to determine initial data, and cache the initial data for the first time to determine primary cache data, and cache the primary cache data for the second time according to the data type to determine secondary cache data; a data storage module for storing secondary cache data to a hard disk through FPGA, and sending data information of the secondary cache data to MCU to establish a data index. By using a single-chip FPGA as the core chip and integrating all functional units of the pre-detection equipment on a circuit board, the pre-detection equipment is lightweight and miniaturized, and can be easily installed on satellite equipment.

[0095] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of this specification are not limited by the order of the actions described, because according to the embodiments of this specification, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the embodiments of this specification.

[0096] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0097] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The optional embodiments do not describe all the details in detail, nor do they limit the invention to only the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of the embodiments of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of this specification, so that technicians in the relevant technical field can well understand and use this specification. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. A pre-detection recording system for satellite-borne multi-channel electromagnetic signals, characterized in that: include: A channel management module is used to obtain the electromagnetic signal of the payload and allocate channel units and AD conversion parameters to the electromagnetic signal through FPGA; A data cache module, used to perform data acquisition on the electromagnetic signal according to the AD conversion parameter through the FPGA to determine initial data, cache the initial data for a first time to determine primary cache data, and cache the primary cache data for a second time according to the data type to determine secondary cache data; A data storage module stores the secondary cache data to a hard disk through the FPGA, and sends data information of the secondary cache data to the MCU to establish a data index; Also includes a data playback module; The data playback module is used to receive a data return instruction from the star service computer through the MCU, determine the data position through the data index based on the data return instruction, and send the data position to the FPGA; the FPGA determines the target data according to the data position, and returns the target data; The data cache module includes a decision unit and a transmission control unit; The decision unit is used to receive the second cached application information, determine the decision result of the application information according to the priority, and send the decision result to the transmission control unit; The transmission control unit is used to determine the target primary cache data according to the decision result, and perform secondary cache on the target primary cache data to determine the secondary cache data; The data cache module includes a secondary cache area; The secondary cache area is used to store the secondary cache data; The secondary buffer area includes at least two data type buffer areas, and any data type buffer area of ​​the at least two data type buffer areas is used to store data of the same type; The data storage module includes a storage controller; The storage controller is used to number the hard disks and hard disk strips; The storage controller includes a data write control interface; the data write control interface is an AXIS interface; The data writing control interface is used to obtain the data addressing number of the data to be written, store the target secondary cache data from the secondary cache area to the current storage position of the hard disk based on the data addressing number, and change the storage position indication value of the hard disk; After writing the target data block into the first hard disk, the storage controller changes the current storage location to the second hard disk, so that the next data block of the target data block is written into the second hard disk.

2. The system according to claim 1, characterized in that The storage controller includes a data readout control interface; the data readout control interface is an AXIS interface; The data read control interface is used to determine the read stripe number of the data to be read, and read the target hard disk data into the secondary cache area based on the read stripe number.

3. The system according to claim 1, characterized in that Also includes: The decision unit is used to receive a data storage request from the secondary cache area, determine a decision result of the data storage request according to a priority, and send the decision result to the storage controller through the data write control interface.

4. The system according to claim 1, characterized in that The data storage module includes a FLASH module; The FLASH module is used to store the data index.

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