Method for processing MIPI D-PHY receiving end signal delay difference

Abstract

The invention discloses a method for processing MIPI D-PHY receiving end signal delay difference, and belongs to the field of high-speed serial buses. One FIFO is placed behind the PPI at the receiving end of each data channel in the MIPI D-PHY; rxSyncHs signals are respectively used for resetting, and RxValidHs signals are respectively used as conditions for writing data into FIFO (First In First Out). According to the invention, the delay problem of the MIPI D-PHY interface in data transmission can be effectively solved, the reliability and stability of the MIPI D-PHY interface are improved, and the MIPI D-PHY interface has great market potential and application value.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed serial bus, and in particular to a method for processing a signal delay difference at a MIPI D-PHY receiving end. Background Art

[0002] MIPI D-PHY interface is a digital serial interface technology used to connect displays and cameras in mobile devices. D-PHY supports data distribution to multiple data channels for simultaneous transmission, such as Figure 1 and Figure 2 However, this will cause the delay of each data channel to be different, and the time for each data channel in DPHY to receive data will also be different. If it is not processed, it may cause the parsed data to be misaligned. Because it is necessary to design a structure at the data receiving end to process the delay difference. Summary of the invention

[0003] The object of the present invention is to provide a method for processing a MIPI D-PHY receiving end signal delay difference, so as to solve the problems in the background technology.

[0004] In order to solve the above technical problems, the present invention provides a method for processing the signal delay difference of the MIPI D-PHY receiving end, comprising: A FIFO is placed after the PPI at the receiving end of each data channel in MIPI D-PHY; The RxSyncHs signal is used for resetting, and the RxValidHs signal is used as the condition for writing data into the FIFO.

[0005] In one implementation, after all used data channels receive the RxSyncHs signal, all FIFOs start reading data simultaneously to ensure that the first data received by each data channel is processed simultaneously. The channel that receives the data first needs to wait until the channel that receives the data last also receives the data before starting processing.

[0006] In one implementation, the depth of the FIFO is determined by measuring the maximum delay of data in each data channel.

[0007] In one implementation, when there is no difference in the time when each data channel receives data, the transmission delay of the entire link will not be increased; the greater the difference in the time when the data is received, the greater the increased link delay.

[0008] In one implementation, the method is applicable to any receiving end other than the MIPI D-PHY receiving end where there is a delay difference between each data stream.

[0009] The present invention provides a method for processing the signal delay difference of the MIPI D-PHY receiving end, which can solve the problem that the time when each D-PHY data channel receives data is different. The circuit is simple, easy to use, and easy to promote and apply. The present application can effectively solve the delay problem existing in the data transmission of the MIPI D-PHY interface, improve its reliability and stability, and has great market potential and application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of data being distributed to multiple data channels for simultaneous transmission.

[0011] Figure 2 This is a timing diagram of the PPI RX signal.

[0012] Figure 3 It is a schematic diagram of placing a FIFO after the PPI of each data channel receiving end provided by the present invention. DETAILED DESCRIPTION

[0013] The following is a further detailed description of a method for processing MIPI D-PHY receiving end signal delay differences proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0014] In order to solve the problem of signal delay difference at the MIPID-PHY receiving end, the present invention provides a method of placing a FIFO after the PPI at the receiving end of each data channel, such as Figure 3 As shown in the figure, the RxSyncHs signal is used to reset, and the RxValidHs signal is used as the condition for writing data into the FIFO. Each RxSyncHs signal is latched at the same time. When all the used data channels receive the RxSyncHs signal, all FIFOs start reading data at the same time. This ensures that the first data received by each data channel is processed at the same time. This means that the data channel that receives the data first needs to wait until the data channel that receives the data last also receives the data before starting to process. Figure 3 shown.

[0015] A delay line is added to the receiving end (rx) of the MIPI D-PHY interface to store the data received by each data channel into the FIFO separately. The data is not read from the FIFO at the same time until all the data channels to be used receive the first data, and then the data is assembled. In this way, the order of the assembled data is consistent with the order of the sent data. The depth of the FIFO needs to be measured and determined by the maximum delay of the data in each data channel.

[0016] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for processing MIPI D-PHY receiving end signal delay difference, characterized in that: include: In MIPI D-PHY, a FIFO is placed after the PPI at the receiving end of each data channel; Use the RxSyncHs signal to reset, and use the RxValidHs signal as the condition for writing data into FIFO; After all used data channels receive the RxSyncHs signal, all FIFOs start reading data at the same time to ensure that the first data received by each data channel is processed at the same time. The channel that receives the data first needs to wait until the channel that receives the data last also receives the data before starting processing.

2. The method for processing MIPI D-PHY receiving end signal delay difference according to claim 1, characterized in that: The depth of the FIFO is determined by measuring the maximum delay of data in each data channel.

3. The method for processing MIPI D-PHY receiving end signal delay difference according to claim 1, characterized in that: When there is no difference in the time when each data channel receives data, the transmission delay of the entire link will not be increased; the greater the difference in the time when the data is received, the greater the increased link delay.

4. The method for processing MIPI D-PHY receiving end signal delay difference according to claim 1, characterized in that: The method is applicable to any receiving end other than the MIPI D-PHY receiving end where there is a delay difference between each data stream.

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