Method for processing delay difference of data sent by MIPI D-PHY (Mobile Industry Processor Interface Delay-Physical Layer) sending end

Abstract

The invention discloses a method for processing delay difference of data sent by an MIPI D-PHY sending end, and belongs to the field of high-speed serial buses, an FIFO is placed in front of a PPI of the sending end of each data channel, and a TxReady HS signal is used as a condition for reading the FIFO; when all the FIFOs are not full of the previous-stage circuit, a new group of data can be written into the FIFOs at the same time, so that the D-PHY upper-layer circuit can process the data of each data channel at the same time, and the circuit is simple and convenient to use. According to the invention, the delay problem of the MIPI D-PHY interface in data transmission can be effectively solved, the reliability and stability of the MIPI D-PHY interface are improved, and the MIPI D-PHY interface has great market potential and application value.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed serial bus, and in particular to a method for processing a delay difference in sending data at a MIPI D-PHY transmitter. Background Art

[0002] MIPI D-PHY is a digital serial interface protocol that is mainly used to process high-speed data transmission and control signals; it supports allocating data to multiple data channels for simultaneous transmission, such as Figure 1 shown.

[0003] The standard interface PPI between MIPI D-PHY and the upper layer is as follows Figure 2 Since each data channel of MIPI D-PHY exists and works independently, the time when each TxReadyHS signal is set to 1 will be different, which means that the upper layer cannot completely synchronize the data output of each lane. However, the upper layer processes the data of each data channel at the same time, so a method is needed to take into account the simultaneous input and separate output of data. Summary of the invention

[0004] The object of the present invention is to provide a method for processing a delay difference in sending data at a MIPI D-PHY transmitter, so as to solve the problems in the background technology.

[0005] In order to solve the above technical problems, the present invention provides a method for processing the delay difference of sending data by a MIPI D-PHY transmitter, comprising: A FIFO is placed before the PPI of each channel transmitter of MIPI D-PHY, and the TxReadyHS signal sent by the D-PHY PPI is used as the condition for reading the FIFO, where PPI is the signal interface between D-PHY and the upper protocol layer specified in the D-PHY protocol.

[0006] In one implementation, when all FIFOs are not full of the previous stage circuit, a new set of data is written into the FIFOs simultaneously.

[0007] In one implementation, data of each channel in the MIPI D-PHY arrives at the same time, but each channel outputs data separately without interfering with each other in time.

[0008] In one implementation, the depth of the FIFO is determined by the maximum difference in TxReadyHS signal delay of each lane of the transmitter of the MIPI D-PHY, and each FIFO has the same depth and the same bit width.

[0009] In one implementation, the method is applicable to any transmitting end other than the MIPI D-PHY transmitting end where there is a delay difference between each data stream.

[0010] The present invention provides a method for processing the delay difference of data transmission of the MIPI D-PHY transmitter, placing a FIFO before the PPI of each data channel transmitter, and using the TxReadyHS signal as the condition for reading the FIFO; when all FIFOs are not full, the previous level circuit can write a new set of data into the FIFO at the same time, so that the DPHY upper layer circuit processes the data of each data channel at the same time, the circuit is simple and easy to use. The present invention can effectively solve the delay problem of the MIPI D-PHY interface in data transmission, improve its reliability and stability, and has great market potential and application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a schematic diagram showing that MIPI D-PHY supports allocating data to multiple data lanes for simultaneous transmission.

[0012] Figure 2 It is a schematic diagram of the standard interface PPI between MIPI D-PHY and the upper layer.

[0013] Figure 3 It is a structural schematic diagram of placing a FIFO before the PPI of each data channel sending end provided by the present invention. DETAILED DESCRIPTION

[0014] The following is a further detailed description of a method for processing the delay difference of sending data by a MIPI D-PHY transmitter proposed in the present invention in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0015] In order to solve the problem of delay difference in data transmission at the MIPI D-PHY transmitter, the present invention provides a method to place a FIFO before the PPI of each data channel transmitter, and use the TxReadyHS signal as the condition for reading the FIFO; HS is the abbreviation of high speed, TxreadyHS is a signal in PPI TX, and TxreadyHS=1 indicates that D-PHY is ready to receive data from the upper layer of D-PHY. When all FIFOs are not full, the previous circuit can write a new set of data into the FIFO at the same time, such as Figure 3 .

[0016] This allows data from N data channels to arrive at the same time, but each data channel outputs data separately without interfering with each other in time. The depth of the FIFO is determined by the maximum difference in the TxReadyHS signal delay of each data channel at the transmitter of MIPI D-PHY.

[0017] In order to solve the problem that the upper layer transmits data to each lane of the MIPI D-PHY transmitter at the same time, but each data channel reads data separately, a FIFO with the same depth and bit width is added before each data channel of the MIPI D-PHY transmitter. When all FIFOs are not full, the upper circuit writes data to the FIFO before each data channel at the same time, and the read data is controlled by the TxReadyHS signal sent by the MIPI D-PHY PPI.

[0018] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for processing the delay difference of sending data at a MIPI D-PHY transmitter, characterized in that: include: A FIFO is placed before the PPI of each data channel transmitter of MIPI D-PHY, and the TxReadyHS signal sent by MIPI D-PHYPPI is used as the condition for reading the FIFO, where PPI is the signal interface between D-PHY and the upper protocol layer specified in the D-PHY protocol.

2. The method for processing the delay difference of sending data by the MIPI D-PHY transmitter according to claim 1, characterized in that: When all FIFOs are not full of the previous stage circuit, a new set of data is written into the FIFO at the same time.

3. The method for processing the delay difference of sending data by the MIPI D-PHY transmitter according to claim 1, characterized in that: The data of each channel in the MIPI D-PHY arrives at the same time, but each channel outputs data separately without interfering with each other in time.

4. The method for processing the delay difference of sending data by the MIPI D-PHY transmitter according to claim 1, characterized in that: The depth of the FIFO is determined by the maximum difference in TxReadyHS signal delay of each channel of the D-PHY transmitter, and each FIFO has the same depth and the same bit width.

5. The method for processing the delay difference of sending data by the MIPI D-PHY transmitter according to claim 1, characterized in that: The method is applicable to any transmitting end other than the MIPI D-PHY transmitting end where there is a delay difference between each data stream.

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