A method and system for implementing an RDMA network card request queue

Abstract

This invention relates to the field of computer network technology, specifically to a method and system for implementing an RDMA network card request queue. The method includes: when a write request is received, checking if there is remaining space within the RDMA Cache module; if so, writing the write request information to the RDMA Cache module, updating the free space bit, and recording the queue pair number and incomplete pointer; if not, writing the write request information to the host memory module; when a read request is received, checking if the queue pair number and incomplete pointer carried by the read request match the historical records in the RDMA Cache module; if they match, reading from the RDMA Cache module; if they do not match, reading from the host memory module. This invention enables multiple QPs within the RDMA network card to share high-speed cache internal resources, reducing resource consumption and improving cache utilization.

Description

Technical Field

[0001] This invention relates to the field of computer network technology, and specifically to a method and system for implementing an RDMA network card request queue. Background Technology

[0002] An RDMA (Remote Direct Memory Access) network card is a high-performance network interface card that allows one computer on a network to directly access the memory of another computer without the need for operating system intervention.

[0003] In RDMA communication, such as Figure 1 As shown, SQ (Send Queue) and RQ (Receive Queue) are the two basic components constituting a QP (Queue Pair), used for sending and receiving data respectively. The local node's TX side sends multiple unanswered request packets (i.e., outstanding requests) to the remote node's RX side via SQ, and the remote node's RX side receives these request packets via RQ. To ensure that the local node's RX side can correctly process the response packets returned by the remote node's TX side, the local node needs to store the corresponding write information in the write information queue when sending request packets. When the number of QPs is large, how to effectively record and manage this request queue information while ensuring read and write performance becomes a key issue in RDMA network card design. Currently, the mainstream RDMA network card request queue implementation schemes are mainly of the following two types: The first is to cache all request queue information internally within the network card, avoiding the high latency of accessing host memory, thereby improving performance. The second approach is to cache only a portion of the information inside the network card, while storing the rest in the host memory. This uses a linked list management method to implement a shared cache across multiple QPs, which effectively reduces internal storage requirements.

[0004] In the above schemes, the first implementation scheme requires a large storage unit inside the RDMA network card, which increases the chip area and power consumption. The second implementation scheme has some limitations due to its linked list management method, which may affect performance, such as write limitations when resources are insufficient and the complexity of packet loss retransmission. Summary of the Invention

[0005] In view of this, the present invention provides a method and system for implementing an RDMA network card request queue to overcome the limitations of existing linked list management methods.

[0006] In a first aspect, the present invention provides a method for implementing an RDMA network card request queue. The method is applied to an RDMACache module in an RDMA network card request queue implementation system. The system further includes a host memory module connected to the RDMACache module. The RDMACache module manages the cache address where the request queue is stored, the free space of the cache address, the queue pair number, and the incomplete pointer. The method includes:

[0007] When a write request is received, check whether there is any remaining space inside the RDMACache module;

[0008] If there is remaining space, the write information of the write request is written to the target free address of the RDMACache module, and the free bit corresponding to the target free address is updated, and the queue pair number and incomplete pointer corresponding to the write request are recorded; if there is no remaining space, the write information of the write request is written to the host memory module.

[0009] When a read request is received, check whether the queue pair number and incomplete pointer carried by the read request match the historical records in the RDMACache module;

[0010] If a match is found, the storage data corresponding to the read request is read from the RDMACache module; if no match is found, the storage data corresponding to the read request is read from the host memory module.

[0011] The above scheme associates the Queue Pair Number (QPN) in the RDMA network card with the incomplete pointer on the host side. By mapping the queue pair number and the incomplete pointer to the internal storage address of the cache, multiple request queues can be effectively managed, thereby enabling multiple QPs within the RDMA network card to share the internal resources of the cache. This mapping mechanism reduces resource consumption and improves cache utilization. Furthermore, the above scheme optimizes the data structure through a direct mapping mechanism, avoiding the performance bottlenecks and resource waste that can occur with traditional linked list management methods, thus improving data access efficiency and enabling the cache to respond to requests more efficiently. In addition, the above scheme uses outstanding read request processing. When the on-chip cache misses, a read request is immediately sent to the host memory module. While waiting for the host memory module's response, the next read request is processed, achieving parallel processing. By processing read requests in parallel, waiting time is reduced, cache read throughput is increased, and overall latency caused by waiting for a single read request to complete is reduced. The above solution achieves efficient resource utilization by sharing cache resources and avoiding linked list management. It improves cache read performance and overall throughput by handling read requests exceptionally well, reduces management complexity and overhead, and enhances system stability and reliability.

[0012] In one optional implementation, the step of checking whether there is remaining space inside the RDMACache module when a write request is received includes:

[0013] When a write request is received, the RDMACache module is queried for free space based on the free space of the cache address to obtain the remaining space in the RDMACache module.

[0014] In one optional implementation, if there is remaining space, the write information of the write request is written to the target free address of the RDMA Cache module, and the free bit corresponding to the target free address is updated. The queue pair number and incomplete pointer corresponding to the write request are recorded, including:

[0015] If there is remaining space in the RDMA Cache module, the target free address is selected from the address free bits of the RDMA Cache module;

[0016] Write the write information of the write request to the target free address, and update the valid address position of the target free address to a non-free state;

[0017] Record the queue pair number and incomplete pointer corresponding to the write request and associate them with the target free address.

[0018] In one optional implementation, the step of checking whether the queue pair number and incomplete pointer carried by the read request match the historical records in the RDMACache module when a read request is received includes:

[0019] When a read request is received, extract the queue pair number and incomplete pointer carried by the read request;

[0020] Determine whether the queue pair number and incomplete pointer carried by the read request match the historical record corresponding to the target cache address in the RDMA Cache module, and simultaneously determine whether the target cache address is in a non-idle state.

[0021] In one optional implementation, the step of reading the storage data corresponding to the read request from the RDMACache module if a match is found includes:

[0022] If a match is found, and the target cache address is not idle, then a cache hit is determined, and the storage data corresponding to the read request is read from the target cache address.

[0023] In one optional implementation, the step of reading the stored data corresponding to the read request from the host memory module if there is a mismatch includes:

[0024] If there is no match, or if the target cache address that is matched is in an idle state, then it is determined that the cache has missed, and a read request is sent to the host memory module to read the storage data corresponding to the read request;

[0025] While waiting for the host memory module to respond, the next read request is processed to achieve parallel processing of multiple read requests.

[0026] In an optional implementation, the method further includes:

[0027] After each matching query, the matching result is recorded in the read direction record FIFO of the RDMA Cache module;

[0028] When the read direction record FIFO is not empty, a data read path is selected according to the record information in the read direction record FIFO; the data read path includes reading the storage data corresponding to the read request from the RDMACache module and reading the storage data corresponding to the read request from the host memory module.

[0029] Secondly, the present invention provides an implementation system for an RDMA network card request queue, the system comprising: an RDMA Cache module and a host memory module connected to each other, wherein the RDMA Cache module manages the Cache address where the request queue is stored, the free space of the Cache address, the queue pair number and the incomplete pointer;

[0030] The RDMA Cache module is used to execute the above-described method for implementing an RDMA network card request queue.

[0031] Thirdly, the present invention provides a computer device, comprising: a memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the computer instructions to perform an implementation method of an RDMA network card request queue as described in the first aspect or any corresponding embodiment thereof.

[0032] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions for causing a computer to execute an implementation method of an RDMA network card request queue according to the first aspect or any corresponding embodiment thereof.

[0033] Fifthly, the present invention provides a computer program product, including computer instructions for causing a computer to execute an RDMA network card request queue implementation method according to the first aspect or any corresponding embodiment thereof.

[0034] This invention associates the Queue Pair Number (QPN) in the RDMA network card with the incomplete pointer on the host side. By mapping the Queue Pair Number and the incomplete pointer to the internal storage address of the cache, multiple request queues can be effectively managed, thereby enabling multiple QPs within the RDMA network card to share the internal resources of the cache. This mapping mechanism reduces resource consumption and improves cache utilization. Furthermore, this invention optimizes the data structure through a direct mapping mechanism, avoiding the performance bottlenecks and resource waste that can occur with traditional linked list management methods, thus improving data access efficiency and enabling the cache to respond to requests more efficiently. In addition, this invention uses outstanding read request processing. When the on-chip cache misses, a read request is immediately sent to the host memory module. While waiting for the host memory module's response, the next read request is processed, achieving parallel processing. By processing read requests in parallel, waiting time is reduced, cache read throughput is increased, and overall latency caused by waiting for a single read request to complete is reduced. This invention achieves efficient resource utilization by sharing cache high-speed caching resources and avoiding linked list management. It improves cache read performance and overall throughput by handling read requests exceptionally well, reduces management complexity and overhead, and enhances system stability and reliability. Attached Figure Description

[0035] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 A schematic diagram of RDMA network card operation is shown;

[0037] Figure 2 This diagram illustrates the structure of a multi-QP shared cache using a traditional linked list management method.

[0038] Figure 3 This is a schematic diagram of the structure of an RDMA network card request queue implementation system according to an embodiment of the present invention;

[0039] Figure 4 This is a flowchart of an implementation method for an RDMA network card request queue according to an embodiment of the present invention;

[0040] Figure 5 This is a flowchart of another method for implementing an RDMA network card request queue according to an embodiment of the present invention;

[0041] Figure 6 This is a flowchart of a write operation implementation method according to an embodiment of the present invention;

[0042] Figure 7 This is a flowchart of a read operation implementation method according to an embodiment of the present invention;

[0043] Figure 8 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] Please see Figure 2 The diagram illustrates a traditional linked list management approach for implementing a shared cache across multiple queue pairs (QPs). When interacting with host memory to manage request information from multiple queue pairs (QPs), Figure 2 The RDMA network card has an internal cache that stores partial request queue information (e.g., request descriptors, metadata, etc.). Complete information, or the remaining information when cache space is insufficient, is stored in host memory. The RDMA network card's cache uses a linked list management method, allowing multiple request queues (QPs) to share the cache space. Each QP has one or more outstanding requests, and information about these requests (such as request status, data location, etc.) is stored in the cache or host memory.

[0046] When an RDMA network card needs to access the request queue information of a specific QP (Queued Request), it first searches the cache. If the required information is not found in the cache (cache miss), the RDMA network card reads the corresponding information from the host memory via the PCIe bus. Each QP's request queue in host memory has an "out-of-chip pointer" (outptr) that points to the position of the currently processed request in the queue. Internally, the cache manages the storage addresses of these request queue information in the cache through a linked list.

[0047] exist Figure 2In the system, the host memory supports "x" QPs, and each QP supports storing "y" unanswered request information, i.e., y data entries. Each entry is associated with a specific outptr value. Each data entry (e.g., entry.0, entry.1, ..., entry.y-1) has an associated outptr value, which represents a pointer to the request queue information in the host memory. RDMA_CACHE is used to cache data from the host memory to improve access speed. Its linked list control module manages the entries in RDMA_CACHE, using a linked list data structure to maintain the relationships between entries. Each cached entry in the linked list control module can contain the following information: ram_addr - the address of the cached entry, ram_data - the data content of the cached entry, bitmap - a bitmap used to mark whether the address is occupied, and next_addr - the address pointing to the next cached entry. In the data content of the ram_data cache entry, info0 represents the first or initial data block of the queue pair, or the information entry with sequence number 0. qp0 refers to queue pair number 0, where "qp" is an abbreviation for queue pair, and the number 0 indicates a specific queue pair number. For example, "info0_of_qp0" represents the first or initial data entry (info0) in the storage area reserved for queue pair number 0 (qp0).

[0048] Figure 2 It can effectively reduce internal storage, but its linked list management method has the following two drawbacks:

[0049] 1) When the cache's internal resources are insufficient, request queue information can only be written to host memory and not to the cache. Even if there is space in the cache later, if information not present in the cache exists in host memory, writing subsequent request queue information for that QP to the cache will incur significant overhead due to the maintenance of the relationship between the cache's internal linked list and the host memory request queue pointers.

[0050] 2) In RDMA protocols, there are scenarios where packet loss during transmission necessitates retransmission of request packets. In such cases, it's necessary to roll back the off-chip pointers of the cache. For linked list management, because it stores requests sequentially, the linked list of the corresponding QP within the cache needs to be cleared to maintain the order of the request queue. To address the drawbacks of linked list management, this embodiment provides a method for implementing request queues in an RDMA network card. It associates the queue pair number (QPN) in the RDMA network card with the incomplete pointer on the host side. By mapping the queue pair number and the incomplete pointer to the internal storage address of the cache, multiple request queues can be effectively managed. This allows multiple QPs within the RDMA network card to share the internal resources of the cache. This mapping mechanism reduces resource consumption and improves cache utilization.

[0051] First, some key terms used in this invention will be explained:

[0052] 1. RDMA (Remote Direct Memory Access): Remote Direct Memory Access is a technology that allows network devices (such as RDMA network cards) to directly access the memory of another computer without the intervention of the operating system. It can reduce the processing latency of data in network transmission and improve data transmission efficiency.

[0053] 2. Cache: A storage device that enables high-speed data exchange. It is typically used to store frequently accessed data to reduce the number of accesses to slow storage (such as hard drives), thereby improving data access speed and optimizing system performance.

[0054] 3. SQ (Send Queue): The send queue in the RDMA protocol, used to store data or requests to be sent.

[0055] 4. RQ (Receive Queue): The receive queue in the RDMA protocol, used to store received data or responses.

[0056] 5. QP (Queue Pair): In the RDMA protocol, the combination of the transmit queue and the receive queue is called a QP, which serves as the basic unit of RDMA communication to realize the transmission and reception of data.

[0057] 6. QPN (Queue Pair Number): The number of the QP, used to uniquely identify different QPs. In RDMA communication, the QPN can be used to determine which QP data should be sent to.

[0058] 7. TX (Transmit): The transmitting side of the RDMA network card, used to send request and response messages.

[0059] 8. RX (Receive): The receiving side of the RDMA network card, used to receive request and response messages.

[0060] 9. Outstanding: This means that after initiating a request, the next request can be sent before a response is received, which can improve the concurrency and throughput of RDMA communication.

[0061] 10. Outptr (Out Pointer): An off-chip pointer, also known as an incomplete pointer, used to identify the corresponding position of different information in the request queue stored in the host memory, so as to quickly locate and process the request in the host memory.

[0062] 11. PCIE (Peripheral Component Interconnect Express): The medium through which the RDMA Cache module accesses host memory, providing a high-speed, reliable connection that enables the RDMA Cache to efficiently access host memory.

[0063] 12. SRAM (Static Random Access Memory): This unit is used internally by the RDMA Cache module to store request queue information, ensuring that the RDMA Cache module can efficiently process request queue information.

[0064] 13. FIFO (First Input First Output): A first-in-first-out queue is a data structure that outputs data according to the order of input to ensure that data is processed in the order of input and to avoid data loss or disorder.

[0065] 14. CAM (Context Addressable Memory): Content-addressable memory is a type of memory that can quickly find and match content.

[0066] According to an embodiment of the present invention, a system embodiment for implementing an RDMA network card request queue is provided. Figure 3 This is a schematic diagram of the structure of an RDMA network card request queue implementation system according to an embodiment of the present invention, as shown below. Figure 3 As shown, the system includes: an interconnected RDMACache module and a host memory module. The RDMACache module manages the cache address where the request queue is stored (i.e., Figure 3 The ram addr), the free bits of the cache address (i.e.) Figure 3 (bitmap in the queue) queue pair number (i.e. Figure 3 QPN in the middle) and unfinished pointer (i.e. Figure 3 The `outptr` in the `RDMACache` module is used to implement one method of RDMA network card request queue, as described below. This method includes:

[0067] When a write request is received, check if there is any remaining space inside the RDMACache module;

[0068] If there is remaining space, the write information of the write request is written to the target free address of the RDMACache module, and the free bit corresponding to the target free address is updated, recording the queue pair number and incomplete pointer corresponding to the write request; if there is no remaining space, the write information of the write request is written to the host memory module.

[0069] When a read request is received, check whether the queue pair number and incomplete pointer carried by the read request match the history in the RDMACache module;

[0070] If a match is found, the storage data corresponding to the read request is read from the RDMA Cache module; if no match is found, the storage data corresponding to the read request is read from the host memory module.

[0071] In one optional implementation, the RDMACache module includes a control unit and an on-chip address mapping management unit. The first end of the control unit is connected to the on-chip address mapping management unit, and the second end of the control unit is also connected to the host memory module. The control unit includes a read control unit and a write control unit.

[0072] The write control unit is used to receive write requests and control write operations; the read control unit is used to receive read requests and control read operations.

[0073] The on-chip address mapping management unit is used to manage the cache address, free bits of the cache address, queue pair number and incomplete pointer stored in the request queue, as well as the mapping relationship between the cache address, the queue pair number and the incomplete pointer. It is also used to store the write information written to the RDMACache module (the on-chip address mapping management unit also includes SRAM static random access memory, which is used to store the write information written to the RDMACache module).

[0074] Furthermore, the ram_data in the SRAM (Static Random Access Memory) is used to cache the data content of each cache entry, such as data in the form of "infoX_of_qpY", where X represents the data number and Y represents the queue pair number (qp).

[0075] In one optional implementation, the system further includes a read initiation module and a write initiation module; the read initiation module is connected to the input terminal of the read control unit through a read interface, and the write initiation module is connected to the input terminal of the write control unit through a write interface.

[0076] The read initiation module is used to initiate a read operation and send a read request to the read control unit; the write initiation module is used to initiate a write operation and send a write request to the write control unit.

[0077] Furthermore, during a write operation, the write initiation module sends a write request to the write control unit via the write interface. The write control unit controls the logic of the write operation, ensuring that the data is written correctly, and searches for a free address on-chip. It then locates a free location in the RDMA Cache module to store the new data and writes the data to the free address in the RDMA Cache module. The on-chip address mapping management unit manages the mapping relationship between cache addresses, queue pair numbers (QPNs), and the out-of-process pointers (Outptr) of the host-side queues.

[0078] During a read operation, the read initiation module sends a read request to the read control unit through the read interface. The read control unit controls the logic of the read operation to ensure that the data is retrieved correctly. The read control unit checks whether the on-chip information of the RDMA Cache module matches the request and checks whether there is data in the RDMA Cache module that matches the request. If it does, the matching data is read from the RDMA Cache module.

[0079] In summary, this embodiment associates the Queue Pair Number (QPN) in the RDMA network card with the incomplete pointer on the host side. By mapping the Queue Pair Number and the incomplete pointer to the internal storage address of the cache, multiple request queues can be effectively managed, thereby enabling multiple QPs within the RDMA network card to share the internal resources of the cache. This mapping mechanism reduces resource consumption and improves the utilization rate of the cache. Furthermore, this embodiment optimizes the data structure through a direct mapping mechanism, avoiding the performance bottlenecks and resource waste that may result from traditional linked list management methods, thus improving data access efficiency and enabling the cache to respond to requests more efficiently. In addition, this embodiment uses outstanding read request processing. When the on-chip cache misses, a read request is immediately initiated to the host memory module. While waiting for the host memory module's response, the next read request is processed, achieving parallel processing. By processing read requests in parallel, waiting time is reduced, the read throughput of the cache is improved, and the overall latency caused by waiting for a single read request to complete is reduced. This embodiment achieves efficient resource utilization by sharing cache high-speed cache resources and avoiding linked list management. It improves cache read performance and overall throughput by handling read requests exceptionally well, reduces management complexity and overhead, and enhances system stability and reliability.

[0080] According to an embodiment of the present invention, an implementation method for an RDMA network card request queue is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0081] This embodiment provides a method for implementing an RDMA network card request queue, which is applied to... Figure 3 In the RDMACache module of the RDMA network card request queue implementation system shown, the system also includes a host memory module connected to the RDMACache module. The RDMACache module manages the cache address where the request queue is stored, the free bits of the cache address, the queue pair number, and the incomplete pointer. Figure 4 This is a flowchart illustrating an implementation method of an RDMA network card request queue according to an embodiment of the present invention, as shown below. Figure 4 As shown, the process includes the following steps:

[0082] Step S401: When a write request is received, check whether there is any remaining space inside the RDMACache module.

[0083] Furthermore, when the RDMA Cache module receives a write request, it first needs to determine whether it has enough internal space to store the data requested. The RDMA Cache module is a cache area located on the RDMA network card, used to temporarily store data to reduce access to the host memory module, thereby improving data transmission efficiency. The purpose of this step is to determine whether the write request can be processed directly in the RDMA Cache module without sending it directly to the host memory module.

[0084] The RDMA Cache module is managed by the RDMA network card and related software (such as drivers). It uses specialized algorithms and data structures to optimize data transmission, such as a mapping mechanism between queue pair numbers (QPNs) and incomplete pointers. When the RDMA network card receives a write request, if the RDMA Cache module has sufficient space, the data is stored in the RDMA Cache module; if the RDMA Cache module is full, the data is written directly to the host memory module. Similarly, when a read request is received, the RDMA Cache module is first checked. If the requested data exists, it is read directly from the RDMA Cache module; otherwise, it is read from the host memory module. The RDMA Cache module and the host memory module work together to support the data storage and access needs of the computer system. By optimizing the data transmission mechanism, the overall performance and stability of the system can be improved. The host memory module is located on the computer motherboard and is the main area in the computer used for temporary data storage. It is directly connected to the CPU and is used to store running programs and data.

[0085] In step S402, if there is remaining space, the write information of the write request is written to the target free address of the RDMA Cache module, and the free bit corresponding to the target free address is updated, and the queue pair number and incomplete pointer corresponding to the write request are recorded; if there is no remaining space, the write information of the write request is written to the host memory module.

[0086] Furthermore, if the RDMA cache module has free space, the write request information (i.e., the data to be written) is stored in the specified free address (i.e., the target free address, which can be any of the free addresses), and the free status of this address is updated (marked as used). Simultaneously, the queue pair number (QPN) and out pointer (combined with the queue pair number to determine the location of the corresponding request information stored in the cache or the host memory module) are recorded for this write request. If the RDMA cache module does not have free space, the write request information is directly stored in the host memory module to avoid delays caused by waiting for cache space.

[0087] Step S403: When a read request is received, check whether the queue pair number and incomplete pointer carried by the read request match the history in the RDMA Cache module.

[0088] Furthermore, when the RDMA Cache module receives a read request, it needs to determine whether the requested data is stored in the RDMA Cache module. This is done by checking whether the queue pair number and incomplete pointer carried by the read request match the historical records in the RDMA Cache module. This step is to determine whether the read request can directly obtain the data from the RDMA Cache module without having to obtain it from the host memory module.

[0089] In step S404, if a match is found, the storage data corresponding to the read request is read from the RDMACache module; if a mismatch is found, the storage data corresponding to the read request is read from the host memory module.

[0090] Furthermore, if the queue pair number and incomplete pointer of the read request match the record in the RDMA Cache module, it means that the data of the read request is already cached in the RDMA Cache module and can be read directly from the RDMA Cache module. If they do not match, it means that the data of the read request is not in the RDMA Cache module and needs to be read from the host memory module. This embodiment effectively manages multiple request queues and enables multiple QPs to share cache resources by mapping the queue pair number of the request queue to the incomplete pointer on the host side.

[0091] In this embodiment, the Queue Pair Number (QPN) is a number used to uniquely identify each queue pair in the RDMA architecture. Each QP has a unique QPN so that the RDMA network card can accurately identify and process requests from different queue pairs. The incomplete pointer is used by the RDMACache module to determine the position of different request information within a single queue pair. As the request is completed, the corresponding pointer is released and can be used to record new request information. Within the RDMACache module of this embodiment, by mapping the Queue Pair Number (QPN) to the host-side incomplete pointer's internal cache storage address, effective management of multiple request queues can be achieved. The mapping mechanism of the on-chip address mapping management unit in the RDMA Cache module allows the RDMA network card to quickly locate the corresponding incomplete pointer based on the QPN and check the request status when it receives a request. When multiple QPs send requests to the RDMA network card simultaneously, the RDMA network card stores them in different locations within the RDMA Cache module according to the QPN of each request. Since each QP has a unique QPN, the RDMA network card can accurately identify and process requests from different QPs without confusion or conflict. That is, through the mapping mechanism of QPN and incomplete pointer, the RDMA Cache module can enable multiple QPs to share cache resources.

[0092] In summary, this embodiment associates the Queue Pair Number (QPN) in the RDMA network card with the incomplete pointer on the host side. By mapping the Queue Pair Number and the incomplete pointer to the internal storage address of the cache, multiple request queues can be effectively managed, thereby enabling multiple QPs within the RDMA network card to share the internal resources of the cache. This mapping mechanism reduces resource consumption and improves the utilization rate of the cache. Furthermore, this embodiment optimizes the data structure through a direct mapping mechanism, avoiding the performance bottlenecks and resource waste that may result from traditional linked list management methods, thus improving data access efficiency and enabling the cache to respond to requests more efficiently. In addition, this embodiment uses outstanding read request processing. When the on-chip cache misses, a read request is immediately initiated to the host memory module. While waiting for the host memory module's response, the next read request is processed, achieving parallel processing. By processing read requests in parallel, waiting time is reduced, the read throughput of the cache is improved, and the overall latency caused by waiting for a single read request to complete is reduced. This embodiment achieves efficient resource utilization by sharing cache high-speed cache resources and avoiding linked list management. It improves cache read performance and overall throughput by handling read requests exceptionally well, reduces management complexity and overhead, and enhances system stability and reliability.

[0093] This embodiment provides another method for implementing RDMA network card request queues, which is applied to Figure 3 The RDMA Cache module in the RDMA network card request queue implementation system shown also includes a host memory module connected to the RDMA Cache module. The RDMA Cache module manages the cache address where the request queue is stored, the free bits of the cache address, the queue pair number, and the incomplete pointer. Figure 5 This is a flowchart of another implementation method of RDMA network card request queue according to an embodiment of the present invention, such as... Figure 5 As shown, the process includes the following steps:

[0094] Step S501: When a write request is received, based on the free space of the cache address, the RDMA cache module is queried for the free space of the cache address in order to obtain the remaining space in the RDMA cache module.

[0095] Furthermore, in this embodiment, when the RDMA Cache module receives a write request, it first performs an address free bit query on the RDMA Cache module based on the free bits of each cache address in the RDMA Cache module (i.e., the bits that mark whether the address has been used) to determine whether there is still space remaining in the RDMA Cache module to store the write information of this write request.

[0096] In step S502, if there is remaining space, the write information of the write request is written to the target free address of the RDMA Cache module, and the free bit corresponding to the target free address is updated, and the queue pair number and incomplete pointer corresponding to the write request are recorded; if there is no remaining space, the write information of the write request is written to the host memory module.

[0097] Furthermore, step S502 includes:

[0098] If there is remaining space in the RDMA Cache module, the target free address is selected from the address free bits of the RDMA Cache module;

[0099] Write the write request information to the target free address and update the valid address position of the target free address to a non-free state;

[0100] Record the queue number and incomplete pointer corresponding to the write request and associate them with the target free address.

[0101] Furthermore, if there is remaining space in the SRAM (Static Random Access Memory) of the RDMA Cache module, a target free address is selected from the address free bits of the RDMA Cache module. These addresses have never been occupied before, or have been released after being occupied, and are now available to store new data. The write control unit in the RDMA Cache module writes the write request information (i.e., the data to be stored) to the selected target free address. After the write operation is completed, the on-chip address mapping management unit in the RDMA Cache module updates the address valid bit (or free bit) of the target free address to a non-free state to indicate that the address is now occupied, and records the queue pair number and incomplete pointer corresponding to the current write request, associating them with the target free address. The queue pair number is used to identify a specific request queue, while the incomplete pointer is used to track the operations that have not yet been completed in that request queue. If there is no remaining space in the RDMA Cache module, the write control unit in the RDMA Cache module will not write data to the RDMA Cache module. Instead, it writes the write request information directly to the host memory module to avoid data loss or overwriting and to ensure that the data can be accessed correctly when needed. Address free bits are an important data structure in the on-chip address mapping management unit of the RDMA cache module used to track the occupancy status of SRAM (Static Random Access Memory). The system needs to update these bits periodically to ensure they reflect the actual state of the SRAM. Queue pair numbers allow the system to identify specific data transfer queues, while incomplete pointers help the system track operations that have not yet been completed in the queues, thereby ensuring data correctness and integrity.

[0102] For further details, please see Figure 6The flowchart illustrates the write operation implementation method. After receiving a write request, the RDMACache module, if having free space within its cache (i.e., SRAM), queries for free address bits, selects one free address, writes the information to be written to that address, updates the corresponding bit's valid address to a non-space value (0), and records the corresponding QPN and Outptr. If there is no free space within the cache, the information to be written is written to the host memory module. Whether the current write request can be written to the cache depends solely on whether there is free space within the cache, and is not affected by whether the previous write request was written to the cache, thus maximizing the utilization of cache resources and minimizing access to main memory. In other words, when the RDMA Cache module receives a write request, it first checks if there is any remaining space within the RDMA Cache module. If there is remaining space in the cache (i.e., SRAM static random access memory), it queries the cache's address free bits to find an available free address, selects a target free address from the free bits, writes the information to be written to this free address, sets the address validity bit of the corresponding free address to a non-free state (usually set to 0), indicating that the address is occupied, and records the corresponding queue pair number (QPN) and out-of-process pointer (Outptr) so that this data can be tracked and accessed in the future. If there is no remaining space in the cache, the data cannot be written to the cache, and therefore needs to be written directly to the host memory. Whether the current write request can be written to the cache depends only on whether there is remaining space in the cache, and is not affected by whether previous write requests have written to the cache. That is, each write request is considered independently, which maximizes the utilization of cache resources.

[0103] Step S503: When a read request is received, extract the queue pair number and incomplete pointer carried by the read request; determine whether the queue pair number and incomplete pointer carried by the read request match the historical record corresponding to the target cache address in the RDMACache module, and at the same time determine whether the target cache address is in a non-idle state.

[0104] Furthermore, when the RDMA Cache module receives a read request, the read control unit extracts the Queue Pair Number (QPN) and Outptr carried in the request, and checks whether these match the historical records of a target cache address stored in the RDMA Cache module. It also checks whether this target cache address is not idle, i.e., whether the address has already been occupied and data is stored.

[0105] Step S504: If a match is found and the target Cache address is not idle, then a Cache hit is determined, and the storage data corresponding to the read request is read from the target Cache address.

[0106] Furthermore, if the information in the read request matches the historical record of a target cache address in the RDMA cache, and that target cache address is not idle, then the read control unit determines that it is a cache hit. In this case, the read control unit will directly read the storage data corresponding to the read request from that target cache address without accessing the host memory module.

[0107] In step S505, if there is no match, or if the target Cache address that is matched is in an idle state, it is determined that the Cache has missed, and a read request is sent to the host memory module to read the storage data corresponding to the read request; while waiting for the host memory module to respond, the next read request is processed to achieve parallel processing of multiple read requests.

[0108] Furthermore, if the information in the read request does not match the historical records of any cache address in the RDMA cache module, or if the matched target cache address is idle, it is determined to be a cache miss. In the case of a cache miss, the read control unit needs to initiate a new read request to the host memory module to read the stored data corresponding to the read request. While waiting for the host memory module's response, to improve efficiency, the read control unit can process the next read request in parallel. This parallel processing of multiple read requests can significantly reduce the total waiting time and improve the system throughput.

[0109] For further details, please see Figure 7The flowchart illustrating the read operation implementation method shows that after receiving a read request, the RDMACache module determines whether the queue pair number (QPN) and the incomplete pointer (Outptr) provided by the read initiating module match the information stored at a certain address within the cache. It also checks whether the corresponding address is not in free space. If a matching address is found and the address is not free, it's considered a cache hit, and the address is recorded. Otherwise, it's a cache miss, and a read request is sent to the host. The miss information is stored in the read direction record FIFO, and the next lookup continues. In other words, when the RDMACache module receives a read request, it typically includes a queue pair number (QPN) and an incomplete pointer (Outptr). The RDMACache module then checks whether the QPN and Outptr in this read request match the information stored at a certain address within the cache. Simultaneously, the RDMACache module checks whether the corresponding address is not in free space, i.e., whether the address is already occupied by valid data. If a matching address is found and it is not in free space, then a cache hit is considered. At this point, the RDMA Cache module records the corresponding cache address so that data can be read from this address later. If no matching address is found, or if the found address is free (i.e., not occupied), then a cache miss is considered. In this case, the read control unit in the RDMACache module needs to initiate a read request to the host to obtain the required data from the host memory module.

[0110] Step S506: After each matching query, the matched result is recorded in the read direction record FIFO of the RDMA Cache module; when the read direction record FIFO is not empty, a data reading path is selected according to the record information in the read direction record FIFO; the data reading path includes reading the storage data corresponding to the read request from the RDMACache module and reading the storage data corresponding to the read request from the host memory module.

[0111] Furthermore, such as Figure 7As shown, when the read direction record FIFO is not empty, based on the previously recorded cache hit information, it selects whether to read SRAM from the address recorded in the "SRAM Read Address FIFO" or read from the "Read Host Memory Data Cache FIFO". Finally, the selected data is output to the read initiation module. The processes of determining whether the queue pair number QPN and the incomplete pointer Outptr match, reading SRAM, and initiating a read request to the host all support outstanding performance. In other words, regardless of whether there is a cache hit, the RDMA Cache module stores the query result (hits) in a read direction record FIFO (FirstIn First Out). This read direction record FIFO is used to record the results of each query so that subsequent data can be read from which data source. When the read direction record FIFO is not empty, the RDMACache module will determine the next operation based on the previously recorded cache hit information. If the cache hits, the RDMACache module will read the previously recorded cache address from the "SRAM read address FIFO" and read the data from that address (i.e., read the storage data corresponding to the read request from the RDMACache module). If the cache misses, the RDMACache module will read the data from the "read host memory data cache FIFO" (i.e., read the storage data corresponding to the read request from the host memory module).

[0112] Furthermore, this embodiment uses a combination of queue pair numbers and unfinished pointers on the host side (implemented by a mapping table in the on-chip address mapping management unit, which includes the mapping relationship between cache addresses, queue pair numbers, and unfinished pointers) to map the internal storage address of the cache, i.e., the cache address where the request queue is stored, thereby enabling multiple QPs to share internal cache resources. The combination of queue pair numbers and unfinished pointers on the host side means that each QP in this embodiment has an associated unfinished pointer, which points to the current location of the QP's operation in the host memory module. The RDMA Cache module uses the combination of queue pair numbers and unfinished pointers as a key to map to the internal storage address of the cache. The implementation is as follows: when a QP initiates a write operation, its queue pair number and unfinished pointer are used to determine a target free address in the RDMA Cache module. The written data is stored in this target free address in the RDMA Cache module, and the status of the target free address is updated to non-free. When another QP initiates a read operation, its queue pair number and unfinished pointer are similarly used to find the corresponding address in the RDMA Cache module.

[0113] In summary, this embodiment associates the Queue Pair Number (QPN) in the RDMA network card with the incomplete pointer on the host side. By mapping the Queue Pair Number and the incomplete pointer to the internal storage address of the cache, multiple request queues can be effectively managed, thereby enabling multiple QPs within the RDMA network card to share the internal resources of the cache. This mapping mechanism reduces resource consumption and improves the utilization rate of the cache. Furthermore, this embodiment optimizes the data structure through a direct mapping mechanism, avoiding the performance bottlenecks and resource waste that may result from traditional linked list management methods, thus improving data access efficiency and enabling the cache to respond to requests more efficiently. In addition, this embodiment uses outstanding read request processing. When the on-chip cache misses, a read request is immediately initiated to the host memory module. While waiting for the host memory module's response, the next read request is processed, achieving parallel processing. By processing read requests in parallel, waiting time is reduced, the read throughput of the cache is improved, and the overall latency caused by waiting for a single read request to complete is reduced. This embodiment achieves efficient resource utilization by sharing cache high-speed cache resources and avoiding linked list management. It improves cache read performance and overall throughput by handling read requests exceptionally well, reduces management complexity and overhead, and enhances system stability and reliability.

[0114] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 8 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 8 Take a processor 10 as an example.

[0115] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0116] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0117] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0118] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0119] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0120] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0121] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0122] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the defined scope.

Claims

1. A method for implementing an RDMA network card request queue, characterized in that, The method is applied to an RDMACache module in an RDMA network card request queue implementation system. The system further includes a host memory module connected to the RDMACache module. The RDMACache module manages the cache address where the request queue is stored, the free space of the cache address, the queue pair number, and the incomplete pointer. The method includes: When a write request is received, check whether there is any remaining space inside the RDMA Cache module; If there is remaining space, the write information of the write request is written to the target free address of the RDMACache module, and the free bit corresponding to the target free address is updated. The queue pair number and incomplete pointer corresponding to the write request are recorded. If there is no remaining space, the write information of the write request is written to the host memory module. When multiple queue pairs send requests to the RDMA network card at the same time, the requests are stored in different locations of the RDMACache module according to the queue pair number of each request. When a read request is received, check whether the queue pair number and incomplete pointer carried by the read request match the historical records in the RDMACache module; If a match is found, the storage data corresponding to the read request is read from the RDMACache module; If there is no match, the storage data corresponding to the read request is read from the host memory module; while waiting for the host memory module to respond, the next read request is processed to achieve parallel processing of multiple read requests.

2. The method according to claim 1, characterized in that, When a write request is received, checking whether there is remaining space inside the RDMACache module includes: When a write request is received, the RDMACache module is queried for free space based on the free space of the cache address to obtain the remaining space in the RDMACache module.

3. The method according to claim 2, characterized in that, If there is remaining space, the write information of the write request is written to the target free address of the RDMACache module, and the free bit corresponding to the target free address is updated. The queue pair number and incomplete pointer corresponding to the write request are recorded, including: If there is remaining space in the RDMA Cache module, the target free address is selected from the address free bits of the RDMA Cache module; Write the write information of the write request to the target free address, and update the valid address position of the target free address to a non-free state; Record the queue pair number and incomplete pointer corresponding to the write request and associate them with the target free address.

4. The method according to claim 3, characterized in that, When a read request is received, checking whether the queue pair number and incomplete pointer carried by the read request match the historical records in the RDMA Cache module includes: When a read request is received, extract the queue pair number and incomplete pointer carried by the read request; Determine whether the queue pair number and incomplete pointer carried by the read request match the historical record corresponding to the target cache address in the RDMA Cache module, and simultaneously determine whether the target cache address is in a non-idle state.

5. The method according to claim 4, characterized in that, If a match is found, the storage data corresponding to the read request is read from the RDMA Cache module, including: If a match is found, and the target cache address is not idle, then a cache hit is determined, and the storage data corresponding to the read request is read from the target cache address.

6. The method according to claim 5, characterized in that, If there is no match, the process of reading the storage data corresponding to the read request from the host memory module includes: If there is no match, or if the target cache address that is matched is in an idle state, then it is determined that the cache has missed, and a read request is sent to the host memory module to read the storage data corresponding to the read request.

7. The method according to any one of claims 1 to 6, characterized in that, The method further includes: After each matching query, the matching result is recorded in the read direction record FIFO of the RDMA Cache module; When the read direction record FIFO is not empty, a data read path is selected according to the record information in the read direction record FIFO; the data read path includes reading the storage data corresponding to the read request from the RDMACache module and reading the storage data corresponding to the read request from the host memory module.

8. A system for implementing an RDMA network card request queue, characterized in that, The system includes: an RDMACache module and a host memory module that are interconnected. The RDMACache module manages the cache address where the request queue is stored, the free space of the cache address, the queue pair number, and the incomplete pointer. The RDMA Cache module is used to execute an implementation method of an RDMA network card request queue according to any one of claims 1 to 7.

9. The system according to claim 8, characterized in that, The RDMACache module includes a control unit and an on-chip address mapping management unit. The first end of the control unit is connected to the on-chip address mapping management unit, and the second end of the control unit is also connected to the host memory module. The control unit includes a read control unit and a write control unit. The write control unit is used to receive write requests and control write operations; the read control unit is used to receive read requests and control read operations. The on-chip address mapping management unit is used to manage the cache address, free space of the cache address, queue pair number and incomplete pointer stored in the request queue, as well as the mapping relationship between the cache address, the queue pair number and the incomplete pointer. It is also used to store write information written to the RDMA cache module.

10. The system according to claim 9, characterized in that, The system also includes a read initiation module and a write initiation module; the read initiation module is connected to the input terminal of the read control unit through a read interface, and the write initiation module is connected to the input terminal of the write control unit through a write interface; The read initiation module is used to initiate a read operation and send a read request to the read control unit; the write initiation module is used to initiate a write operation and send a write request to the write control unit.

11. A computer device, characterized in that, include: The system includes a memory and a processor, which are interconnected. The memory stores computer instructions, and the processor executes the computer instructions to perform an implementation method for an RDMA network card request queue as described in any one of claims 1 to 7.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute a method for implementing an RDMA network card request queue according to any one of claims 1 to 7.

13. A computer program product, characterized in that, Includes computer instructions for causing a computer to execute a method for implementing an RDMA network card request queue according to any one of claims 1 to 7.

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