Translation lookaside buffer query acceleration system, method, device, medium and product

Abstract

The invention discloses a translation lookaside buffer query acceleration system, method and device, a medium and a product, and relates to the technical field of electric digital data processing, and the system comprises a multi-stage translation lookaside buffer and a translation lookaside buffer filter which are in communication connection with each other. The translation backup buffer filter comprises a hash function module and a digit array module which are in communication connection with each other. The multi-level translation lookaside buffer is used for receiving an address translation request and querying target address mapping corresponding to the address translation request, the translation lookaside buffer filter and the multi-level translation lookaside buffer work in parallel, at least one hash abstract value is generated according to the address translation request, and the at least one hash abstract value is sent to the multi-level translation lookaside buffer. And comparing the hash digest value with a historical hash digest value in the digit array module to judge whether the target address mapping exists in the multi-level translation lookaside buffer, if not, interrupting the on-going query operation of the multi-level translation lookaside buffer, performing memory access to obtain the target address mapping, and if not, performing memory access to obtain the target address mapping. And the query efficiency of the translation lookaside buffer is improved.

Description

Technical Field

[0001] The present application relates to the field of electronic digital data processing technology, and in particular to a translation lookaside buffer query acceleration system, method, device, medium and product. Background Art

[0002] Traditional IOMMU (I / O Memory Management Unit) & MMU (Memory Management Unit) provide conversion functions related to address isolation such as address mapping and remapping for devices and systems respectively, and also provide management functions such as read and write permissions, memory attributes, and cache attributes. In the soc (system on chip) system, this type of memory management unit converts the virtual address issued by the master (which can be a CPU (Central Processing Unit) core or device) into the physical address of the main memory. There is a TLB (translation lookaside buffer) inside the MMU / IOMMU for caching address mapping translation. And in most processor architectures, the translation lookaside buffer is usually multi-level. The design of the multi-level translation lookaside buffer structure reduces the probability of translation lookaside buffer misses and adapts to different access modes, which is necessary for improving system performance. However, the design of the multi-level translation lookaside buffer brings a problem that cannot be ignored, that is, all translation requests from the master will first query the multi-level translation lookaside buffer to see if there is a corresponding address mapping cache. When there are multi-level translation lookaside buffers, as the number of levels increases, the time consumed in the query process will gradually increase. In addition, in some special scenarios (such as the initial system startup or large-scale page table updates), a large number of cache misses will occur during the query of the multi-level translation lookaside buffer, and this part of the time overhead will become huge and meaningless. Summary of the invention

[0003] The main purpose of the present application is to provide a translation lookaside buffer query acceleration system, method, device, medium and product, aiming to solve the technical problem of low translation lookaside buffer query efficiency.

[0004] To achieve the above-mentioned purpose, the present application proposes a translation lookaside buffer query acceleration system, which includes a multi-level translation lookaside buffer and a translation lookaside buffer filter that are communicatively connected to each other, and the multi-level translation lookaside buffer and the translation lookaside buffer filter are placed in a translation buffer unit and connected to a translation control unit, and the translation lookaside buffer filter includes a hash function module and a bit array module that are communicatively connected to each other,

[0005] A multi-level translation backup buffer is used to receive address translation requests sent by external devices and query the target address mapping corresponding to the address translation request.

[0006] A translation lookaside buffer filter is used to generate at least one hash summary value in a hash function module according to an address translation request, compare all hash summary values ​​with historical hash summary values ​​stored in a bit array module to obtain a comparison result, and determine whether a target address mapping exists in a multi-level translation lookaside buffer according to the comparison result. If the target address mapping does not exist in the multi-level translation lookaside buffer, the query operation of the multi-level translation lookaside buffer for querying the target address mapping corresponding to the address translation request is interrupted, and a preset translation control unit obtains the target address mapping by accessing memory and sends the target address mapping to an external device.

[0007] In one embodiment, the multi-level translation lookaside buffer includes a first-level translation lookaside buffer and a second-level translation lookaside buffer.

[0008] The first-level translation lookaside buffer is used to receive an address translation request sent by an external device, query the target address mapping corresponding to the address translation request, and send the address translation request to the second-level translation lookaside buffer if the target address mapping does not exist.

[0009] The second-level translation lookaside buffer is used to receive the address translation request sent by the first-level translation lookaside buffer, query the target address mapping, and if the target address mapping does not exist, the preset translation control unit obtains the target address mapping by accessing the memory.

[0010] In one embodiment, a translation lookaside buffer query acceleration system includes a multi-level translation lookaside buffer and a translation lookaside buffer filter that are communicatively connected to each other, and the multi-level translation lookaside buffer and the translation lookaside buffer filter are placed in a translation buffer unit and connected to a translation control unit, and the translation lookaside buffer filter includes a hash function module and a bit array module that are communicatively connected to each other, and a translation lookaside buffer query acceleration method includes:

[0011] receiving an address translation request sent by an external device to a translation lookaside buffer filter and a multi-stage translation lookaside buffer;

[0012] querying a target address mapping corresponding to the address translation request in a multi-level translation lookaside buffer;

[0013] According to the address translation request, in the translation lookaside buffer filter, at least one hash summary value is generated using a hash function module, all hash summary values ​​are compared with the historical hash summary values ​​stored in the bit array module to obtain a comparison result, and according to the comparison result, it is determined whether the target address mapping exists in the multi-level translation lookaside buffer. If the target address mapping does not exist in the multi-level translation lookaside buffer, the query operation of the multi-level translation lookaside buffer for the target address mapping corresponding to the address translation request is interrupted, and the preset translation control unit obtains the target address mapping by accessing the memory, and sends the target address mapping to the external device.

[0014] In one embodiment, the multi-level translation lookaside buffer includes a first-level translation lookaside buffer and a second-level translation lookaside buffer, and the step of querying the target address mapping corresponding to the address translation request in the multi-level translation lookaside buffer includes:

[0015] receiving an address translation request sent by an external device in a first-level translation lookaside buffer, and querying a target address mapping corresponding to the address translation request;

[0016] If the target address mapping does not exist in the first-level translation lookaside buffer, querying the target address mapping in the second-level translation lookaside buffer;

[0017] If the target address mapping does not exist in the second-level translation lookaside buffer, the preset translation control unit obtains the target address mapping by accessing the memory.

[0018] In one embodiment, the step of comparing all hash digest values ​​with historical hash digest values ​​stored in the bit array module includes:

[0019] Compare the hash digest value with the historical hash digest value in the position where the identifier is stored in the bit array;

[0020] If the hash digest value is the same as any historical hash digest value, it is determined that the hash digest value exists in the bit array.

[0021] In one embodiment, the step of comparing all hash digest values ​​with the historical hash digest values ​​stored in the bit array module includes:

[0022] If all hash digest values ​​match the historical hash digest values ​​stored in the bit array module, it is determined that the target address mapping exists in the multi-level translation lookaside buffer;

[0023] If there is at least one hash digest value that does not match the historical hash digest value stored in the bit array module, it is determined that the target address mapping does not exist in the multi-level translation lookaside buffer.

[0024] In one embodiment, the step of obtaining the target address mapping by accessing memory by a preset translation control unit includes:

[0025] updating the target address mapping into the first-level translation lookaside buffer or the second-level translation lookaside buffer and storing all hash digest values ​​into the bit array;

[0026] Mark the storage locations of all hash summary values ​​in the bit array with a stored flag.

[0027] In addition, to achieve the above-mentioned purpose, the present application also proposes a medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the translation backup buffer query acceleration method as described above are implemented.

[0028] In addition, to achieve the above-mentioned purpose, the present application also provides a product, which is a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps of the translation backup buffer query acceleration method as described above are implemented.

[0029] One or more technical solutions proposed in this application have at least the following technical effects:

[0030] In the present application, a translation lookaside buffer query acceleration system is provided, which includes a multi-level translation lookaside buffer and a translation lookaside buffer filter that are communicatively connected to each other, and the multi-level translation lookaside buffer and the translation lookaside buffer filter are placed in a translation buffer unit and connected to a translation control unit, thereby achieving efficient processing of address translation requests. The translation lookaside buffer filter comprises a hash function module and a bit array module which are communicatively connected to each other; the module is used to generate at least one hash summary value in the hash function module according to the address translation request sent by the external device, compare all the hash summary values ​​with the historical hash summary values ​​stored in the bit array module to obtain a comparison result, and judge whether the target address mapping exists in the multi-level translation lookaside buffer according to the comparison result, thereby greatly shortening the judgment time; if the target address mapping does not exist in the multi-level translation lookaside buffer, the query operation of the multi-level translation lookaside buffer to query the target address mapping corresponding to the address translation request is interrupted, and the preset translation control unit obtains the target address mapping by accessing the memory, and sends the target address mapping to the external device. Through this design, the system can effectively avoid continuing the meaningless query process in the case of a translation lookaside buffer miss, significantly reducing the query delay and resource waste caused by a high miss rate, and improving the efficiency of the translation lookaside buffer query. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A flowchart for translating a lookaside buffer for a query;

[0034] Figure 2 A schematic diagram of the structure of the translation backup buffer query acceleration system for this application;

[0035] Figure 3 A flowchart of a second embodiment of the translation backup buffer query acceleration method of the present application;

[0036] Figure 4 It is another flowchart of the second embodiment of the translation backup buffer query acceleration method of the present application;

[0037] Figure 5 Schematic diagram of the device structure of the hardware operating environment involved in the translation backup buffer query acceleration method in the embodiment of the present application.

[0038] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0039] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0040] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0041] For requests from devices, it is necessary to first query the multi-level translation lookaside buffer in the process of obtaining the corresponding address mapping relationship from the IOMMU / MMU and sending the request to the system. Taking IOMMU as an example, when the traffic of the master accessing the system increases, especially the DMA (Direct Memory Access) requests from multiple devices need to go through the IOMMU, then the time consumed in querying the multi-level translation lookaside buffer in the IOMMU cannot be ignored. Especially in the early stage of system startup or when the system updates the page table on a large scale, the first-level translation lookaside buffer / second-level translation lookaside buffer in the IOMMU does not cache any valid address mapping entries. At this time, a large number of requests pass through the IOMMU and check the cache, which will inevitably cause a large number of cache misses. The flowchart of querying the translation lookaside buffer once is as follows: Figure 1 As shown:

[0042] ① The device initiates an address translation request and sends the following request information: is_sec / sid / ssid / IA(inputaddress) / flow / …;

[0043] ② The hardware queries the first-level translation lookaside buffer based on the request information, and finds out whether there is a corresponding cache line by comparing the request information with the tags of all cache lines in the first-level translation lookaside buffer:

[0044] a) If the corresponding cache line is found, the control bit field (vmid, allow_ur, ...) related to the permission in the tag is compared to determine whether the access has permission to translate; if the permission is passed, the corresponding data is obtained from the data array, and the corresponding address attributes (hwattr, privcfg, ...) are set for the translation request. The query ends with a translation lookaside buffer hit, and the physical address in the data array is returned to the device.

[0045] b) If the corresponding cache line is not found in the first level translation lookaside buffer, it is a translation lookaside buffer miss.

[0046] ③If the first-level translation lookaside buffer does not hit, it enters the second-level translation lookaside buffer and directly finds out whether there is a corresponding cache line by comparing the tag:

[0047] a) If the corresponding cache line is found, check and set it according to the same process as step ②. End the query with a translation lookaside buffer hit and return the physical address to the device.

[0048] b) If the corresponding cache line is not found in the second level translation lookaside buffer, it is a translation lookaside buffer miss.

[0049] ④ If the second-level translation lookaside buffer does not hit, the memory is accessed through the bus through the translation control unit, and the device table -> context descriptor -> page table is searched according to the request information to obtain the final address mapping relationship, which is returned to the device and cached in the translation lookaside buffer at the same time.

[0050] In the above system scenario, if the translation lookaside buffer miss rate is very high, then each request may need to go through steps ①->②(->③)->④, and when querying the first-level translation lookaside buffer or the second-level translation lookaside buffer, there are various permission checks, address attribute assignments, etc., which will consume a certain amount of time, which will cause the transmission of requests from the device at the IOMMU layer to become slow, reducing system performance. If the translation lookaside buffer miss rate is very high, the time spent on steps ② / ③ is unnecessary.

[0051] To solve the above problems, the present embodiment provides a translation lookaside buffer query acceleration solution, which introduces a translation lookaside buffer filter in the traditional translation lookaside buffer query process, which is used to pre-judge the probability of the translation lookaside buffer hit and assert that the translation lookaside buffer misses, such as a bloom filter, whose hardware position in the TBU (Translation Buffer Unit) is shown in the figure above, and its characteristic is that it is composed of a large bit array and a series of random mapping functions, which can be used to retrieve whether an element is in a set. Its advantage is that it can improve the query efficiency of multi-level translation lookaside buffers and reduce query pressure, especially the system bottleneck pressure under low translation lookaside buffer hit rate. It saves the time consumed by the entire translation process.

[0052] The present embodiment is from the angle of improving efficiency, because the translation lookaside buffer filter determines whether to intervene in the flow process of querying the first level / second level translation lookaside buffer, so the translation lookaside buffer filter can save the time cost that a known translation lookaside buffer miss brings.Particularly in the multi-stage translation lookaside buffer structure, the more the number of stages, the longer the query time is, so it is known that the time spent in the translation lookaside buffer hit / miss is also longer, and if once it is a translation lookaside buffer miss, then this part of time cost is actually meaningless.And under some special system scenes, such as the system startup initial stage or the system changes the page table in a large number of situations, when querying the multi-stage translation lookaside buffer, a large amount of translation lookaside buffer misses will definitely be caused, and this will certainly hinder the system performance.Therefore, if the query result of the multi-stage translation lookaside buffer can be known in advance in the translation lookaside buffer filter, it is possible to terminate or not intervene in the normal query process, thereby the time loss and the flow congestion caused by the potential large amount of translation lookaside buffer misses can be avoided.

[0053] Based on this, an embodiment of the present application provides a translation lookaside buffer query acceleration system.

[0054] In this embodiment, the translation lookaside buffer query acceleration system includes a multi-level translation lookaside buffer and a translation lookaside buffer filter that are communicatively connected to each other, and the multi-level translation lookaside buffer and the translation lookaside buffer filter are placed in a translation buffer unit and connected to a translation control unit, and the translation lookaside buffer filter includes at least one hash function module and a bit array module that are communicatively connected to each other.

[0055] A multi-level translation backup buffer is used to receive address translation requests sent by external devices and query the target address mapping corresponding to the address translation request.

[0056] A translation lookaside buffer filter is used to generate at least one hash summary value in a hash function module according to an address translation request, compare all hash summary values ​​with historical hash summary values ​​stored in a bit array module to obtain a comparison result, and determine whether a target address mapping exists in a multi-level translation lookaside buffer according to the comparison result. If the target address mapping does not exist in the multi-level translation lookaside buffer, the query operation of the multi-level translation lookaside buffer for querying the target address mapping corresponding to the address translation request is interrupted, and a preset translation control unit obtains the target address mapping by accessing memory and sends the target address mapping to an external device.

[0057] In the present embodiment, the translation buffer unit is a high-speed cache memory inside a processor, which is specifically used to store and accelerate the conversion process of virtual addresses to physical addresses. The information in the conversion process usually comes from a page table, but direct access to the page table may be very time-consuming because the page table may be stored in a slower memory, such as a main memory. The translation buffer unit reduces the number of direct accesses to the page table by caching the most recently used address conversion information, thereby improving the speed of address conversion. It includes a multi-level translation backup buffer and a translation backup buffer filter. The translation control unit is responsible for controlling and managing the address conversion process, including the traversal and updating of the page table. The translation buffer unit works closely with the translation control unit, and the translation buffer unit is responsible for caching the address conversion results, while the translation control unit is responsible for ensuring the accuracy and effectiveness of these results. When the information in the translation buffer unit is invalid or needs to be updated, the translation control unit will instruct the translation buffer unit to perform corresponding operations.

[0058] The multi-level translation lookaside buffer consists of multiple levels of translation lookaside buffers. The translation lookaside buffer is a CPU cache used by the memory management unit to improve the speed of translating virtual addresses to physical addresses. The translation lookaside buffer has a fixed number of space slots for storing tag page table entries that map virtual addresses to physical addresses. When the CPU needs to access memory, it first checks whether the translation lookaside buffer contains the required virtual address to physical address mapping. If it exists, the physical address can be used directly to access the memory, thus avoiding access to the slower main memory or page table. If it does not exist, a virtual-to-real address conversion is required, which usually involves accessing the page table, which significantly reduces the memory access speed.

[0059] The translation lookaside buffer filter can be a special hardware module for improving the efficiency of address translation. The translation lookaside buffer filter is provided with complex logic circuits and storage units. The translation lookaside buffer filter can pre-judge and interrupt queries for address translation requests that are unlikely to be found in the multi-level translation lookaside buffer.

[0060] The hash function module can be several sets of predefined hash algorithms, which are used to encrypt input data and generate a unique hash value (digest value). When a set of input data is processed by multiple hash functions, multiple different hash values ​​can be obtained.

[0061] The bit array can be a large storage structure for storing all possible hash values. A large number of storage locations are set in the bit array, and the bit array can quickly update and check the existence of hash values.

[0062] The hash function module and the bit array communicate with each other in the translation lookaside buffer filter. Each hash value generated by the hash function module is used to query the bit array to determine whether the corresponding address translation request can be found in the multi-level translation lookaside buffer. The bit array provides the ability to store and retrieve hash values, while the hash function module is responsible for generating these values.

[0063] At least one hash function is used to ensure that the address translation request can be checked from multiple perspectives to reduce the possibility of false positives. Multiple hash functions can provide more comprehensive coverage, thereby improving the accuracy of filter predictions. In addition, different hash functions may reveal different data patterns, which can help to more accurately predict the existence of address mappings.

[0064] After the device sends the address translation request to the multi-level translation lookaside buffer, the multi-level translation lookaside buffer query process and the translation lookaside buffer filter judgment process are performed synchronously. In the translation lookaside buffer filter judgment process, the translation lookaside buffer filter generates a hash summary value and compares it with the bit array. If it is judged as a miss, the query of the multi-level translation lookaside buffer is interrupted, and the translation control unit is instructed to obtain the address mapping through the page table traversal operation, and the cache in the multi-level translation lookaside buffer is updated at the same time, and the hash summary value is stored in the bit array.

[0065] In this embodiment, a translation lookaside buffer query acceleration system is provided, which includes a multi-level translation lookaside buffer and a translation lookaside buffer filter that are communicatively connected to each other, and the multi-level translation lookaside buffer and the translation lookaside buffer filter are placed in a translation buffer unit and connected to a translation control unit, thereby achieving efficient processing of address translation requests. The translation lookaside buffer filter comprises a hash function module and a bit array module which are communicatively connected to each other; the module is used to generate at least one hash summary value in the hash function module according to the address translation request sent by the external device, compare all the hash summary values ​​with the historical hash summary values ​​stored in the bit array module to obtain a comparison result, and judge whether the target address mapping exists in the multi-level translation lookaside buffer according to the comparison result, thereby greatly shortening the judgment time; if the target address mapping does not exist in the multi-level translation lookaside buffer, the query operation of the multi-level translation lookaside buffer to query the target address mapping corresponding to the address translation request is interrupted, and the preset translation control unit obtains the target address mapping by accessing the memory, and sends the target address mapping to the external device. Through this design, the system can effectively avoid continuing the meaningless query process in the case of a translation lookaside buffer miss, significantly reducing the query delay and resource waste caused by a high miss rate, and improving the efficiency of the translation lookaside buffer query.

[0066] In a feasible implementation, the multi-level translation lookaside buffer includes a first-level translation lookaside buffer and a second-level translation lookaside buffer.

[0067] The first-level translation lookaside buffer is used to receive an address translation request sent by an external device, query the target address mapping corresponding to the address translation request, and send the address translation request to the second-level translation lookaside buffer if the target address mapping does not exist.

[0068] The second-level translation lookaside buffer is used to receive the address translation request sent by the first-level translation lookaside buffer, query the target address mapping, and if the target address mapping does not exist, the preset translation control unit obtains the target address mapping by accessing the memory.

[0069] In this embodiment, the first-level translation lookaside buffer may be a high-speed cache integrated in the CPU, which is used to quickly respond to address translation requests. A fast-access data structure is provided in the first-level translation lookaside buffer, which can quickly respond to address translation requests. For example, a plurality of cache entries may be provided in the first-level translation lookaside buffer, which are stored in a fully associative mapping structure, and contain attributes such as a tag of a virtual address and a corresponding physical address and access rights, and are used to quickly determine whether an address translation request issued by a device can find a corresponding mapping relationship at the first level.

[0070] The second-level translation lookaside buffer can be a cache that is larger than the first-level translation lookaside buffer but has a slightly slower access speed. The data structure stored in the second-level translation lookaside buffer is consistent with the first-level translation lookaside buffer, and a multi-way set-associated mapping structure can be used. The second-level translation lookaside buffer can provide backup address translations for requests that miss in the first level.

[0071] During a multi-level translation lookaside buffer query, if the first-level translation lookaside buffer misses, the request flows to the second-level translation lookaside buffer.

[0072] Exemplary, reference Figure 2 The translation lookaside buffer filter in the embodiment includes a hash function and a bit array, wherein there are two hash functions. When the translation lookaside buffer filter receives the request information 2 sent by the device, two hash summary values ​​are generated according to the request information 2 and compared in the bit array. There are two results after the comparison. Result 1 is that the two hash summary values ​​exist in the position marked as 1 in the bit array. At this time, it means that the address mapping corresponding to the request information 2 exists in the first-level translation lookaside buffer or the second-level translation lookaside buffer. The translation lookaside buffer filter does not need to interfere with the multi-level translation lookaside buffer query process; Result 2 is two At least one of the hash summary values ​​does not exist in the position marked as 1 in the bit array, which means that the address mapping corresponding to the request information 2 does not exist in the first-level translation lookaside buffer or the second-level translation lookaside buffer. The translation lookaside buffer filter needs to interrupt the query of the first-level translation lookaside buffer and the second-level translation lookaside buffer, and the translation control unit directly obtains the address mapping through memory access, updates the address mapping to the first-level translation lookaside buffer or the second-level translation lookaside buffer, stores all hash summary values ​​in the bit array, and marks the storage positions of all hash summary values ​​in the bit array as 1.

[0073] In this embodiment, by providing a translation lookaside buffer query acceleration system, including a first-level translation lookaside buffer, a second-level translation lookaside buffer and a translation lookaside buffer filter that are communicatively connected to each other, the system significantly improves the efficiency of the system in processing address translation requests. The first-level translation lookaside buffer is used to cache the first-level address mapping information, receive the address translation request sent by the device and return the target address mapping corresponding to the address translation request, thereby reducing the need for direct access to the main memory. The second-level translation lookaside buffer is used to cache the second-level address mapping information, and when the target address mapping does not exist in the first-level translation lookaside buffer, the target address mapping is queried, which effectively reduces the situation of direct access to the page table and improves the performance of the system. A translation lookaside buffer filter is used to generate a hash summary value for an address translation request and compare all hash summary values ​​with the values ​​in a bit array. This process is performed synchronously with a multi-level translation lookaside buffer query without additional time overhead. Based on the comparison result, it is determined whether the address mapping exists in the first-level translation lookaside buffer or the second-level translation lookaside buffer. If the address mapping does not exist in the first-level translation lookaside buffer or the second-level translation lookaside buffer, the query of the first-level translation lookaside buffer and the second-level translation lookaside buffer is interrupted, and the translation control unit obtains the address mapping by accessing the memory. Through this design, the system can effectively avoid continuing a meaningless query process in the event of a translation lookaside buffer miss, significantly reducing query delays and resource waste caused by a high miss rate, and improving the efficiency of the translation lookaside buffer query.

[0074] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the first embodiment can be referred to the above introduction and will not be repeated later.

[0075] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device capable of realizing the above functions, a terminal system, etc. The following takes the translation lookaside buffer query acceleration system (hereinafter referred to as the system) as an example to illustrate this embodiment and the following embodiments.

[0076] This embodiment also provides a translation lookaside buffer query acceleration method, referring to Figure 3 , Figure 3 This is a flow chart of a second embodiment of the translation lookup buffer acceleration method of the present application, the method comprising steps S10 to S30:

[0077] Step S10, receiving an address translation request sent by an external device to a translation lookaside buffer filter and a multi-stage translation lookaside buffer;

[0078] It should be noted that an address translation request is a request initiated by a device to convert a virtual memory address into a physical memory address so that the CPU or other processing units can access the actual physical memory location. The translation lookaside buffer filter is an acceleration component that runs in parallel with the translation lookaside buffer and is used to quickly determine whether an address mapping already exists in the translation lookaside buffer to reduce the number of accesses to slow memory (such as page tables).

[0079] The device sends an address translation request to the system, requesting to convert the virtual memory address into a physical memory address, and the system receives the address translation request from the external device.

[0080] Step S20, querying the target address mapping corresponding to the address translation request in the multi-level translation lookaside buffer;

[0081] The system first attempts to find the target address mapping corresponding to the address translation request in the multi-level translation lookaside buffer, which searches through its hierarchical structure, starting from the fastest but smallest level and gradually moving to the slower but larger levels.

[0082] In a feasible implementation manner, step S20 may include steps P10 to P20:

[0083] Step P10, receiving an address translation request sent by an external device in the first-level translation lookaside buffer, and querying a target address mapping corresponding to the address translation request;

[0084] It should be noted that the first-level translation lookaside buffer is a high-speed cache that stores the mapping between recently accessed memory addresses and their corresponding physical addresses. This mapping is crucial for virtual memory management, which can speed up the address translation process and reduce the number of CPU accesses to the memory management unit (MMU).

[0085] When the CPU needs to access a memory address, it first checks whether the mapping of the virtual address to the physical address is already stored in the first-level translation lookaside buffer. This is because the first-level translation lookaside buffer is located at the cache level closest to the CPU and has the fastest access speed, which can significantly reduce the time required for address translation. If the address mapping exists in the first-level translation lookaside buffer, the physical address is directly used to access the memory, and the process ends.

[0086] Step P20, if the target address mapping does not exist in the first-level translation lookaside buffer, query the target address mapping in the second-level translation lookaside buffer;

[0087] It should be noted that it is similar to the first-level translation lookaside buffer, but is located at a lower level in the memory hierarchy, usually with a larger capacity but a slightly slower access speed. When the required address mapping is not found in the first-level translation lookaside buffer, the system will try to find it in the second-level translation lookaside buffer to expand the search range and improve the efficiency of address translation.

[0088] If the required address mapping is not found in the first-level translation lookaside buffer, the CPU will further search in the second-level translation lookaside buffer. Although the second-level translation lookaside buffer has a slightly slower access speed, it can store more address mapping information due to its larger capacity. If the target address mapping is found in the second-level translation lookaside buffer, the physical address is also used to access the memory, and the process ends.

[0089] Step P30: If the target address mapping does not exist in the second-level translation lookaside buffer, the preset translation control unit obtains the target address mapping by accessing the memory.

[0090] It should be noted that the core component responsible for memory address translation usually works closely with the MMU. When neither the first-level translation lookaside buffer nor the second-level translation lookaside buffer can provide the required address mapping, the translation control unit will intervene and may obtain or calculate the missing address mapping by querying the page table or other mechanisms.

[0091] If both the first-level and second-level translation lookaside buffers fail to provide the required address mapping, it must be obtained through a more complex mechanism. At this point, the CPU will issue a request to the translation control unit, which may find the missing address mapping by consulting a page table (a data structure that stores virtual address to physical address mappings) or other mechanisms. Once the translation control unit successfully finds the address mapping, it is added to the first-level or second-level translation lookaside buffer (depending on the implementation and strategy) so that future accesses can be completed faster. Finally, the obtained physical address is used to access the memory, completing the entire address translation process.

[0092] For example, in the Xiangshan processor architecture, the MMU has a built-in 2-level translation lookaside buffer. The first-level translation lookaside buffer includes ITLB (instruction translation lookaside buffer) and DTLB (Data translation lookaside buffer), which adopts a fully associative mapping structure, characterized by fast query speed, but small capacity, and the number of cache entries does not exceed 80. The second-level translation lookaside buffer can usually cache more entries, usually at the KB (Kilobyte, a unit of information measurement) level, and is characterized by a multi-way group-associated mapping structure. The query speed will be slower than the first-level translation lookaside buffer. When the query of the first-level translation lookaside buffer does not hit, the query will be made to the second-level translation lookaside buffer. It is similar in the MMU / IOMMU in the ARM architecture. For example, the IOMMU has a built-in 2-level translation lookaside buffer - uTLB (microTLB, micro translation lookaside buffer, also called first-level translation lookaside buffer) & mTLB (main TLB, main translation lookaside buffer, also called second-level translation lookaside buffer).

[0093] The present embodiment uses a hierarchical translation lookaside buffer structure, firstly uses a high-speed and CPU-close first-level translation lookaside buffer for fast search, greatly shortens the search time of common address mapping, and improves system performance. When there is a miss in the first-level translation lookaside buffer, it automatically turns to the second-level translation lookaside buffer with larger capacity but slightly slower speed, widens the search range, and still maintains a higher translation efficiency. If both levels of translation lookaside buffers cannot meet the demand, the target address mapping is accurately obtained by a preset translation control unit with the help of a complex page table query mechanism, ensuring the integrity and accuracy of address translation. The whole process effectively reduces the direct access of the CPU to the memory management unit, reduces system overhead, and improves overall memory access efficiency, which is particularly important for large-scale applications and complex systems that need to frequently perform address translation.

[0094] Step S30: Generate at least one hash summary value in the translation lookaside buffer filter using a hash function module according to the address translation request, compare all hash summary values ​​with the historical hash summary values ​​stored in the bit array module to obtain a comparison result, and determine whether the target address mapping exists in the multi-level translation lookaside buffer according to the comparison result; if the target address mapping does not exist in the multi-level translation lookaside buffer, interrupt the query operation of the multi-level translation lookaside buffer for the target address mapping corresponding to the address translation request, and obtain the target address mapping by accessing the memory through a preset translation control unit, and send the target address mapping to an external device.

[0095] It should be noted that a hash function is a function that converts an input of any length (such as an address in an address translation request) into a fixed-length output (i.e., a hash summary value) through a certain algorithm. It is used to quickly retrieve and verify whether data exists. In this embodiment, there are multiple hash functions, and the specific number can be freely set, depending on the specific situation. The purpose of setting multiple hash functions is to reduce the error rate and increase the judgment accuracy. The hash summary value is a fixed-length value calculated by a hash function, which is usually used for fast comparison and verification of data. A bit array is a data structure stored in bits, usually used to represent a set, and each bit represents whether an element in the set exists. In the translation lookaside buffer filter, it is used to store the hash summary value to determine whether the address mapping already exists in the translation lookaside buffer. The first-level translation lookaside buffer is a translation lookaside buffer close to the CPU in the CPU cache hierarchy, with an extremely fast access speed, and is used to store the most commonly used address mappings. The second-level translation lookaside buffer is a translation lookaside buffer located after the first-level translation lookaside buffer, with a slightly slower access speed but a larger capacity, and is used to store more address mappings.

[0096] The translation lookaside buffer filter compares all generated hash digest values ​​with the values ​​stored in the bit array. Each bit (or a group of bits) in the bit array corresponds to a hash digest value. If a hash digest value exists in the bit array, it means that the address mapping may exist in the first-level translation lookaside buffer or the second-level translation lookaside buffer. The "may" here is because the hash function may produce a collision (different inputs produce the same output), that is, multiple address mappings may be mapped to the same hash digest value. Based on the comparison results of the bit array, the translation lookaside buffer filter can preliminarily determine whether the address mapping exists in the first-level translation lookaside buffer or the second-level translation lookaside buffer. If all relevant hash digest values ​​exist in the bit array, the translation lookaside buffer filter may believe that the address mapping exists, but it needs to be confirmed by querying the first-level translation lookaside buffer and the second-level translation lookaside buffer. If any hash digest value does not exist in the bit array, the translation lookaside buffer filter can directly determine that the address mapping does not exist in the first-level translation lookaside buffer and the second-level translation lookaside buffer.

[0097] In this embodiment, a translation lookaside buffer query acceleration system is provided, which includes a multi-level translation lookaside buffer and a translation lookaside buffer filter that are communicatively connected to each other, and the multi-level translation lookaside buffer and the translation lookaside buffer filter are placed in a translation buffer unit and connected to a translation control unit, thereby achieving efficient processing of address translation requests. The translation lookaside buffer filter comprises a hash function module and a bit array module which are communicatively connected to each other; the module is used to generate at least one hash summary value in the hash function module according to the address translation request sent by the external device, compare all the hash summary values ​​with the historical hash summary values ​​stored in the bit array module to obtain a comparison result, and judge whether the target address mapping exists in the multi-level translation lookaside buffer according to the comparison result, thereby greatly shortening the judgment time; if the target address mapping does not exist in the multi-level translation lookaside buffer, the query operation of the multi-level translation lookaside buffer to query the target address mapping corresponding to the address translation request is interrupted, and the preset translation control unit obtains the target address mapping by accessing the memory, and sends the target address mapping to the external device. Through this design, the system can effectively avoid continuing the meaningless query process in the case of a translation lookaside buffer miss, significantly reducing the query delay and resource waste caused by a high miss rate, and improving the efficiency of the translation lookaside buffer query.

[0098] In one possible implementation, refer to Figure 4 , Figure 4 This is another flowchart of the second embodiment of the translation backup buffer query acceleration method of the present application. Step S30 may include steps T10 to T20:

[0099] Step T10, updating the address mapping into the multi-level translation lookaside buffer and storing all hash summary values ​​into a bit array;

[0100] It should be noted that the first-level translation lookaside buffer is a type of CPU cache that is used to store a mapping table from virtual addresses to physical addresses to speed up memory access. When the CPU tries to access memory, it first checks whether there is already a mapping for the virtual address in the first-level translation lookaside buffer, thereby avoiding slower memory access or page table traversal. In some complex systems, there may be a multi-level translation lookaside buffer structure. The second-level translation lookaside buffer is a supplement to the first level, storing more or more detailed mapping information to provide additional address translation support when the first-level translation lookaside buffer misses.

[0101] When the system needs to update the mapping of a virtual address to a physical address, it first calculates the hash summary value of the virtual address. Then, the system decides whether to update the mapping to the first-level translation lookaside buffer or the second-level translation lookaside buffer based on a certain strategy (such as the mapping rule of the hash table). This decision may be based on the current usage of the translation lookaside buffer (such as hit rate, capacity, etc.) or a specific system strategy. When the target translation lookaside buffer is determined, the system creates or updates the corresponding mapping entry in the translation lookaside buffer to store the correspondence between the virtual address and the physical address. Regardless of which level of the translation lookaside buffer the mapping is updated to, the system stores the calculated hash summary value in the bit array.

[0102] Step T20, marking the storage locations of all hash summary values ​​in the bit array with a stored flag.

[0103] It should be noted that the stored flag is an flag in the bit array used to mark whether a hash summary value has been stored at that position. It can be a bit (0 or 1), where 1 indicates that it has been stored and 0 indicates that it has not been stored.

[0104] When storing the hash summary value in the bit array, the system will set the stored flag at the corresponding position (such as setting the bit to 1). The purpose of this flag is to tell the system or other query mechanism that the hash summary value already exists in the bit array and does not need to be calculated or queried again. When the system needs to verify whether a virtual address has been translated, it will first calculate the hash summary value of the address and search the bit array for the hash summary value in the position marked with the stored flag. If the hash summary value exists in the bit array, it indicates that the address mapping information may exist in a translation backup buffer, and the system can further search the translation backup buffer for a specific address mapping.

[0105] Through this embodiment, the system significantly enhances the update efficiency and query accuracy of address mapping. Whenever the address mapping is updated to the first-level or second-level translation backup buffer, its corresponding hash summary value is immediately stored in the bit array and marked as stored. This process ensures the consistency and integrity of the data. The stored identifier in the bit array serves as an index for fast retrieval, which greatly reduces repeated calculations and query time, especially when processing high-frequency access address mappings, and can significantly improve the system response speed and performance. In addition, this mechanism also optimizes memory usage, avoids unnecessary resource consumption, and makes the management of the translation backup buffer more efficient and flexible.

[0106] Based on the first or second embodiment of the present application, in the third embodiment of the present application, the same or similar contents as those in the first or second embodiment can be referred to the above introduction, and will not be described in detail later. Step S30 also includes steps A10 to A20:

[0107] Step A10, comparing the hash summary value with the historical hash summary value in the position where the identifier is stored in the bit array;

[0108] It should be noted that the historical hash digest value refers to the hash digest value represented by the bit with a stored flag (ie, marked as 1) in the bit array.

[0109] First, the hash digest value to be checked is compared with the historical hash digest values ​​in all the positions in the bit array that have stored flags (i.e. marked as 1). This step involves traversing all occupied positions in the bit array and taking out the hash digest values ​​stored in them. During the traversal process, each historical hash digest value taken out is compared one by one with the hash digest value to be checked. The comparison is based on an exact match at the bit level, that is, two hash digest values ​​are considered to be the same only if they are exactly the same in each bit.

[0110] Step A20: If the hash digest value is the same as any historical hash digest value, it is determined that the hash digest value exists in the bit array.

[0111] If any historical hash summary value is found to be exactly the same as the hash summary value to be checked during the traversal process, it can be determined that the hash summary value does exist in the bit array. At this point, the process ends and returns a confirmation result of existence. If after traversing all historical hash summary values, no value identical to the hash summary value to be checked is found, it can be determined that the hash summary value does not exist in the bit array. At this point, the process also ends, but returns a result of non-existence.

[0112] Through this embodiment, the system can efficiently and accurately verify whether the hash summary value already exists in the bit array. This process uses the stored identifier to quickly locate the location that may contain the target hash summary value, and then confirms the existence of the hash summary value through precise comparison operations. This mechanism not only improves query efficiency and reduces unnecessary memory access, but also ensures data consistency and accuracy. In the scenario of processing a large number of hash summary values, this optimization strategy is particularly important and can significantly improve the overall performance and stability of the system.

[0113] In a feasible implementation manner, step S30 may include steps B10 to B20:

[0114] Step B10, if all hash digest values ​​match the historical hash digest values ​​stored in the bit array module, it is determined that the target address mapping exists in the multi-level translation lookaside buffer;

[0115] If the system finds that all the hash digest values ​​to be checked exist in the bit array, then it can be inferred that these address mappings exist at least in the multi-level translation lookaside buffer. This is because the mark in the bit array is set synchronously based on the previous addition of the address mapping to the translation lookaside buffer. This process is based on the uniqueness of the hash function and the efficiency of the bit array, and indirectly determines whether the address mapping exists in the translation lookaside buffer by quickly comparing the hash digest value. When all the hash digest values ​​to be checked can be found in the bit array of the translation lookaside buffer filter, it can only indicate that the address mapping corresponding to the address translation request has a great probability of being stored in the multi-level translation lookaside buffer, but it cannot be guaranteed to exist. This is due to the fact that the translation lookaside buffer filter has a certain miscalculation rate. Taking the number of input elements of 64k, the bit array width of 200KB, and the 2-round hash function processing as an example, the miscalculation rate is as low as 0.5%, which is very impressive. Therefore, there is enough confidence to ensure that the corresponding cache exists. Even if it is misjudged, it will not affect the original multi-level translation lookaside buffer query route, that is, it will not have any negative impact on normal working efficiency.

[0116] Through this embodiment, the system can efficiently determine whether the address mapping exists in the translation lookaside buffer, significantly improving memory access efficiency. The existence of all hash summary values ​​in the bit array indirectly proves the high probability of the address mapping. Although there is a small miscalculation rate, this mechanism ensures that the system can quickly locate the potential address mapping location with extremely low misjudgment cost, thereby optimizing the query path and reducing unnecessary page table access. This strategy not only improves the system response speed, but also maintains the integrity and flexibility of multi-level translation lookaside buffer queries.

[0117] Step B20: If there is at least one hash digest value that does not match the historical hash digest value stored in the bit array module, it is determined that the target address mapping does not exist in the multi-level translation lookaside buffer.

[0118] If the system finds that at least one of the hash digest values ​​to be checked does not exist in the bit array, then it can conclude that these address mappings are not in the multi-level translation lookaside buffer. This is because each missing flag in the bit array directly corresponds to an address mapping that is missing in the translation lookaside buffer.

[0119] Through this embodiment, the system can not only efficiently determine whether the address mapping exists in the translation lookaside buffer, significantly improving the efficiency of memory access, but also quickly and accurately determine whether the address mapping is missing in the translation lookaside buffer, effectively avoiding unnecessary cache queries and significantly improving the efficiency of memory access. The existence of all hash summary values ​​in the bit array indirectly proves the high probability of the existence of the address mapping. Although there is a small miscalculation rate, this mechanism ensures that the system can quickly locate the potential address mapping location with extremely low misjudgment cost, thereby optimizing the query path and reducing unnecessary page table access.

[0120] It should be noted that, under the condition that the technology is feasible and the logic is clear, the above embodiments can be combined in pairs or in multiple combinations.

[0121] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the translation backup buffer query acceleration method of the present application. More simple transformations based on this technical concept are all within the protection scope of the present application.

[0122] The present application provides a translation lookaside buffer query acceleration device, which includes: at least one processor; and a memory that is communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the translation lookaside buffer query acceleration method in the above-mentioned embodiment 1.

[0123] Reference below Figure 5 , which shows a schematic diagram of the structure of a translation lookaside buffer query acceleration device suitable for implementing the embodiments of the present application. The translation lookaside buffer query acceleration device in the embodiments of the present application may include but is not limited to mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 5 The translation lookaside buffer query acceleration device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0124] like Figure 5As shown, the translation lookaside buffer query acceleration device may include a processing device 1001 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. Various programs and data required for the operation of the translation lookaside buffer query acceleration device are also stored in the RAM 1004. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems may be connected to the I / O interface 1006: input devices 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 1003 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 1009. The communication device 1009 may allow the translation lookaside buffer query acceleration device to communicate wirelessly or by wire with other devices to exchange data. Although the figure shows a translation lookaside buffer query acceleration device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or have instead.

[0125] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0126] The translation lookaside buffer query acceleration device provided by the present application adopts the translation lookaside buffer query acceleration method in the above embodiment, which can solve the technical problem of low translation lookaside buffer query efficiency. Compared with the prior art, the beneficial effects of the translation lookaside buffer query acceleration device provided by the present application are the same as the beneficial effects of the translation lookaside buffer query acceleration method provided by the above embodiment, and other technical features in the translation lookaside buffer query acceleration device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0127] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0128] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0129] The present application provides a medium, which is a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the translation backup buffer query acceleration method in the above-mentioned embodiment.

[0130] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0131] The computer-readable storage medium may be included in the translation lookaside buffer query acceleration device; or may exist independently without being assembled into the translation lookaside buffer query acceleration device.

[0132] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the translation lookaside buffer query acceleration device, the translation lookaside buffer query acceleration device:

[0133] receiving an address translation request sent by an external device to a translation lookaside buffer filter and a multi-stage translation lookaside buffer;

[0134] querying a target address mapping corresponding to the address translation request in a multi-level translation lookaside buffer;

[0135] According to the address translation request, in the translation lookaside buffer filter, at least one hash summary value is generated using a hash function module, all hash summary values ​​are compared with the historical hash summary values ​​stored in the bit array module to obtain a comparison result, and according to the comparison result, it is determined whether the target address mapping exists in the multi-level translation lookaside buffer. If the target address mapping does not exist in the multi-level translation lookaside buffer, the query operation of the multi-level translation lookaside buffer for the target address mapping corresponding to the address translation request is interrupted, and the preset translation control unit obtains the target address mapping by accessing the memory, and sends the target address mapping to the external device.

[0136] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0137] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0138] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0139] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned translation lookaside buffer query acceleration method, and can solve the technical problem of low efficiency of translation lookaside buffer query. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the translation lookaside buffer query acceleration method provided by the above-mentioned embodiment, and will not be described in detail here.

[0140] The present application also provides a product, which is a computer program product, including a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned translation backup buffer query acceleration method are implemented.

[0141] The computer program product provided by the present application can solve the technical problem of low efficiency of translation lookaside buffer query. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as the beneficial effects of the translation lookaside buffer query acceleration method provided by the above embodiment, which will not be described in detail here.

[0142] The above are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A translation lookaside buffer query acceleration system, characterized in that: The translation lookaside buffer query acceleration system comprises a multi-level translation lookaside buffer and a translation lookaside buffer filter which are communicatively connected to each other, and the multi-level translation lookaside buffer and the translation lookaside buffer filter are placed in a translation buffer unit and connected to a translation control unit, and the translation lookaside buffer filter comprises a hash function module and a bit array module which are communicatively connected to each other; The multi-level translation backup buffer is used to receive an address translation request sent by an external device and query the target address mapping corresponding to the address translation request; The translation lookaside buffer filter is used to generate at least one hash summary value in a hash function module according to the address translation request sent by an external device, compare all the hash summary values ​​with the historical hash summary values ​​stored in the bit array module to obtain a comparison result, and determine whether the target address mapping exists in the multi-level translation lookaside buffer according to the comparison result. If the target address mapping does not exist in the multi-level translation lookaside buffer, the query operation of the multi-level translation lookaside buffer to query the target address mapping corresponding to the address translation request is interrupted, and the preset translation control unit obtains the target address mapping by accessing the memory, and sends the target address mapping to the external device.

2. The translation lookaside buffer query acceleration system according to claim 1, wherein: The multi-level translation lookaside buffer comprises a first-level translation lookaside buffer and a second-level translation lookaside buffer; The first-level translation lookaside buffer is used to receive an address translation request sent by an external device, query a target address mapping corresponding to the address translation request, and if the target address mapping does not exist, send the address translation request to the second-level translation lookaside buffer; The second-level translation lookaside buffer is used to receive the address translation request sent by the first-level translation lookaside buffer, query the target address mapping, and if the target address mapping does not exist, obtain the target address mapping by accessing memory through a preset translation control unit.

3. A translation lookaside buffer query acceleration method, characterized in that: A translation lookaside buffer query acceleration system according to any one of claims 1 to 2, wherein the translation lookaside buffer query acceleration system comprises a multi-level translation lookaside buffer and a translation lookaside buffer filter which are communicatively connected to each other, and the multi-level translation lookaside buffer and the translation lookaside buffer filter are placed in a translation buffer unit and connected to a translation control unit, the translation lookaside buffer filter comprises a hash function module and a bit array module which are communicatively connected to each other, and the translation lookaside buffer query acceleration method comprises: receiving an address translation request sent by an external device to the translation lookaside buffer filter and the multi-stage translation lookaside buffer; querying the target address mapping corresponding to the address translation request in the multi-level translation lookaside buffer; According to the address translation request, at least one hash summary value is generated in the translation lookaside buffer filter using the hash function module, all the hash summary values ​​are compared with the historical hash summary values ​​stored in the bit array module to obtain a comparison result, and according to the comparison result, it is determined whether the target address mapping exists in the multi-level translation lookaside buffer; if the target address mapping does not exist in the multi-level translation lookaside buffer, the query operation of the multi-level translation lookaside buffer to query the target address mapping corresponding to the address translation request is interrupted, and the preset translation control unit obtains the target address mapping by memory access, and sends the target address mapping to an external device.

4. The method for accelerating the query of the translation lookaside buffer according to claim 3, wherein: The multi-level translation lookaside buffer comprises a first-level translation lookaside buffer and a second-level translation lookaside buffer, and the step of querying the target address mapping corresponding to the address translation request in the multi-level translation lookaside buffer comprises: receiving an address translation request sent by an external device in the first-level translation lookaside buffer, and querying a target address mapping corresponding to the address translation request; If the target address mapping does not exist in the first-level translation lookaside buffer, querying the target address mapping in the second-level translation lookaside buffer; If the target address mapping does not exist in the second-level translation lookaside buffer, the preset translation control unit obtains the target address mapping by accessing the memory.

5. The method for accelerating the query of the translation lookaside buffer according to claim 3, wherein: The step of comparing all the hash summary values ​​with the historical hash summary values ​​stored in the bit array module comprises: Comparing the hash digest value with the historical hash digest value in the position where the identifier is stored in the bit array; If the hash digest value is the same as any of the historical hash digest values, it is determined that the hash digest value exists in the bit array.

6. The method for accelerating the query of the translation lookaside buffer according to claim 3, wherein: The step of comparing all the hash digest values ​​with the historical hash digest values ​​stored in the bit array module includes: If all of the hash digest values ​​match the historical hash digest values ​​stored in the bit array module, determining that the target address mapping exists in the multi-level translation lookaside buffer; If there is at least one hash digest value that does not match the historical hash digest value stored in the bit array module, it is determined that the target address mapping does not exist in the multi-level translation lookaside buffer.

7. The method for accelerating the query of the translation lookaside buffer according to claim 3, wherein: After the step of obtaining the target address mapping by memory access by the preset translation control unit, the following steps are included: updating the target address mapping into the multi-level translation lookaside buffer and storing all the hash digest values ​​into the bit array; A stored flag is marked on the storage locations of all the hash summary values ​​in the bit array.

8. A translation lookaside buffer query acceleration device, characterized in that: The translation lookaside buffer query acceleration device comprises: a translation lookaside buffer query acceleration system as described in any one of claims 1 to 2, a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the computer program is configured to implement the steps of the translation lookaside buffer query acceleration method as described in any one of claims 3 to 7.

9. A medium, characterized in that The medium is a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the translation lookaside buffer query acceleration method according to any one of claims 3 to 7 are implemented.

10. A product, characterized in that The product is a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the translation lookaside buffer query acceleration method according to any one of claims 3 to 7 are implemented.

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