Analysis method of digital logic circuit, computer device and storage medium

Abstract

The present application provides a method, computer device, and storage medium for analyzing digital logic circuits. The method includes: obtaining a digital logic circuit to be analyzed; performing circuit grading using triggers of the digital logic circuit as nodes, and selecting a digital logic circuit between any two adjacent levels as a target circuit; wherein the target circuit includes at least one path, and the at least one path includes at least one combinational logic unit; determining a variable sequence of the target circuit, and based on the variable sequence, determining a first result of the at least one combinational logic unit according to a Boolean function; wherein the first result corresponds to the Boolean difference of the output of the at least one combinational logic unit with respect to the input; determining a target path in the at least one path, performing an ITE operation based on the first result corresponding to the target path; and determining an identification result of the target path based on the operation result.

Description

Technical Field

[0001] The present application relates to the technical field of digital logic circuits, and in particular to a digital logic circuit analysis method, a computer device, and a storage medium. Background Art

[0002] As modern digital logic circuits become larger and more complex, how to efficiently analyze and optimize circuits has become an indispensable and important part of modern EDA (Electronic Design Automation) tools.

[0003] During digital logic circuit design, false paths can account for 80% or even more of all paths. Identifying false paths reduces the workload of tools for correcting these violations. However, in digital circuits, where logic gates can reach millions or even tens of millions, identifying false paths within acceptable resource constraints is a challenge. Summary of the Invention

[0004] In view of this, the present application proposes a digital logic circuit analysis method, a computer device, and a storage medium to solve or partially solve the above problems.

[0005] Based on the above objectives, in a first aspect, the present application provides a method for analyzing a digital logic circuit, comprising:

[0006] Obtaining a digital logic circuit to be analyzed;

[0007] Performing circuit grading using the triggers of the digital logic circuit as nodes, and selecting a digital logic circuit between any two adjacent levels as a target circuit; wherein the target circuit includes at least one path, and the at least one path includes at least one combinational logic unit;

[0008] Determining a variable order of the target circuit, and determining a first result of the at least one combinational logic unit based on the variable order according to a Boolean function; wherein the first result corresponds to a Boolean difference between an output and an input of the at least one combinational logic unit;

[0009] determining a target path among the at least one path, and performing an ITE operation according to a first result corresponding to the target path;

[0010] The identification result of the target path is determined according to the operation result.

[0011] In a second aspect of the present application, a computer device is provided, comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to the first aspect.

[0012] In a third aspect of the present application, a non-volatile computer-readable storage medium containing a computer program is provided. When the computer program is executed by one or more processors, the processors execute the method described in the first aspect.

[0013] As can be seen from the above, the present application provides a method, computer device, and storage medium for analyzing digital logic circuits. The present application determines the variable order of a target circuit, then uses a Boolean function to represent the ROBDD, thereby determining the first result of the combinational logic unit in the target circuit. Finally, an ITE operation is performed based on the first result. If the operation result is always 0, it indicates that the target circuit belongs to a false path. In this way, when analyzing the target circuit, the number of nodes can be reduced by reducing the ordered binary decision graph. Furthermore, the above method can reduce space complexity and computation time to a certain extent, improve analysis efficiency, and accelerate the false path identification process. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1 A schematic diagram of the hardware structure of an exemplary computer device provided by an embodiment of the present disclosure is shown.

[0016] Figure 2 A basic structural diagram of an EDA tool according to an embodiment of the present disclosure is shown.

[0017] Figure 3 A schematic diagram showing a basic execution flow of a calculation command of an EDA tool according to an embodiment of the present disclosure is shown.

[0018] Figure 4 A flow chart of an exemplary method provided according to an embodiment of the present application is shown.

[0019] Figure 5 A schematic structural diagram of an exemplary target circuit provided according to an embodiment of the present application is shown.

[0020] Figure 6A A schematic diagram of an exemplary BDD provided according to an embodiment of the present application is shown.

[0021] Figure 6B A schematic diagram of an exemplary ROBDD provided according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of this specification more clear, this specification is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0023] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the usual meanings understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in the embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements, objects or method steps that appear before the word cover the elements, objects or method steps listed after the word and their equivalents, without excluding other elements, objects or method steps. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0024] Figure 1 The following is a schematic diagram of the structure of a computer device 100 provided in an embodiment of the present application. The computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. The processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are connected to each other within the device via the bus 110.

[0025] The processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, the processor 102 may also include multiple processors integrated into a single logical component. Figure 1As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0026] The memory 104 may be configured to store data (eg, instruction sets, computer code, intermediate data, etc.). Figure 1 As shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solutions of the present application) and data to be processed. The processor 102 may also access the stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include random access memory (RAM), read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0027] The network interface 106 can be configured to provide the computer device 100 with communication with other external devices via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near-field communication (NFC)), a cellular network, the Internet, or a combination thereof. It will be appreciated that the type of network is not limited to the specific examples above. In some embodiments, the network interface 106 can include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.

[0028] The peripheral interface 108 can be configured to connect the computer device 100 to one or more peripheral devices to enable information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touchpad, a touch screen, a microphone, and various sensors, as well as output devices such as a display, a speaker, a vibrator, and an indicator light.

[0029] The bus 110 may be configured to transmit information between various components of the computer device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0030] It should be noted that although the above device only shows the processor 102, memory 104, network interface 106, peripheral interface 108 and bus 110, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it is understood by those skilled in the art that the above device may also only include the components necessary to implement the embodiment of the present application, and does not necessarily include Figure 1 All components shown in .

[0031] Figure 2 FIG. 2 shows a basic structural diagram of an EDA tool 200 according to an embodiment of the present application.

[0032] like Figure 2 As shown, the part above the dotted line is the user part; the part below the dotted line is the EDA tool 200, which can be Figure 1 The device 100 shown is implemented. In some embodiments, the EDA tool 200 can be implemented as EDA software. More specifically, the EDA tool 200 can be software that performs placement and routing based on chip design. The simulation tool 200 can include a Tcl command (or graphical / window interface) module 204, various calculation modules (e.g., a Placement calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc.), and a database system 212. A user 202 can operate the EDA tool 200 by entering relevant commands in the Tcl command (or graphical / window interface) module 204.

[0033] The Tcl command module 204 mainly performs the function of message transmission or command transmission. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can distribute and transmit the instructions to the corresponding computing modules to perform specific tasks according to the specific content of the instructions.

[0034] Depending on the calculation task, each calculation module can be divided into, for example, a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc. The Place calculation module 206 can be used to calculate a reasonable placement position for all components, the Route calculation module 208 can be used to calculate a reasonable wire connection method between each component, and the Optimization calculation module 210 can be used to optimize the placement position and wire connection method between each component. The calculation process of these calculation modules can be, for example, Figure 1 is performed in the processor 102.

[0035] The database system 212 can be used to completely and comprehensively record and store all information of the chip being simulated or designed (such as location, direction, size, structure, wire connection method, etc.). This information can be stored in, for example, Figure 1 in the memory 104.

[0036] Figure 3 FIG. 3 shows a basic execution flow 300 of a calculation command of the EDA tool 200 according to an embodiment of the present application. Figure 3As shown, in step 302, user 202 can issue a command (e.g., the do_place command) to the EDA tool 200 via the command interface or graphical user interface (GUI) provided by the Tcl command module 204. Then, in step 304, the Tcl command module 204 parses the command and dispatches it to the corresponding computation module (e.g., the Place computation module 206). In step 306, each computation module performs its required calculations. During this process, as shown in step 308, each computation module needs to frequently and repeatedly access data from the database system 212 to perform its calculations. After the calculations are complete, as shown in step 310, each computation module can write the results to the database system 212 and return the results to the Tcl command module 204. In step 312, the Tcl command module 204 returns the results to user 202 via the command interface or graphical user interface (GUI), concluding the processing of the computation command by the EDA tool 200. In step 314, the user can evaluate the results and determine the next steps.

[0037] As mentioned in the background section, a key task of current EDA tools is to analyze and optimize digital logic circuits. Initially designed digital logic circuits often contain numerous false paths, which EDA tools must first identify and mark before performing other operations such as pruning.

[0038] To facilitate understanding, some concepts involved in the embodiments of the present application are explained below.

[0039] First, the digital logic circuit in this application refers to a circuit composed of sequential logic units and combinational logic units, which can be collectively referred to as "combos." The basic unit that constitutes a sequential logic unit is a flip-flop (FF). A combinational logic unit (gate) is a circuit composed of logic gates (such as AND gates, OR gates, and NOT gates). Its output is a function of the input signal and does not involve memory or storage.

[0040] Next, a path is defined as a sequence of nodes where any two consecutive nodes in the sequence have a directed edge between them, making the two nodes the tail and head nodes of the edge, respectively. Specifically, 1) the first node in the sequence is the starting node of the path; 2) the last node in the sequence is the ending node of the path. In the context of this application, a path is a sequence from a starting node to an ending node, passing only through combos. Specifically, the starting node can be the output pin (Q pin or input data port) of a launch FF in the data path, which is directly connected to the input pin of a combo; the ending node can be the input pin (D pin or output port) of a capture FF in the data path, which is directly connected to the output pin of a combo. This shows that between the starting node and the ending node of a path, only the combinatorial logic units (gates) in the combo exist.

[0041] After defining the concept of a path, false paths can generally be categorized into three types: 1) a timing-insensitive false path, where timing is irrelevant due to asynchronous clocks. 2) a logically unsensitizable false path, where sensitization is not logically possible. 3) a delay-dependent false path, where sensitization is logically possible but the path's signal is controlled by a signal from a pin outside the path.

[0042] In a typical digital logic circuit, false paths can account for 80% or more of all paths. Identifying false paths reduces the workload of tools for fixing these illegal paths. However, in digital logic circuits, where the number of logic gates reaches millions or even tens of millions, identifying false paths within acceptable resource limits is a challenge.

[0043] In view of this, the present application proposes a method for analyzing digital logic circuits. This method determines the variable order of the target circuit, and then uses a Boolean function to represent the ROBDD to determine the first result of the combinational logic unit in the target circuit. Finally, an ITE operation is performed based on the first result. If the operation result is always 0, it means that the target circuit belongs to a false path. In this way, when analyzing the target circuit, the number of nodes can be reduced by reducing the ordered binary decision graph. The above method can also reduce space complexity and computation time to a certain extent, improve analysis efficiency, and accelerate the false path identification process.

[0044] In a specific application scenario, the solution proposed in this application has a more prominent recognition effect on the second type of false path among the aforementioned false paths.

[0045] Figure 4 The flow chart of the exemplary method 400 provided in the embodiment of the present application is shown. The method 400 may be Figure 1 The computer device 100 is implemented and can be implemented as Figure 2 A portion of the functionality of the EDA tool 200. Figure 4 As shown, the method 400 may further include the following steps.

[0046] Step 402: Obtain a digital logic circuit to be analyzed.

[0047] In this step, the digital logic circuit to be analyzed and optimized can be generated based on the chip design. For example, it can be converted into a netlist file through logic synthesis, and then the digital logic circuit to be analyzed and optimized can be obtained after layout and routing. In combination with the above, the digital logic circuit to be analyzed in this application can be an initial digital logic circuit.

[0048] It can be understood that, in combination with the foregoing, the analysis and optimization in the embodiment of the present application can be analysis or optimization, or analysis and optimization. The specific operations can be set according to user needs and are not limited here.

[0049] Step 404 : performing circuit grading using the triggers of the digital logic circuit as nodes, and selecting a digital logic circuit between any two adjacent levels as a target circuit; wherein the target circuit includes at least one path, and the at least one path includes at least one combinational logic unit.

[0050] In this step, as mentioned above, the digital logic circuit of the present application is composed of a sequential logic unit and a combinational logic unit, wherein the basic unit of the digital logic circuit is a flip-flop (FF). Thus, a digital logic circuit can be hierarchical with each flip-flop (FF) as a node.

[0051] Specifically, for a digital logic circuit to be analyzed, the circuit's FFs are first classified into different levels. The total input data ports can be set to level 0. Then, the input data ports pass through the combo (as previously mentioned, the combo only exists in the combinational logic unit gate) to the input pin (D pin) of the next flip-flop (FF). This flip-flop (FF) is considered the first level. The output pin or clock pin (CK pin) of the first-level flip-flop (FF) passes through the combo to the input pin (D pin) of the next flip-flop (FF). This flip-flop (FF) is considered the second level. This process continues in this order until the output pin or clock pin (CK pin) of the n-th level flip-flop (FF) reaches the total output ports.

[0052] After that, after the grading is completed, the circuit between any two adjacent levels can be selected as the target circuit. For example, the clock pin (CK pin) of the i-th level trigger (FF) is combined to the input pin (Dpin) of the i+1-th level trigger (FF), and this is used as the target circuit. Among them, the i-th level trigger (FF) is the launch FF, and the i+1-th level trigger (FF) is the capture FF. Through the aforementioned grading method, it can be seen that for two adjacent levels, there may be multiple launch FFs and multiple capture FFs. Specifically, as Figure 5 As shown, this is a schematic diagram of the specific structure of a target circuit, where 、 and It can be considered that they represent three different launch FFs of level i, and It represents the capture FF of the i+1th level. It can be seen that in this target circuit, 、 or arrive There can be many paths, and the units identified from a to g are all combinational logic units.

[0053] Step 406: Determine the variable order of the target circuit, and determine a first result of the at least one combinational logic unit based on the variable order according to a Boolean function; wherein the first result corresponds to the Boolean difference of the output of the at least one combinational logic unit with respect to the input.

[0054] In this step, variable ordering generally refers to the process of arranging a set of variables into a certain order. This process can be applied in a variety of scenarios. For example, in topological sorting, vertices (variables) in a directed acyclic graph (DAG) are arranged in a topological order, ensuring that for any directed edge u→v, vertex u appears before vertex v in the sorted result.

[0055] What needs to be explained here is that as a form of expression of a directed acyclic graph (DAG), a binary decision diagram (BDD) is essentially a rooted directed acyclic graph with one or two terminal nodes with an out-degree of 0, labeled 0 or 1, and including a set of variable nodes u with an out-degree of 2. The two outgoing edges of the variable node are defined by low(u) and high(u). Furthermore, if the variables follow a given linear order on all paths in the directed acyclic graph (DAG), the BDD is ordered (Ordered Binary Decision Diagram, OBDD). And further, it is a reduced ordered binary decision diagram (Reduced Ordered Binary Decision Diagram, ROBDD), which is obtained by reducing the BDD. If a BDD is reduced, no two different variable nodes u and v have the same variable names low and high child nodes, and no variable node u has the same low- and high-child nodes. As Figure 6A and 6B As shown, Figure 6A As shown, this is a binary decision diagram (BDD) expression for a target circuit; Figure 6B As shown in the figure, it is the reduced ordered binary decision diagram (ROBDD) expression of the same target circuit, where low(u) and high(u) are in Figure 6A and Figure 6B In the figure, the dotted and solid lines are shown, and the node is associated with the variable var(u); the circular nodes marked with the variable name are internal nodes, that is, non-leaf nodes. Figure 6A and 6B The three internal nodes a, b, and c are shown as examples; the square nodes at the bottom are leaf nodes. Figure 6A and 6B Marked as 1 or 0.

[0056] In some embodiments, digital logic circuits can be abstracted into Boolean logic networks, and Boolean functions can be used to convert between them. Furthermore, since the output of a combinatorial logic cell (gate) can be represented as a Boolean function expression of its input, as previously mentioned, by combining variable order with Boolean functions, a unique ROBDD representation can be generated for any combinatorial logic cell in the target circuit using a given variable order. Using the Boolean expression determined by the Boolean function, the Boolean difference between the input and output of a combinatorial logic cell can be determined.

[0057] Specifically, a combinational logic unit The input pin is denoted as , The value is 1, 2, 3...j. j is the combinational logic unit The number of input pins, such as Figure 5 As shown, the combinational logic units a, b, etc. have 2 input pins, and the combinational logic unit f has 1 input pin. Represents a combinational logic unit The only output pin. The Boolean expression can be written as: .and then right The Boolean difference of can be written as:

[0058]

[0059] in, represents the negation factor of the Shannon expansion, represents the positive factor of the Shannon expansion.

[0060] In some embodiments, the first result corresponds to the Boolean difference between the output and input of a combinatorial logic unit, and thus can be directly the calculated result of this Boolean difference. That is, the first result is the Boolean difference result of the ROBDD of the at least one combinatorial logic unit determined according to the Boolean function. In other scenarios, for larger circuits, the calculation of the Boolean function or Boolean difference is very large, and directly performing the calculation would occupy a large amount of computing space. Therefore, the first result here can correspond only to the logical expression of the Boolean difference, that is, only the calculation method is recorded without performing specific calculations. This allows the first result to be obtained quickly, saving computing resources at this time. That is, the logical expression corresponding to the Boolean difference of the ROBDD of the at least one combinatorial logic unit determined according to the Boolean function.

[0061] In some more specific scenarios, since the process of finding Boolean differences is independent of each other, multi-threading can be used for processing. Assuming there are n nodes, n-1 threads can be established to obtain n-1 Boolean difference logical expressions in parallel with multi-threading (one Boolean difference calculation is required for each two adjacent nodes, so n-1 Boolean differences need to be calculated for n nodes), and they are saved in the form of suffix expressions in a map. The key of the map can be<celltype,inputpin> , value is the suffix expression form of the logical expression for the Boolean difference between the output pin of the cell type (and, or, not, or not, etc.) and the input pin.

[0062] In some embodiments, the variable order can be determined by determining the level of each starting point in the target circuit. In combination with the above, there may be multiple starting points in a target circuit, and there may also be multiple end points, such as Figure 5 As shown, 、 and It can be considered that they represent three different launch FFs of level i, i.e., three starting points, and This represents the capture FF at level i+1, i.e., one endpoint. Starting from the endpoint, the search proceeds forward along different paths, incrementing by 1 for each combinatorial logic unit level passed. Due to different paths, each starting point may correspond to multiple levels. A depth-first search (DFS) approach can be used for the search. This can be understood as selecting the highest level for each starting point. Of course, according to the principle of depth-first search, the level of the combinatorial logic unit within it is also set to the highest level. The level of each starting point is thus determined, and the starting points can then be sorted based on the level, for example, in descending or ascending order, or other specifically defined sorting methods. Specifically, in some embodiments, determining the variable order of the target circuit includes: determining at least one starting point and at least one endpoint of the target circuit; starting with the at least one endpoint, determining the level of the at least one starting point through a depth-first search; wherein the level of any starting point corresponds to the number of combinatorial logic units traversed from the starting point to the endpoint; and sorting the at least one starting point based on its level to determine the variable order.

[0063] Furthermore, the representation of BDD is highly correlated with the order of variables. A bad order of variables may result in the number of nodes in the BDD being This is unacceptable. Furthermore, in order to reduce the number of nodes and reduce time and space complexity, the starting points may be sorted in descending order according to their rank. That is, in some embodiments, sorting the at least one starting point according to its rank includes sorting the at least one starting point in descending order according to its rank.

[0064] In a more specific embodiment, assume that there are m launch FFs in the target circuit, and their Q pins are startpoints. There are m independent variables. Assume that there are q capture FFs in the target circuit, and the drivers corresponding to their D pins are q endpoints. Since the representation of BDD is highly dependent on the order of variables, a bad order of variables may result in a BDD with a number of nodes of , which is unacceptable. Therefore, for a target circuit, the variable order can be determined as follows: select a path in the target circuit, denoted as path1, According to the above definition, Is an endpoint, composed of A forward depth-first search (DFS) is initiated to determine the level of each node, or combinatorial logic unit. If the endpoint's level is 0, the level of the i-th node is the maximum of the determined levels. Finally, the starting point levels are sorted in descending order. The resulting order of the starting points becomes the uniform variable order used when representing the ROBDD associated with the target circuit. This variable order effectively reduces the number of nodes in the BDD.

[0065] Step 408: Determine a target path among the at least one path, and perform an ITE operation according to the first result corresponding to the target path.

[0066] In this step, after determining the first result, a target path can be selected from the multiple paths of the target circuit. The target path generally does not include all combinational logic units in the target circuit. It is necessary to first determine the corresponding combinational logic unit and its first result. After that, the ITE operation can be used to perform an operation calculation based on the first result. Based on the calculation result, it can be determined whether the target path is a false path. The ITE operation here is a ternary Boolean operator that implements if f, then g, else h. f, g, and h are three Boolean functions with the same variable order. That is, .

[0067] It should be noted that, assuming a path is represented by ,in Represents a node in the path, such as the previous combinational logic unit The only output pin. Combinational Logic Unit The only output pin of go through ,arrive . is a starting point, is an endpoint. Furthermore, the condition for determining whether a path is a false path, particularly the aforementioned second type of false path, can be: if the value of the following formula is always 0, then the path is a second type of false path.

[0068]

[0069] in, According to the above, it can be known that it is a combinational logic unit The Boolean difference of the output pin of the path with respect to the input pin on the path. Therefore, determining whether a path is a second-type false path depends on whether the Boolean expression in the preceding step is always 0. This can be converted into determining whether the ROBDD contains only leaf nodes with a value of 0.

[0070] In some embodiments, since the first result can only store a logical expression, for a target path, the target combinational logic unit corresponding to the target path can be first determined. The logical expressions corresponding to these target combinational logic units can then be used as necessary logical expressions. A Boolean difference calculation of the ROBDD is then performed based on the specific logical expression, and then combined with an ITE operation to ultimately obtain a calculation result. That is, in some embodiments, performing an ITE operation based on the first result corresponding to the target path includes: in response to the first result being the logical expression, determining the target combinational logic unit corresponding to the target path, determining the necessary logical expression based on the target combinational logic unit, performing a Boolean difference calculation of the ROBDD based on the necessary logical expression, and performing the ITE operation based on the calculation result.

[0071] Furthermore, during the process of determining the logical expressions, these logical expressions can be simplified as much as possible, and the first result stored in this manner. This simplification process may ultimately leave only a constant or a node pointing to a path. A node-pointing logical expression may instead point to the start of the target path or another combinational logic unit. Because a constant or a ROBDD pointing to the start of the target path is relatively simple or can directly determine the corresponding result, it can be removed when determining the necessary logical expressions, leaving the remaining one as the necessary logical expression. Specifically, for a combo with n inputs and 1 output, the output of a logical expression for the Boolean difference of a particular input may not be related to all other input pins. For example, for a combo with 4 inputs and 1 output, the output of a logical expression for the Boolean difference of input 1 will definitely not include input 1 and may include three other inputs, or only two, or even one. Therefore, after determining the logical expression for each combo, it is now known which combo pins are required and which are irrelevant. For irrelevant combo pins, there is no need to generate ROBDDs, further saving time. Specifically, in some embodiments, when the first result is the logical expression, the logical expression is simplified to store the first result. Determining the necessary logical expression based on the target combinatorial logic unit includes determining all simplified logical expressions corresponding to the target combinatorial logic unit, removing any simplified logical expressions that are constants or point to the starting point of the target path, and using the remaining simplified logical expressions as the necessary logical expressions.

[0072] Finally, for the target path containing n nodes, perform an AND operation (using the IRE operator) on the ROBDDs represented by the n-1 Boolean differences to obtain the final ROBDD. If its only leaf node is node 0, it indicates the second type of false path.

[0073] Furthermore, according to the above method, it can be seen that due to It is a multiplication process. If there is a value of 0 in the calculation process, then It must be 0. Then, during the evaluation process, if the ROBDD of the product of several Boolean differences is always 0, pruning can be performed, and the final result is always 0. This evaluation process may occur in the formula simplification process, or it may occur in the specific calculation process. That is, in some embodiments, the Boolean difference calculation of ROBDD based on the necessary logical expressions includes: in response to the result of the simplified logical expression corresponding to any target combinational logic unit being 0, stopping the calculation of other logical expressions; or performing the Boolean difference calculation of ROBDD on the necessary logical expressions in sequence according to the variable order, and in response to the calculation result of any necessary logical expression being 0, stopping the calculation of other necessary logical expressions.

[0074] Furthermore, since the calculation of each ROBDD may be relatively large, multithreading can be used for parallel processing to speed up processing time and improve efficiency. For example, for the product of n-1 ROBDDs, it can be divided into [n-1 / 2] threads. The calculation is put into 1 thread, The calculation of is placed in the second thread, and so on. Although the total number of operations is still at the O(n) level, multithreading can be used to accelerate the operation. That is, in some embodiments, performing Boolean difference calculation of ROBDD based on the necessary logical expressions includes: determining the number of necessary logical expressions and allocating at least one processing thread based on the number.

[0075] In some embodiments, during the calculation of ROBDD, ROBDD can be understood as a graph, such as Figure 6B As shown, there are two types of nodes, leaf nodes and non-leaf nodes. Since leaf nodes have only two values, 0 and 1 are used as examples. Afterwards, for each node, it generally corresponds to two ROBDDs, that is, two logical expressions. and (No ) is expressed. Figure 6B In the scenario shown, and The non-leaf nodes of the ROBDD are exactly the same, but The edges pointing to leaf node 0, Will point to leaf node 1. The edges pointing to leaf node 1, Will point to 0. Generally, in other scenarios, and However, in combination with the specific scenario of this application, since the leaf node has only two values, such as 0 and 1, if but In this way, the calculation process of ROBDD can be further simplified. For two ROBDDs with exactly the same non-leaf nodes: and , record the value of only one of them, and then and All point to this value, and for the value of another ROBDD, directly perform a non-operation on the recorded value, that is, after determining which value is recorded, directly output another value. In a more specific scenario, for the convenience of explanation, the variable sequence obtained by a ROBDD is used The non-start point combo pins on this path can be expressed as For the logical expression of the variable, each logical expression can be represented by a ROBDD. ROBDD is unique when the variable order is fixed. To save time and space, for each pin, when creating ROBDD, add a bool variable is_not. If it is known that The ROBDD is expressed as , then , bool is_not is false; , bool is_not is true. and The difference is that if you want , just follow When the ROBDD reaches the leaf node, if it is 0, it is 1, and if it is 1, it is 0. Therefore, it does not occupy memory and stores and Instead, the two ROBDDs are obtained by reusing the bool is_not variable and taking the value according to the above rules. That is, in some embodiments, performing the ITE operation according to the first result corresponding to the target path includes: creating a ROBDD for the combinational logic unit that needs to be calculated on the target path; wherein the ROBDD of each combinational logic unit corresponds to only two results; determining at least one pair of target ROBDDs with completely identical non-leaf nodes in the created ROBDD; performing result calculation on one of the at least one pair of target ROBDDs to obtain a first result; and directing the result of the other of the at least one pair of target ROBDDs to the first result through a negation operation.

[0076] Step 410: Determine the recognition result of the target path according to the operation result.

[0077] In this step, after obtaining the final result from the aforementioned ITE operation, if the result is always 0, it indicates that the target path is a false path, specifically the second type of false path mentioned above, and thus confirms the facial path recognition result. In subsequent steps, appropriate operations can be performed based on the recognition results, using operations such as removal to analyze and optimize the digital logic circuit.

[0078] In a more specific scenario, Figure 5 The target circuit shown illustrates the process of analyzing false paths using ROBDD.

[0079] like Figure 5 As shown, considering the path ,by Start and move forward 、 、 The level of is 4, then the variable order is For the convenience of explanation, note: and: ;or: ;No: ; AND NOT: .but:

[0080]

[0081] Therefore, it can be seen that only and Perform ROBDD representation. Expressed as The pointer of ROBDD and boolis_not = true.

[0082]

[0083] The combo pins on all paths are shown below for clarity. First, the following conventions are made:

[0084]

[0085]

[0086]

[0087]

[0088] but 、 and The ROBDD representations are:

[0089]

[0090]

[0091]

[0092] Then ROBDD is expressed as:

[0093]

[0094] Finally, the ROBDD contains only leaf nodes of 0, so the path is a false path.

[0095] As can be seen from the above, the embodiment of the present application provides a method for analyzing digital logic circuits. The present application determines the variable order of the target circuit, and then uses a Boolean function to represent the ROBDD to determine the first result of the combinational logic unit in the target circuit. Finally, the ITE operation is performed based on the first result. If the operation result is always 0, it means that the target circuit belongs to a false path. In this way, when analyzing the target circuit, the number of nodes can be reduced by reducing the ordered binary decision diagram. The above method can also reduce the space complexity and calculation time to a certain extent, improve the analysis efficiency, and accelerate the false path identification process.

[0096] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of the embodiment of the present application can also be applied in a distributed scenario and completed by multiple devices working together. In the case of such a distributed scenario, one of the multiple devices may only perform one or more steps of the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the method described.

[0097] It should be noted that the above description is of specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the above embodiments and still achieve the desired results. In addition, the processes depicted throughout the figures do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0098] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides a non-volatile computer-readable storage medium containing a computer program, wherein the non-volatile computer-readable storage medium containing a computer program stores computer instructions, and the computer instructions are used to enable the computer to execute method 400 described in any of the above embodiments.

[0099] The computer-readable storage media of this embodiment includes permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0100] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the method 400 described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0101] Based on the same inventive concept, corresponding to method 400 in any of the above embodiments, this application also provides a computer program product comprising a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to perform method 400. For the execution entities corresponding to the steps in each embodiment of method 400, the processors executing the corresponding steps may belong to the corresponding execution entities.

[0102] The computer program product of the above embodiment is used to enable a processor to execute the method 400 described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0103] Finally, to simplify the description and discussion, and to avoid obscuring the embodiments of the present application, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in all of the provided figures. Furthermore, devices may be shown in block diagram form to avoid obscuring the embodiments of the present application, and this also takes into account the fact that the implementation details of these block diagram devices are highly dependent on the platform on which the embodiments of the present application will be implemented (i.e., these details should be fully understood by those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application can be implemented without or with variations in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0104] Although the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the discussed embodiments.

[0105] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. A method for analyzing a digital logic circuit, characterized in that: include: Obtaining a digital logic circuit to be analyzed; Performing circuit grading using the triggers of the digital logic circuit as nodes, and selecting a digital logic circuit between any two adjacent levels as a target circuit; wherein the target circuit includes at least one path, and the at least one path includes at least one combinational logic unit; Determining a variable sequence of the target circuit, and determining a first result of the at least one combinatorial logic unit based on the variable sequence according to a Boolean function; wherein the first result corresponds to a Boolean difference between an output and an input of the at least one combinatorial logic unit, and the variable sequence is formed by arranging the target circuit in a set order; determining a target path among the at least one path, and performing an ITE operation according to a first result corresponding to the target path; The identification result of the target path is determined according to the operation result.

2. The method according to claim 1, characterized in that Determining the variable sequence of the target circuit includes: determining at least one starting point and at least one end point of the target circuit; Starting from the at least one end point, determining the level of the at least one starting point by depth-first search; wherein the level of any starting point corresponds to the number of combinational logic units passed through from any starting point to any end point; The variable order is determined by sorting the at least one starting point according to the rank of the at least one starting point.

3. The method according to claim 2, characterized in that The sorting of the at least one starting point according to the level of the at least one starting point comprises: The at least one starting point is arranged in descending order according to the corresponding level.

4. The method according to claim 1, wherein The first result is a Boolean difference result of the ROBDD of the at least one combinational logic unit determined according to the Boolean function, or a logical expression corresponding to the Boolean difference of the ROBDD of the at least one combinational logic unit determined according to the Boolean function.

5. The method according to claim 4, characterized in that The performing the ITE operation according to the first result corresponding to the target path includes: In response to the first result being the logical expression, the target combinational logic unit corresponding to the target path is determined, the first logical expression is determined according to the target combinational logic unit, a Boolean difference calculation of the ROBDD is performed according to the first logical expression, and the ITE operation is performed according to the calculation result.

6. The method according to claim 5, characterized in that When the first result is the logical expression, simplifying the logical expression to store the first result; The determining a first logical expression according to the target combinational logic unit includes: All simplified logical expressions corresponding to the target combinational logic unit are determined, logical expressions whose simplified results are constants or point to the starting end of the target path are removed, and the remaining ones are used as the first logical expression.

7. The method according to claim 6, characterized in that The performing Boolean difference calculation of the ROBDD according to the first logical expression includes: In response to the result of simplifying the logic expression corresponding to any target combinational logic unit being 0, the calculation of other logic expressions is stopped; Alternatively, the Boolean difference calculation of ROBDD is performed on the first logical expressions in sequence according to the variable sequence, and in response to the calculation result of any first logical expression being 0, the calculation of other first logical expressions is stopped.

8. The method according to claim 5, characterized in that The performing Boolean difference calculation of the ROBDD according to the first logical expression includes: The number of the first logical expressions is determined, and at least one processing thread is allocated according to the number.

9. The method according to claim 1, characterized in that The performing the ITE operation according to the first result corresponding to the target path includes: Creating a ROBDD for the combinational logic unit that needs to perform calculation on the target path; wherein the ROBDD of each combinational logic unit corresponds to only two results; Determine at least one pair of target ROBDDs with identical non-leaf nodes in the created ROBDD; performing result calculation on one of the at least one pair of target ROBDDs to obtain a first result; The result of the other one of the at least one pair of target ROBDDs is directed to the first result through a negation operation.

10. A computer device, characterized in that: The method comprises one or more processors, a memory, and one or more programs; wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to any one of claims 1 to 9.

11. A non-volatile computer-readable storage medium containing a computer program, characterized in that When the computer program is executed by one or more processors, the processors are caused to perform the method according to any one of claims 1 to 9.

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