Parametrically configurable digital ldo auto-generation method and apparatus

Abstract

The application discloses a parameterizable configuration digital LDO automatic generation method and device, aiming at the problems of long cycle and high cost of repeated simulation verification and modification of a schematic layout in an existing digital LDO design method, based on a given digital LDO architecture, performing configuration design on changeable design parameters in the digital LDO circuit, corresponding the configurable performance parameters and the circuit design parameters, and only needing to input specified performance parameters to generate corresponding digital LDO net list files and layout files. The design time of the circuit is greatly reduced, and agile design is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital LDO design, and particularly relates to a parameterizable configuration digital LDO automatic generation method and device. BACKGROUND

[0002] Digital LDO (DLDO) is concerned due to its low-voltage working capability and good process scalability; compared with traditional analog LDO (ALDO), the digital LDO needs smaller power tube area under the same load current, and has fewer stability problems; although there are disadvantages such as steady-state ripple and lower power supply rejection ratio, it is still widely used in high-efficiency power management systems of digital circuits to realize fine-grained power supply of digital circuits.

[0003] The traditional digital LDO is composed of a clock-controlled voltage comparator, a bidirectional shift register and a PMOS switch array. The output voltage VOUT and the reference voltage VREF complete comparison through the clock-controlled comparator, and the comparison result is output to the bidirectional shift register to control the shift direction of the bidirectional shift register to output digital 0 or 1; so as to turn on or turn off one PMOS in the PMOS array each time to adjust the output voltage. The PMOS array is composed of PMOS tubes with consistent size, which is in the linear region when turned on and in the off state when turned off.

[0004] At present, most LDO designs adopt a customized design method, according to the user's requirements to design the circuit schematic and layout, and when the design requirements change, the design and simulation verification need to be re-performed.

[0005] For digital LDO circuits with similar design requirements, the traditional customized design method needs repeated simulation verification and modification of the schematic and layout, which is long in cycle and high in cost. For example, the current circuit design usually adopts a customized design method: determine the circuit specification requirements -> architecture design, select a suitable circuit architecture -> schematic design -> simulation -> modify the schematic according to the simulation results -> layout design -> DRC / LVS -> parasitic extraction PEX -> post-layout simulation -> modify the schematic and layout according to the post-simulation results -> export gds file. SUMMARY

[0006] The purpose of the application is to provide a parameterizable configuration digital LDO automatic generation device, which realizes parameter configurable digital LDO under the same architecture, and can automatically generate the same architecture digital LDO circuit and layout according to the input design parameters, greatly reducing the design time of the circuit and realizing agile design.

[0007] To solve the above problems, the technical scheme of the application is:

[0008] A parameterizable digital LDO automatic generation device, comprising:

[0009] A digital LDO architecture is provided, wherein the digital LDO architecture includes a control logic structure and an analog topology structure;

[0010] A template module is used to template the digital LDO architecture to obtain templates including control logic code templates, digital LDO netlist file templates, digital synthesis script templates, and digital back-end automatic layout and routing script templates;

[0011] The digital control logic automatic generation module is used to configure the control logic parameters based on the control logic structure of a given digital LDO architecture, and pass the parameters to the control logic code template, digital synthesis script template, and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic;

[0012] The digital LDO automatic generation module is used to configure the analog parameters in the digital LDO architecture based on the analog topology of the given digital LDO architecture to obtain the corresponding analog units; combine the analog units with the netlist file of the digital control logic to generate the netlist file of the digital LDO; and combine the layout file of the analog units with the layout file of the digital control logic according to the splicing rules to obtain the layout file of the digital LDO;

[0013] The control logic structure of the digital LDO architecture includes a counter, a sequence detector, and a shift control logic. The input of the counter is connected to the clock signal, and the output is connected to the shift control logic. The input of the sequence detector is connected to the clock signal, and the output is connected to the shift control logic to control the digital LDO to enter the coarse loop logic or the fine loop logic.

[0014] The template module uses Verilog code to design the counter, sequence detector and shift control logic to generate a control logic Verilog template.

[0015] According to one embodiment of the present invention, the digital control logic automatic generation module performs parameter configuration on the control signal bit width of the shift control logic, the counting threshold of the counter, and the sequence detectable by the sequence detector, and passes the configured parameters to the control logic Verilog template to obtain the Verilog code of the digital control logic.

[0016] According to an embodiment of the present invention, the digital control logic automatic generation module calls the digital synthesis script template in the template module to convert the digital logic Verilog code into a digital control logic gate netlist, and combines it with the digital LDO netlist file template to generate a digital control logic netlist file;

[0017] Call the digital back-end automatic placement and routing script template to convert the digital control logic gate netlist into a digital control logic layout file.

[0018] According to an embodiment of the present invention, the analog topology of the digital LDO architecture includes a clock-controlled comparator, two sets of PMOS switch arrays, a load capacitor, and a feedback resistor;

[0019] The negative phase terminal of the clock control comparator is connected to the reference voltage, the positive phase terminal is connected to the feedback voltage obtained by dividing the output voltage of the digital LDO through the feedback resistor, and the output terminal is connected to the control logic structure; the gates of the two groups of PMOS switch arrays are respectively connected to the coarse adjustment loop and the fine adjustment loop of the control logic structure; one end of the load capacitor is connected to the output voltage, and the other end is grounded;

[0020] The digital LDO automatic generation module configures parameters of the number of two groups of PMOS switch arrays, the size of the load capacitor, the number of feedback resistors and the voltage division ratio based on the analog topology to obtain a corresponding analog unit.

[0021] According to an embodiment of the present invention, the number of the two groups of PMOS switch arrays is determined by the input voltage, output voltage and maximum load current of the digital LDO;

[0022] The size of the load capacitance is determined by the clock frequency;

[0023] The number of feedback voltage divider resistors and the voltage divider ratio are determined by the input voltage, output voltage and reference voltage of the digital LDO.

[0024] According to an embodiment of the present invention, the digital LDO automatic generation module combines the layout file of the analog unit and the layout file of the digital control logic according to the pin alignment splicing rule to obtain the layout file of the digital LDO.

[0025] A parameterizable and configurable digital LDO automatic generation method, comprising:

[0026] Obtain a given digital LDO architecture, where the digital LDO architecture includes a control logic structure and an analog topology structure;

[0027] Template the digital LDO architecture to obtain templates including control logic code template, digital LDO netlist file template, digital synthesis script template and digital back-end automatic layout and routing script template;

[0028] Based on the control logic structure of a given digital LDO architecture, configure the control logic parameters of the control logic structure and pass the parameters to the control logic code template, digital synthesis script template, and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic;

[0029] Based on the given analog topology of the digital LDO architecture, the analog parameters in the digital LDO architecture are configured to obtain the corresponding analog units; the analog units are combined with the netlist file of the digital control logic to generate the netlist file of the digital LDO;

[0030] The layout file of the analog unit and the layout file of the digital control logic are combined according to the splicing rules to obtain the layout file of the digital LDO.

[0031] According to an embodiment of the present invention, the automatic generation of a netlist file and a layout file of digital control logic further includes:

[0032] Parameterizing the control signal bit width of the control logic in the digital LDO basic architecture, and passing the configured parameters to the control logic code template to obtain the control logic code; wherein the configured parameters include the number of bits of the PMOS array;

[0033] Apply the control logic code to the digital synthesis script template to automatically generate a digital control logic gate netlist, and combine it with the digital LDO netlist file template to generate a digital control logic netlist file;

[0034] Apply the digital control logic gate netlist to the digital backend automatic placement and routing script template to automatically generate the digital control logic layout file.

[0035] According to one embodiment of the present invention, the control logic structure of the digital LDO architecture includes a counter, a sequence detector, and a shift control logic. The input of the counter is connected to a clock signal, and the output is connected to the shift control logic. The input of the sequence detector is connected to a clock signal, and the output is connected to the shift control logic to control the digital LDO to enter the coarse loop logic or the fine loop logic.

[0036] Designing the counter, sequence detector and shift control logic using Verilog code to generate a control logic Verilog template;

[0037] Parameter configuration is performed on the control signal bit width of the shift control logic, the counting threshold of the counter, and the sequence detectable by the sequence detector, and the configured parameters are passed to the control logic Verilog template to obtain the Verilog code of the digital control logic;

[0038] Call the digital synthesis script template to convert the digital logic Verilog code into a digital control logic gate netlist, and combine it with the digital LDO netlist file template to generate a digital control logic netlist file;

[0039] Call the digital back-end automatic placement and routing script template to convert the digital control logic gate netlist into a digital control logic layout file.

[0040] According to one embodiment of the present invention, the analog topology of the digital LDO architecture includes a clocked comparator, two groups of PMOS switch arrays, a load capacitor, and a feedback resistor; the negative phase terminal of the clocked comparator is connected to a reference voltage, the positive phase terminal is connected to a feedback voltage obtained by dividing the output voltage of the digital LDO through the feedback resistor, and the output terminal is connected to a control logic structure; the gates of the two groups of PMOS switch arrays are respectively connected to a coarse adjustment loop and a fine adjustment loop of the control logic structure; one end of the load capacitor is connected to the output voltage, and the other end is grounded;

[0041] Based on the analog topology, the number of two groups of PMOS switch arrays, the size of the load capacitor, the number of feedback resistors and the voltage division ratio are parameterized to obtain a corresponding analog unit;

[0042] The number of the two PMOS switch arrays is determined by the input voltage, output voltage, and maximum load current of the digital LDO; the size of the load capacitor is determined by the clock frequency; and the number and voltage division ratio of the feedback voltage divider resistors are determined by the input voltage, output voltage, and reference voltage of the digital LDO.

[0043] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0044] The method for automatically generating a parameterizable digital LDO circuit, in one embodiment of the present invention, addresses the long and costly cycles associated with existing digital LDO design methods, which require repeated simulation verification and schematic layout modifications. Based on a given digital LDO architecture, this method implements a configurable design for the changeable design parameters of the digital LDO circuit. The configurable performance parameters are then mapped to the circuit design parameters. Simply inputting the specified performance parameters allows the corresponding digital LDO netlist and layout files to be generated. This significantly reduces circuit design time and enables agile design. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A block diagram of a device for automatically generating a parameterizable digital LDO according to an embodiment of the present invention;

[0046] Figure 2 A basic architecture diagram of a digital LDO according to an embodiment of the present invention;

[0047] Figure 3 A flow chart for generating a digital LDO circuit file in one embodiment of the present invention;

[0048] Figure 4 The figure is a flow chart of a method for automatically generating a parameterizable digital LDO according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following is a detailed description of a parameterizable digital LDO automatic generation method and device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims.

[0050] This embodiment provides a parameterizable digital LDO automatic generation device. Figure 1 ,include:

[0051] A digital LDO architecture is provided, wherein the digital LDO architecture includes a control logic structure and an analog topology structure;

[0052] A template module is used to template the digital LDO architecture to obtain templates including control logic code templates, digital LDO netlist file templates, digital synthesis script templates, and digital back-end automatic layout and routing script templates;

[0053] The digital control logic automatic generation module is used to configure the control logic parameters based on the control logic structure of a given digital LDO architecture, and pass the parameters to the control logic code template, digital synthesis script template, and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic;

[0054] The digital LDO automatic generation module is used to configure the analog parameters in the digital LDO architecture based on the analog topology of the given digital LDO architecture to obtain the corresponding analog units; combine the analog units with the netlist file of the digital control logic to generate the netlist file of the digital LDO; and combine the layout file of the analog units with the layout file of the digital control logic according to the splicing rules to obtain the layout file of the digital LDO.

[0055] Through the above-mentioned digital LDO automatic generation device, the corresponding digital LDO netlist file and layout file can be generated by simply inputting the specified performance parameters, which can greatly reduce the design time of the circuit and realize agile design.

[0056] For a specific digital LDO architecture, see Figure 2The digital LDO architecture includes: a clock-controlled comparator, a counter, a sequence detector, shift control logic (coarse-loop logic and fine-loop logic), two PMOS switch arrays, two feedforward auxiliary PMOS arrays (two in total), an undershoot detection circuit, load capacitors, and feedback resistors. The control logic structure of the given digital LDO architecture includes a counter, a sequence detector, and shift control logic. The counter's input is connected to a clock signal, and its output is connected to the shift control logic. The sequence detector's input is connected to a clock signal, and its output is connected to the shift control logic, controlling the digital LDO to enter coarse-loop logic or fine-loop logic.

[0057] The template module uses Verilog code to design the counter, sequence detector and shift control logic and generates a Verilog template for the control logic.

[0058] Please see Figure 3 ,The digital control logic automatic generation module configures the parameters of the ,control signal width of the shift control logic, the counting threshold of the ,counter, and the sequence detectable by the sequence detector, ,and passes the configured parameters to the control logic Verilog template to ,obtain the Verilog code of the digital control logic.

[0059] The digital control logic automatic generation module calls the digital synthesis script template in the templated module to convert the digital logic Verilog code into a digital control logic gate netlist, and combines it with the digital LDO netlist file template to generate a digital control logic netlist file; calls the digital back-end automatic layout and routing script template to convert the digital control logic gate netlist into a digital control logic layout file.

[0060] The analog topology of this digital LDO architecture includes a clock-controlled comparator, two groups of PMOS switch arrays, a load capacitor, and a feedback resistor. The negative phase terminal of the clock-controlled comparator is connected to a reference voltage, the positive phase terminal is connected to a feedback voltage obtained by dividing the output voltage of the digital LDO through a feedback resistor, and its output terminal is connected to a control logic structure. The gates of the two groups of PMOS switch arrays are respectively connected to the coarse adjustment loop and the fine adjustment loop of the control logic structure. One end of the load capacitor is connected to the output voltage, and the other end is grounded.

[0061] The digital LDO automatic generation module, based on an analog topology, configures the number of two PMOS switch arrays, the size of the load capacitors, the number of feedback resistors, and the voltage divider ratio to create the corresponding analog unit. The number of the two PMOS switch arrays is determined by the digital LDO's input voltage, output voltage, and maximum load current; the size of the load capacitors is determined by the clock frequency; and the number and voltage divider ratio of the feedback resistors are determined by the digital LDO's input voltage, output voltage, and reference voltage.

[0062] The analog topology of the aforementioned digital LDO architecture can also include two sets of feedforward auxiliary PMOS and undershoot detection circuits, wherein the gates of the two sets of feedforward auxiliary PMOS are connected to the output of the clock control comparator, the sources are connected to the input voltage, and the drains are connected to the output voltage. The input of the undershoot detection circuit is connected to the output voltage of the digital LDO, and its output is connected to the shift control logic. The analog units and analog layouts of the two sets of feedforward auxiliary PMOS and undershoot detection circuits are input into the digital LDO automatic generation module, and the netlist files of the analog units and digital control logic are combined to generate the netlist file of the digital LDO. The layout files of the analog units and the layout files of the digital control logic are combined according to the splicing rules to obtain the layout file of the digital LDO.

[0063] The digital LDO automatic generation module combines the layout file of the analog unit and the layout file of the digital control logic according to the pin alignment splicing rule to obtain the layout file of the digital LDO.

[0064] Based on the same concept, this embodiment provides a parameterizable digital LDO automatic generation method, see Figure 4 , the method comprises the following steps:

[0065] S1: Obtain a given digital LDO architecture, where the digital LDO architecture includes a control logic structure and an analog topology structure;

[0066] S2: Template the digital LDO architecture to obtain templates including a control logic code template, a digital LDO netlist file template, a digital synthesis script template, and a digital back-end automatic layout and routing script template;

[0067] S3: Based on the control logic structure of a given digital LDO architecture, configure the control logic parameters of the control logic structure and pass the parameters to the control logic code template, digital synthesis script template, and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic;

[0068] S4: Based on the given analog topology of the digital LDO architecture, configure analog parameters in the digital LDO architecture to obtain corresponding analog units; combine the analog units with the netlist file of the digital control logic to generate a netlist file of the digital LDO;

[0069] S5: Combine the layout file of the analog unit and the layout file of the digital control logic according to the splicing rules to obtain the layout file of the digital LDO.

[0070] Through the above-mentioned digital LDO automatic generation method, the corresponding digital LDO netlist file and layout file can be generated by simply entering the specified performance parameters, which can greatly reduce the circuit design time and achieve agile design.

[0071] In step S2, the control logic code template is a template that includes the digital control logic of the digital LDO, such as the control of the coarse and fine adjustment logic in the digital LDO. Most of the content of this template can be reused, and only minor changes need to be made based on the external variables passed in to obtain the control logic code for a specific circuit. Similarly, most of the content of the digital LDO netlist file template can be reused, and only minor changes need to be made based on the external variables passed in to obtain the netlist file for a specific circuit. The digital synthesis script template contains the synthesis script code and can be automatically modified based on the variables passed in externally to complete the conversion from digital logic code to gate-level netlist. The digital back-end layout and routing script template contains the layout and routing code, which is also automatically modified based on the external variables to complete the process from gate-level netlist to layout.

[0072] The above template can be used to adapt digital LDO circuits with different specifications, which is the basis for realizing agile design of digital LDOs.

[0073] In step S3, this part focuses on the automatic generation of relevant files of digital control logic circuit. For details, please refer to Figure 2 , configure the parameters of the control signal bit width of the control logic in the basic architecture of the digital LDO, such as the number of bits of the PMOS array. In the coarse adjustment and fine adjustment control logic, the bit width of the control signal is determined by the number of bits of the PMOS array. Pass the configured parameters to the control logic code template to obtain the control logic code. Apply the control logic code to the digital synthesis script template to complete the conversion from digital logic code to gate-level netlist, and automatically generate the digital control logic gate netlist. On the one hand, the digital control logic gate netlist is combined with the digital LDO netlist file template to generate a digital control logic netlist file. On the other hand, the digital control logic gate netlist is applied to the digital back-end automatic layout and routing script template to complete the conversion from gate-level netlist to layout, and automatically generate the digital control logic layout file.

[0074] In step S4, analog parameters in the digital LDO architecture are configured to obtain corresponding analog units. The analog units are then combined with the netlist file for the digital control logic to generate the netlist file for the digital LDO. In a digital LDO architecture, in addition to components related to the control logic, there are also analog units such as clocked comparators and PMOS switch arrays. When designing circuits for a given digital LDO architecture, these analog units require parameter configuration. After parameter configuration, the analog units can be used in circuit design, resulting in a layout for the analog units. The analog units are then combined with the netlist file for the digital control logic to generate the netlist file for the digital LDO.

[0075] In step S5, the layout file of the analog unit and the layout file of the digital control logic are combined according to the splicing rules to obtain the layout file of the digital LDO. The layout file of the analog unit obtained in step S4 and the layout file of the digital control logic obtained in step S3 are combined according to the splicing rules of pin alignment to obtain the layout file of the digital LDO.

[0076] Once the digital LDO netlist and layout files are obtained, the circuit design for a given digital LDO architecture is complete. This method allows for the implementation of parameter-configurable digital LDOs within the same architecture. Furthermore, the circuit and layout for digital LDOs with the same architecture can be automatically generated based on the input design parameters, significantly reducing circuit design time and enabling agile design.

[0077] The following describes the parameterizable and configurable digital LDO automatic generation method in this embodiment using an application example.

[0078] Please see Figure 2 The figure shows a digital LDO architecture, which includes: a clock-controlled comparator, a counter, a sequence detector, a shift control logic (coarse loop logic and fine loop logic), two sets of PMOS switch arrays, two sets of feedforward auxiliary PMOS (two in number each), an undershoot detection circuit, a load capacitor, and a feedback resistor; the counter, sequence detector, and shift control logic are designed using digital Verilog code.

[0079] The configurable performance parameters of the digital LDO architecture circuit are: input voltage VIN and output voltage VOUT, maximum load current, input clock frequency, and reference voltage.

[0080] The configurable circuit design parameters of this digital LDO architecture circuit are mainly: the number N and M of the two groups of PMOS switch arrays, which corresponds to the control signal bit width output by the shift control logic; and the voltage divider ratio of the load capacitance and the feedback resistor.

[0081] The automatic generation of digital control logic for this digital LDO architecture includes the following steps:

[0082] 1. Automatic Verilog Generation: The counter, sequence detector, and shift control logic in this digital LDO architecture are designed using Verilog code. The control signal width of the shift control logic, the counter's count threshold, and the sequence detector's detectable sequence are configurable parameters. The control signal width is determined by the number of PMOS arrays, N and M. Passing these two parameters into a Verilog template generates the Verilog code for the shift control logic. The counter's count count and the sequence detector's detection sequence are then determined. The template then automatically generates the Verilog code for the digital control logic based on these input parameters.

[0083] 2. Automatic generation of digital control logic circuits and layouts: Using the digital back-end process, you can directly generate the cdl and gds files of the digital control logic, pass the parameters N and M to the digital synthesis script template and the digital back-end automatic layout and routing script template, and then use the corresponding tools to complete the self-generation.

[0084] The automatic generation of this digital LDO includes the following steps:

[0085] 1. Configurable analog part parameters: The analog part (including the clock control comparator, two PMOS switch arrays, two feedforward auxiliary PMOS arrays (each with two), undershoot detection circuit, load capacitors, and feedback resistors) has adjustable parameters, including the number N and M of coarse and fine ring PMOS arrays, the size of the PMOS arrays, the size of the load capacitors, and the number and divider ratio of the feedback divider resistors.

[0086] 2. Automatic generation of digital LDO netlist file: After determining the parameters of the analog part, use the corresponding analog unit and the CDL of the digital control logic to combine them to generate the netlist file of the complete digital LDO.

[0087] 3. Automatic generation of digital LDO layout files: Use the corresponding analog unit layout files and the automatically generated digital layout files to combine the layouts according to the splicing rules.

[0088] The relationship between the configurable parameters of the digital LDO is as follows:

[0089] 1. The number N and M of the coarse and fine ring PMOS arrays. The size of the PMOS array is determined by the input performance parameters VIN, VOUT and the maximum load current;

[0090] 2. The size of the load capacitance is determined by the input clock frequency;

[0091] 3. The number of feedback voltage divider resistors and the voltage divider ratio are determined by the input VIN, VOUT and reference voltage.

[0092] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they still fall within the scope of protection of the present invention.

Claims

1. A parameterizable digital LDO automatic generation device, characterized in that: include: A digital LDO architecture is provided, wherein the digital LDO architecture includes a control logic structure and an analog topology structure; A template module is used to template the digital LDO architecture to obtain templates including control logic code templates, digital LDO netlist file templates, digital synthesis script templates, and digital back-end automatic layout and routing script templates; The digital control logic automatic generation module is used to configure the control logic parameters based on the control logic structure of a given digital LDO architecture, and pass the parameters to the control logic code template, digital synthesis script template, and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic; The digital LDO automatic generation module is used to configure the analog parameters in the digital LDO architecture based on the analog topology of the given digital LDO architecture to obtain the corresponding analog units; combine the analog units with the netlist file of the digital control logic to generate the netlist file of the digital LDO; and combine the layout file of the analog units with the layout file of the digital control logic according to the splicing rules to obtain the layout file of the digital LDO; The control logic structure of the digital LDO architecture includes a counter, a sequence detector, and a shift control logic. The input of the counter is connected to the clock signal, and the output is connected to the shift control logic. The input of the sequence detector is connected to the clock signal, and the output is connected to the shift control logic to control the digital LDO to enter the coarse loop logic or the fine loop logic. The template module uses Verilog code to design the counter, sequence detector and shift control logic to generate a control logic Verilog template; The analog topology of the digital LDO architecture includes a clock control comparator, two sets of PMOS switch arrays, load capacitors and feedback resistors; The negative phase terminal of the clock control comparator is connected to the reference voltage, the positive phase terminal is connected to the feedback voltage obtained by dividing the output voltage of the digital LDO through the feedback resistor, and the output terminal is connected to the control logic structure; the gates of the two groups of PMOS switch arrays are respectively connected to the coarse adjustment loop and the fine adjustment loop of the control logic structure; one end of the load capacitor is connected to the output voltage, and the other end is grounded; The digital LDO automatic generation module configures parameters of the number of two groups of PMOS switch arrays, the size of the load capacitor, the number of feedback resistors and the voltage division ratio based on the analog topology to obtain a corresponding analog unit.

2. The parameterizable digital LDO automatic generation device according to claim 1, wherein: The digital control logic automatic generation module configures parameters of the control signal bit width of the shift control logic, the counting threshold of the counter, and the sequence detectable by the sequence detector, and passes the configured parameters to the control logic Verilog template to obtain the Verilog code of the digital control logic.

3. The parameterizable digital LDO automatic generation device according to claim 2, wherein: The digital control logic automatic generation module calls the digital synthesis script template in the template module to convert the digital logic Verilog code into a digital control logic gate netlist, and combines it with the digital LDO netlist file template to generate a digital control logic netlist file; Call the digital back-end automatic placement and routing script template to convert the digital control logic gate netlist into a digital control logic layout file.

4. The parameterizable digital LDO automatic generation device according to claim 1, wherein: The number of the two groups of PMOS switch arrays is determined by the input voltage, output voltage and maximum load current of the digital LDO; The size of the load capacitance is determined by the clock frequency; The number of feedback resistors and the voltage division ratio are determined by the input voltage, output voltage and reference voltage of the digital LDO.

5. The parameterizable digital LDO automatic generation device according to claim 1, wherein: The digital LDO automatic generation module combines the layout file of the analog unit and the layout file of the digital control logic according to the pin alignment splicing rule to obtain the layout file of the digital LDO.

6. A parameterizable digital LDO automatic generation method, applied to the parameterizable digital LDO automatic generation device according to claim 1, characterized in that: include: Obtain a given digital LDO architecture, where the digital LDO architecture includes a control logic structure and an analog topology structure; Template the digital LDO architecture to obtain templates including control logic code template, digital LDO netlist file template, digital synthesis script template and digital back-end automatic layout and routing script template; Based on the control logic structure of a given digital LDO architecture, configure the control logic parameters of the control logic structure and pass the parameters to the control logic code template, digital synthesis script template, and digital back-end automatic layout and routing script template to automatically generate the netlist file and layout file of the digital control logic; Based on the given analog topology of the digital LDO architecture, the analog parameters in the digital LDO architecture are configured to obtain the corresponding analog units; the analog units are combined with the netlist file of the digital control logic to generate the netlist file of the digital LDO; The layout file of the analog unit and the layout file of the digital control logic are combined according to the splicing rules to obtain the layout file of the digital LDO.

7. The method for automatically generating a parameterizable digital LDO according to claim 6, wherein: The automatic generation of the netlist file and layout file of the digital control logic further includes: Parameterizing the control signal bit width of the control logic in the digital LDO basic architecture, and passing the configured parameters to the control logic code template to obtain the control logic code; wherein the configured parameters include the number of bits of the PMOS array; Apply the control logic code to the digital synthesis script template to automatically generate a digital control logic gate netlist, and combine it with the digital LDO netlist file template to generate a digital control logic netlist file; Apply the digital control logic gate netlist to the digital backend automatic placement and routing script template to automatically generate the digital control logic layout file.

8. The parameterizable digital LDO automatic generation method according to claim 6, wherein: The control logic structure of the digital LDO architecture includes a counter, a sequence detector, and a shift control logic. The input of the counter is connected to the clock signal, and the output is connected to the shift control logic. The input of the sequence detector is connected to the clock signal, and the output is connected to the shift control logic to control the digital LDO to enter the coarse loop logic or the fine loop logic. Designing the counter, sequence detector and shift control logic using Verilog code to generate a control logic Verilog template; Parameter configuration is performed on the control signal bit width of the shift control logic, the counting threshold of the counter, and the sequence detectable by the sequence detector, and the configured parameters are passed to the control logic Verilog template to obtain the Verilog code of the digital control logic; Call the digital synthesis script template to convert the digital logic Verilog code into a digital control logic gate netlist, and combine it with the digital LDO netlist file template to generate a digital control logic netlist file; Call the digital back-end automatic placement and routing script template to convert the digital control logic gate netlist into a digital control logic layout file.

9. The method for automatically generating a parameterizable digital LDO according to claim 6, wherein: The analog topology of the digital LDO architecture includes a clock-controlled comparator, two sets of PMOS switch arrays, a load capacitor, and a feedback resistor; the negative phase terminal of the clock-controlled comparator is connected to a reference voltage, the positive phase terminal is connected to a feedback voltage obtained by dividing the output voltage of the digital LDO through the feedback resistor, and the output terminal is connected to a control logic structure; the gates of the two sets of PMOS switch arrays are respectively connected to the coarse control loop and the fine control loop of the control logic structure; one end of the load capacitor is connected to the output voltage, and the other end is grounded; Based on the analog topology, the number of two groups of PMOS switch arrays, the size of the load capacitor, the number of feedback resistors and the voltage division ratio are parameterized to obtain a corresponding analog unit; The number of the two PMOS switch arrays is determined by the input voltage, output voltage, and maximum load current of the digital LDO; the size of the load capacitor is determined by the clock frequency; and the number of feedback resistors and the voltage division ratio are determined by the input voltage, output voltage, and reference voltage of the digital LDO.

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