Memory device

Abstract

The present invention addresses the problem of shortening the operation time. According to one embodiment, a memory device includes a plurality of bit lines, a plurality of strings, first and second wirings, a word line, and a sequencer. The plurality of strings are connected to the plurality of bit lines, respectively. Each string includes a memory cell, and first and second transistors. The first wiring is connected to the first transistor of each of the plurality of strings. The second wiring is connected to the second transistor of each of the plurality of strings. The word lines are connected to the respective memory cells of the plurality of strings. The sequencer applies a first voltage to one of the first and second wirings and applies a second voltage higher than the first voltage to the other of the first and second wirings in a read operation in which N (N is an integer of 1 or more) bytes of the word line are selected. The sequencer applies a third voltage higher than the first voltage to each of the first and second wirings in a read operation of 2 * N bytes in which the word line has been selected.

Description

Technical Field

[0001] Embodiments relate to a memory device. Background Art

[0002] A NAND (Not and) type flash memory capable of storing data in a nonvolatile manner is known.

[0003] [Prior Technical Literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2021-072313 Summary of the invention

[0006] [Problems to be solved by the invention]

[0007] Shorten the action time.

[0008] [Technical means to solve the problem]

[0009] The memory device of the embodiment includes a plurality of bit lines, a plurality of strings, a first wiring, a second wiring, a word line, and a sequencer. One end of each of the plurality of strings is connected to the plurality of bit lines, respectively. The plurality of strings respectively include memory cells connected in series, and first and second transistors. The first wiring is connected to the first transistor of each of the plurality of strings. The second wiring is connected to the second transistor of each of the plurality of strings. The word line is connected to the memory cell of each of the plurality of strings. In a read operation in which N (N is an integer greater than 1) bytes of a word line are selected, the sequencer applies a first voltage to one of the first wiring and the second wiring, and applies a second voltage higher than the first voltage to the other of the first wiring and the second wiring. In a read operation in which 2×N bytes of a word line are selected, the sequencer applies a third voltage higher than the first voltage to each of the first wiring and the second wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a block diagram showing an example of the overall configuration of the memory device according to the first embodiment.

[0011] Figure 2 This is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the memory device according to the first embodiment.

[0012] Figure 3 This is a circuit diagram showing an example of the circuit configuration of a row decoder module included in the memory device according to the first embodiment.

[0013] Figure 4 This is a circuit diagram showing an example of the circuit configuration of a data register and a sense amplifier module included in the memory device according to the first embodiment.

[0014] Figure 5 1 is a circuit diagram showing an example of a circuit configuration of a sense amplifier unit included in a sense amplifier module included in the memory device according to the first embodiment.

[0015] Figure 6 This is a perspective view showing an example of the appearance of the memory device according to the first embodiment.

[0016] Figure 7 It is a schematic diagram showing an example of a planar layout of a bonding surface included in the memory device according to the first embodiment.

[0017] Figure 8 It is a plan view showing an example of a planar layout of a memory layer included in the memory device according to the first embodiment.

[0018] Fig. 9 It is a plan view showing an example of a plan layout of a storage area of ​​a memory layer included in the memory device according to the first embodiment.

[0019] Fig.10 An example of a cross-sectional structure of a storage region of a memory layer included in the memory device of the first embodiment is shown, along Fig. 9 Cross-sectional view of line XX.

[0020] Fig.11 An example of a cross-sectional structure of a memory pillar included in a memory layer provided in the memory device according to the first embodiment is shown, along Fig.10 A cross-sectional view taken along line XI-XI.

[0021] Fig.12 It is a plan view showing an example of a plan layout of a lead-out region of a memory layer included in the memory device according to the first embodiment.

[0022] Fig.13 FIG. 1 is an example of a cross-sectional structure of a lead-out region of a memory layer included in the memory device of the first embodiment, along the Fig.12 A cross-sectional view along line XII-XIII.

[0023] Fig.14 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the first embodiment.

[0024] Fig.15 This is a schematic diagram showing an example of threshold voltage distribution and data allocation of memory cell transistors in the memory device according to the first embodiment.

[0025] Fig.16 This is a schematic diagram showing an example of the threshold voltage distribution of the selection transistor in the memory device according to the first embodiment.

[0026] Fig.17 This is a schematic diagram showing an example of threshold voltage distribution of selection transistors in the memory device according to the first embodiment.

[0027] Fig.18 This is a timing chart showing an example of the parity bit line read operation of the memory device according to the first embodiment.

[0028] Fig.19 This is a schematic diagram showing an example of a method of selecting a bit line in a parity bit line read operation of the memory device according to the first embodiment.

[0029] Fig. 20 This is a timing chart showing an example of the even-numbered bit line read operation of the memory device according to the first embodiment.

[0030] Fig.21 This is a schematic diagram showing an example of a method of selecting a bit line in an even-numbered bit line read operation of the memory device according to the first embodiment.

[0031] Fig. 22 This is a timing chart showing an example of an odd-numbered bit line read operation of the memory device according to the first embodiment.

[0032] Fig.23 This is a schematic diagram showing an example of a method of selecting a bit line in an odd-numbered bit line read operation of the memory device according to the first embodiment.

[0033] Fig.24 This is a block diagram showing an example of the overall configuration of a memory device according to the second embodiment.

[0034] Fig.25 This is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the memory device according to the second embodiment.

[0035] Fig.26 This is a circuit diagram showing an example of the circuit configuration of a row decoder module included in the memory device according to the second embodiment.

[0036] Fig. 27 1 is a circuit diagram showing an example of a circuit configuration of a sense amplifier unit included in a sense amplifier module included in a memory device according to a second embodiment.

[0037] Fig.28 It is a perspective view showing an example of the appearance of the memory device according to the second embodiment.

[0038] Fig.29 It is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the second embodiment.

[0039] Fig.30This is a schematic diagram showing an example of threshold voltage distribution of selection transistors in the memory device according to the second embodiment.

[0040] Fig.31 This is a timing chart showing an example of a first read operation of the memory device according to the second embodiment.

[0041] Fig.32 This is a schematic diagram showing an example of a method of selecting a bit line in the first read operation of the memory device according to the second embodiment.

[0042] Fig.33 This is a schematic diagram showing an example of a method of selecting a bit line in the first read operation of the memory device according to the second embodiment.

[0043] Fig.34 This is a timing chart showing an example of the second read operation of the memory device according to the second embodiment.

[0044] Fig.35 This is a timing chart showing an example of a shield read operation of the memory device according to the second embodiment.

[0045] Fig.36 This is a schematic diagram showing an example of a method of selecting a bit line in a mask read operation of the memory device according to the second embodiment.

[0046] Fig.37 This is a timing chart showing an overview of the write operation of the memory device according to the second embodiment.

[0047] Fig.38 This is a timing chart showing an example of a programming operation of a write operation of the memory device according to the second embodiment.

[0048] Fig.39 This is a schematic diagram showing an example of a method of selecting a bit line in a programming operation of a writing operation of the memory device according to the second embodiment.

[0049] Fig.40 It is a schematic diagram showing a variation of the allocation of bit line groups.

[0050] Fig.41 It is a cross-sectional view showing a modified example of the structure of the memory device.

[0051] Fig.42 It is a cross-sectional view showing an example of a detailed cross-sectional structure of a bonding portion of a bonding pad. DETAILED DESCRIPTION

[0052] Below, each embodiment is described with reference to the accompanying drawings. Each embodiment illustrates an apparatus and method for concretizing the technical idea of ​​the invention. The accompanying drawings are schematic diagrams or conceptual diagrams. The dimensions and proportions of each drawing may not be the same as in reality. The illustrations of the components may be omitted as appropriate. The hatching added in the drawings may not be related to the materials or characteristics of the components. The same symbols are marked on the components with roughly the same functions and structures. The numbers attached to the reference symbols are used to distinguish similar elements represented by the same reference symbols from each other.

[0053] <1> First Embodiment

[0054] The memory device 1 of the first embodiment is a NAND type flash memory capable of storing data in a nonvolatile manner. In the memory device 1 of the first embodiment, a plurality of bit lines are divided into two groups. Furthermore, the memory device 1 performs selected operations on the two groups individually by using two types of selection transistors included in the NAND string. The first embodiment will be described in detail below.

[0055] <1-1>Composition

[0056] First, the configuration of the memory device 1 according to the first embodiment will be described.

[0057] <1-1-1> Overall Configuration of Memory Device 1

[0058] Figure 1 1 is a block diagram showing an example of the overall structure of the memory device 1 according to the first embodiment. Figure 1 As shown, the memory device 1 is controlled by an external memory controller 2. The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, a data register 17, and a sense amplifier module 18.

[0059] The memory cell array 10 is a collection of multiple memory cells. The memory cell array 10 includes multiple blocks BLK0~BLKn ("n" is an integer greater than 1). Block BLK corresponds to a unit for erasing data, for example, and includes multiple pages. A page corresponds to a unit for performing reading and writing of data. The memory cell array 10 is provided with multiple bit lines BL0~BLm ("m" is an integer greater than 1) and multiple word lines WL (not shown). Each memory cell is associated with a group of bit lines BL and word lines WL. When a group of bit lines BL and word lines WL are associated with multiple memory cells, these multiple memory cells are configured to be individually accessible through selection transistors.

[0060] The input-output circuit 11 is an interface circuit responsible for sending and receiving (input and output) input-output signals with the memory controller 2. The input-output signals include, for example, data DAT, status information, addresses, instructions, etc. The input-output circuit 11 can input and output data DAT between the data register 17 and the memory controller 2, respectively. The input-output circuit 11 can output the status information transmitted from the register circuit 13 to the memory controller 2. The input-output circuit 11 can output the addresses and instructions transmitted from the memory controller 2 to the register circuit 13, respectively.

[0061] The logic controller 12 is a controller that controls the input / output circuit 11 and the sequencer 14 based on the control signal input from the memory controller 2. The logic controller 12 instructs the input / output circuit 11 to input a signal from the memory controller 2 or to output a signal to the memory controller 2. In addition, the logic controller 12 notifies the input / output circuit 11 of the type of the input / output signal received by the input / output circuit 11 (for example, any of data DAT, command, and address).

[0062] The register circuit 13 is a circuit for temporarily storing states, addresses, and instructions. The state is information indicating the operating state of the memory device 1. The state is updated based on the control of the sequencer 14 and transmitted to the memory controller 2 via the input / output circuit 11. The address may include a block address, a page address, a column address, etc. The instruction includes commands related to various operations of the memory device 1.

[0063] The sequencer 14 is a controller that controls the overall operation of the memory device 1. The sequencer 14 executes a read operation, a write operation, an erase operation, and the like based on the command and address stored in the register circuit 13.

[0064] The driver circuit 15 is a circuit that generates a voltage used in a read operation, a write operation, an erase operation, etc. The driver circuit 15 supplies the generated voltage to the row decoder module 16 or the sense amplifier module 18 .

[0065] The row decoder module 16 is a circuit for selecting a block BLK to be operated in a read operation or the like, and for transmitting a voltage to wirings such as a word line WL. The row decoder module 16 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are respectively associated with the blocks BLK0 to BLKn. The detailed structure of the row decoder RD will be described below.

[0066] The data register 17 is a circuit for temporarily storing data DAT. The data register 17 can input and output the data DAT between the input / output circuit 11 and the sense amplifier module 18. The data register 17 can also be called a cache memory.

[0067] The sense amplifier module 18 is a circuit for transmitting voltage to each bit line BL and reading data. The sense amplifier module 18 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are respectively associated with a plurality of bit lines BL0 to BLm. The detailed structure of the sense amplifier unit SAU will be described below.

[0068] In addition, the combination of the memory device 1 and the memory controller 2 may also constitute a semiconductor device. As such a semiconductor device, for example, an SD TM Cards such as memory cards, SSDs (solid state drives), etc. A group consisting of the memory cell array 10, the row decoder module 16, and the sense amplifier module 18 is called a "memory plane", for example. The memory device 1 may include a plurality of memory planes.

[0069] <1-1-2> Circuit Configuration of Memory Device 1

[0070] Next, the circuit structure of the memory device 1 of the first embodiment is described. Hereinafter, a MOS (Metal Oxide Semiconductor) transistor with a high withstand voltage is referred to as an "HV (High-Voltage) transistor". A MOS transistor with a lower withstand voltage than an HV transistor is referred to as an "LV (Low-Voltage) transistor". For example, an LV transistor has a gate insulating film thinner than an HV transistor and can operate at a higher speed than an HV transistor.

[0071] (1: Circuit Configuration of Memory Cell Array 10)

[0072] Figure 2 1 is a circuit diagram showing an example of a circuit configuration of a memory cell array 10 included in the memory device 1 according to the first embodiment. Figure 2 FIG. 2 shows one block BLK among a plurality of blocks BLK included in the memory cell array 10. Figure 2 As shown, the block BLK is connected to the selection gate lines SGD0 to SGD4, SGe and SGo, the word lines WL0 to WL(k-1) (k is an integer greater than 2), the selection gate line SGS, the bit lines BL0 to BLm, and the source line SL. The selection gate lines SGD0 to SGD4, the selection gate lines SGe and SGo, the word lines WL0 to WL(k-1), and the selection gate line SGS are provided for each block BLK. The bit lines BL0 to BLm and the source line SL can be shared by multiple blocks BLK.

[0073] Block BLK includes, for example, five string units SU0 to SU4. Each string unit SU includes NAND strings NS0 to NSm. NAND strings NS0 to NSm are associated with bit lines BL0 to BLm, respectively. Each NAND string NS is connected between the associated bit line BL and the source line SL. Each bit line BL is shared by NAND strings NS assigned the same column address among multiple blocks BLK.

[0074] Each NAND string NS includes, for example, a selection transistor STD, selection transistors STe and STo, k memory cell transistors MT0 to MT(k-1), and a selection transistor STS. In each NAND string NS, the selection transistors STD, STe and STo, the memory cell transistors MT(k-1) to MT0, and the selection transistor STS are connected in series in sequence. Moreover, in each NAND string NS, the drain of the selection transistor STD is connected to the associated bit line BL, and the source of the selection transistor STS is connected to the source line SL.

[0075] Each memory cell transistor MT has a control gate and a charge storage layer to store (store) data in a non-volatile manner. The memory cell transistor MT can be a charge capture type memory cell or a floating gate type memory cell. The selection transistors STD and STS are used to select the string unit SU. The selection transistors STe and STo can each have the same structure as the memory cell transistor MT, and can also be called memory cells. The selection transistors STe and STo are used to select a group of bit lines BL. In the first embodiment, an example is taken in which an even bit line group including even bit lines BLe (BL0, BL2, BL4, ...) and an odd bit line group including odd bit lines BLo (BL1, BL3, BL5, ...) can be individually selected from a plurality of bit lines BL0 to BLm.

[0076] The selection gate lines SGD0 to SGD4 are associated with the string units SU0 to SU4, respectively. Each selection gate line SGD is connected to the gate terminal of each of the multiple selection transistors STD included in the associated string unit SU. The selection gate line SGe is connected to the gate terminal of each of the multiple selection transistors STe included in the block BLK. The selection gate line SGo is connected to the gate terminal of each of the multiple selection transistors STo included in the block BLK. The selection gate line SGS is connected to the gate terminal of each of the multiple selection transistors STS included in the block BLK. The word lines WL0 to WL(k-1) are connected to the control gate terminals of each of the memory cell transistors MT0 to MT(k-1) included in the block BLK, respectively.

[0077] A collection of multiple memory cell transistors MT included in the same string unit SU and connected to the same word line WL is called, for example, a "unit set CU". For example, the storage capacity of the unit set CU when each memory cell transistor MT stores 1 bit of data is defined as "1 page of data". 1 page of data is, for example, 16KB (kilobytes). The size of 1 page of data can be appropriately changed according to the design of the memory device 1. In addition, the unit set CU can store more than 2 pages of data according to the number of bits of data stored in each memory cell transistor MT.

[0078] In addition, the memory cell array 10 may also be other circuit structures. The selection transistors STe and STo may not be adjacent, may be arranged on the selection gate line SGS side, or may be arranged in the middle part of the NAND string NS. For example, the number of string units SU included in the block BLK, the memory cell transistors MT included in the NAND string NS, and the number of selection transistors STD, STS, STe, and STo may be designed to be any number. In the first embodiment, the case where the number of memory cell transistors MT included in the NAND string NS is 6 is taken as an example for explanation.

[0079] (2: Circuit Configuration of Row Decoder Module 16)

[0080] Figure 3 1 is a circuit diagram showing an example of the circuit configuration of the row decoder module 16 included in the memory device 1 according to the first embodiment. Figure 3 The figure shows the connection relationship between the driver circuit 15 and the memory cell array 10 and the row decoder module 16, and the detailed circuit structure of one row decoder RD0 included in the row decoder module 16. In addition, the circuit structure of the row decoder RD other than the row decoder RD0 is the same as that of the row decoder RD0 except for the associated block BLK. Figure 3 As shown, each row decoder RD is connected to signal lines CG0 to CG5, SGDD0 to SGDD4, SGSD, SGeD, SGoD, USGD, and USGS connected to the driver circuit 15. In addition, each row decoder RD is connected to word lines WL0 to WL5 of the associated block BLK, and selection gate lines SGD0 to SGD4, SGe, SGo, and SGS.

[0081] The row decoder RD0 includes, for example, transistors TR0 to TR19, transmission gate lines TG and bTG, and a block decoder BD. Transistors TR0 to TR19 are respectively N-type HV transistors. The transmission gate line TG is connected to the gate terminals of transistors TR0 to TR13. The transmission gate line bTG is connected to the gate terminals of transistors TR14 to TR19. The drain terminals of transistors TR0 to TR13 are respectively connected to signal lines SGSD, CG0 to CG5, SGoD, SGeD, and SGDD0 to SGDD4. The source terminals of transistors TR0 to TR13 are respectively connected to the selection gate line SGS of block BLK0, word lines WL0 to WL5, and selection gate lines SGo, SGe, and SGD0 to SGD4. The drain terminal and source terminal of transistor TR14 are respectively connected to the signal line USGS and the selection gate line SGS of block BLK0. The drain terminals of transistors TR15 to TR19 are respectively connected to the signal line USGD. The source terminals of the transistors TR15 to TR19 are connected to the selection gate lines SGD0 to SGD4 of the block BLK0 , respectively.

[0082] The block decoder BD is a circuit that decodes the block address. Based on the decoding result of the block address, the block decoder BD applies a voltage of one of the "H" level and the "L" level to the transmission gate line TG, and applies a voltage of the other of the "H" level and the "L" level to the transmission gate line bTG. Specifically, the block decoder BD of the selected block BLK applies voltages of the "H" level and the "L" level to the transmission gate lines TG and bTG, respectively. The block decoder BD of the unselected block BLK applies voltages of the "L" level and the "H" level to the transmission gate lines TG and bTG, respectively. As a result, the voltages of the signal lines CG0~CG5, SGoD and SGeD are respectively transmitted to the word lines WL0~WL5 and the selection gate lines SGo and SGe of the selected block BLK, the voltages of the signal lines SGDD0~SGDD4 and SGSD are respectively transmitted to the selection gate lines SGD0~SGD4 and SGS of the selected block BLK, and the voltages of the signal lines USGD and USGS are respectively transmitted to the selection gate lines SGD and SGS of the unselected block BLK.

[0083] In addition, the row decoder module 16 may also be composed of other circuits. For example, the number of transistors TR included in the row decoder module 16 can be appropriately changed according to the number of wirings of each block BLK. The signal line CG is shared by multiple blocks BLK, so it can also be called a "global word line". The word line WL is set for each block separately, so it can also be called a "local word line". The signal lines SGDD, SGeD, SGoD and SGSD are shared by multiple blocks BLK, so they can also be called "global transmission gate lines". The selection gate lines SGD, SGe, SGo and SGS are each set for each block separately, so they can also be called "local transmission gate lines".

[0084] (3: Circuit Configuration of Sense Amplifier Module 18 and Data Register 17)

[0085] Figure 4 1 is a circuit diagram showing an example of the circuit configuration of the sense amplifier module 18 and the data register 17 included in the memory device 1 according to the first embodiment. Figure 4 As shown, each sense amplifier unit SAU includes, for example, a bit line connection unit BLHU, a sense amplifier unit SA, buses DBUS and LBUS, latch circuits SDL, ADL, BDL and CDL, and a transistor T0. The data register 17 includes, for example, a plurality of latch circuits XDL0 to XDLm. The latch circuits XDL0 to XDLm are respectively associated with the sense amplifier units SAU0 to SAUm. The latch circuits XDL0 to XDLm are respectively connected to the associated sense amplifier units SAU via the bus DBUS.

[0086] The bit line connection part BLHU is a protection circuit for preventing a high voltage applied to a channel of the NAND string NS during an erase operation from being applied to the sense amplifier part SA. The bit line connection part BLHU may be configured to be able to apply a predetermined voltage to unselected bit lines BL.

[0087] The sense amplifier unit SA is a circuit for determining data based on the voltage of the bit line BL and applying a voltage to the bit line BL. Each sense amplifier unit SA is connected to the associated bit line BL via the bit line connection unit BLHU. When the control signal STB is activated during the read operation, the sense amplifier unit SA determines whether the data read from the selected memory cell transistor MT is "0" data or "1" data based on the voltage of the associated bit line BL.

[0088] The latch circuits SDL, ADL, BDL, and CDL are circuits capable of temporarily storing data, respectively. The latch circuits SDL, ADL, BDL, and CDL and the sense amplifier unit SA are configured to be capable of transmitting and receiving data via the bus LBUS.

[0089] The transistor T0 of each sense amplifier unit SAU controls the signal transmission between the associated buses DBUS and LBUS. One end of the transistor T0 of each sense amplifier unit SAU is connected to the associated bus DBUS. The other end of the transistor T0 of each sense amplifier unit SAU is connected to the associated bus LBUS. A control signal DSW is input to the gate end of the transistor T0 of each sense amplifier unit. The control signal DSW is generated by, for example, the sequencer 14.

[0090] Each latch circuit XDL is a circuit capable of temporarily storing data. Each latch circuit XDL is configured to be able to transmit and receive data with the associated sense amplifier unit SAU via the bus DBUS. Each latch circuit XDL is used to input and output data DAT between the sense amplifier module 18 and the input / output circuit 11. Each latch circuit XDL can also be shared by multiple sense amplifier units SAU.

[0091] (4: Circuit Configuration of Sense Amplifier Unit SAU)

[0092] Figure 5 1 is a circuit diagram showing an example of a circuit configuration of a sense amplifier unit SAU included in the sense amplifier module 18 included in the memory device 1 according to the first embodiment. Figure 5 As shown, the sense amplifier unit SA includes, for example, transistors T1 to T8, a capacitor CP, and nodes ND1, ND2, SEN, and SRC. The bit line connection unit BLHU includes, for example, transistors T9 and T10, and a node BLBIAS. The latch circuit SDL includes, for example, inverters IV0 and IV1, transistors T11 and T12, and nodes SINV and SLAT. Transistor T1 is a P-type LV transistor. Transistors T2 to T8, T11, and T12 are respectively N-type LV transistors. Transistors T9 and T10 are respectively N-type HV transistors.

[0093] The source terminal, drain terminal and gate terminal of transistor T1 are respectively connected to a power supply line, a node ND1 and a node SINV. For example, a power supply voltage VDD is applied to the power supply line. The drain terminal and source terminal of transistor T2 are respectively connected to nodes ND1 and ND2. A control signal BLX is input to the gate terminal of transistor T2. The drain terminal and source terminal of transistor T3 are respectively connected to nodes ND1 and SEN. A control signal HLL is input to the gate terminal of transistor T3. The drain terminal and source terminal of transistor T4 are respectively connected to nodes SEN and ND2. A control signal XXL is input to the gate terminal of transistor T4. The drain terminal of transistor T5 is connected to node ND2. A control signal BLC is input to the gate terminal of transistor T5. The drain terminal, source terminal and gate terminal of transistor T6 are respectively connected to nodes ND2, SRC and SINV. For example, a ground voltage VSS is applied to node SRC. The source terminal and gate terminal of transistor T7 are respectively connected to a ground node and a node SEN. For example, a ground voltage VSS is applied to the ground node. The drain terminal and source terminal of the transistor T8 are connected to the bus LBUS and the drain terminal of the transistor T7, respectively. The control signal STB is input to the gate terminal of the transistor T8. One electrode of the capacitor CP is connected to the node SEN. The clock signal CLK is input to the other electrode of the capacitor CP.

[0094] The drain terminal and source terminal of transistor T9 are respectively connected to the source terminal of transistor T8 and the associated bit line BL. The control signal BLS is input to the gate terminal of transistor T9. The drain terminal and source terminal of transistor T10 are respectively connected to the node BLBIAS and the associated bit line BL. The control signal BIAS is input to the gate terminal of transistor T10.

[0095] One end and the other end of the transistor T11 are connected to the bus LBUS and the node SINV, respectively. A control signal STI is input to the gate end of the transistor T11. One end and the other end of the transistor T12 are connected to the bus LBUS and the node SLAT, respectively. A control signal STL is input to the gate end of the transistor T12. The input node and the output node of the inverter IV0 are connected to the nodes SLAT and SINV, respectively. The input node and the output node of the inverter IV1 are connected to the nodes SINV and SLAT, respectively. The latch circuit SDL stores data at the node SLAT and stores the inverted data of the data stored at the node SLAT at the node SINV. In addition, the respective structures of the latch circuits ADL, BDL and CDL are the same as the latch circuit SDL except that the nodes for storing data, the nodes for storing inverted data, and the control signals respectively input to the transistors T11 and T12 are prepared independently of the latch circuit SDL.

[0096] In addition, the control signals BLX, HLL, XXL, BLC, STB, BLS, BIAS, STI and STL, and the clock signal CLK are generated by, for example, the sequencer 14, respectively. The sense amplifier module 18 may also be composed of other circuits. For example, the number of latch circuits provided in each sense amplifier unit SAU may be appropriately changed. The sense amplifier unit SAU may also have an operation circuit capable of performing simple logical operations. The sense amplifier module 18 can determine (determine) the data stored in the memory cell transistor MT by appropriately performing an operation process using a latch circuit in the read operation of each page.

[0097] Hereinafter, the sense amplifier unit SAU connected to the even bit line BLe is referred to as a “sense amplifier unit SAUe”. The sense amplifier unit SAU connected to the odd bit line BLo is referred to as a “sense amplifier unit SAUo”. In the first embodiment, the sequencer 14 is configured to be able to control the control signal BLC for controlling the sense amplifier unit SAUe and the control signal BLC for controlling the sense amplifier unit SAUo individually. Hereinafter, the control signal BLC for controlling the sense amplifier unit SAUe is referred to as a “control signal BLCe”. The control signal BLC for controlling the sense amplifier unit SAUo is referred to as a “control signal BLCo”.

[0098] <1-1-3> Configuration of memory device 1

[0099] Next, the structure of the memory device 1 of the first embodiment is described. A three-dimensional orthogonal coordinate system is used in the drawings referred to below. The X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction relative to the front side of the substrate serving as a reference. The XZ plane corresponds to a plane parallel to the X direction and the Z direction, respectively. "Up and down" in this specification is defined based on the Z direction, and the direction away from the substrate serving as a reference is assumed to be the positive direction (upward). Regarding the substrate serving as a reference, for example, the substrate arranged at the bottom in the drawings is used. The front side of the substrate corresponds to the side for forming a transistor (CMOS (Complementary Metal Oxide Semiconductor) circuit). The back side of the substrate corresponds to the side opposite to the front side.

[0100] (1: Appearance of the memory device 1)

[0101] Figure 6 1 is a perspective view showing an example of the appearance of the memory device 1 according to the first embodiment. Figure 6As shown, the memory device 1 has a structure in which, for example, a first substrate W1 , a CMOS layer 100 , a memory layer 200 , a second substrate W2 , and a wiring layer 300 are stacked in order from the bottom.

[0102] The CMOS layer 100 includes a CMOS circuit formed using the first substrate W1. The CMOS layer 100 includes, for example, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, a data register 17, and a sense amplifier module 18. The memory layer 200 includes a memory cell array 10 formed using the second substrate W2. The wiring layer 300 includes, for example, a plurality of pads PD. The plurality of pads PD are used to connect the memory device 1 to the memory controller 2 and are exposed on the surface of the memory device 1.

[0103] The first substrate W1 and the second substrate W2 are silicon substrates, respectively. The first substrate W1 has an impurity diffusion region that matches the circuit design of the memory device 1. The memory device 1 has a bonding surface between the CMOS layer 100 and the memory layer 200. The bonding surface corresponds to the boundary portion of the two bonded substrates. In this example, through the bonding process of the first substrate W1 and the second substrate W2, the surface of the CMOS layer 100 on the first substrate W1 is bonded to the surface of the memory layer 200 on the second substrate W2. In addition, the second substrate W2 can also be removed after the first substrate W1 and the second substrate W2 are bonded. In this case, the memory device 1 does not have the second substrate W2.

[0104] (2: Plane layout of the joint surface)

[0105] Figure 7 It is a schematic diagram showing an example of a planar layout of a bonding surface included in the memory device 1 according to the first embodiment. Figure 7 FIG. 2 shows a planar layout of the interface between the CMOS layer 100 and the memory layer 200. Figure 7 As shown, the memory layer 200 includes, for example, a storage region MR, lead-out regions HR1 and HR2, and an input-output region IOR1. The CMOS layer 100 includes, for example, a sense amplifier region SR, a peripheral circuit region PERI, transmission regions XR1 and XR2, and an input-output region IOR2.

[0106] The storage region MR is used to store data and includes a plurality of NAND strings NS. The storage region MR is separated from the lead-out regions HR1 and HR2 in the X direction. The lead-out region HR is a region for connecting the stacked wiring provided in the storage region MR to the transistor provided in the transmission region XR opposite in the Z direction. The input-output region IOR1 is adjacent to the storage region MR and the lead-out regions HR1 and HR2 in the Y direction. The input-output region IOR1 includes a circuit related to the input-output circuit 11.

[0107] The sense amplifier region SR includes a sense amplifier module 18. The peripheral circuit region PERI includes a sequencer 14 and the like. The sense amplifier region SR and the peripheral circuit region PERI are arranged adjacent to each other in the Y direction, and overlap with the storage region MR in the Z direction. The transmission regions XR1 and XR2 include a row decoder module 16. The transmission regions XR1 and XR2 are separated by the sense amplifier region SR and the peripheral circuit region PERI in the X direction, and the transmission regions XR1 and XR2 overlap with the lead-out regions HR1 and HR2 in the Z direction, respectively. The input-output region IOR2 includes an input-output circuit 11 and the like. The input-output region IOR2 overlaps with the input-output region IOR1 in the Z direction.

[0108] The memory layer 200 has a plurality of bonding pads BP connected to the bonding surface. Similarly, the CMOS layer 100 has a plurality of bonding pads BP connected to the bonding surface. The plurality of bonding pads BP disposed on the bonding surface of the memory layer 200 are respectively arranged opposite to the plurality of bonding pads BP disposed on the bonding surface of the CMOS layer 100. The two bonding pads BP disposed opposite to each other in a group between the memory layer 200 and the CMOS layer 100 are bonded by bonding processing ( Figure 7 Thus, the two bonding pads BP arranged opposite to each other are electrically connected.

[0109] In addition, the planar layout of the bonding surface of the memory device 1 may be another layout. For example, at least one lead-out region HR is sufficient. The memory device 1 may also include a plurality of storage regions MR. The configuration of the storage region MR, the lead-out region HR, the sense amplifier region SR, the peripheral circuit region PERI, the transmission region XR, and the input / output region IOR may be appropriately changed. The bonding pad BP may also be referred to as a "bonding metal".

[0110] (3: Planar layout of memory layer 200)

[0111] Figure 8 It is a plan view showing an example of the planar layout of the memory layer 200 included in the memory device 1 according to the first embodiment. Figure 8FIG. 2 shows an area corresponding to four blocks BLK0 to BLK3 included in the memory cell array 10. Figure 8 As shown, the memory cell array 10 includes, for example, a plurality of slits SLT and a plurality of slits SHE.

[0112] Each slit SLT has a portion extending along the X direction, and crosses the lead-out region HR1, the storage region MR, and the lead-out region HR2 along the X direction. A plurality of slits SLT are arranged along the Y direction. Each slit SLT has, for example, a structure with an embedded insulator. Each slit SLT separates adjacent wirings (for example, word lines WL0 to WL5, and selection gate lines SGD, SGe, SGo, and SGS) separated by the slit SLT. In the memory cell array 10, the regions divided by the slits SLT correspond to one block BLK respectively.

[0113] Each slit SHE has a portion extending along the X direction, and crosses the storage region MR along the X direction. A plurality of slits SHE are arranged along the Y direction. In this example, four slits SHE are respectively arranged between two adjacent slits SLT in the Y direction. Each slit SHE has, for example, a structure with an embedded insulator. Each slit SHE separates the adjacent wiring (at least the selection gate line SGD) across the slit SHE. In the memory cell array 10, the areas divided by the slits SLT and SHE correspond to one string unit SU respectively.

[0114] In addition, the planar layout of the memory layer 200 may be other layouts. For example, the number of slits SHE arranged between two adjacent slits SLT may be designed to be any number. The number of string units SU provided in each block BLK may be changed based on the number of slits SHE arranged between two adjacent slits SLT.

[0115] (4: Planar layout of storage area MR)

[0116] Fig. 9 It is a plan view showing an example of a plan layout of a memory region MR of a memory layer 200 included in the memory device 1 according to the first embodiment. Fig. 9 FIG. 2 shows an area including one block BLK (string units SU0 to SU4). Fig. 9 As shown, the memory device 1 includes, for example, a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL in a memory region MR.

[0117] Each storage column MP functions as one NAND string NS. A plurality of storage columns MP are arranged in a staggered manner, for example, in 24 columns in the region between two adjacent slits SLT. For example, one slit SHE is arranged in an overlapping manner in each of the 5th column of storage columns MP, the 10th column of storage columns MP, the 15th column of storage columns MP, and the 20th column of storage columns MP from the top of the paper.

[0118] Each bit line BL has a portion extending along the Y direction. A plurality of bit lines BL are arranged along the X direction. Each bit line BL is configured to overlap at least one storage column MP for each string unit SU. In this example, two bit lines BL are overlapped in one storage column MP. The storage column MP is electrically connected to one bit line BL of the plurality of bit lines BL overlapped via a contact CV. In addition, the contact CV between the storage column MP connected to two different selection gate lines SGD and the bit line BL can be omitted.

[0119] In addition, the planar layout of the memory region MR may be another layout. For example, the number and arrangement of the memory pillars MP and slits SHE disposed between two adjacent slits SLT may be changed appropriately. The number of bit lines BL overlapping each memory pillar MP may be designed to be any number.

[0120] (5: Cross-sectional structure of storage region MR)

[0121] Fig.10 FIG. 1 is an example of a cross-sectional structure of a memory region MR of a memory layer 200 included in the memory device 1 according to the first embodiment, along the Fig. 9 Cross-sectional view of line XX. Fig.10 FIG. 1 shows an example of the structure of the memory cell array 10 formed on the second substrate W2 before being bonded to the first substrate W1, and the coordinate axes based on the second substrate W2 are marked. Fig.10 As shown, the memory region MR includes, for example, conductive layers 20 to 28 , insulating layers 30 to 37 , and contacts V0 and V1 .

[0122] The conductor layer 20 is provided on the second substrate W2. An insulator layer 30 and a conductor layer 21 are provided in sequence on the conductor layer 20. An insulator layer 31 and a conductor layer 22 are provided alternately on the conductor layer 21. An insulator layer 32, a conductor layer 23, an insulator layer 33, a conductor layer 24, an insulator layer 34, a conductor layer 25, an insulator layer 35 and a conductor layer 26 are provided in sequence on the uppermost conductor layer 22. A contact V0 is provided on the conductor layer 26. A conductor layer 27 is provided on the contact V0. A contact V1 is provided on the conductor layer 27. A conductor layer 28 is provided on the contact V1. The contact V0, the conductor layer 27 and the contact V1 are covered by the insulator layer 36. The insulator layer 36 may be composed of a plurality of insulator layers. An insulator layer 37 is provided on the insulator layer 36. Hereinafter, the layers at which the conductor layers 26 and 27 are located are referred to as wiring layers M0 and M1, respectively. The layer at which the conductor layer 28 and the insulating layer 37 are located is referred to as a "bonding layer B1."

[0123] The conductor layers 21, 22, 23, 24 and 25 are formed into, for example, a plate shape extending along the XY plane. The conductor layer 26 is formed into, for example, a line extending along the Y direction. The conductor layers 20, 21, 23, 24 and 25 are used as the source line SL, the selection gate lines SGS, SGo, SGe and SGD, respectively. The plurality of conductor layers 22 are used as word lines WL0 to WL5 in sequence from the bottom. The conductor layer 26 is used as the bit line BL. The contacts V0 and V1 are set in a columnar shape. The conductor layers 26 and 27 are connected via the contact V0. The conductor layer 27 and the conductor layer 28 are connected via the contact V1. The conductor layer 28 corresponds to the bonding pad BP. The conductor layer 28 contains, for example, copper.

[0124] The slit SLT has a plate-shaped portion extending along the XZ plane, dividing the insulating layers 30 to 34 and the conductive layers 21 to 25. Each storage column MP is arranged to extend along the Z direction, penetrating the insulating layers 30 to 34 and the conductive layers 21 to 25. Each storage column MP includes, for example, a core component 40, a semiconductor layer 41, and a laminated film 42. The core component 40 is an insulator arranged to extend along the Z direction. The semiconductor layer 41 covers the core component 40. The lower part of the semiconductor layer 41 is in contact with the conductive layer 20. The laminated film 42 covers the side of the semiconductor layer 41. A contact CV is provided on the semiconductor layer 41. The semiconductor layer 41 and the conductive layer 26 are connected via the contact CV.

[0125] The portion where the storage column MP intersects with the conductor layer 21 functions as a selection transistor STS. The portion where the storage column MP intersects with the conductor layer 22 functions as a storage cell transistor MT. The portion where the storage column MP intersects with the conductor layer 23 functions as a selection transistor STo. The portion where the storage column MP intersects with the conductor layer 24 functions as a selection transistor STe. The portion where the storage column MP intersects with the conductor layer 25 functions as a selection transistor STD. In the storage column MP, the semiconductor layer 41 is used as a channel (current path) for the storage cell transistors MT0 to MT5 and the selection transistors STD, STe, STo, and STS.

[0126] (6: Cross-sectional structure of storage column MP)

[0127] Fig.11 FIG. 1 is an example of a cross-sectional structure of a memory pillar MP included in the memory layer 200 provided in the memory device 1 according to the first embodiment, along the Fig.10 A cross-sectional view taken along line XI-XI. Fig.11 FIG. 2 shows a cross section including the memory pillar MP and the conductive layer 22 and parallel to the front surface of the source line SL. Fig.11 As shown, the stacked film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a blocking insulating film 45. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The blocking insulating film 45 surrounds the side surface of the insulating film 44. The conductive layer 22 surrounds the side surface of the blocking insulating film 45. The tunnel insulating film 43 and the blocking insulating film 45 each include, for example, silicon oxide. The insulating film 44 is used as a charge storage layer of the memory cell transistor MT. The insulating film 44 includes, for example, silicon nitride.

[0128] (7: Planar layout of lead-out area HR1)

[0129] Fig.12 It is a plan view showing an example of the plan layout of the lead-out region HR1 of the memory layer 200 included in the memory device 1 according to the first embodiment. Fig.12 1 shows an area including the lead-out area HR1 and a part of the storage area MR and corresponding to the even-numbered blocks BLKe (BLK0, BLK2, ...) among the plurality of blocks BLK. Fig.12 As shown, in the lead-out region HR1, the select gate line SGS, the word lines WL0 to WL5, and the select gate lines SGo, SGe, and SGD of the even block BLKe each have a stepped portion at their end.

[0130] The terrace portion corresponds to a portion that does not overlap with the upper wiring layer (conductor layer) in the stacked wiring. The structure formed by multiple terrace portions is similar to a step, a terrace, a rimstone, etc. In this example, a step structure with a step difference in the X direction is formed by the end portions of the selection gate line SGS, the word lines WL0 to WL5, the selection gate lines SGo, SGe, and SGD.

[0131] In addition, the memory layer 200 includes a plurality of contacts CC in the lead-out region HR. The contacts CC are conductors for connecting the row decoder module 16 to the stacked wiring. The plurality of contacts CC paired with the even-numbered blocks BLKe are respectively connected to the select gate lines SGS, SGo, SGe, and SGD provided in the lead-out region HR1, and the respective step portions of the word lines WL0 to WL5.

[0132] (8: Cross-sectional structure of lead-out region HR1)

[0133] Fig.13 FIG. 1 is an example of a cross-sectional structure of a lead-out region HR1 of a memory layer 200 included in the memory device 1 according to the first embodiment, taken along Fig.12 A cross-sectional view taken along line XIII-XIII. Fig.13 FIG. 1 shows an example of the structure of the memory cell array 10 formed on the second substrate W2 before being bonded to the first substrate W1, and the coordinate axes based on the second substrate W2 are marked. Fig.13 As shown, the lead region HR1 includes, for example, a plurality of contacts CC, a plurality of contacts V0 and V1 , a plurality of conductor layers 27 to 29 , and insulating layers 35 to 37 .

[0134] In the lead-out region HR1, the ends of the respective conductive layers 21 to 25 are arranged in a step shape and covered by an insulating layer 35. A plurality of contacts CC are arranged on the step portions of the selection gate line SGS, the word lines WL0 to WL5, and the selection gate lines SGo, SGe, and SGD. Each contact CC penetrates the insulating layer 35. A conductive layer 29 is arranged on each of the plurality of contacts CC. The conductive layer 29 is included in the wiring layer M0.

[0135] Each conductor layer 29 is connected to the corresponding conductor layer 28 via the contact point V0, the conductor layer 27, and the contact point V1. Fig.13, contacts V0 and V1 corresponding to the selection gate line SGS among the plurality of contacts V0, and the conductive layers 27 and 28 are shown. The group consisting of the conductive layers 27, 28 and 29 and the contacts CC, V0 and V1 corresponds to the wiring and contacts for connecting any one of the conductive layers 21 to 25 to the row decoder module 16. The conductive layers 22 to 25 are connected to the row decoder module 16 through the groups consisting of the paired conductive layers 27, 28 and 29 and the contacts CC, V0 and V1, similarly to the conductive layer 21, but the relevant illustrations are omitted.

[0136] In addition, in this example, the layout and cross-sectional structure of the portion where the lead-out region HR2 overlaps with the odd-numbered blocks BLKo (BLK1, BLK3, ...) of the plurality of blocks BLK are the same as the layout obtained by reversing the layout and cross-sectional structure of the portion where the lead-out region HR1 overlaps with the even-numbered blocks BLKe in the X direction. However, this is not limited to this, and the planar layout of the lead-out region HR can be appropriately changed. The lead-out region HR can also be configured to divide the storage region MR. The lead-out region HR only needs to include at least a plurality of contacts CC and wiring that connect the row decoder module 16 to the stacked wiring.

[0137] (9: Cross-sectional structure of the memory device 1)

[0138] Fig.14 It is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the first embodiment. Fig.14 The cross section of the memory device 1 including the storage region MR and the lead-out region HR1 is shown, and the coordinate axes based on the first substrate W1 are indicated. Fig.14 2 shows a configuration corresponding to the transistor T9 in the sense amplifier region SR and a configuration corresponding to the transistor TR1 in the transmission region XR2. Fig.14 As shown, the memory device 1 has a corresponding memory layer 200. Fig.10 The structure of the storage area MR shown, and Fig.13 The structures of the lead-out region HR1 shown are structures obtained by inverting the structures upside down.

[0139] The first substrate W1 includes a plurality of well regions (not shown). Transistors and the like are formed in each of the plurality of well regions. The plurality of well regions are separated from each other by, for example, STI (Shallow Trench Isolation).

[0140] The CMOS layer 100 includes, for example, insulator layers 50 and 51, conductive layers GC and 52 to 55, and contacts CS and C0 to C3. The insulator layer 50 is disposed on the first substrate W1. The insulator layer 50 covers the circuit disposed on the first substrate W1. The insulator layer 50 may be composed of a plurality of insulator layers. In addition, the insulator layer 50 includes wiring layers D0, D1, and D2 in order from the bottom. The insulator layer 51 is disposed on the insulator layer 50. The insulator layer 51 is in contact with the insulator layer 35. The boundary portion between the insulator layers 51 and 35 corresponds to the bonding surface between the first substrate W1 and the second substrate W2. The insulator layer 51 is, for example, a silicon oxide film. Hereinafter, the layer at the height where the insulator layer 51 is located is referred to as the "bonding layer B2".

[0141] The conductor layer GC is provided on the gate insulating film provided on the first substrate W1. The conductor layer GC in the sense amplifier region SR is used, for example, as the gate electrode of the transistor T9. The conductor layer GC in the transmission region XR2 is used, for example, as the gate electrode of the transistor TR1. A contact C0 is provided on each conductor layer GC. The two contacts CS included in the sense amplifier region SR are connected, for example, to two impurity diffusion regions (not shown) corresponding to the source terminal and the drain terminal of the transistor T9. Similarly, the two contacts CS included in the transmission region XR1 are connected, for example, to two impurity diffusion regions (not shown) corresponding to the source terminal and the drain terminal of the transistor TR1.

[0142] A conductor layer 52 is provided on each of the contacts CS and C0. The conductor layer 52 is included in the wiring layer D0. A conductor layer 53 is provided on the conductor layer 52 across the contact C1. The conductor layer 53 is included in the wiring layer D1. A conductor layer 54 is provided on the conductor layer 53 across the contact C2. The conductor layer 54 is included in the wiring layer D2. A conductor layer 55 is provided on the conductor layer 54 across the contact C3. The conductor layer 55 is included in the bonding layer B2 and corresponds to the bonding pad BP for bonding the first substrate W1 and the second substrate W2. The conductor layer 55 contains, for example, copper. On the conductor layer 55, a conductor layer 28 is provided in contact therewith, and the conductor layer 28 is a conductor layer arranged opposite to the conductor layer 55 between the CMOS layer 100 and the memory layer 200. Thus, the conductor layer 26 (bit line BL) is electrically connected to the transistor T9 provided on the first substrate W1. Similarly, the conductor layer 29 is electrically connected to the transistor TR provided on the first substrate W1 via the conductor layers 52 to 55 and the contacts CS and C1 to C3.

[0143] An insulator layer 70 is provided on the second substrate W2. The insulator layer 70 is included in the wiring layer 300. The wiring layer 300 includes a conductor layer connected to a circuit included in any one of the CMOS layer 100 and the memory layer 200. The conductor layer is connected to, for example, a pad PD (not shown) provided to penetrate the insulator layer 70.

[0144] <1-1-4> Characteristics of transistors

[0145] Next, an example of the characteristics of each transistor included in the NAND string NS of the memory device 1 according to the first embodiment will be described.

[0146] (1: Threshold voltage distribution and data allocation of memory cell transistor MT)

[0147] Fig.15 1 is a schematic diagram showing an example of the threshold voltage distribution and data allocation of the memory cell transistor MT in the memory device 1 of the first embodiment. The vertical axis "NMTs" represents the number of memory cell transistors MT. The horizontal axis "Vth" represents the threshold voltage of the memory cell transistor MT. Fig.15 As shown, when each memory cell transistor MT stores 3 bits of data, the threshold voltage distribution of the plurality of memory cell transistors MT forms 8 states. In this specification, these 8 states are referred to as "S0" state, "S1" state, "S2" state, "S3" state, "S4" state, "S5" state, "S6" state, and "S7" state in the order of threshold voltage from low to high. Different 3-bit data are assigned to the "S0" to "S7" states. The following is an example of assigning data to the 8 states.

[0148] "S0" state: "111 (upper bit / middle bit / lower bit)" data

[0149] "S1" state: "110" data

[0150] "S2" state: "100" data

[0151] "S3" state: "000" data

[0152] "S4" state: "010" data

[0153] "S5" state: "011" data

[0154] "S6" state: "001" data

[0155] "S7" status: "101" data.

[0156] The read voltage and the verification voltage are set between adjacent states. Specifically, the read voltage R1 is set between the "S0" and "S1" states. The read voltage R2 is set between the "S1" and "S2" states. The read voltage R3 is set between the "S2" and "S3" states. The read voltage R4 is set between the "S3" and "S4" states. The read voltage R5 is set between the "S4" and "S5" states. The read voltage R6 is set between the "S5" and "S6" states. The read voltage R7 is set between the "S6" and "S7" states. The verification voltages VS1 to VS7 are set in pairs with the "S1" to "S7" states, respectively. The verification voltages VS1 to VS7 can be the same as the read voltages R1 to R7, respectively, or can be different from them. In addition, the read path voltage VREAD is set to a voltage higher than the state "S7" with the highest threshold voltage. The memory cell transistor MT to which the read path voltage VREAD is applied is turned on regardless of the data stored therein.

[0157] In the application Fig.15 In the case of the data allocation shown, 1 page of data (lower page data) consisting of lower bits is determined by a read operation using read voltages R1 and R5. 1 page of data (middle page data) consisting of middle bits is determined by a read operation using read voltages R2, R4, and R6. 1 page of data (upper page data) consisting of upper bits is determined by a read operation using read voltages R3 and R7. In the page read operation using multiple read voltages, the operation processing is appropriately performed in the sense amplifier unit SAU. In addition, 1 bit, 2 bits, or 4 bits or more of data can also be stored in each storage cell transistor MT, and other data allocations can also be applied.

[0158] (2: Threshold voltage distribution of selection transistors STe and STo)

[0159] Fig.16 1 is a schematic diagram showing an example of the threshold voltage distribution of the selection transistors STe and STo in the memory device 1 of the first embodiment. The vertical axis "NMTs" represents the number of the selection transistors STe and STo. The horizontal axis "Vth" represents the threshold voltage of the selection transistors STe and STo. Fig.16 As shown, the threshold voltage distribution of the plurality of selection transistors STe and STo forms two states. In this specification, these two states are referred to as an "LS" state and an "HS" state, respectively.

[0160] The "LS" state is set in the same manner as the "S0" state corresponding to the erase state, for example. The "HS" state is set to a voltage higher than that of the "LS" state. The "HS" state may also be the same as any of the "S1" to "S7" states. The settings of the "HS" state and the "LS" state may be appropriately changed according to the threshold voltage distribution of the memory cell transistor MT. The selection transistors STe and STo to which the read path voltage VREAD is applied are turned on regardless of the set state.

[0161] The read voltage VMID is set between the "LS" state and the "HS" state. As the read voltage VMID, the same voltage as any one of the read voltages R1 to R7 may be used according to the setting of the "LS" state and the "HS" state. A verification voltage paired with the "HS" state may also be set for the memory device 1. The "LS" state and the "HS" state are formed, for example, by writing flag data to the selection transistors STe and STo. The writing of the flag data may be performed after erasing the data of the block BLK, or may be performed at the time of shipment.

[0162] Fig.17 1 is a schematic diagram showing an example of threshold voltage distribution of the selection transistors STe and STo in the memory device 1 according to the first embodiment. Fig.17 FIG. 4 shows a portion of transistors of a NAND string NSe connected to an even bit line BLe, and a portion of transistors of a NAND string NSo connected to an odd bit line BLo. Fig.17 As shown, the threshold voltage of the selection transistor STe of the NAND string NSe is set to the "LS" state. The threshold voltage of the selection transistor STo of the NAND string NSe is set to the "HS" state. The threshold voltage of the selection transistor STe of the NAND string NSo is set to the "HS" state. The threshold voltage of the selection transistor STo of the NAND string NSo is set to the "LS" state.

[0163] Furthermore, in the first embodiment, the threshold voltage of the selection transistor STe of each NAND string NS is set to one of the "LS" state and the "HS" state, and the threshold voltage of the selection transistor STo is set to the other of the "LS" state and the "HS" state. Moreover, as long as the threshold voltage of the selection transistor STe of the NAND string NSe is set to a state different from the threshold voltage of the selection transistor STe of the NAND string NSo, the threshold voltage of the selection transistor STo of the NAND string NSe is set to a state different from the threshold voltage of the selection transistor STo of the NAND string NSo. The operation of the first embodiment described below can be appropriately changed according to the states to which the selection transistors STe and STo of the NAND strings NSe and NSo belong.

[0164] <1-2>Action

[0165] Next, the operation of the memory device 1 according to the first embodiment will be described.

[0166] The memory device 1 can perform an odd bit line read operation, an even bit line read operation, and an odd bit line read operation. The odd bit line read operation is a read operation that selects both the even bit line group and the odd bit line group. The even bit line read operation is a read operation that selects the even bit line group. The odd bit line read operation is a read operation that selects the odd bit line group.

[0167] For example, the data size read in the parity bit line read operation is twice the page size read in the even bit line read operation, and is twice the page size read in the odd bit line read operation. The parity bit line read operation is, for example, a 16KB page read operation (16KB page read). The even bit line read operation and the odd bit line read operation are, for example, 8KB page read operations (8KB page read). The memory device 1 may also be configured to perform the even bit line read operation when the 8KB page read is in the first mode, and to perform the odd bit line read operation when the 8KB page read is in the second mode.

[0168] Hereinafter, the selected word line WL is referred to as "word line WLsel". The unselected word line WL is referred to as "word line WLusel". The selected selection gate line SGD is referred to as "selection gate line SGDsel". The unselected selection gate line SGD is referred to as "selection gate line SGDusel". The memory cell transistor MT connected to the word line WLsel is referred to as "memory cell transistor MTsel". The memory cell transistor MT connected to the word line WLusel is referred to as "memory cell transistor MTusel". Hereinafter, the parity bit line read action, the even bit line read action, and the odd bit line read action performed by the memory device 1 are described by taking the case of reading the lower page data as an example.

[0169] <1-2-1> Parity bit line read operation

[0170] Fig.18 1 is a timing chart showing an example of the parity bit line read operation of the memory device 1 according to the first embodiment. Fig.18 The figure shows the voltage changes of the select gate lines SGDsel, SGDusel, SGe and SGo, the word lines WLsel and WLusel, the select gate line SGS, the control signals BLCe and BLCo, the bit lines BLe and BLo, and the control signal STB in the parity bit line read operation for the following bit page. Fig.18 As shown, in the parity bit line read operation targeting the lower bit page data, the sequencer 14 sequentially executes the processing at times t0 to t5.

[0171] When the parity bit line read operation starts, the voltage applied to each wiring is the ground voltage VSS, and each control signal is at the "L" level.

[0172] At time t0, the sequencer 14 applies voltage VSG to the select gate lines SGDsel, SGDusel and SGS, applies read path voltage VREAD to the select gate lines SGe and SGo and word line WLusel, and applies read voltage R1 to word line WLsel. Thereafter, the sequencer 14 applies ground voltage VSS to the select gate line SGDusel.

[0173] At time t1, the sequencer 14 sets the control signals BLCe and BLCo to "H" level. Then, the sense amplifier unit SAUe charges the bit line BLe, and the voltage of the bit line BLe rises to the voltage VBL. Similarly, the sense amplifier unit SAUo charges the bit line BLo, and the voltage of the bit line BLo rises to the voltage VBL. Thereafter, the memory cell transistor MTsel to which the read voltage R1 is applied becomes turned on or off according to the data to be stored.

[0174] Although not shown in the figure, between time t1 and time t2, the sequencer 14 charges the node SEN of each sense amplifier unit SAU by making the control signal HLL at the "H" level for a predetermined period. Thereafter, the sequencer 14 makes the control signal XXL at the "H" level. In this way, the voltage of the node SEN of each sense amplifier unit SAU is discharged or maintained according to the state of the memory cell transistor MTsel paired with the sense amplifier unit SAU.

[0175] At time t2, the sequencer 14 makes the control signal STB "H" level for a predetermined time. That is, at time t2, the sequencer 14 makes the control signal STB effective. In this way, the transistor T7 of each sense amplifier unit SAU becomes turned on or off according to the voltage of the node SEN of the sense amplifier unit SAU. As a result, the read result using the read voltage R1 is reflected on the bus LBUS, and the read result using the read voltage R1 is stored in a predetermined latch circuit.

[0176] The operations at time t3 and t4 are the same as the operations described for time t1 and t2, respectively, after the voltage applied to the word line WLsel is changed from the read voltage R1 to the read voltage R5. In short, at time t3, the sequencer 14 applies the read voltage R5 to the word line WLsel. Then, at time t4, the sequencer 14 validates the control signal STB. As a result, the read result using the read voltage R5 is reflected on the bus LBUS, and the read result using the read voltage R5 is stored in a predetermined latch circuit.

[0177] At time t5, the sequencer 14 converts the voltage applied to each wiring and the voltage of each control signal to the state at the start of the parity bit line read operation. Then, the sequencer 14 determines the lower bit data based on the read result using the read voltage R1 and the read result using the read voltage R5. Thereafter, the memory device 1 sends the determined lower bit data group as the lower page data to the memory controller 2, and ends the parity bit line read of the lower page data.

[0178] Fig.19 This is a schematic diagram showing an example of a method of selecting the bit line BL in the parity bit line read operation of the memory device 1 according to the first embodiment. Fig.19 Shows the execution Fig.18 During the parity bit line read operation shown in FIG. 1 , the operation states of some elements of the sense amplifier units SAUe and SAUo, and the NAND strings NSe and NSo are shown. Fig.19 As shown, in the parity bit line read operation, by setting the control signals BLCe and BLCo to "H" level, the transistors T5 of the sense amplifier units SAUe and SAUo are turned on.

[0179] In addition, during the period when the control signals BLCe and BLCo are respectively at the "H" level, by setting the control signal BLS to the "H" level, the transistors T9 of the sense amplifier units SAUe and SAUo are turned on. In the NAND string NSe, the selection transistors STe and STo to which the read path voltage VREAD is applied are turned on. In the NAND string NSo, the selection transistors STe and STo to which the read path voltage VREAD is applied are turned on.

[0180] As a result, the sense amplifier unit SAUe and the NAND string NSe are connected via the even bit line BLe (BLe: conductive). Similarly, the sense amplifier unit SAUo and the NAND string NSo are connected via the even bit line BLe (BLo: conductive). Therefore, the memory device 1 can Fig.18 In the odd-even bit line read operation shown, the memory cell transistor MTsel connected to the even bit line BLe and the memory cell transistor MTsel connected to the odd bit line BLo are selected, respectively, to read lower bit data.

[0181] Furthermore, the memory device 1 can also perform the parity bit line read operation for the middle page data and the upper page data in the same manner as for the lower page data by changing the read voltage or the number of reads.

[0182] <1-2-2> Even-numbered bit line read operation

[0183] Fig. 20 1 is a timing chart showing an example of an even-numbered bit line read operation of the memory device 1 according to the first embodiment. Fig. 20 The figure shows the voltage changes of the select gate lines SGDsel, SGDusel, SGe and SGo, the word lines WLsel and WLusel, the select gate line SGS, the control signals BLCe and BLCo, the bit lines BLe and BLo, and the control signal STB in the even bit line read operation for the lower bit page. Fig. 20 As shown, in the even-numbered bit line read operation targeting the lower-bit page data, the sequencer 14 sequentially executes the processing at times t0 to t5.

[0184] Comparison of processing at times t0 to t5 in the even bit line read operation Fig.18 For the described odd and even bit line read action, the voltage applied to the selection gate lines SGe and SGo, and the control method of the control signals BLCe and BLCo are different. Specifically, at time t0 of the even bit line read action, the sequencer 14 applies the voltage VMID to the selection gate line SGe, and applies the read path voltage VREAD to the selection gate line SGo. At time t1, the sequencer 14 makes the control signals BLCe and BLCo become "H" level and "L" level, respectively. Through the action at time t1, the sense amplifier unit SAUe charges the bit line BLe to the voltage VBL. In addition, the bit line BLo becomes a floating state during the period from time t1 to time t5. The other actions of the even bit line read action are the same as the odd and even bit line read action.

[0185] Fig.21 This is a schematic diagram showing an example of a method of selecting the bit line BL in the even-numbered bit line read operation of the memory device 1 according to the first embodiment. Fig.21 Shows the execution Fig. 20 During the even bit line read operation shown in FIG. 1 , the operating states of some elements of the sense amplifier units SAUe and SAUo, and the NAND strings NSe and NSo are shown. Fig.21 As shown, in the even bit line read operation, the control signal BLCe is set to "H" level and the control signal BLCo is set to "L" level. In this case, the transistor T5 of the sense amplifier unit SAUe is turned on and the transistor T5 of the sense amplifier unit SAUo is turned off.

[0186] In addition, during the period when the control signals BLCe and BLCo are at the "H" level and the "L" level, respectively, by setting the control signal BLS to the "H" level, the transistors T9 of the sense amplifier units SAUe and SAUo are turned on. In the NAND string NSe, the selection transistor STe to which the voltage VMID is applied and the selection transistor STo to which the read path voltage VREAD is applied are turned on. In the NAND string NSo, the selection transistor STe to which the voltage VMID is applied is turned off.

[0187] As a result, the sense amplifier unit SAUe and the NAND string NSe are connected via the even bit line BLe (BLe: conductive). On the other hand, the odd bit line BLo connecting the sense amplifier unit SAUo and the NAND string NSo becomes floating (BLo: floating) as the transistor T5 of the sense amplifier unit SAUo and the selection transistor STe of the NAND string NSo are turned off. Therefore, the memory device 1 can Fig. 20 In the even bit line read operation shown, the odd bit line BLo is placed in a floating state, and lower bit data is read from the memory cell transistor MTsel connected to the even bit line BLe.

[0188] Furthermore, the memory device 1 can also perform the even-numbered bit line read operation for the middle page data and the upper page data in the same manner as for the lower page data by changing the read voltage or the number of reads.

[0189] <1-2-3> Odd-numbered bit line read operation

[0190] Fig. 22 This is a timing chart showing an example of the odd-numbered bit line read operation of the memory device 1 according to the first embodiment. Fig. 22 The figure shows the voltage changes of the select gate lines SGDsel, SGDusel, SGe and SGo, the word lines WLsel and WLusel, the select gate line SGS, the control signals BLCe and BLCo, the bit lines BLe and BLo, and the control signal STB in the odd bit line read operation for the following bit page. Fig. 22 As shown, in the odd-numbered bit line read operation targeting the lower-bit page data, the sequencer 14 sequentially executes the processing at times t0 to t5.

[0191] Comparison of processing at times t0 to t5 in odd-numbered bit line readout operation Fig.18For the described odd and even bit line readout action, the voltage applied to the selection gate lines SGe and SGo, and the control method of the control signals BLCe and BLCo are different. Specifically, at time t0 of the odd bit line readout action, the sequencer 14 applies the voltage VMID to the selection gate line SGo and applies the readout path voltage VREAD to the selection gate line SGe. At time t1, the sequencer 14 makes the control signals BLCe and BLCo become "L" level and "H" level, respectively. Through the action at time t1, the sense amplifier unit SAUo charges the bit line BLo to the voltage VBL. In addition, the bit line BLe becomes a floating state during the period from time t1 to time t5. The other actions of the odd bit line readout action are the same as the odd and even bit line readout action.

[0192] Fig.23 This is a schematic diagram showing an example of a method of selecting the bit line BL in the odd-numbered bit line read operation of the memory device 1 according to the first embodiment. Fig.23 Shows the execution Fig. 22 During the odd bit line read operation shown in FIG. 1 , the operating states of some elements of the sense amplifier units SAUe and SAUo, and the NAND strings NSe and NSo are shown. Fig.23 As shown, in the odd bit line read operation, the control signal BLCo is set to "H" level and the control signal BLCe is set to "L" level. In this case, the transistor T5 of the sense amplifier unit SAUo is turned on and the transistor T5 of the sense amplifier unit SAUe is turned off.

[0193] In addition, during the period when the control signals BLCe and BLCo are at the "L" level and the "H" level, respectively, by setting the control signal BLS to the "H" level, the transistors T9 of the sense amplifier units SAUe and SAUo are turned on. In the NAND string NSo, the selection transistor STe to which the read path voltage VREAD is applied and the selection transistor STo to which the voltage VMID is applied are turned on. In the NAND string NSe, the selection transistor STo to which the voltage VMID is applied is turned off.

[0194] As a result, the sense amplifier unit SAUo and the NAND string NSo are connected via the odd bit line BLo (BLo: conductive). On the other hand, the even bit line BLe connecting the sense amplifier unit SAUe and the NAND string NSe becomes floating (BLe: floating) as the transistor T5 of the sense amplifier unit SAUe and the selection transistor STo of the NAND string NSe are both turned off. Therefore, the memory device 1 can Fig. 22In the odd bit line read operation shown, the even bit line BLe is placed in a floating state, and lower bit data is read from the memory cell transistor MTsel connected to the odd bit line BLo.

[0195] Furthermore, the memory device 1 can also perform odd-numbered bit line read operations for the middle page data and the upper page data in the same manner as for the lower page data by changing the read voltage or the number of reads.

[0196] <1-3> Effects of the First Embodiment

[0197] According to the memory device of the first embodiment described above, the operation time of the read operation can be shortened. Next, the detailed effects of the first embodiment will be described.

[0198] In flash memories in which memory cells are stacked in a three-dimensional shape, the demand for increasing the speed of the read operation, that is, shortening the operation time, is increasing with the development of the times. In addition, there are known memory devices that support not only the usual 16KB page read but also 8KB page read (so-called fast read) with an increased read operation speed. In the 8KB page read, for example, by setting every other bit line BL to a floating state, the apparent capacitance of the bit line BL is halved. As a result, the charging time of the bit line BL can be shortened, and the time of the read operation can be shortened.

[0199] As a method of making the bit line BL float, it is possible to consider increasing the number of selection gate lines SGD in the block BLK and controlling the selection transistor STD connected to the bit line BL that is desired to be floated to be disconnected. However, in this method, as the number of selection gate lines SGD in the block BLK increases, the resistance value of the selection gate line SGD increases. As a result, the speed of the read operation and the like may decrease. That is, in order to shorten the operation time, it is preferable to control the bit line BL to float without increasing the number of selection gate lines SGD as much as possible.

[0200] Therefore, in the memory device 1 of the first embodiment, the NAND string NS has a selection transistor STe into which flag data paired with the selection of the even bit line BLe is written, and a selection transistor STo into which flag data paired with the selection of the odd bit line BLo is written. These flag data are pre-written to the selection transistors STe and STo, respectively, before the read operation is performed. For example, the selection transistors STe and STo of the NAND string NSe connected to the even bit line BLe are written to the "LS" state and the "HS" state, respectively, and the selection transistors STe and STo of the NAND string NSo connected to the odd bit line BLo are written to the "HS" state and the "LS" state, respectively.

[0201] Furthermore, when reading a 16KB page, a read path voltage VREAD is applied to the selection transistors STe and STo, respectively, so that both the selection transistor written in the "LS" state and the selection transistor written in the "HS" state are turned on. When reading an 8KB page, a voltage VMID is applied to one of the selection transistors STe and STo, depending on which of the even bit lines BLe and the odd bit lines BLo are selected. As a result, the 8KB memory cell transistors MT are electrically connected to the bit lines BL, and the remaining 8KB memory cell transistors MT are not electrically connected to the bit lines BL.

[0202] In this way, the memory device 1 of the first embodiment can control any one of the selection transistors STe and STo to be in an off state. Furthermore, the memory device 1 can control the bit line BL connected to the selection transistor STe or STo in an off state to be in a floating state by independently controlling the control signals BLSa and BLSb to appropriately turn the transistor T9 into an off state.

[0203] As described above, the memory device 1 of the first embodiment can halve the apparent capacitance of the bit line BL by controlling every other bit line BL to be in a floating state. As a result, the memory device 1 of the first embodiment can shorten the precharge time of the bit line BL in the read operation, the waiting time for the voltage of the bit line BL to stabilize, etc., and can increase the speed of the read operation. Therefore, the memory device 1 of the first embodiment can shorten the operation time of the read operation. In addition, the memory device 1 can halve the total current flowing through the memory cell transistor MT when performing an 8KB page read by controlling any one of the selection transistors STe and STo to be in an off state, and can reduce the read current.

[0204] In addition, in the first embodiment, the case where the control signal BLC is independently controlled in the sense amplifier units SAUe and SAUo is described, but the present invention is not limited thereto. The operation described in the first embodiment can also be achieved by independently controlling the control signal BLS instead of the control signal BLC. In this case, the memory device 1 can also perform the same operation as the first embodiment and obtain the same effect as the first embodiment.

[0205] <2> Second Embodiment

[0206] The memory device 1A of the second embodiment has a structure in which a memory cell array 10 is stacked and the concept described in the first embodiment is combined. The details of the second embodiment will be described below, mainly focusing on the differences from the first embodiment.

[0207] <2-1>Composition

[0208] <2-1-1> Overall Configuration of Memory Device 1A

[0209] Fig.24 1 is a block diagram showing an example of the overall configuration of a memory device 1A according to the second embodiment. Fig.24 As shown, the memory device 1A includes, for example, a memory cell array 10A, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15A, a row decoder module 16A, a data register 17, and a sense amplifier module 18A. The input / output circuit 11, the logic controller 12, the register circuit 13, the sequencer 14, and the data register 17 in the memory device 1A are respectively the same as those in the first embodiment.

[0210] The memory cell array 10A has sub-arrays 101a and 101b. The sub-arrays 101a and 101b have structures similar to the memory cell array 10 described in the first embodiment. The sub-array 101a includes a plurality of sub-blocks SBLKa0 to SBLKan ("n" is an integer greater than 1). The sub-array 101b includes a plurality of sub-blocks SBLKb0 to SBLKbn. The sub-blocks SBLKa0 to SBLKa are respectively combined with sub-blocks SBLKb0 to SBLKbn. In the memory cell array 10A, the combined group of sub-blocks SBLKa and SBLKb constitute one block BLK. The sub-blocks SBLKa0 to SBLKan are connected to the bit lines BLa0 to BLam ("m" is an integer greater than 1). The sub-blocks SBLKb0 to SBLKbn are connected to the bit lines BLb0 to BLbm.

[0211] The driver circuit 15A has a configuration in which the driver circuit 15 of the first embodiment is modified in accordance with the memory cell array 10A. The driver circuit 15A generates voltages to be applied to various wirings provided in the sub-array 101a and the sub-array 101b.

[0212] The row decoder module 16A has a configuration in which the row decoder module 16 of the first embodiment is modified in accordance with the memory cell array 10A. The row decoder module 16A transmits a voltage generated by the driver circuit 15A to various wirings provided in the sub-arrays 101a and 101b.

[0213] The sense amplifier module 18A has a structure that is modified from the sense amplifier module 18 of the first embodiment according to the memory cell array 10A. Each sense amplifier unit SAU of the sense amplifier module 18A is connected to a set of bit lines BLa and BLb. Specifically, the sense amplifier units SAU0 to SAUm are connected to the bit lines BLa0 to BLam, respectively, and further connected to the bit lines BLb0 to BLbm, respectively.

[0214] <2-1-2> Circuit Configuration of Memory Device 1A

[0215] Next, a circuit configuration of a memory device 1A according to the second embodiment will be described.

[0216] (1: Circuit Configuration of Memory Cell Array 10A)

[0217] Fig.25 It is a circuit diagram showing an example of the circuit configuration of a memory cell array 10A included in a memory device 1A according to the second embodiment. Fig.25 FIG. 2 shows one block BLK among a plurality of blocks BLK included in the memory cell array 10A. Fig.25 As shown, in the block BLK of the second embodiment, for example, sub-blocks SBLKa and SBLKb are respectively connected to the selection gate line SGS, word lines WL0 to WL(k-1) (k is an integer greater than 1), and source line SL. Sub-block SBLKa is connected to bit lines BLa0 to BLam, selection gate lines SGDa0 to SGDa4, SGae, and SGao. Sub-block SBLKb is connected to bit lines BLb0 to BLbm, selection gate lines SGDb0 to SGDb4, SGbe, and SGbo.

[0218] In the block BLK of the second embodiment, the selection gate lines SGDa0 to SGDa4, the selection gate lines SGDb0 to SGDb4, the selection gate lines SGae, SGao, SGbe and SGbo, the selection gate line SGS, and the word lines WL0 to WL(k-1) are provided for each block BLK. The bit lines BLa0 to BLam are shared by a plurality of sub-blocks SBLKa. The bit lines BLb0 to BLbm are shared by a plurality of sub-blocks SBLKb. The source line SL is shared by a plurality of blocks BLK.

[0219] Sub-block SBLKa, for example, includes 5 string units SUa0~SUa4. Each string unit SUa includes multiple NAND strings NSa0~NSam. NAND strings NSa0~NSam are associated with bit lines BLa0~BLam, respectively. NAND string NSa is connected between the associated bit line BLa and the source line SL. Each NAND string NSa, for example, includes k storage cell transistors MTa0~MTa(k-1), and selection transistors STDa, STae, STao and STSa. In each NAND string NSa, selection transistors STDa, STae and STao, storage cell transistors MTa(k-1)~MTa0, and selection transistor STSa are connected in series in sequence from the bit line BLa toward the source line SL. Selection transistors STDa and STSa are respectively used to select the string unit SUa. Selection transistors STae and STao are respectively used to select a group of bit lines BLa.

[0220] Sub-block SBLKb, for example, includes 5 string units SUb0~SUb4. Each string unit SUb includes multiple NAND strings NSb0~NSbm. NAND strings NSb0~NSbm are associated with bit lines BLb0~BLbm, respectively. NAND string NSb is connected between the associated bit line BLb and the source line SL. Each NAND string NSb, for example, includes k memory cell transistors MTb0~MTb(k-1), and selection transistors STDb, STbe, STbo and STSb. In each NAND string NSb, selection transistors STDb, STbe and STbo, memory cell transistors MTb(k-1)~MTb0, and selection transistor STSb are connected in series from the bit line BLb toward the source line SL. Selection transistors STDb and STSb are respectively used to select string unit SUb. Selection transistors STbe and STbo are respectively used to select bit line BLb.

[0221] In the second embodiment, a case where an even bit line group including even bit lines BLae (BLa0, BLa2, BLa4, ...) and an odd bit line group including odd bit lines BLao (BLa1, BLa3, BLa5, ...) can be individually selected from among a plurality of bit lines BLa0 to BLam connected to a sub-block SBLKa is described as an example. In this case, the memory device 1A is configured to be able to individually select an even bit line group including even bit lines BLbe (BLb0, BLb2, BLb4, ...) and an odd bit line group including odd bit lines BLbo (BLb1, BLb3, BLb5, ...) from among a plurality of bit lines BLb0 to BLbm connected to a sub-block SBLKb.

[0222] The selection gate lines SGDa0 to SGDa4 are associated with the string units SUa0 to SUa4, respectively. Each selection gate line SGDa is connected to the gate end of each of the multiple selection transistors STDa included in the associated string unit SUa. The selection gate line SGae is connected to the gate end of each of the multiple selection transistors STae included in the sub-block SBLKa. The selection gate line SGao is connected to the gate end of each of the multiple selection transistors STao included in the sub-block SBLKa.

[0223] The selection gate lines SGDb0 to SGDb4 are associated with the string units SUb0 to SUb4, respectively. Each selection gate line SGDb is connected to the gate terminals of the plurality of selection transistors STDb included in the associated string unit SUb. The selection gate line SGbe is connected to the gate terminals of the plurality of selection transistors STbe included in the sub-block SBLKb. The selection gate line SGbo is connected to the gate terminals of the plurality of selection transistors STbo included in the sub-block SBLKb.

[0224] The selection gate line SGS of the second embodiment is connected to the gate terminals of each of the plurality of selection transistors STSa and STSb included in the block BLK. The word line WL(K) of the second embodiment (“K” is, for example, an integer greater than 0 and less than (k-1)) is connected to the control gate terminals of each of the plurality of memory cell transistors MTa(K) and MTb(K) included in the block BLK.

[0225] As described above, in the memory cell array 10A, the word line WL is shared between the grouped sub-blocks SBLKa and SBLKb. A selection gate line SGD is provided for each string unit SU. A selection gate line SGo and SGe are provided for each sub-block SBLK. The selection gate line SGS can be shared within the block BLK, or can be provided for each sub-block SBLK, or can be provided for each string unit SU.

[0226] In addition, the memory cell array 10A may also be other circuit configurations. For example, the number of string cells SUa and SUb included in the block BLK, the number of memory cell transistors MTa and the number of selection transistors STDa, STae, STao and STSa included in the NAND string NSa, and the number of memory cell transistors MTb and the number of selection transistors STDb, STbe, STbo and STSb included in the NAND string NSb may be designed to be any number. Below, the case where the number of memory cell transistors MTa included in the NAND string NSa is 6 and the number of memory cell transistors MTb included in the NAND string NSb is 6 is described as an example.

[0227] (2: Circuit Configuration of Row Decoder Module 16A)

[0228] Fig.26 It is a circuit diagram showing an example of the circuit configuration of a row decoder module 16A included in the memory device 1A according to the second embodiment. Fig.26 FIG. 1 shows the connection relationship between the driver circuit 15A and the memory cell array 10A and the row decoder module 16A, and the detailed circuit structure of one row decoder RD. Fig.25 As shown, the row decoder RD of the second embodiment is connected to the signal lines CG0 to CG5, SGDDa0 to SGDDa4, SGDDb0 to SGDDb4, SGaeD, SGaoD, SGbeD, SGboD, SGSD, USGD, and USGS connected to the driver circuit 15A, respectively. In addition, the row decoder RD of the second embodiment is connected to the word lines WL0 to WL5 of the associated block BLK, and the selection gate lines SGDa0 to SGDa4, SGDb0 to SGDb4, SGae, SGao, SGbe, SGbo, and SGS.

[0229] The row decoder RD of the second embodiment includes, for example, transistors TR0 to TR6, TR7a to TR13a, TR7b to TR13b, TR14, TR15a to TR19a, TR15b to TR19b, transmission gate lines TG and bTG, and a block decoder BD. The transistors TR0 to TR6 and TR14, and the block decoder BD are respectively the same as the row decoder RD of the first embodiment. The transistors TR7a to TR13a, TR15a to TR19a, TR7b to TR13b, and TR15b to TR19b are respectively N-type HV transistors. The transmission gate line TG of the second embodiment is connected to the gate terminals of the transistors TR7a to TR13a and TR7b to TR13b. The transmission gate line bTG of the second embodiment is connected to the gate terminals of the transistors TR15a to TR19a and TR15b to TR19b.

[0230] The drain terminals of transistors TR7a and TR8a are connected to signal lines SGaoD and SGaeD, respectively. The source terminals of transistors TR7a and TR8a are connected to selection gate lines SGao and SGae of the associated blocks BLK, respectively. The drain terminals of transistors TR9a to TR13a are connected to signal lines SGDDa0 to SGDDa4, respectively. The source terminals of transistors TR9a to TR13a are connected to selection gate lines SGDa0 to SGDa4 of the associated blocks BLK, respectively. The drain terminals of transistors TR15a to TR19a are connected to signal line USGD. The source terminals of transistors TR15a to TR19a are connected to selection gate lines SGDa0 to SGDa4 of the associated blocks BLK, respectively.

[0231] The drain terminals of transistors TR7b and TR8b are connected to signal lines SGboD and SGbeD, respectively. The source terminals of transistors TR7b and TR8b are connected to selection gate lines SGbo and SGbe, respectively, of the associated blocks BLK. The drain terminals of transistors TR9b to TR13b are connected to signal lines SGDDb0 to SGDDb4, respectively. The source terminals of transistors TR9b to TR13b are connected to selection gate lines SGDb0 to SGDb4, respectively, of the associated blocks BLK. The drain terminals of transistors TR15b to TR19b are connected to signal line USGD. The source terminals of transistors TR15b to TR19b are connected to selection gate lines SGDb0 to SGDb4, respectively, of the associated blocks BLK.

[0232] In addition, the row decoder module 16A may have other circuit configurations. The number of transistors TR included in the row decoder module 16A may be changed as appropriate according to the number of wirings provided on each block BLK.

[0233] (3: Circuit Configuration of Sense Amplifier Unit SAU)

[0234] Fig. 27 This is a circuit diagram showing an example of the circuit configuration of the sense amplifier unit SAU included in the sense amplifier module 18A included in the memory device 1A of the second embodiment. The sense amplifier unit SAU of the second embodiment is different from the sense amplifier unit SAU of the first embodiment in the circuit configuration of the bit line connection unit BLHU. The bit line connection unit BLHU of the second embodiment includes, for example, transistors T9a, T10a, T9b, and T10b. The group consisting of transistors T9a and T10a and the group consisting of transistors T9b and T10b are similar to the group consisting of transistors T9 and T10 of the first embodiment, and are configured to be individually controllable.

[0235] Specifically, the drain terminals of transistors T9a and T9b are connected to the source terminals of transistor T5. The source terminals of transistors T9a and T9b are connected to bit lines BLa and BLb, respectively. The drain terminals of transistors T10a and T10b are connected to node BLBIAS. The source terminals of transistors T10a and T10b are connected to bit lines BLa and BLb, respectively. Control signals BLSa and BLSb are input to the gate terminals of transistors T9a and T9b, respectively. Control signals BIASa and BIASb are input to the gate terminals of transistors T10a and T10b, respectively.

[0236] The other structures of the sense amplifier unit SAU of the second embodiment are the same as those of the sense amplifier unit SAU of the first embodiment. Hereinafter, the sense amplifier unit SAU connected to the group of even bit lines BLae and BLbe is referred to as "sense amplifier unit SAUe". The sense amplifier unit SAU connected to the group of odd bit lines BLao and BLbo is referred to as "sense amplifier unit SAUo". In the second embodiment, the sequencer 14 is configured to be able to independently control the control signals BLSa, BLSb, BIASa and BIASb for controlling the sense amplifier unit SAUe and the control signals BLSa, BLSb, BIASa and BIASb for controlling the sense amplifier unit SAUo. Hereinafter, the control signals BLSa, BLSb, BIASa and BIASb for controlling the sense amplifier unit SAUe are referred to as control signals BLSae, BLSbe, BIASae and BIASbe, respectively. The control signals BLSa, BLSb, BIASa, and BIASb for controlling the sense amplifier unit SAUo are referred to as control signals BLSao, BLSbo, BIASao, and BIASbo, respectively.

[0237] <2-1-3> Configuration of memory device 1A

[0238] Next, the structure of the memory device 1A according to the second embodiment will be described.

[0239] (1: Appearance of memory device 1A)

[0240] Fig.28 1 is a perspective view showing an example of the appearance of a memory device 1A according to the second embodiment. Fig.28 As shown, the memory device 1A has a structure in which, for example, a first substrate W1, a CMOS layer 100, a memory layer 200a, a memory layer 200b, a third substrate W3, and a wiring layer 300 are stacked in order from the bottom.

[0241] The CMOS layer 100 of the second embodiment includes, for example, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15A, a row decoder module 16A, a data register 17, and a sense amplifier module 18A. The memory layer 200a includes a sub-array 101a formed using a second substrate W2. In this example, the second substrate W2 is removed after the first substrate W1 and the second substrate W2 are bonded. The memory layer 200b includes a sub-array 101b formed using a third substrate W3.

[0242] The third substrate W3 is a silicon substrate. The memory device 1A has bonding surfaces between the CMOS layer 100 and the memory layer 200a, and between the memory layers 200a and 200b. In this example, the surface of the CMOS layer 100 on the first substrate W1 is bonded to the surface of the memory layer 200a on the second substrate W2 by the bonding process of the first substrate W1 and the second substrate W2. In addition, by the bonding process of the substrate (bonding substrate) formed by bonding the first substrate W1 and the second substrate W2 and the third substrate W3, the surface of the memory layer 200a on the bonding substrate is bonded to the surface of the memory layer 200b on the third substrate W3. In addition, the third substrate W3 can also be removed after the bonding substrate and the third substrate W3 are bonded. In this case, the memory device 1A does not have the third substrate W3.

[0243] (2: Cross-sectional structure of memory device 1A)

[0244] Next, the cross-sectional structure of the memory device 1A of the second embodiment is described. In the memory device 1A, the cross-sectional structure of the CMOS layer 100 is the same as that of the first embodiment. The memory layers 200a and 200b, for example, each include the same structure as the memory layer 200 of the first embodiment. Hereinafter, regarding the same structural elements as the memory layer 200, if they are included in the memory layer 200a, "a" is added to the end of the reference symbol, and if they are included in the memory layer 200b, "b" is added to the end of the reference symbol.

[0245] Fig.29 It is a cross-sectional view showing an example of a cross-sectional structure of a memory device 1A according to the second embodiment. Fig.29 FIG. 1 shows a cross section of the memory device 1A including the memory region MR and the lead-out region HR1, and indicates coordinate axes based on the first substrate W1. Fig.29 As shown, the memory layer 200a has, for example, a configuration in which the second substrate W2 is omitted and insulator layers 80 and 81, a conductor layer 82, and a contact V2 are added compared to the memory layer 200 of the first embodiment. The memory layer 200b has, for example, a configuration in which the second substrate W2 is replaced by a third substrate W3 compared to the memory layer 200 of the first embodiment. As with the memory layer 200 of the first embodiment, an insulator layer 70 (wiring layer 300) is provided on the third substrate W3.

[0246] In the memory layer 200a, similarly to the memory layer 200 of the first embodiment, the conductive layer 26a (bit line BLa) is connected to the sense amplifier unit SA (transistor T9a) provided on the first substrate W1 via the conductive layers 27a, 28a, 52 to 55, and contacts V0a, V1a, C1 to C3, and CS. Similarly, the conductive layer 22a (for example, the word line WL1) is connected to the row decoder RD (for example, the transistor TR2) on the first substrate W1 via the conductive layers 27a to 29a and 52 to 55, and contacts V0a, V1a, C1 to C3, and CS. The other conductive layers 21a to 25a are also connected to the row decoder RD on the first substrate W1 similarly to the conductive layer 22a.

[0247] In the memory layer 200a, the insulator layer 80 is arranged on the conductor layer 20a. The insulator layer 81 is arranged on the insulator layer 80. The insulator layer 81 is in contact with the bonding surface of the memory layers 200a and 200b. Hereinafter, the layer at the height of the insulator layer 81 is referred to as the "bonding layer B3". The conductor layer 82 is included in the bonding layer B3 and corresponds to the bonding pad BP. The contact V2 is included in the lead-out region HR1. The contact V2 is arranged to pass through the step portion of the stacked wiring of the memory layer 200a, and connects the paired conductor layer 29a and the conductor layer 82. The side of the contact V2 is covered by a spacer SP. The spacer SP is composed of an insulating component to insulate the contact V2 from the stacked wiring of the memory layer 200a.

[0248] In the memory layer 200b, the insulating layer 37b is in contact with the bonding surface of the memory layers 200a and 200b. Each conductive layer 28b is included in the bonding layer B1b. Each conductive layer 28b is arranged opposite to and bonded to the conductive layer 82 of the memory layer 200a. As a result, the conductive layer 22b (for example, the word line WL1) is electrically connected to the paired conductive layer 82 in the memory layer 200a via the conductive layers 27b to 29b, and the contacts V0b and V1b. As a result, the conductive layers 22a and 22b paired with the same word line WL1 are electrically connected. The conductive layers 21b to 25b are also electrically connected to the paired conductive layers 21a to 25a, respectively, similarly to the conductive layer 22b.

[0249] In the memory layer 200b, the conductive layer 26b (bit line BLb) is connected to the sense amplifier unit SA (transistor T9b) provided on the first substrate W1 via the conductive layers 27a, 27b, 28a, 28b, 29a, 29b, 52 to 55, and contacts V0a, V0b, V1a, V1b, C1 to C3, and CS, but the relevant diagram is omitted. The other structures of the memory device 1A of the second embodiment are the same as those of the memory device 1 of the first embodiment.

[0250] <2-1-4> Characteristics of transistors

[0251] Fig.30 1 is a schematic diagram showing an example of threshold voltage distribution of the selection transistors STae, STbe, STao, and STbo in the memory device 1A according to the second embodiment. Fig.30 Shown are a portion of transistors of the NAND string NSae connected to the even bit line BLae and a portion of transistors of the NAND string NSao connected to the bit line BLao in the sub-block SBLKa, as well as a portion of transistors of the NAND string NSbe connected to the even bit line BLbe in the sub-block SBLKb and a portion of transistors of the NAND string NSbo connected to the odd bit line BLbo.

[0252] like Fig.30As shown, the threshold voltage of the selection transistor STae of the NAND string NSae is set to the "LS" state. The threshold voltage of the selection transistor STao of the NAND string NSae is set to the "HS" state. The threshold voltage of the selection transistor STae of the NAND string NSao is set to the "HS" state. The threshold voltage of the selection transistor STao of the NAND string NSao is set to the "LS" state. The threshold voltage of the selection transistor STbe of the NAND string NSbe is set to the "HS" state. The threshold voltage of the selection transistor STbo of the NAND string NSbe is set to the "LS" state. The threshold voltage of the selection transistor STbe of the NAND string NSbo is set to the "LS" state. The threshold voltage of the selection transistor STbo of the NAND string NSbo is set to the "HS" state.

[0253] Furthermore, in the second embodiment, the threshold voltage of the selection transistor STae of each NAND string NSae of the sub-block SBLKa is set to one of the "LS" state and the "HS" state, and the threshold voltage of the selection transistor STao is set to the other of the "LS" state and the "HS" state. Furthermore, as long as the threshold voltage of the selection transistor STae of the NAND string NSao is set to a state different from the threshold voltage of the selection transistor STae of the NAND string NSae, the threshold voltage of the selection transistor STao of the NAND string NSao may be set to a state different from the threshold voltage of the selection transistor STao of the NAND string NSae.

[0254] Similarly, in the second embodiment, the threshold voltage of the selection transistor STbe of each NAND string NSbe of the sub-block SBLKb is set to one of the "LS" state and the "HS" state, and the threshold voltage of the selection transistor STbo is set to the other of the "LS" state and the "HS" state. Furthermore, as long as the threshold voltage of the selection transistor STbe of the NAND string NSbo is set to a state different from the threshold voltage of the selection transistor STbe of the NAND string NSbe, the threshold voltage of the selection transistor STbo of the NAND string NSbo is set to a state different from the threshold voltage of the selection transistor STbo of the NAND string NSbe.

[0255] In addition, in the second embodiment, the threshold voltage of the selection transistor STae of each NAND string NSae is set to a state different from the threshold voltage of the selection transistor STbe of the NAND string NSbe, and the threshold voltage of the selection transistor STao of the NAND string NSae is set to a state different from the threshold voltage of the selection transistor STbo of the NAND string NSbe. The threshold voltage of the selection transistor STae of each NAND string NSao is set to a state different from the threshold voltage of the selection transistor STbe of the NAND string NSbo, and the threshold voltage of the selection transistor STao of the NAND string NSao is set to a state different from the threshold voltage of the selection transistor STbo of the NAND string NSbo.

[0256] That is, the threshold voltages of the selection transistors ST configured in the same layer in the NAND string NSae and the NAND string NSao are set to different levels from each other. The threshold voltages of the selection transistors ST configured in the same layer in the NAND string NSbe and the NAND string NSbo are set to different levels from each other. The threshold voltages of the selection transistors ST configured in the same layer in the NAND string NSae and the NAND string NSbe are set to different levels from each other. The threshold voltages of the selection transistors ST configured in the same layer in the NAND string NSao and the NAND string NSbo are set to different levels from each other.

[0257] In addition, "the same layer" means that when the sub-blocks SBLK to which the selection transistors ST as the comparison object belong are different, the relative position of the selection transistors ST in the sub-block SBLKa and the relative position of the selection transistors ST in the sub-block SBLKb are at the same height. The operation of the second embodiment described below can be appropriately changed according to the states to which the selection transistors STae and STao of the NAND strings NSae and NSao belong, and the states to which the selection transistors STbe and STbo of the NAND strings NSbe and NSbo belong.

[0258] <2-2>Action

[0259] Next, the operation of the memory device 1A according to the second embodiment will be described. The memory device 1A can perform a first read operation, a second read operation, a masked read operation, and a write operation. The first read operation, the second read operation, the masked read operation, and the write operation will be described in detail below.

[0260] <2-2-1> First read operation

[0261] The first read operation is a read operation in which an even bit line group (even bit line BLae) is selected in the sub-block SBLKa and an odd bit line group (odd bit line BLbo) is selected in the sub-block SBLKb. In the first read operation, the memory device 1A performs an operation similar to the even bit line read operation with the sub-block SBLKa as the object, and performs an operation similar to the odd bit line read operation with the sub-block SBLKb as the object. In addition, in the first read operation, one string unit SU is selected in each of the paired sub-blocks SBLKa and SBLKb. That is, in the first read operation, one selection gate line SGDa and one selection gate line SGDb are selected.

[0262] Fig.31 This is a timing chart showing an example of the first read operation of the memory device 1A according to the second embodiment. Fig.31 The figure shows the voltage changes of the selection gate lines SGDsel and SGDusel, the selection gate lines SGae, SGbe, SGao and SGbo, the word lines WLsel and WLusel, the selection gate line SGS, the control signals BLC, BLSae, BLSbe, BLSao, BLSbo, BIASae, BIASbe, BIASao and BIASbo, the bit lines BLae, BLbe, BLao and BLbo, and the control signal STB in the first read operation targeting the following bit page. Fig.31 As shown, in the first read operation targeting the lower page data, the sequencer 14 sequentially executes the processing at times t0 to t5.

[0263] When the first read operation starts, the voltage applied to each wiring is the ground voltage VSS, and each control signal is at the “L” level.

[0264] At time t0, the sequencer 14 applies voltage VSG to the selection gate lines SGDsel, SGDusel, and SGS, respectively, applies read path voltage VREAD to the selection gate lines SGao and SGbo, and the word line WLusel, respectively, applies voltage VMID to the selection gate lines SGae and SGbe, and applies read voltage R1 to the word line WLsel. Thereafter, the sequencer 14 applies ground voltage VSS to the selection gate line SGDusel.

[0265] At time t1, the sequencer 14 sets the control signals BLC, BLSae, and BLSbo to "H" level. Then, the sense amplifier unit SAUe charges the bit line BLae, causing the voltage of the bit line BLae to rise to the voltage VBL. Similarly, the sense amplifier unit SAUo charges the bit line BLbo, causing the voltage of the bit line BLbo to rise to the voltage VBL. Thereafter, the memory cell transistor MTsel to which the read voltage R1 is applied becomes turned on or off based on the data to be stored. In addition, the bit lines BLao and BLbe become floating states.

[0266] At time t2, the sequencer 14 validates the control signal STB. Thus, the transistor T7 of each sense amplifier unit SAU becomes conductive or disconnected according to the voltage of the node SEN of the sense amplifier unit SAU. As a result, the read result using the read voltage R1 is reflected on the bus LBUS, and the read result using the read voltage R1 is stored in a predetermined latch circuit.

[0267] The operations at time t3 and t4 are the same as the operations described for time t1 and t2, respectively, after the voltage applied to the word line WLsel is changed from the read voltage R1 to the read voltage R5. In short, at time t3, the sequencer 14 applies the read voltage R5 to the word line WLsel. Then, at time t4, the sequencer 14 validates the control signal STB. As a result, the read result using the read voltage R5 is reflected on the bus LBUS, and the read result using the read voltage R5 is stored in a predetermined latch circuit.

[0268] At time t5, the sequencer 14 converts the voltage applied to each wiring and the voltage of each control signal to the state at the start of the first read operation. Then, the sequencer 14 determines the lower bit data based on the read result using the read voltage R1 and the read result using the read voltage R5. Thereafter, the memory device 1 sends the determined lower bit data group as the lower page data to the memory controller 2, and ends the first read of the lower page data.

[0269] Fig.32 This is a schematic diagram showing an example of a method of selecting the bit line BL in the first read operation of the memory device 1A according to the second embodiment. Fig.32 Shows the execution Fig.31 In the first read operation shown in FIG. 1 , the operating states of the sensing amplifier unit SAUe and some elements of the NAND strings NSae and NSbe are shown. Fig.32 As shown, in the first read operation, by setting the control signal BLC to the “H” level, the transistor T5 of the sense amplifier unit SAUe is turned on.

[0270] In addition, by setting the control signal BLSae to the "H" level, the transistor T9a of the sense amplifier unit SAUe becomes conductive. By setting the control signals BLSbe, BIASae, and BIASbe to the "L" level, respectively, the transistors T9b, T10a, and T10b of the sense amplifier unit SAUe become disconnected. In the NAND string NSae, the selection transistor STae to which the voltage VMID is applied, and the selection transistor STao to which the read path voltage VREAD is applied become conductive. In the NAND string NSbe, the selection transistor STbe to which the voltage VMID is applied becomes disconnected.

[0271] As a result, the sense amplifier unit SAUe and the NAND string NSae are connected via the even bit line BLae (BLae: conductive). On the other hand, the even bit line BLbe connecting the sense amplifier unit SAUe and the NAND string NSbe becomes floating (BLbe: floating) as the transistors T9b and T10b of the sense amplifier unit SAUe and the selection transistor STbe of the NAND string NSbe are turned off.

[0272] Fig.33 This is a schematic diagram showing an example of a method of selecting the bit line BL in the first read operation of the memory device 1A according to the second embodiment. Fig.33 Shows the execution Fig.31 In the first read operation shown in FIG. 1 , the operating states of the sensing amplifier unit SAUo and some elements of the NAND strings NSao and NSbo are shown. Fig.33 As shown, in the first read operation, by setting the control signal BLC to the “H” level, the transistor T5 of the sense amplifier unit SAUo is turned on.

[0273] In addition, by setting the control signal BLSbo to the "H" level, the transistor T9b of the sense amplifier unit SAUo becomes conductive. By setting the control signals BLSao, BIASao, and BIASbo to the "L" level, respectively, the transistors T9a, T10a, and T10b of the sense amplifier unit SAUo become disconnected. In the NAND string NSbo, the selection transistor STbe to which the voltage VMID is applied, and the selection transistor STbo to which the read path voltage VREAD is applied become conductive, respectively. In the NAND string NSao, the selection transistor STae to which the voltage VMID is applied becomes disconnected.

[0274] As a result, the sense amplifier unit SAUo and the NAND string NSbo are connected via the odd bit line BLbo (BLbo: conductive). On the other hand, the odd bit line BLao connecting the sense amplifier unit SAUo and the NAND string NSao becomes floating (BLao: floating) as the transistors T9a and T10a of the sense amplifier unit SAUo and the selection transistor STae of the NAND string NSao are turned off.

[0275] As described above, the memory device 1A Fig.31 In the first read operation shown, the odd bit line BLao of the sub-block SBLKa can be made to float, and the lower bit data can be read from the memory cell transistor MTsel connected to the even bit line BLae of the sub-block SBLKa. In addition, the memory device 1A can make the even bit line BLbe of the sub-block SBLKb float, and read the lower bit data from the memory cell transistor MTsel connected to the odd bit line BLbo of the sub-block SBLKb. That is, in the first read operation, the memory device 1A can simultaneously perform a read operation targeting the NAND string NSae of the sub-block SBLKa and a read operation targeting the NAND string NSbo of the sub-block SBLKb. Therefore, the memory device 1A can read (m+1) bits of data at one time through the first read operation.

[0276] Furthermore, the memory device 1A can also perform the first read operation on the middle page data and the upper page data in the same manner as on the lower page data by changing the read voltage or the number of reads.

[0277] <2-2-2> Second reading operation

[0278] The second read operation is a read operation in which an odd bit line group (odd bit line BLao) is selected in the sub-block SBLKa and an even bit line group (even bit line BLbe) is selected in the sub-block SBLKb. In the second read operation, the memory device 1A performs an operation similar to the odd bit line read operation with the sub-block SBLKa as the target, and performs an operation similar to the even bit line read operation with the sub-block SBLKb as the target. In addition, in the second read operation, similarly to the first read operation, one string unit SU is selected in each of the paired sub-blocks SBLKa and SBLKb.

[0279] Fig.34 This is a timing chart showing an example of the second read operation of the memory device 1A according to the second embodiment. Fig.3410 shows voltage changes of the selection gate lines SGDsel, SGDusel, SGae, SGbe, SGao and SGbo, the word lines WLsel and WLusel, the selection gate line SGS, the control signals BLC, BLSae, BLSbe, BLSao, BLSbo, BIASae, BIASbe, BIASao and BIASbo, the bit lines BLae, BLbe, BLao and BLbo, and the control signal STB in the second read operation targeting the lower bit page. Fig.34 As shown, in the second read operation targeting the lower page data, the sequencer 14 sequentially executes the processing at times t0 to t5.

[0280] Comparative use of processing at times t0 to t5 in the second readout operation Fig.31 For the first read operation described, the voltage applied to the selection gate lines SGae, SGao, SGbe and SGbo, and the control method of the control signals BLSae, BLSao, BLSbe and BLSbo are different. Specifically, at time t0 of the second read operation, the sequencer 14 applies the voltage VMID to the selection gate lines SGao and SGbo, respectively, and applies the read path voltage VREAD to the selection gate lines SGae and SGbe, respectively. At time t1, the sequencer 14 makes the control signals BLSao and BLSbe become "H" level, respectively, and makes the control signals BLSae, BLSbo, BIASae, BIASbe, BIASao and BIASbo become "L" level, respectively. Through the action at time t1, the sense amplifier unit SAUo charges the bit line BLao to the voltage VBL, and the sense amplifier unit SAUe charges the bit line BLbe to the voltage VBL. In addition, the bit lines BLae and BLbo become floating during the period from time t1 to time t5. The other actions of the second read operation are the same as those of the first read operation.

[0281] The method of selecting the bit line BL in the second read operation is the same as that in the first read operation, except that the operation related to the sub-block SBLKa and the operation related to the sub-block SBLKb are switched. Fig.34In the second read operation shown, the even bit line BLae can be made floating for the sub-block SBLKa, and the lower bit data can be read from the memory cell transistor MTsel connected to the odd bit line BLao. In addition, the memory device 1A can make the odd bit line BLbo floating for the sub-block SBLKb, and read the lower bit data from the memory cell transistor MTsel connected to the even bit line BLbe. That is, in the second read operation, the memory device 1A can simultaneously perform a read operation targeting the NAND string NSao of the sub-block SBLKa and a read operation targeting the NAND string NSbe of the sub-block SBLKb. Therefore, the memory device 1A can read (m+1) bits of data at one time through the second read operation.

[0282] Furthermore, the memory device 1A can also perform the second read operation on the middle page data and the upper page data in the same manner as on the lower page data by changing the read voltage or the number of reads.

[0283] <2-2-3> Shield read operation

[0284] The shielded read operation is a read operation performed in a state where a shield voltage is applied to the unselected bit lines BL, and can be performed by selecting the bit lines BL in the same manner as the first read operation or the second read operation. Next, a case where the bit lines BL are selected in the shielded read operation for the lower bit page in the same manner as the first read operation will be described.

[0285] Fig.35 This is a timing chart showing an example of the mask read operation of the memory device 1A according to the second embodiment. Fig.35 The figure shows the voltage changes of the selection gate lines SGDsel and SGDusel, the selection gate lines SGae, SGbe, SGao and SGbo, the word lines WLsel and WLusel, the selection gate line SGS, the control signals BLC, BLSae, BLSbe, BLSao, BLSbo, BIASae, BIASbe, BIASao and BIASbo, the bit lines BLae, BLbe, BLao and BLbo, and the control signal STB in the shielded read operation for the following bit page. Fig.35 As shown, in the mask read operation targeting the lower page data, the sequencer 14 sequentially executes the processing at times t0 to t5.

[0286] Comparison of processing at times t0 to t5 in the mask read operation Fig.31For the first read operation described, the voltages of the selection gate lines SGae, SGao, SGbe and SGbo, the control method of the group consisting of the control signals BLSae, BLSao, BLSbe, BLSbo, BIASae, BIASbe, BIASao and BIASbo, and the voltages of the bit lines BLao and BLbe are different. Specifically, at time t0 of the shielded read operation, the sequencer 14 applies the read path voltage VREAD to the selection gate lines SGae, SGao, SGbe and SGbo, respectively. At time t1 of the shielded read operation, the sequencer 14 makes the control signals BLSae, BLSbo, BIASao and BIASbo become "H" levels, respectively, and makes the control signals BLSao, BLSbe, BIASae and BIASbe become "L" levels, respectively. Through the operation at time t1, the bit lines BLae and BLbo are charged to the voltage VBL, respectively. In addition, based on the voltage of the node BLBIAS, the shielding voltage VSHIELD is applied to the bit lines BLae and BLbo, respectively. The shield voltage VSHIELD corresponds to, for example, the potential of the source line SL. The other operations of the shield read operation are the same as those of the first read operation.

[0287] Fig.36 This is a schematic diagram showing an example of a method of selecting the bit line BL in the mask read operation of the memory device 1A according to the second embodiment. Fig.36 Shows the execution Fig.35 During the shielded read operation shown in FIG. 1 , the operating states of the sense amplifier unit SAUe and some of the components of the NAND strings NSae and NSbe are shown. Fig.36 As shown, the shield readout action in this example is compared with the use of Fig.32 The first read operation described above is different in that the control signal BIASbe is at the "H" level. As a result, the transistor T10b of the sense amplifier unit SAUe is turned on. As a result, the voltage of the node BLBIAS (shielding voltage VSHIELD) is applied to the even bit line BLbe (BLbe: shield) via the transistor T10b. In the sense amplifier unit SAUo, the voltage of the node BLBIAS (shielding voltage VSHIELD) is applied to the odd bit line BLao (not shown) via the transistor T10a.

[0288] Thus, the memory device 1A Fig.35 In the shielded read operation shown, the odd bit lines BLao can be shielded for the sub-block SBLKa, and the lower bit data can be read from the memory cell transistor MTsel connected to the even bit lines BLae. In addition, the memory device 1A can shield the even bit lines BLbe for the sub-block SBLKb, and the lower bit data can be read from the memory cell transistor MTsel connected to the odd bit lines BLbo.

[0289] In addition, in the shielded read operation for the lower bit page, when the bit line BL is selected in the same manner as in the second read operation, the operation is the same as in the shielded read operation in which the operation related to the sub-block SBLKa and the operation related to the sub-block SBLKb are switched. The memory device 1A can also perform the shielded read operation for the middle bit page data and the upper bit page data in the same manner as for the lower bit page data by changing the read voltage or the number of reads, respectively. In addition, in the shielded read operation, the gate lines SGae, SGao, SGbe, and SGbo can also be controlled in the same manner as in the first read operation and the second read operation.

[0290] <2-2-4> Writing operation

[0291] Next, the writing operation of the memory device 1A will be described.

[0292] (1: Overview of writing operation)

[0293] Fig.37 This is a timing chart schematically showing a write operation of the memory device 1A according to the second embodiment. Fig.37 FIG. 2 shows the voltage change of the word line WLsel during the write operation. Fig.37 As shown, the memory device 1A performs a loop process (program loop process) including a programming operation and a verification operation during a writing operation. Fig.37 3 cycles (the first cycle, the second cycle, and the third cycle) are shown in FIG. 1 , and the number of cycles can be changed according to the setting of the writing operation and the like.

[0294] The programming action is an action that can increase the threshold voltage of the memory cell transistor MTsel. The sequencer 14 sets each memory cell transistor MTsel as a programming object or prohibits programming, and performs the programming action. The memory cell transistor MTsel that is the programming object is a memory cell transistor MTsel that has not reached the threshold voltage corresponding to the state (hereinafter referred to as the "target state") of the data to be written. The memory cell transistor MTsel that is prohibited from programming is a memory cell transistor MTsel that has reached the threshold voltage of the target state.

[0295] In the programming operation, the sequencer 14 applies a programming voltage VPGM to the word line WLsel. VPGM is a high voltage that can increase the threshold voltage of the memory cell transistor MTsel. In this way, in the memory cell transistor MTsel that is the programming object, electrons are injected into the charge storage layer based on the voltage difference between the word line WLsel and the channel, and the threshold voltage increases. In the memory cell transistor MTsel that is prohibited from programming, since the selection transistor STD is turned off, the channel potential is increased, and the increase in the threshold voltage is suppressed.

[0296] The verification action is a read action to confirm whether the threshold voltage of the memory cell transistor MTsel has reached the threshold voltage of the target state. In the verification action, a read action using the verification voltage Vvfy is performed. In this example, the verification voltage Vvfy is any one of the verification voltages VS1, VS2, VS3, VS4, VS5, VS6, and VS7. In the verification action, when the threshold voltage of the memory cell transistor MTsel exceeds the verification voltage Vvfy, it is determined as "verification is successful." And when the threshold voltage of the memory cell transistor MTsel is below the verification voltage Vvfy, it is determined as "verification fails."

[0297] After the verification operation is completed, the sequencer 14 sets the memory cell transistor MTsel whose threshold voltage has reached the target state to program-inhibit based on the verification read result in the current loop processing. Then, the sequencer 14 starts the next loop processing. The value of the programming voltage VPGM increases as the loop processing is repeated. Fig.31 The voltage difference corresponding to the increase of VPGM in each cycle process is denoted as DVPGM. In each cycle process, a read operation using a plurality of verification voltages may be performed.

[0298] In addition, the memory device 1A can perform a detection operation after each loop process. In the detection operation, the number of successfully verified memory cell transistors MTsel is counted for each state. Moreover, the sequencer 14 determines whether the writing is completed for each state. For example, the writing is determined to be completed based on the fact that the number of memory cell transistors MTsel that failed the verification is lower than the specified number. In the repetition of the loop process, the sequencer 14 ends the writing operation once it detects that the writing of each of the "S1" to "S7" states has been completed.

[0299] (2: Programming action)

[0300] Fig.38 This is a timing chart showing an example of a programming operation of a writing operation of the memory device 1A according to the second embodiment. Fig.38 The example shows a case where a programming operation of the sense amplifier unit SAUe targeting the NAND string NSae and a programming operation of the sense amplifier unit SAUo targeting the NAND string NSbo are performed simultaneously. Fig.381 shows voltage changes of the select gate lines SGDsel, SGDusel, SGae, SGao, SGbe and SGbo, the word lines WLsel and WLusel, the select gate line SGS, the control signals BLC, BLSae, BLSbe, BLSao, BLSbo, BIASae, BIASbe, BIASao and BIASbo, and the bit lines BLae, BLbe, BLao and BLbo during the programming operation. Fig.38 As shown, in the programming operation, the sequencer 14 sequentially executes the processing at times t0 to t5.

[0301] When the programming operation starts, the voltage applied to each wiring is the ground voltage VSS, and each control signal is at the "L" level.

[0302] At time t0, the sequencer 14 applies voltage VSGDH to the selection gate lines SGDsel and SGDusel, respectively, so that the control signals BLC, BLSae, BLSbo, BIASao, and BIASbe become "H" level. Then, the voltage Vinhibit is applied to the bit lines BLao and BLbe, respectively. In addition, the ground voltage VSS is applied to the bit line BLae that is the object of programming, and the voltage Vinhibit is applied to the bit line BLae that is prohibited from programming. Similarly, the ground voltage VSS is applied to the bit line BLbo that is the object of programming, and the voltage Vinhibit is applied to the bit line BLbo that is prohibited from programming. Each selection transistor STD becomes conductive as the voltage VSGDH is applied.

[0303] At time t1, the sequencer 14 applies the ground voltage VSS to the selection gate lines SGDsel and SGDusel, respectively. Then, each selection transistor STD of the selected block BLK is turned off. At this time, the channel voltage of the NAND string NS connected to the bit line BL as the programming object is, for example, the ground voltage VSS. The channel voltage of the NAND string NS connected to the bit line BL that is prohibited from programming maintains the state after rising based on the voltage Vinhibit.

[0304] At time t2, the sequencer 14 applies voltage VSGD to the selection gate line SGDsel and applies write path voltage VPASS to the word lines WLsel and WLusel, respectively. Voltage VSGD is higher than the ground voltage VSS and lower than voltage VSGDH. Write path voltage VPASS is higher than voltage VSGDH. At this time, the selection transistor STD connected to the bit line BL to be programmed becomes conductive. The selection transistor STD connected to the bit line BL that is prohibited from programming becomes disconnected, and the channel voltage of the floating NAND string NS rises through coupling with the word lines WLsel and WLusel.

[0305] At time t3, the sequencer 14 applies the programming voltage VPGM to the word line WLsel. After the programming voltage VPGM is applied to the word line WLsel, electrons are injected into the charge storage layer based on the voltage difference between the channel and the control gate in the memory cell transistor MTsel to be programmed, and the threshold voltage rises. However, the rise in the threshold voltage of the memory cell transistor MT in the other NAND string NS is suppressed due to the rise in the channel voltage (self-boosting).

[0306] At time t4 , the sequencer 14 drops the voltage of the word line WLsel to the write path voltage VPASS.

[0307] At time t5, the sequencer 14 switches the voltage applied to each wiring and the voltage of each control signal to the state at the start of the parity bit line read operation. Thereafter, the memory device 1A ends the programming operation.

[0308] Fig.39 This is a schematic diagram showing an example of a method of selecting the bit line BL in a programming operation of a writing operation of the memory device 1A according to the second embodiment. Fig.39 Shows the execution Fig.38 During the programming operation shown in FIG. 1 , the operating states of the sensing amplifier unit SAUe and some components of the NAND strings NSae and NSbe are shown. Fig.39 As shown, in the programming operation, by setting the control signal BLC to the “H” level, the transistor T5 of the sense amplifier unit SAUe is turned on.

[0309] In addition, by setting the control signals BLSae and BLSbe to the "H" level and the "L" level, respectively, the transistors T9a and T9b of the sense amplifier unit SAUo are respectively turned on and off. By setting the control signals BIASae and BIASbe to the "L" level and the "H" level, respectively, the transistors T10a and T10b of the sense amplifier unit SAUe are respectively turned off and on. In the NAND strings NSae and NSbe, the selection transistors STae, STao, STbe and STbo to which the write path voltage VPASS is applied are respectively turned on. As a result, the even bit line BLae is charged according to the write data via the transistor T9a (BLae: (data (0 / 1)). In addition, via the transistor T10b, the even bit line BLbe is charged according to the voltage of the node BLBIAS (BLbe: prohibited).

[0310] Thus, the sense amplifier unit SAUe can perform a programming action targeting one of the sub-blocks SBLKa and SBLKb. Similarly, the sense amplifier unit SAUo can perform a programming action targeting one of the sub-blocks SBLKa and SBLKb (not shown). That is, the memory device 1A can simultaneously perform a programming action targeting the NAND string NSae of the sub-block SBLKa and a programming action targeting the NAND string NSbo of the sub-block SBLKb. In addition, the memory device 1A can simultaneously perform a programming action targeting the NAND string NSbe of the sub-block SBLKa and a programming action targeting the NAND string NSao of the sub-block SBLKb. Therefore, the memory device 1A can program (m+1) bits of data at one time.

[0311] (3: Verification action)

[0312] As a verification operation of the memory device 1A according to the second embodiment, either the first read operation or the second read operation is performed according to the address. Alternatively, as a verification operation of the memory device 1A, a mask read operation may be performed.

[0313] <2-3> Effects of the Second Embodiment

[0314] A memory device having a structure in which a memory cell array 10 (sub-array 101) is stacked is known. In such a memory device, in order to suppress the increase in the number of transistors TR and the step width of the lead-out region HR as the number of stacked word lines WL increases, the word line WL is shared between the upper and lower sub-blocks SBLKa and SBLKb. In addition, a configuration in which a 16KB bit line BL is provided in each of the sub-arrays 101a and 101b, and the 16KB bit line BL of each of the sub-arrays 101a and 101b is connected to a 16KB sense amplifier unit SAU can be considered.

[0315] Furthermore, the memory device 1A of the second embodiment performs a read operation (a first read operation and a second read operation) capable of reading 8KB page data from the sub-array 101a and 8KB page data from the sub-array 101b, and reading a total of 16KB data at one time. That is, the memory device 1A can realize 16KB page reading, and performs the read operation in a state where every other bit line BL is set to a floating state and the apparent capacitance of the bit line BL is halved.

[0316] Thus, the memory device 1A according to the second embodiment can increase the speed of the read operation and shorten the operation time.

[0317] Furthermore, the memory device 1A of the second embodiment can realize 16KB page reading in the shielded read operation by making every other bit line BL a shielded state (for example, a state where a source line potential is applied). The shielded read operation can increase the precharge speed of the bit line BL, etc., compared with the case of using a floating state. Therefore, the memory device 1A of the second embodiment can use the same 16KB sense amplifier unit SAU as before to operate, and can realize 16KB page reading with shortened operation time without increasing the circuit area. For example, in the power-on read (POR, Power on Read), instead of using an 8KB shielded read operation, a 16KB page data shielded read is used, thereby shortening the startup time of the memory device 1A. In addition, if it is a shielded read, the current will not flow arbitrarily, so the power consumption of the memory device 1A can be suppressed.

[0318] In addition, the method of reading 8KB page data from each of the sub-arrays 101a and 101b can also be used in the verification operation during the write operation. In this case, the speed of the verification operation can be increased in the same manner as the read operation. In addition, during the programming operation, the precharge time and stabilization time of the bit line BL can also be shortened. Therefore, the memory device 1A of the second embodiment can not only shorten the operation time of the read operation and the verification operation, but also shorten the operation time of the programming operation.

[0319] <3>Examples of changes, etc.

[0320] Next, modification examples of the memory device 1 described in the above embodiment will be described.

[0321] In the first embodiment, the case where the read path voltage VREAD is used as the voltage for turning on the selection transistors SGe and SGo is illustrated, but the present invention is not limited thereto. As long as the selection transistors STe and STo can be turned on, respectively, a voltage different from the read path voltage VREAD may be used. Similarly, in the second embodiment, the case where the read path voltage VREAD is used as the voltage for turning on the selection transistors STae, STao, STbe, and STbo is illustrated, but the present invention is not limited thereto. As long as the selection transistors STae, STao, STbe, and STbo can be turned on, respectively, a voltage different from the read path voltage VREAD may be used.

[0322] Fig.40 It is a schematic diagram showing a variation example of the allocation of the bit line BL groups. Fig.40(A) in FIG. 1 corresponds to the group division of the bit lines BL described in the first embodiment. Specifically, the plurality of bit lines BL are divided into an even bit line group (group GR1) consisting of even bit lines BLe (BL0, BL2, ...), and an odd bit line group (group GR2) consisting of odd bit lines BLo (BL1, BL3, ...). Fig.40 In the grouping of the bit lines BL shown in (A) in FIG. 8 , the capacitance of the bit lines BL is reduced to approximately half.

[0323] In contrast, if Fig.40 As shown in (B) in the figure, the group division of the bit lines BL can also be changed. Specifically, a plurality of groups of two bit lines BL adjacent in the X direction are arranged along the X direction. Then, the plurality of groups of two bit lines BL are divided into a group GR1 including an even number group, and a group GR2 including an odd number group. In this case, the memory device 1 can also reduce the bit line capacitance and shorten the operation time. The capacitance of the bit line BL is largely related to the capacitance component of the adjacent bit line BL, so it is better to make the bit line BL set to the floating state adjacent to the bit line BL as the operation object. This variation can also be combined with the second embodiment. In the memory device 1A, it is sufficient to be configured in such a way that the grouped bit lines BLa and BLb connected to the same sense amplifier unit SAU are included in different groups.

[0324] Fig.41 It is a cross-sectional view showing a modified example of the structure of the memory device 1 . Fig.41 The same as described in the first embodiment is shown. Fig.14 Same area. Fig.41 In the variation shown, none of the conductor layers 21 to 25 has a stepped portion. In this case, in the lead-out regions HR1 and HR2, the conductor layers 21 to 25 are respectively arranged in a plate shape. Moreover, each contact CC in this variation penetrates the conductor layer between the wiring layer M0 and the conductor layer at the connection point. Therefore, a spacer SP is provided on the side of each contact CC. Thus, each contact CC in the variation can function in the same manner as the contact CC of the first embodiment. In this way, even if the memory device 1 does not have a stepped portion in the lead-out region HR, it is sufficient to have a structure in which a group consisting of a certain contact CC and the associated wiring is electrically connected to other stacked wiring without short-circuiting. This variation can also be combined with the second embodiment.

[0325] Fig.42 It is a cross-sectional view showing an example of a detailed cross-sectional structure of a bonding portion of the bonding pad BP. Fig.42 The conductive layer 55 (bonding pad BP) of the CMOS layer 100 and the conductive layer 28 (bonding pad BP) of the memory layer 200 are shown, as well as some contacts and wirings connected to these bonding pads BP. Fig.42As shown, the two bonding pads BP arranged opposite to each other may have different taper shapes based on the etching direction during formation. Specifically, the conductive layer 55 formed using the first substrate W1, for example, has an inverted taper shape that becomes thinner as it approaches the substrate W1. The conductive layer 28 formed using the second substrate W2, for example, has a taper shape that becomes thicker as it approaches the substrate W1. In addition, the two bonding pads BP arranged opposite to each other in a group may be staggered and bonded according to the alignment during the bonding process. Therefore, a step difference is formed between the upper surface of the conductive layer 55 and the lower surface of the conductive layer 28. The two bonding pads BP arranged opposite to each other in a group may have a boundary or may be integrated. The bonding pad BP and the contact connected to the bonding pad BP may be formed as one. The conductive layer 55 may also be connected to the conductive layer 54 via a plurality of contacts C3. Similarly, the conductive layer 28 may also be connected to the conductive layer 27 via a plurality of contacts V1.

[0326] In the above embodiment, the memory layer 200 is provided above the CMOS layer 100, but the CMOS layer 100 may be provided above the memory layer 200. In this case, for example, the wiring layer 300 (pad PD) is provided on the CMOS layer 100.

[0327] In the above-described embodiment, the circuit configuration, planar layout, and cross-sectional structure of the memory device 1 may be appropriately changed. For example, the semiconductor layer 41 of the memory column MP and the source line SL may be connected via the side of the memory column MP. The memory column MP may have a structure in which two or more of a plurality of columns are connected in the Z direction. The memory column MP may have a structure in which a column corresponding to the selection gate line SGD is connected to a column corresponding to the word line WL. Each contact may be connected via a plurality of contacts connected in the Z direction. A conductive layer may be inserted into the connection portion of the plurality of contacts. The number of wiring layers and contacts provided in the memory device 1 may be appropriately changed.

[0328] In the drawings used to illustrate the embodiment, the case where the storage column MP has the same diameter in the Z direction is shown as an example, but it is not limited to this. The storage column MP may also have a conical shape, an inverted conical shape, or a curved shape. Similarly, the slits SLT and SHE may each have a conical shape, an inverted conical shape, or a curved shape. Similarly, each contact may also have a conical shape, an inverted conical shape, or a curved shape. The cross-sectional structure of the storage column MP, and the contacts V0~V3, CC and C3 may be circular or elliptical.

[0329] In this specification, "connection" means electrical connection, and does not exclude the situation where other elements are interposed in between. "Electrical connection" can be operated in the same way as in the case of electrical connection, and can also be separated by an insulator. "Conical shape" means a shape that becomes thinner as it is farther away from the substrate serving as a reference. "Inverted cone shape" means a shape that becomes thicker as it is farther away from the substrate serving as a reference. "Columnar" means a structure arranged in a hole formed in the manufacturing process of the memory device 1. "Semiconductor layer" can also be called "conductive layer". Word lines WL, selection gate lines SGD, SGS, SGe and SGo, etc. can also be simply referred to as "wiring".

[0330] In this specification, the components used as the reference for even and odd numbers are not necessarily components arranged at the ends. Any components can be used as the reference for even and odd numbers. In this specification, the NAND string NS may also be referred to as a "string". The NAND string NS connected to the even bit line BLe may also be referred to as an "even string". The NAND string NS connected to the odd bit line BLo may also be referred to as an "odd string". The voltage at the "H" level is a logic level at which an N-type transistor with a voltage of this level applied to the gate becomes a conducting state. The voltage at the "L" level is a logic level at which an N-type transistor with a voltage of this level applied to the gate becomes a disconnected state.

[0331] In this specification, applying a voltage to a word line WL corresponds to applying a voltage to the word line WL by the driver circuit 15 via the row decoder module 16. Applying a voltage to other stacked wirings also corresponds to applying a voltage to the word line WL by the driver circuit 15 via the row decoder module 16, similarly to the word line WL. The voltage of the stacked wiring can also be estimated based on the voltage of the signal line connecting the driver circuit 15 and the row decoder module 16. In this specification, a "region" can also be regarded as a structure included in the substrate serving as a reference. For example, in the case where it is specified that the first substrate W1 includes a storage region MR and a lead-out region HR, the storage region MR and the lead-out region HR are respectively associated with different regions above the first substrate W1.

[0332] Several embodiments of the present invention have been described, but these embodiments are only presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A memory device comprising: a plurality of bit lines; A plurality of strings, each having one end connected to the plurality of bit lines, respectively, and comprising a memory cell, a first transistor, and a second transistor connected in series; a first wiring connected to each of the first transistors of the plurality of strings; a second wiring connected to each of the second transistors of the plurality of strings; A word line connected to each of the plurality of strings; and a sequencer; and The sequencer In a read operation in which N (N is an integer greater than or equal to 1) bytes of the word line are selected, a first voltage is applied to one of the first wiring and the second wiring, and a second voltage higher than the first voltage is applied to the other of the first wiring and the second wiring, In the 2×N-byte read operation in which the word line is selected, a third voltage higher than the first voltage is applied to each of the first wiring and the second wiring.

2. The memory device according to claim 1, wherein A plurality of sense amplifier units are further provided, the sense amplifier units being connected to the plurality of bit lines, respectively, and configured to be capable of determining data; and The plurality of sense amplifier units each include a third transistor connected to any one of the plurality of bit lines, In a read operation of N bytes in which the word line is selected, the third transistors included in the plurality of sense amplifier units and corresponding to the number of N bytes are controlled to be in an on state, and the remaining third transistors are controlled to be in an off state. In the read operation of 2×N bytes in which the word line is selected, the third transistors included in the plurality of sense amplifier units and corresponding in number to 2×N bytes are controlled to be in an on state.

3. The memory device according to claim 2, wherein The N-byte read operation has a first mode and a second mode, and The sequencer applies the first voltage and the second voltage to the first wiring and the second wiring, respectively, in the first mode, and applies the second voltage and the first voltage to the first wiring and the second wiring, respectively, in the second mode.

4. The memory device of claim 3, wherein In the N-byte read operation, the sequencer In the first mode, the third transistor connected to the even-numbered bit lines included in the plurality of bit lines is controlled to be in an on state, In the second mode, the third transistor connected to the odd-numbered bit lines included in the plurality of bit lines is controlled to be in an on state.

5. The memory device of claim 3, wherein In an even-numbered string connected to the even-numbered bit line among the plurality of strings, a threshold voltage of the first transistor is lower than a threshold voltage of the second transistor, In an odd-numbered string connected to the odd-numbered bit line among the plurality of strings, a threshold voltage of the first transistor is higher than a threshold voltage of the second transistor.

6. The memory device of claim 1, wherein The first voltage is a voltage between a threshold voltage of the first transistor and a threshold voltage of the second transistor in the even-numbered string, and is a voltage between a threshold voltage of the first transistor and a threshold voltage of the second transistor in the odd-numbered string, The second voltage is a voltage higher than a threshold voltage of the second transistor in the even-numbered string and higher than a threshold voltage of the first transistor in the odd-numbered string.

7. The memory device according to claim 1, wherein Also provided is a substrate, and In each of the plurality of strings, the first transistor, the second transistor, and the memory cell are arranged along a direction intersecting a front surface of the substrate.

8. The memory device of claim 1, wherein The second voltage is substantially equal to the third voltage.

9. A memory device comprising: A CMOS layer, a first memory layer, and a second memory layer stacked in a first direction; and a sequencer; and The first memory layer includes a plurality of first bit lines and a plurality of first strings each having one end connected to the plurality of first bit lines. The second memory layer includes a plurality of second bit lines and a plurality of second strings each having one end connected to the plurality of second bit lines. The CMOS layer includes a plurality of sense amplifier units, the sense amplifier units are connected to the plurality of first bit lines, respectively, and are connected to the plurality of second bit lines, respectively, and are configured to be able to determine data; the plurality of sense amplifier units respectively include a first transistor connected to any one of the plurality of first bit lines, a second transistor connected to any one of the plurality of second bit lines, and a sensing node connected to the first transistor and the second transistor, respectively, the plurality of sense amplifier units include a plurality of first sense amplifier units and a plurality of second sense amplifier units, The sequencer is in the read operation, applying a voltage of a first logic level to the first transistor of each of the plurality of first sense amplifier units, and applying a voltage of a second logic level different from the first logic level to the second transistor of each of the plurality of first sense amplifier units, A voltage of the second logic level is applied to the first transistor of each of the plurality of second sense amplifier units, and a voltage of the first logic level is applied to the second transistor of each of the plurality of second sense amplifier units.

10. The memory device of claim 9, wherein The sequencer In the first read operation, the first transistor of the first sense amplifier unit and the second transistor of the second sense amplifier unit are controlled to be in an on state, and the second transistor of the first sense amplifier unit and the first transistor of the second sense amplifier unit are controlled to be in an off state, respectively. In the second read operation, the second transistor of the first sense amplifier unit and the first transistor of the second sense amplifier unit are controlled to be in an on state, respectively, and the first transistor of the first sense amplifier unit and the second transistor of the second sense amplifier unit are controlled to be in an off state, respectively.

11. The memory device of claim 9, wherein The plurality of first strings respectively include a first storage unit, a third transistor, and a fourth transistor connected in series, the first memory layer further includes a first wiring connected to the third transistor of each of the plurality of first strings, a second wiring connected to the fourth transistor of each of the plurality of first strings, and a first word line connected to the first storage unit of each of the plurality of first strings, The plurality of second strings respectively include a second storage unit, a fifth transistor, and a sixth transistor connected in series, the second memory layer further includes a third wiring connected to the fifth transistor of each of the plurality of second strings, a fourth wiring connected to the sixth transistor of each of the plurality of second strings, and a second word line connected to the second storage unit of each of the plurality of second strings and electrically connected to the first word line, and The sequencer In the first read operation in which the first and second word lines are selected, a first voltage is applied to the first wiring, a second voltage higher than the first voltage is applied to the second wiring, the first voltage is applied to the third wiring, and the second voltage is applied to the fourth wiring.

12. The memory device of claim 11, wherein The sequencer In the second read operation in which the first and second word lines are selected, the second voltage is applied to the first wiring, the first voltage is applied to the second wiring, the second voltage is applied to the third wiring, and the first voltage is applied to the fourth wiring.

13. The memory device of claim 11, wherein In the even-numbered first strings connected to the even-numbered first bit lines among the plurality of first strings, the threshold voltage of the third transistor is lower than the threshold voltage of the fourth transistor, In the odd-numbered first strings connected to the odd-numbered first bit lines among the plurality of first strings, the threshold voltage of the third transistor is higher than the threshold voltage of the fourth transistor, In the even-numbered second strings connected to the even-numbered second bit lines among the plurality of second strings, the threshold voltage of the fifth transistor is higher than the threshold voltage of the sixth transistor, In the odd-numbered second strings connected to the odd-numbered second bit lines among the plurality of second strings, the threshold voltage of the fifth transistor is lower than the threshold voltage of the sixth transistor.

14. The memory device of claim 13, wherein The first voltage is a voltage between a threshold voltage of the third transistor and a threshold voltage of the fourth transistor in the first even-numbered string, a voltage between a threshold voltage of the third transistor and a threshold voltage of the fourth transistor in the first odd-numbered string, a voltage between a threshold voltage of the fifth transistor and a threshold voltage of the sixth transistor in the second even-numbered string, and a voltage between a threshold voltage of the fifth transistor and a threshold voltage of the sixth transistor in the second odd-numbered string, The second voltage is a voltage higher than the threshold voltage of the fourth transistor in the even-numbered first string, higher than the threshold voltage of the third transistor in the odd-numbered first string, higher than the threshold voltage of the fifth transistor in the even-numbered second string, and higher than the threshold voltage of the sixth transistor in the odd-numbered second string.

15. The memory device of claim 9, wherein The plurality of sense amplifier units respectively include a seventh transistor connected to any one of the plurality of first bit lines, an eighth transistor connected to any one of the plurality of second bit lines, and a first node connected to the seventh transistor and the eighth transistor, respectively. The sequencer applies the voltage of the second logic level to the seventh transistor and the eighth transistor of each of the plurality of sense amplifier units in the read operation.

16. The memory device of claim 9, wherein The plurality of sense amplifier units respectively include a seventh transistor connected to any one of the plurality of first bit lines, an eighth transistor connected to any one of the plurality of second bit lines, and a first node connected to the seventh transistor and the eighth transistor, respectively. In the read operation, the sequencer applies the voltage of the first logic level to the seventh transistor and the eighth transistor of each of the plurality of sense amplifier units, and applies a third voltage to the first node.

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