Memory device, memory system and method of manufacturing semiconductor device

Abstract

A memory device includes anti-fuse memory cells that randomly assume a first logic state or a second logic state. A memory cell is formed on a front side of a substrate and includes at least a first program transistor formed in a first metallization layer of a plurality of metallization layers disposed on the front side and gated by a first program word line and a first read transistor formed in a second metallization layer of the plurality of metallization layers disposed on the front side and gated by a second program word line. And a first read word line formed in or along a main surface of the front side in a second metallization layer of the plurality of metallization layers disposed over the front side, coupled in series to the first program transistor and the first bit line, and gated by the first read word line. The embodiment of the invention also discloses a memory system and a method for manufacturing the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory device, a memory system, and a method of manufacturing a semiconductor device. Background Art

[0002] Integrated circuits (ICs) sometimes include one-time programmable (OTP) memory to provide non-volatile memory (NVM) in which data is not lost when the IC is powered off. One type of OTP device includes an anti-fuse memory. The anti-fuse memory includes a plurality of anti-fuse memory cells (or bit cells) whose terminals are disconnected before programming and short-circuited (e.g., connected) after programming. The anti-fuse memory can be based on metal oxide semiconductor (MOS) technology. For example, an anti-fuse memory cell can include a programming MOS transistor (or MOS capacitor) and at least one reading MOS transistor coupled in series. The gate dielectric of the programming MOS transistor may be broken down, resulting in the interconnection of the programming MOS transistor gate and source / drain. Depending on whether the gate dielectric of the programming MOS transistor is broken down, the anti-fuse memory cell can present different data bits by reading the composite current flowing through the programming MOS transistor and the reading MOS transistor. The anti-fuse memory has the advantage of reverse engineering proof because the programming state of the anti-fuse cell cannot be determined by reverse engineering. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: an anti-fuse memory cell configured to present a first logic state or a second logic state, wherein the memory cell is formed on the front side of a substrate and comprises at least: a first programming transistor formed in a first metallization layer among a plurality of metallization layers arranged above the front side and selected by a first programming word line; and a first read transistor formed in a second metallization layer among a plurality of metallization layers arranged above the front side or formed along a main surface on the front side, coupled in series to the first programming transistor and a first bit line, and selected by a first read word line.

[0004] According to another aspect of an embodiment of the present application, a memory system is provided, comprising: a memory array, comprising a plurality of anti-fuse memory cells formed on a front side of a substrate, each memory cell presenting a logical state of a first logical state or a second logical state, and comprising at least: a first programming transistor, formed in a first metallization layer among a plurality of metallization layers arranged above the front side, and selected by a first programming word line; and a first reading transistor, formed in a second metallization layer among a plurality of metallization layers arranged above the front side or formed along a main surface on the front side, coupled to the first programming transistor and a first bit line, and selected by a first reading word line; and an authentication circuit, operably coupled to the memory array, and configured to generate bits of a physically unclonable function (PUF) signature for each memory cell based on the logical state of each of the memory cells.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, including: forming a first read transistor along a main surface on a front side of a substrate; forming a first metallization layer among a plurality of metallization layers arranged above the first read transistor to connect a gate of the first read transistor to a first read word line and to connect the first read transistor to a first bit line; forming a second metallization layer among a plurality of metallization layers above the first metallization layer among the plurality of metallization layers; forming a first programming transistor in the second metallization layer among the plurality of metallization layers; and forming a third metallization layer among a plurality of metallization layers above the first metallization layer among the plurality of metallization layers to connect a gate of the first programming transistor to a first programming word line and to connect the first programming transistor to the first read transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A A block diagram of an example memory system is shown in accordance with some embodiments.

[0008] Figure 1B According to some embodiments Figure 1A An example circuit diagram of a portion of a memory array of a memory system.

[0009] Figure 2A According to some embodiments Figure 1A-1B An example circuit diagram of a memory cell of a memory array of FIG.

[0010] Figure 2B According to some embodiments Figure 2A Another example circuit diagram of a memory cell of a memory array of FIG.

[0011] Figure 2C According to other embodiments Figure 1A An example circuit diagram of a memory cell of a memory array of FIG.

[0012] Figure 3 illustrates the operation according to some embodiments Figure 1A A flowchart of an example method of a memory system.

[0013] Figure 4 According to some embodiments, Figure 2A-2B A cross-sectional view of a memory device showing a memory cell.

[0014] Figure 5 According to some embodiments, Figure 2C A cross-sectional view of a memory device showing a memory cell.

[0015] Fig. 6A , Figure 6B and Figure 6C According to other embodiments Figure 1A Various example circuit diagrams of memory cells of a memory array of FIG.

[0016] Fig. 7A , Figure 7B and Figure 7C According to some embodiments, Fig. 6A Various cross-sectional views of a memory device formed by a circuit diagram.

[0017] Fig. 8A A 2D access transistor is shown in accordance with some embodiments.

[0018] Figure 8B A 3D access transistor is shown in accordance with some embodiments.

[0019] Fig. 9 The manufacturing method according to some embodiments is shown as follows Figure 4 A flow chart of a method for a memory device is shown. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0022] Physically Unclonable Functions (PUFs) are commonly used for authentication and key storage without the need for secure Electrically Erasable Programmable Read-Only Memory (EEPROM) and / or other expensive hardware (e.g., battery-backed static random access memory). Instead of storing secrets in digital memory, PUFs derive secret information from the physical properties of an integrated circuit (IC). PUFs are based on the idea that even if the same manufacturing process is used to manufacture multiple ICs, each IC may be slightly different due to manufacturing variability. PUFs exploit this variability to derive “secret” information that is unique to each IC (e.g., a silicon biometric). Often, this secret information is referred to as the “PUF signature” of the IC. Furthermore, due to the manufacturing variability that defines the PUF signature, no two identical ICs can be manufactured, even if the IC’s design is fully understood. Various types of variability in ICs can be used to define this signature.

[0023] Embodiments of the present disclosure provide various systems and methods for generating and reading at least one bit (or PUF bit) of a PUF signature for a memory device including a plurality of memory cells. In some embodiments, each memory cell is implemented as an anti-fuse unit, which includes a first and a second programming transistor and a first and a second reading transistor, wherein the first programming transistor and the first reading transistor are coupled in series, and the second programming transistor and the second reading transistor are connected in series. According to various embodiments, even if the first and second programming transistors are formed with the same size and the same material, and have the same level of programming voltage, one of the first and second programming transistors may be broken down by the programming voltage before the other. When one of the first and second programming transistors is broken down, the programming process may stop. Therefore, one of the two programming transistors may be randomly programmed. Based on which of the two programming transistors is broken down first, the disclosed system generates at least one PUF bit for the memory device / generates a PUF bit from the memory device. Applying the same principle to all memory cells, the disclosed system can generate a unique PUF signature for the memory device / generate a unique PUF signature from the memory device.

[0024] In some embodiments, the first and second read transistors are formed along the main surface of the front side of the substrate in a front end of the line (FEOL) network, and the first and second programming transistors are formed in one of the metallization layers of the back end of the line (BEOL) network disposed above the first and second read transistors, thereby resulting in a reduced memory cell area and a lower programming voltage.

[0025] Figure 1A Memory system 100 is shown according to various embodiments. Figure 1A In the illustrated embodiment, memory system 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuitry 108, authentication circuitry 110, and control logic circuitry 112. Figure 1A Although not shown in FIG. 1 , all components of the memory system 100 may be coupled to each other and to the control logic circuit 112. Figure 1A In the illustrated embodiment, for the purpose of clarity, each component is shown as a separate block, but in other embodiments, Figure 1A Some or all of the components shown in can be integrated together.For example, memory array 102 can include an embedded authentication circuit (eg, 110).

[0026] The memory array 102 is a hardware component that stores data. In one aspect, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or storage cells) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... RM Each row extends in a first direction (eg, X direction), and a plurality of columns C1, C2, C3, ... N , each column extends in a second direction (e.g., Y direction). Each row / column may include one or more conductive structures used as access lines. In some embodiments, each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and can be operated according to a voltage or current through the corresponding conductive structures of the column and row.

[0027] In some embodiments, each memory cell 103 is implemented as an anti-fuse memory cell, including first and second programming transistors and first and second read transistors. The first programming transistor and the first read transistor are coupled in series, and the second programming transistor and the second read transistor are coupled in series. The first and second read transistors can be turned on / off simultaneously or separately to enable / disable access (e.g., programming or reading) to the corresponding (first and second) programming transistors. For example, after enabling, the two programming transistors can be programmed at the same time (e.g., by applying a programming voltage together). Randomly, one programming transistor can be broken down faster than the other, so the logical state of the memory cell can be determined based on which of the two programming transistors is broken down. This randomly determined logical state of the memory cell can form the basis of the PUF signature. The following will refer to Figure 2A-2C and Figure 3 A detailed description regarding the configuration and operation of the memory unit 103 to generate a PUF signature is discussed.

[0028] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., a word line) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert one or more conductive structures (e.g., a pair of source lines) at the column address. The I / O circuit 108 is a hardware component that can access (e.g., read or program) each memory cell 103 asserted by the row decoder 104 and the column decoder 106. The authentication circuit 110 is a hardware component that can generate a PUF signature based on the respective logic states of the memory cells read by the I / O circuit 108. The control logic circuit 112 is a hardware component that can control the coupled components (e.g., 102 to 110).

[0029] Figure 1B 1 shows an example circuit diagram of a portion of a memory device 100 (eg, some memory cells 103) according to some embodiments. Figure 1BIn the example shown, anti-fuse memory cells 103A, 103B, 103C, and 103D are shown for the memory array 102. It should be understood that the memory array 102 can have any number of anti-fuse memory cells 103 while still being within the scope of the present disclosure.

[0030] As described above, the memory cells 103 may be arranged in an array. Figure 1B As shown, memory cells 103A and 103B may be arranged in the same row but in different columns; and memory cells 103C and 103D may be arranged in the same row but in different columns. For example, memory cells 103A and 103B are arranged in the same row R1 but in different columns C1 and C2; and memory cells 103C and 103D are arranged in the same row R2 but in different columns C1 and C2. With such a configuration, each memory cell can be operably coupled to the access lines in the corresponding row and column, respectively.

[0031] For example, in Figure 1B In the example, memory cell 103A is operably coupled to a first programming word line, a second programming word line, and a read word line (hereinafter referred to as WLP, respectively) in row R1. 10 、WLP 11 and WLR1) and a bit line in column C1 (hereinafter referred to as BL1); memory cell 103B is operably coupled to a third programming word line in row R1 (hereinafter referred to as WLP 12 ), the fourth programming word line (hereinafter referred to as WLP 13 ), read word line WLR1 and a bit line in column C2 (hereinafter referred to as BL2); memory cell 103C is operably coupled to a first programming word line, a second programming word line and a read word line (hereinafter referred to as WLP, respectively) in row R2. 20 、WLP 21 and WLR2) and bit line BL1 in column C1; and memory cell 103D is operably coupled to a third programming word line (hereinafter referred to as WLP) in row R2 22 ), the fourth programming word line (hereinafter referred to as WLP 23 ), read word line WLR2 and bit line BL2 in column C2.

[0032] In some embodiments, each of the memory cells 103A to 103D may be operably coupled to the I / O circuit 108 through respective WLRs, WLPs, and BLs for access (e.g., programming or reading). For example, the I / O circuit 108 may cause the row decoder 104 to assert the WLP 10 、WLP 11and WLR1, and causes column decoder 106 to assert BL1, thereby accessing memory cell 103A. Thus, each memory cell 103A-103D can be individually selected for programming. The details regarding programming and reading memory cells will be discussed in more detail below.

[0033] Each of the memory cells 103A to 103D includes a plurality of programming transistors and a plurality of reading transistors, wherein each programming transistor is serially coupled to a corresponding one of the reading transistors. Furthermore, according to various embodiments, the programming transistors are individually gated, while the reading transistors may or may not be commonly gated. In some embodiments, as shown in FIG. Figure 1B As shown, read transistors arranged along the same row are generally commonly gated. In the following discussion, memory cell 103A is selected as a representative example.

[0034] like Figure 1B As shown, the memory cell 103A includes two programming transistors 120A and 122A and two reading transistors 124A and 126A. The programming transistor 120A is coupled in series to the reading transistor 124A; and the programming transistor 122A is coupled in series to the reading transistor 126A. The source / drain terminal of each of the programming transistors 120A and 122A is floating (i.e., not connected to any other functional component); and the other source / drain terminal of each of the programming transistors 120A and 122A is coupled in series to one source / drain terminal of the corresponding reading transistor 124A / 126A, and the other source / drain terminal of the reading transistors 124A and 126A is commonly coupled to BL1.

[0035] Specifically, programming transistor 120A is provided by WLP 10 The gate terminal of the programming transistor 120A is coupled to the WLP 10 ), programming transistor 122A is WLP 11 The gate terminal of the programming transistor 1220A is coupled to the WLP 11 ). Both read transistors 124A and 126A are gated by WLR1 (i.e., both gate terminals of read transistors 124A and 126A are coupled to WLR1). However, it should be understood that the gate terminals of read transistors 124A and 126A can be coupled to corresponding different WLRs. In some embodiments, the gate terminals of programming transistors 120A and 122A (formed as gate structures described below) can be isolated from each other by forming a dielectric structure between the gate structures (not shown).

[0036] The configuration of each of the other memory cells (e.g., 103B, 103C, and 103D) is substantially the same as that of the memory cell 103A, and thus the memory cells 103B to 103D are briefly described as follows. The memory cell 103B includes a WLP 12 and WLP 13 The memory cell 103C includes programming transistors 120B and 122B selected by WLR1, and read transistors 124B and 126B selected by WLR2. 20 and WLP 21 The memory cell 103D includes programming transistors 120C and 122C selected by WLR2, and read transistors 124C and 126C selected by WLR2; 22 and WLP 23 Program transistors 120D and 122D are gated, and read transistors 124D and 126D are gated by WLR2.

[0037] Reference Figure 2A , an example circuit diagram 200A of a memory cell 103A is provided to illustrate the operation of each memory cell 103 according to some embodiments. As shown, each of the programming / reading transistors 120A to 126A may include an n-type metal oxide semiconductor field effect transistor (n-type MOSFET) or referred to as an NMOS transistor. However, it should be understood that each of the programming / reading transistors 120A to 126A may include a p-type metal oxide semiconductor field effect transistor (p-type MOSFET) while still being within the scope of the present disclosure.

[0038] Specifically, drain terminals 120AD and 122AD of programming transistors 120A and 122A are floating (e.g., not coupled to a functional component), and their source terminals 120AS and 122AS are coupled to drain terminals 124AD and 126AD of read transistors 124A and 126A, respectively. Source terminals 124AS ​​and 126AS of read transistors 124A and 126A are commonly coupled to BL1. Gate terminal 120AG of programming transistor 120A is coupled to WLP 10 The gate terminal 122AG of the programming transistor 122A is coupled to the WLP 11 On the other hand, the gate terminals 124AG and 126AG of the read transistors 124A and 126A are commonly coupled to WLR1.

[0039] To program memory cell 103A, read transistors 124A and 126A are turned on by providing a sufficiently high voltage (e.g., a positive voltage corresponding to a logic high state) to gate terminals 124AG and 126AG of read transistors 124A and 126A via WLR1. Before, simultaneously with, or after read transistors 124A and 126A are turned on, WLP 10 and WLP 11 At the same time, a sufficiently high voltage (e.g., breakdown voltage (V BD ), called the programming voltage), and applies a sufficiently low voltage (e.g., a positive voltage corresponding to a logic low state or a ground voltage) to BL1. A sufficiently low voltage (applied to BL1) can be passed to the source terminals 120AS and 122AS. Therefore, V BD It may be present simultaneously on the source terminal 120AS and the gate terminal 120AG of the programming transistor 120A and on the source terminal 122AS and the gate terminal 122AG of the programming transistor 122A.

[0040] Due to process variability, even if the two programming transistors 120A and 122A are formed of the same material (e.g., the same dielectric layer) and manufactured in the same size, one of the two transistors should break down faster than the other programming transistor. Specifically, a portion of the gate dielectric layer of the programming transistor 120A (e.g., the portion between the source terminal 120AS and the gate terminal 120AG) or a portion of the gate dielectric layer of the programming transistor 122A (e.g., the portion between the drain terminal 122AS and the gate terminal 122AG) will be pre-broken down. Since the gate terminal 120AG of the programming transistor 120A and the gate terminal 122AG of the programming transistor 122A are isolated from each other, such a previous breakdown may occur randomly and individually.

[0041] After the gate dielectric layer of the programming transistor 120A or 122A is broken down, the portion of the gate dielectric layer interconnecting the gate terminal 120AG / 122AG and the source terminal 120AS / 122AS behaves as a resistor. Figure 2A As shown, the portion of the gate dielectric layer of programming transistor 120A (if it breaks down first) can serve as resistor 150, while the portion of the gate dielectric layer of programming transistor 122A (if it breaks down first) can serve as resistor 155. Before programming (e.g., before the gate dielectric layer of either programming transistor 120A or 122A is broken down), even if read transistors 124A and 126A are turned on, BL1 and WLP 10 and WLP 11 There is no conductive path between BL1 and WLP after programming when read transistors 124A and 126A are turned on.10 between BL1 and WLP (eg, via resistor 150), or between BL1 and WLP 11 There is a conductive path between (eg, via resistor 155).

[0042] When one of the programming transistors 120A and 122A breaks down, a conductive path is established. In the example where the programming transistor 120A is broken down first, a sudden increase in voltage may occur on the source terminal 120AS, which may cause a sudden increase in voltage on BL1. Therefore, the voltage level at the source terminal 122AS of the programming transistor 122A can be increased so that the programming process on the transistor 122A can be automatically stopped (because the voltage drop across its gate and source terminals is reduced). Therefore, the memory cell 103A can be "randomly" programmed to the first logic state or the second logic state. Whether the first or second logic state is programmed into the memory cell can correspond to which programming transistor is (first) broken down, which can be determined based on a further reading process.

[0043] In some embodiments, the reading process includes applying a relatively low level voltage (referred to as a read voltage) to both programming transistors simultaneously, and there may be an observable decrease in the read voltage on the damaged programming transistor, while the read voltage applied to the undamaged programming transistor may remain substantially unchanged. In the above example where programming transistor 120A is broken down (while programming transistor 122A remains intact), the voltage applied to WLP 10 The read voltage on the WLP may be observed to be lower than that applied 11 The read voltage on . Therefore, the logic state (PUF bit) of the cell 103A can be determined accordingly. Based on this random programming logic state on each memory cell, a PUF signature (formed by the various PUF bits of the memory cell) can be generated.

[0044] Figure 2B Another example circuit diagram 200B of a memory cell 103A is shown in accordance with some embodiments. Figure 2B The circuit diagram and Figure 2A The circuit diagram is basically similar, except that the two read transistors 124A and 126A are respectively composed of different WLR 10 and WLR 11 Therefore, the discussion will not be repeated.

[0045] Figure 2C Yet another example circuit diagram 200C of a memory cell 103A is shown in accordance with some embodiments. Figure 2C The circuit diagram and Figure 2AThe circuit diagram of is substantially similar, except that two additional read transistors 128A and 130A are coupled in series to the programming transistors 120A and 122A and the read transistors 124A and 126A, respectively. By means of the two additional read transistors 128A and 130A, the read margin of the memory cell 103A can be improved. As shown, the source terminals 128AS and 130AS of the read transistors 128A and 130A are coupled to the drain terminals 120AD and 122AD, respectively. The source terminals of the read transistors 124A and 126A are coupled in common to BL1. The gate terminals 128AG and 130AG of the read transistors 128A and 130A are coupled in common to another read word line WLR2. However, it should be understood that the gate terminals 128AG and 130AG can be coupled to corresponding different read word lines while still being within the scope of the present disclosure.

[0046] Figure 3 An exemplary flow chart of a method 300 for generating a PUF signature based on an anti-fuse memory cell including a pair of programming transistors and a pair of reading transistors according to various embodiments is shown. Figure 1A-Figure 2C (For example, Figure 2A The following embodiment of method 300 is described with reference to memory unit 103A of FIG. 3. The illustrated embodiment of method 300 is merely an example, and thus any of the various operations may be omitted, reordered, and / or added while still within the scope of the present disclosure.

[0047] Method 300 begins with operation 302 of a programming process. Specifically, operation 302 includes operation 304 of selecting a bit line, applying a high programming voltage (e.g., V BD ) and assert one or more read word lines 308. It should be noted that the order of operations 304 to 308 can be changed while still within the scope of the present disclosure. For example, operation 308 can be performed before operations 304 and 306.

[0048] Also refer to Figure 1A and Figure 2A In operation 304, the control logic circuit 112 may provide a column address to the column decoder 106 to select columns C1 to C2 of the memory array 102. N After selecting a column, the I / O circuit 108 may send a BL (e.g. Figure 2A In some embodiments, the selected BL1 may be pulled to ground. Next, the control logic circuit 112 may provide a row address to the row decoder 104 to select rows R1 to R2 of the memory array 102. MWhen a row is selected, I / O circuit 108 may provide a pair of programming word lines (e.g., Figure 2A WLP 10 and WLP 11 ) provides programming voltage (V BD ) (operation 306), and the I / O circuit 108 may provide a read word line (eg, corresponding to a word line) arranged in the selected row. Figure 2A The WLR1 of the selected column and row provides a voltage (eg, corresponding to a logic high state) (operation 308), thereby turning on the read transistors 124A and 126A. Thus, the memory cell (eg, 103A) arranged at the intersection of the selected column and row can be programmed.

[0049] Next, the method 300 continues to operation 310 to determine whether one of the programming transistors of the selected memory cell has been broken down (i.e., programmed). If so, the method 300 continues to operation 312, including one or more reading processes; if not, the method 300 returns to operation 302 to perform the programming process again. In various embodiments, as described above, the I / O circuit 108 can determine whether one of the programming transistors has broken down based on detecting a voltage increase present on the selected BL (e.g., BL1).

[0050] Operation 312 also includes operation 314, where a bit line and a read word line are selected or asserted, operation 316, where a relatively low read voltage (Vread) is simultaneously applied to a pair of programming word lines, operation 318, where a sensing occurs as to which programming word line exhibits a signal drop, and operation 320, where a PUF bit is generated.

[0051] Referring first to operation 314, the control logic circuit 112 may provide a column address to the column decoder 106 to select columns C1 to C2 of the memory array 102. N and provides a row address to the row decoder 104 to select the rows R1 to R2 of the memory array 102. M In some embodiments, the column and row asserted in operation 314 are the same as the column asserted in operation 304 and the row asserted in operation 308, respectively. As a result, BL1 is again pulled to ground, and read transistors 124A and 126A are again turned on.

[0052] Referring next to operation 316, based on the selected row, the I / O circuit 108 may provide a programming word line (eg, Figure 2A WLP 10 and WLP 11 ) provides Vread. Therefore, the memory cell 103A can be read. Next, in operation 318, the I / O circuit 108 can sense the WLP connected to the memory cell 103A. 10and WLP 11 Which of the above shows a signal drop.

[0053] Therefore, the control logic circuit 112 may be based on whether it is a WLP 10 and WLP 11 The signal falls to determine the logic state programmed into the memory cell 103A and provides this logic state to the authentication circuit 110 to generate the PUF bit (operation 320). 10 If there is a signal drop on WLP (ie, programming transistor 120A has broken down), control logic circuit 112 may determine that the first logic state has been programmed into memory cell 103A. 11 If there is a signal drop on 103A (ie, programming transistor 122A has broken down), control logic circuit 112 may determine that the second logic state has been programmed into memory cell 103A.

[0054] Figure 4 FIG. 4 shows a cross-sectional view of a memory device 400 according to some embodiments, the memory device 400 includes at least Figure 2A 103A. In some embodiments, the memory cell 103A is based on Figure 2A The circuit diagram 200A ("4T" configuration) is implemented, so it will reuse Figure 2A Memory cell 103A is used as a representative example, however, Figure 1A The structure and configuration of each memory cell 103 in can be the same as or similar to memory cell 103A.

[0055] like Figure 4 As shown, the memory device 400 includes an anti-fuse memory cell 103A formed on a front side 403 of a substrate 401, and includes at least a first programming transistor 120 and a second programming transistor 122 formed in a first metallization layer (e.g., M2) of a plurality of metallization layers (e.g., M0, M1, M2) disposed above the front side 403, and respectively connected to a first programming word line (e.g., WLP 10 ) and a second programming word line (eg, WLP 11 ) is selected; and a first read transistor 124 and a second read transistor 126 formed in a second metallization layer (e.g., M1) of a plurality of metallization layers (e.g., M0, M1, M2) above the front side or along a main surface on the front side 403. The anti-fuse memory cell 103A randomly presents a first logic state or a second logic state. In some embodiments, the gate dielectric layer of the first programming transistor 120 or the gate dielectric layer of the second programming transistor 122 is randomly broken down to present the first logic state or the second logic state.

[0056] The first read transistor 124 and the second read transistor 126 are coupled in series to the first programming transistor 120 and the second programming transistor 122, respectively, are commonly coupled to the first bit line BL1, and are commonly selected by the first read word line (e.g., WLR1). In some embodiments, the first bit line is formed in a third metallization layer (e.g., M0) among a plurality of metallization layers (e.g., M0, M1, M2), and the third metallization layer is different from the first metallization layer and the second metallization layer. In some embodiments, the source / drain terminals of the first programming transistor 120 and the source / drain terminals of the second programming transistor 122 are commonly coupled to each other and are floating.

[0057] Reference Figure 4 The memory device 400 includes a substrate 401 having a front side 403 and a back side 405, an active area 402 formed along a main surface of the front side surface 403 and extending in a first lateral direction (e.g., X direction), and a first gate structure 412 and a second gate structure 414 formed covering the active area 402 and extending in parallel in a second lateral direction (e.g., Y direction).

[0058] Such active regions and gate structures are referred to as part of a "front end of line (FEOL) process / network" because they are formed along the major surface of the front side 403 of the substrate 401. On the front side surface of the substrate, multiple front side metallization layers (referred to as part of a "middle of line (MEOL) process / network") may be formed. Above and away from the major surface of the front side of the substrate, multiple front side metallization layers (referred to as part of a "back end of line (BEOL) process / network") may be formed. Over the back side 405 of the substrate 401, multiple back side metallization layers (e.g., BMO) may be formed.

[0059] In some embodiments, the active region 402 is formed by a stacked structure (not shown) protruding from the main surface of the front side 403 of the substrate 401 in the FEOL network. The stack includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and vertically separated from each other. The portion of the semiconductor nanostructure covered by the gate structures 412 and 414 in the stack is retained, while the other portion is replaced by a plurality of epitaxial structures. The remaining portion of the semiconductor nanostructure can be configured as a channel of a corresponding transistor, the epitaxial structure coupled to both sides (or ends) of the remaining portion of the semiconductor nanostructure can be configured as a source / drain structure (or terminal) of the transistor, and a portion of the gate structure covering (e.g., crossing) the remaining portion of the semiconductor nanostructure can be configured as a gate structure (or terminal) of the transistor.

[0060] As Figure 4 In a representative example, in a FEOL network, the portion of the active region 402 covered by the gate structure 412 can be used as Figure 4The portion of the active area 402 disposed on the opposite side of the gate structure 412 is replaced by the epitaxial structure and can thus be used as the source / drain terminal of the first read transistor 124, respectively. The gate structure 412 can be used as the gate terminal of the first read transistor 124. Similarly, the portion of the active area 402 covered by the gate structure 414 can be used as Figure 4 The channel of the second read transistor 126 in the active region 402 is replaced by the epitaxial structure, and thus can be used as the source / drain terminal of the second read transistor 126, respectively. The gate structure 414 can be used as the gate terminal of the second read transistor 126. Thus, in some embodiments, Figure 4 The first read transistor 124 and the second read transistor 126 in the FEOL network are formed along a main surface of the front side 403 of the substrate 401 in the FEOL network.

[0061] like Figure 4 As shown, in the MEOL network, a plurality of intermediate-end interconnect structures (referred to as MD, such as 422, 424, and 426) are formed above the corresponding source / drain terminals of the first read transistor 124 and the second read transistor 126. The intermediate-end interconnect structures can connect the corresponding source / drain terminals to the upper interconnect structure through intermediate-end via structures (referred to as VD, such as VD1 and VD2). The gate structure can be coupled to the upper interconnect structure through another intermediate-end via structure (referred to as VG, such as VG1 and VG2). Therefore, the gate structures 412 and 414 can be coupled to one or more metal tracks formed thereon.

[0062] Over these intermediate terminal structures on the front side of the substrate, a plurality of metallization layers (e.g., M0, M1, and M2) may be formed, each of which includes a plurality of metal tracks or lines embedded in a corresponding dielectric material (e.g., an intermetallic dielectric (IMD) / interlayer dielectric (ILD)). Figure 4 As shown, memory device 400 includes metal tracks 432, 434, and 436 in the M0 layer; metal tracks 442 and 444 in the M1 layer; and metal tracks 452, 454, and 456 in the M2 layer.

[0063] For example, gate structure 412 is coupled to M0 metal rail 434 through VG1, and gate structure 414 is coupled to M0 metal rail 434 through VG2. MD 422, together with at least M0 metal rail 432 and M1 metal rail 442, can couple one of the source / drain terminals (e.g., epitaxial structure) of first read transistor 124 to one end of M2 metal rail 452; MD 426, together with at least M0 metal rail 436 and M1 metal rail 444, can couple one of the source / drain terminals (e.g., epitaxial structure) of second read transistor 126 to one end of M2 metal rail 456. The other of the source / drain terminals of first read transistor 124 and second read transistor 126 is commonly coupled to MD 424 used as bit line BL1. In some embodiments, MD 424 is coupled to a power supply voltage (V SS ), and coupled to ground (GND) in other embodiments.

[0064] like Figure 4 As shown, the memory device 400 also includes a metal track 492 (referred to as "BM0 track 492") in the first backside metallization layer, which is the bottommost metallization layer relative to the backside 405 of the substrate 401. For simplicity, Figure 4 However, on the back side of the substrate 401, multiple metallization layers (e.g., referred to as BM0, BM1, BM2, and BM3) may be formed, each of which includes one or more metal tracks or lines embedded in a corresponding dielectric material (e.g., an intermetallic dielectric (IMD) or an interlayer dielectric (ILD)).

[0065] like Figure 4 As shown, in some embodiments, the first read transistor 124 and the second read transistor 126 are formed along the main surface of the front side 403 of the substrate 401, and the first programming transistor 120 and the second programming transistor 122 are formed in a metallization layer (e.g., M2) disposed above the first read transistor 124 and the second read transistor 126 in the BEOL network. As shown, the first programming transistor 120 and the second programming transistor 122 formed in the BEOL network are used to be vertically farther away from the main surface of the front side 403 than the first read transistor 124 and the second read transistor 126 formed in the FEOL network. In this way, each anti-fuse memory cell of the memory device can be reduced, thereby increasing the density of the memory cells in the memory device and improving the performance of the memory device.

[0066] Figure 5 FIG. 5 shows a cross-sectional view of a memory device 500 according to some embodiments, the memory device 500 includes at least Figure 2C Memory cell 103A shown. In some embodiments, according to Figure 2C 200C (“6T” configuration), the memory cell 103A of the memory device 500 is implemented as an anti-fuse memory cell, so the memory cell 103A of the memory device 500 is reused. Figure 2C Some references. Figure 5 The memory cell 103A in is used as a representative example, however, Figure 1A The structure and configuration of each memory cell 103 in Figure 5 The memory cell 103A shown in FIG. 1 is the same as or similar to the memory cell 103A shown in FIG.

[0067] Reference Figure 2C and Figure 5 , the memory cell 103A includes a first programming transistor 120 coupled in series between a first read transistor 124 and a third read transistor 128, and a second programming transistor 122 coupled in series between a second read transistor 126 and a fourth read transistor 130. Figure 5 As shown, the anti-fuse memory cell 103A is formed on the front side 503 of the substrate 501 and includes a first portion 103A-1 formed on the first active area 502-1 and a second portion 103A-2 formed on the second active area 502-2. The first portion 103A-1 of the memory cell 103A includes a first programming transistor 120 coupled in series between the first read transistor 124 and the third read transistor 128, and the second portion 103A-2 of the memory cell 103A includes a second programming transistor 122 coupled in series between the second read transistor 126 and the fourth read transistor 130. At least some portions of the first portion 103A-1 and the second active area 502-2 are connected as described below.

[0068] refer to Figure 5 In some embodiments, all read transistors (e.g., 124, 126, 128, and 130) are typically gated by a read word line WLR0 through at least some gate structures (e.g., 512, 514, 513, and 515) and some metal tracks (e.g., M0 metal tracks 534 and 535). For example, M0 metal tracks 534 and 535 are coupled to each other (not shown). In some embodiments, the first read transistor 124 and the third read transistor 128 are commonly coupled to the bit line BL1 through MD 524, and the second read transistor 126 and the fourth read transistor 130 are commonly coupled to the bit line BL1 through MD 525. For example, MD 524 and MD 525 are coupled to each other (not shown). The first programming transistor 120 is gated by WLP 10 The second programming transistor 122 is selected by WLP 11 Select.

[0069] like Figure 5As shown, in some embodiments, in the FEOL network, all read transistors (e.g., 124, 126, 128, and 130) are formed along the main surface of the front side 503 of the substrate 501, and the first and second programming transistors 120 and 122 are formed in a metallization layer (e.g., M2) disposed on all read transistors in the BEOL network. As shown, the first and second programming transistors 120, 122 formed in the BEOL network are vertically farther away from the main surface of the front side 503 than all read transistors formed in the FEOL network. In this way, the area and programming voltage of each memory cell can be reduced, resulting in a relatively high density of memory cells in the memory device and improved performance of the memory device.

[0070] Fig. 6A , Figure 6B and Figure 6C According to other embodiments Figure 1A 1. An example circuit diagram of a memory cell 103 of a memory array 102 of FIG. 1. In some embodiments, each memory cell 103 is implemented as an anti-fuse memory cell. Fig. 6A As shown, in some embodiments, the anti-fuse memory cell 103 includes a programming transistor 620 selected by WLP1, a first read transistor 624 selected by WLR1, and a second read transistor 626 selected by WLR2. The programming transistor 620 is coupled in series between the first read transistor 624 and the second read transistor 626. The source / drain (S / D) terminal of the first read transistor 624 is coupled to the first bit line BL1, and the source / drain terminal of the second read transistor 626 is connected to the second bit line BL2.

[0071] In some embodiments, the programming transistor 620 includes a gate terminal 620G including a gate metal 621 and a gate dielectric layer 623 made of a dielectric material and deposited under the gate metal 621. In some embodiments, the dielectric material of the gate dielectric layer 623 is selected from HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide and / or a combination thereof. The gate dielectric layer 623 includes a first dielectric portion 623A and a second dielectric portion 623B, which have the same size and can be turned on / off simultaneously or individually to enable / disable access to programming or reading of the programming transistor 620.

[0072] During the programming process, in order to program the programming transistor 620, a programming enable voltage (e.g., 1.2V) may be applied simultaneously or separately to the gates 624G and 626G of the first and second read transistors 624 and 626. After being enabled, the programming transistor 620 may be programmed by applying a programming voltage (e.g., 5V) to its gate 620G and applying a low bit line voltage (e.g., 0V) to the bit lines BL1 and BL2.

[0073] During the programming process, randomly, one of the first and second dielectric portions 623A and 623B of the gate dielectric layer 623 of the programming transistor 620 of the selected memory cell 103 may be broken down faster than the other, even if the probability of either of them being broken down is 50%. After one of the first and second dielectric portions (e.g., 623A) is broken down first, the programming process stops, so the other (e.g., 623B) remains intact. Therefore, a bit (e.g., 1) of the logic state or logic state (1 or 0) of the memory cell 103 can be randomly generated based on whether the first dielectric portion 623A or the second dielectric portion 623B of its gate dielectric layer 623 has been broken down, thereby generating a PUF signature bit for the anti-fuse memory cell 103. This is Fig. 6A The mechanism of randomly generating PUF signature bits in the anti-fuse memory unit 103 is applicable to Figure 1A In this way, a PUF signature of the memory device including the memory cells can be generated.

[0074] During the reading process, the memory cell 103 is selected and read by applying a read selection voltage (e.g., 1.5V) to the gate 620G of its programming transistor 620, applying a read selection voltage (e.g., 0.75V) to the gates 624G and 626G of its first and second read transistors 624 and 626, and applying a low BL voltage (e.g., 0V) to the corresponding source / drain terminals of its first and second read transistors 624 and 626 through bit lines BL1 and BL2.

[0075] Figure 6B According to some embodiments, Fig. 6A An example circuit diagram 600B of an anti-fuse memory cell 103 connected to a differential amplifier 630 is shown. The differential amplifier 630 has first and second input terminals 631A and 631B coupled to bit lines BL1 and BL2, respectively, and an output terminal 632 for outputting a state result (e.g., 1 or 0) of the memory cell 103. The result indicates whether the first dielectric portion 623A or the second dielectric portion 623B of the gate dielectric layer 623 has been broken down based on a sensed current detected in the first input terminal 631A or the second input terminal 631B, thereby determining the logic state of the memory cell 103.

[0076] During the reading process, when an observable current is detected in the first input terminal 631A, it is determined that the first dielectric portion 623A has been broken down, and thus the memory cell 103 is determined to be in the first logic state "1". Otherwise, when an observable current is detected in the second input terminal 631B, it is determined that the second dielectric portion 623B has been broken down, and thus the memory cell 103 is determined to be in the second logic state "0". Figure 6B This mechanism for reading the logic state of memory cell 103 is applicable to Figure 1A All memory cells 103 in . In this way, the PUF signature of the memory device is read and thus authenticated.

[0077] Figure 6C An example circuit diagram 600C of a memory device including an anti-fuse memory cell 103 according to some embodiments is shown. As shown, the anti-fuse memory cell 103 is configured to Fig. 6A The anti-fuse memory cell 103 in FIG. Figure 6C , the anti-fuse memory cell 103 is implemented as a "3T" symmetric configuration and includes a programming transistor 620, a first read transistor 624, and a second read transistor 626. The programming transistor 620 is coupled in series between the first read transistor 624 and the second read transistor 626. In some embodiments, the memory device further includes BL1 and BL2 coupled to the first read transistor 624 and the second read transistor 626, respectively.

[0078] like Figure 6C As shown, a source / drain terminal 620D of the programming transistor 620 is coupled to a source / drain terminal 624D of a first read transistor 624, and another source / drain terminal 620S of the programming transistor 620 is coupled to a source / drain terminal 626D of a second read transistor 626. The programming transistor 620 is gated by WLP1 via its gate terminal 620G, the first read transistor 624 is gated by WLR1 via its gate terminal 624G, and the second read transistor 626 is gated by WLR2 via its gate terminal 626G. In some embodiments, a source / drain terminal 624S of the first read transistor 624 is operably coupled to BL1, and a source / drain terminal 626S of the second read transistor 626 is operably coupled to BL2.

[0079] like Figure 6CAs shown, the gate terminal 620G includes a gate metal 621 and a gate dielectric layer 623 having a first dielectric portion 623A and a second dielectric portion 623B. The first dielectric portion 623A is coupled between the gate metal 621 and a source / drain terminal 620D of the programming transistor 620, and the second dielectric portion 623B is coupled between the gate metal 621 and another source / drain terminal 620S of the programming transistor 620. As described above, the memory cell 103 randomly presents a logic state of a first logic state (e.g., 1) or a second logic state (e.g., 0) based on which of the first dielectric portion 623A or the second dielectric portion 623B of the gate dielectric layer 623 is determined to have been broken down. Figure 6B The method of generating and reading the PUF signature by the anti-fuse memory unit 103 in Figure 6C The anti-fuse memory cell 103 in.

[0080] Fig. 7A Shown based on Fig. 6A 600A in the circuit diagram 700A of the memory device design. In some embodiments, Fig. 7A The memory cell 103A in is implemented as Fig. 6A The anti-fuse memory cell shown is designed in a "3T RPR" configuration, so Fig. 6A Some references will be reused. Memory cell 103A is used as a representative example.

[0081] like Fig. 7A As shown, the memory device 700A includes an anti-fuse memory cell 103A, which randomly presents a first logic state or a second logic state, and is formed on a main surface of a front side 703 of a substrate 701. The memory cell 103A includes at least a programming transistor 620, a first read transistor 624, and a second read transistor 626. The programming transistor 620 is coupled in series between the first read transistor 624 and the second read transistor 626. The memory device 700A also includes BL1 and BL2 coupled to the first read transistor 624 and the second read transistor 626, respectively. The programming transistor 620 is formed by a WLP 00 Select.

[0082] In some embodiments, in the FEOL, the first and second read transistors 624 and 626 are formed along the main surface of the front side 703 of the substrate 701, while the programming transistor 620 is formed in a metallization layer (e.g., M2) of a plurality of metallization layers (e.g., M0, M1, and M2) disposed in the BEOL network above the first and second read transistors 624, 626. As shown, the programming transistor 620 formed in the BEOL network is farther from the front side 703 of the substrate 701 in the vertical direction than the first and second read transistors 624 and 626 formed in the FEOL network. In this way, the area and programming voltage of each anti-fuse memory cell can be reduced, thereby improving the density and performance of memory cells in the memory device.

[0083] In some embodiments, the first read transistor 624 is gated by the read word line WLR1 through the first gate structure 712, and the second read transistor 626 is gated by the second read word line WLR0 through the second gate structure 714. In some embodiments, the first read transistor 624 is formed in a first active area 702-1 arranged along the main surface of the front side 703 of the substrate 701, and the second read transistor 626 is formed in a second active area 702-2 arranged along the main surface of the front side 703 of the substrate 701. In some embodiments, the first active area 702-1 and the second active area 702-2 are separated from each other by a dielectric structure. In some embodiments, the programming transistor 620 includes a first active area 702-1 and a second active area 702-2. Fig. 8A and Figure 8B A thin film (or 2D) transistor is shown which can be programmed using a relatively low programming voltage.

[0084] Figure 7B Shown based on Figure 6B The cross-sectional view 700B of the anti-fuse memory cell 103A designed in the circuit diagram 600B in FIG. Figure 6B In some embodiments, Figure 7B The memory cell 103A in FIG. 1 is implemented as an anti-fuse memory cell designed in a "3T RPR" configuration and includes Figure 6B The differential amplifier 630 is shown. Figure 7B The memory cell 103A shown is similar to Fig. 7A Memory cell 103A is shown, but with some differences.

[0085] In some embodiments, Figure 7BAs shown, the programming transistor 620 is coupled in series between the first read transistor 624 and the second read transistor 626, and all the programming transistors 620, the first read transistor 624 and the second read transistor 626 are formed in a metallization layer (e.g., M2) of a plurality of metallization layers (e.g., M0, M1, M2) in a BEOL network disposed on a main surface of the front side 703 of the substrate 701. In some embodiments, all the programming transistors 620, the first read transistor 624 and the second read transistor 626 are formed as Fig. 8A and Figure 8B The 2D transistor shown can be programmed by a relatively low programming voltage.

[0086] In some embodiments, as shown, some peripheral components, such as transistors 724, 726, and 728, are formed along the main surface of the front side 703 of the substrate 701. In some embodiments, some of the transistors 724, 726, and 728 are used as differential amplifiers 630, which have first and second input terminals 631A and 631B coupled to BL1 and BL2, respectively. Fig. 6A and Figure 6B The result output from the differential amplifier 630 indicates whether the first dielectric portion 623A or the second dielectric portion 623B of the gate dielectric layer 623 has been broken down based on the appreciable current detected in the first input terminal 631A or the second input terminal 631B, thereby determining the logic state of the memory cell 103A.

[0087] Figure 7C Shown based on Figure 6B The cross-sectional view 700C of the anti-fuse memory cell 103A designed in the circuit diagram 600B is thus reused. Figure 6B Some references. Figure 7C The memory cell 103A in Figure 7B The memory cell 103A in FIG. 1 is substantially similar, but there are some differences. Figure 7C As shown, all programming transistors 620, first read transistor 624 and second read transistor 626 are formed in a metallization layer (e.g., M2) of a plurality of metallization layers (e.g., M0, M1, M2) disposed in a BEOL network above the main surface of the front side 703 of the substrate 701. The programming transistor 620 is Fig. 8A and Figure 8B The 2D access transistor shown in FIG. 1 can be programmed by a relatively low programming voltage, while the first read transistor 624 and the second read transistor 626 are as shown in FIG. Fig. 9 The 3D access transistors shown, each transistor can bear or withstand a relatively large current, thereby achieving a relatively fast reading speed.

[0088] Fig. 8A An access transistor 800A is shown in accordance with some embodiments. As shown, the access transistor 800A is a thin film transistor including a bottom gate 816, a gate dielectric 818 disposed on the bottom gate 816, a channel structure 820 disposed on the gate dielectric 818, and a pair of source / drain structures 822 and 824 disposed on the channel structure 820. Fig. 8A The thin film transistor 800A in the embodiment may be referred to as a "two-dimensional back-gate transistor" or "2D transistor". The term "two-dimensional back-gate transistor" may refer to a transistor whose gate is formed as a relatively flat or thinner structure and whose channel structure contacts the top surface of its gate. In some embodiments, the bottom gate 816 includes TiN, the gate dielectric 818 includes a high-K dielectric material (e.g., HfO2), the channel structure 820 includes InGaZnO (IGZO), and the source / drain structures 822 and 824 include TiN. Fig. 8A The 2D transistor 800A shown may be implemented as Figure 7A-7C Any one of the programming transistor 620, the first read transistor 624, and the second read transistor 626 shown. In some embodiments, as Fig. 8A The illustrated 2D transistor 800A is implemented as a programming transistor 620. Due to its structure (eg, thinner gate oxide), the 2D programming transistor 620 is relatively easy to be broken down (or programmed), thereby achieving a relatively fast programming speed and a relatively low programming voltage.

[0089] Figure 8B Another access transistor 800B is shown according to other embodiments. As shown, the access transistor 800B includes a bottom gate 826, a gate dielectric 828 disposed on the bottom gate 826, a channel structure 830 disposed over the bottom gate 826, and a pair of source / drain structures 832 and 834 disposed over the channel structure 830. Figure 8B The access transistor 800B in the embodiment may be referred to as a "three-dimensional back-gate transistor" or "3D transistor". The term "three-dimensional back-gate transistor" may refer to a transistor whose gate is formed as a relatively protruding structure and whose channel structure contacts multiple surfaces of its gate. In some embodiments, the bottom gate 826 includes TiN, the gate dielectric 828 includes a high-K dielectric material (e.g., HfO2), the channel structure 830 includes InGaZnO (IGZO), and the source / drain structures 832 and 834 include TiN. In some embodiments, the 3D transistor 800B may be implemented as Figure 7C Any one of the first read transistor 624 and the second read transistor 626 is shown. Due to their structure, the 3D read transistors 624 and 626 can afford or withstand a relatively large read current passing therethrough and achieve a relatively fast read speed.

[0090] Fig. 9 The manufacturing method according to some embodiments is shown as follows Figure 4 The flowchart of the method 900 of the memory device 400 is shown, and thus the method 900 will be reused in the following discussion. Figure 4 Some references used in the description. It should be noted that method 900 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional operations may be provided before, during, and after method 900, and that only some other operations may be briefly described herein. The order of operations may be interchangeable.

[0091] As described above, the memory device 400 includes at least a memory cell 103A designed in a 4T configuration and formed on the front side 403 of the substrate 401, and a plurality of metallization layers (e.g., M0, M1, M2, ...) respectively disposed on the front side 403 of the substrate 401. In some embodiments, the memory cell 103A includes a first read transistor 124 and a second read transistor 126 formed along a main surface of the front side 403 of the substrate 401 in the FEOL network, and a first programming transistor 120 and a second programming transistor 122 formed in a first metallization layer (e.g., M2) of a plurality of metallization layers located above the first read transistor 24 and the second read transistor 126 in the BEOL network.

[0092] According to various embodiments, method 900 starts from operation 902, where a substrate is provided. The substrate includes a semiconductor material substrate, such as silicon. Alternatively, the substrate may include other elemental semiconductor materials, such as germanium. The substrate may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate may include alloy semiconductors, such as silicon germanium, silicon carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate includes an epitaxial layer. For example, the substrate may have an epitaxial layer covering a bulk semiconductor. In addition, the substrate may include a semiconductor on insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable techniques (e.g., wafer bonding and grinding).

[0093] Method 900 continues to operation 904, where a stack comprising an alternating series of first and second nanostructures is formed according to various embodiments. Such a stack may be formed based on one of the above-mentioned (active region) patterns. The stack may be formed on the front side of the substrate. In some embodiments, the first nanostructure may include a SiGe sacrificial nanostructure, and the second nanostructure may include a Si channel nanostructure. Such a stack may be referred to as a superlattice. In a non-limiting example, the SiGe sacrificial nanostructure may be SiGe 25%. The symbol "SiGe 25%" is used to indicate that 25% of the SiGe material is Ge. It should be understood that the percentage of Ge in each SiGe sacrificial nanostructure may be any value between 0 and 100 (excluding 0 to 100) while still within the scope of the present disclosure. In some other embodiments, the second nanostructure may include a first semiconductor material other than Si, and the first nanostructure may include a second semiconductor material other than SiGe, as long as the first and second semiconductors have different etching characteristics (e.g., etching rates), respectively.

[0094] The alternating series of nanostructures can be formed by epitaxially growing one layer and then the next layer until the desired number and desired thickness of nanostructures are reached. The epitaxial material can be grown from gaseous or liquid precursors. The epitaxial material can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable processes. Depending on the type of transistor, the epitaxial silicon, silicon germanium and / or carbon-doped silicon (Si:C) can be doped during the deposition process by adding dopants, n-type dopants (such as phosphorus or arsenic) or p-type dopants (such as boron or gallium) (in situ doping).

[0095] The method 900 continues to operation 906, where a plurality of dummy gate structures are formed according to various embodiments. Such dummy gate structures may be formed based on one of the above-described (gate structure) patterns. The dummy gate structures may extend in a direction perpendicular to the length direction of the dielectric fin structure (and stack). In addition, in one of the various embodiments, the dummy gate structures may be formed shorter than the dielectric fin structures, and thus, the formed dummy gate structures are cut (or otherwise separated) by the dielectric fin structures.

[0096] The pseudo gate structure can be formed by depositing amorphous silicon (a-Si) on the stack. Other materials suitable for forming the pseudo gate (e.g., polysilicon) can be used while still within the scope of the present disclosure. The a-Si is then flattened to the desired level. A hard mask is deposited and patterned on the flattened a-Si. The hard mask can be formed by a nitride or oxide layer. An etching process (e.g., a reactive ion etching (RIE) process) is applied to the a-Si to form a pseudo gate structure. After the pseudo gate structure is formed, a gate spacer can be formed to extend along the sidewall of the pseudo gate structure. The gate spacer can be formed by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials) followed by directional etching (e.g., RIE).

[0097] According to various embodiments, method 900 proceeds to operation 908, where an internal spacer is formed by replacing the end of each SiGe sacrificial nanostructure with a dielectric material. After forming a pseudo gate structure covering certain portions of the stack (e.g., portions of the stack separated by a dielectric fin structure), the non-covered portions of the stack are removed. Next, the corresponding ends of each SiGe sacrificial nanostructure covering the stack are removed. The internal spacer is formed by filling the recess of each SiGe sacrificial nanostructure with a dielectric material by chemical vapor deposition (CVD), or by single-layer doping (MLD) of nitride followed by spacer RIE. The material of the internal spacer can be formed of the same or different material as the gate spacer described above. For example, the internal spacer can be formed of silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxycarbonitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k less than about 5).

[0098] According to various embodiments, method 900 continues to operation 910, where a plurality of epitaxial structures are formed. After forming the internal spacers, an epitaxial structure is formed on the exposed end of the Si nanostructure using an epitaxial layer growth process. In-situ doping (ISD) can be applied to form a doped epitaxial structure to create the necessary junctions for the corresponding transistors (or sub-transistors). N-type and p-type FETs are formed by injecting different types of dopants into selected areas of the device to form the necessary junctions. N-type devices can be formed by injecting arsenic (As) or phosphorus (P), and P-type devices can be formed by injecting boron (B). After the epitaxial structure is formed, an interlayer dielectric (e.g., silicon dioxide) is deposited to cover the epitaxial structure.

[0099] Method 900 proceeds to operation 912, where the dummy gate structure and the remaining SiGe sacrificial nanostructures are replaced with corresponding active gate structures according to various embodiments. After forming the interlayer dielectric, the dummy gate structure is removed by an etching process (e.g., RIE or chemical oxide removal (COR)). Next, the remaining SiGe sacrificial nanostructures are removed by applying a selective etch (e.g., hydrochloric acid (HCl)) while keeping the Si channel nanostructures substantially intact. After removing the SiGe sacrificial nanostructures, the top surface, bottom surface, and sidewalls of each Si channel nanostructure can be exposed, except for the sidewalls in contact with the dielectric fin structure. Next, multiple active gate structures can be formed to wrap each silicon channel nanostructure, except for the sidewalls in contact with the dielectric fin structure. Each active gate structure includes at least a gate dielectric layer (e.g., a high-k dielectric layer) and a gate metal layer (e.g., a work function metal layer). After forming the active gate structure, one or more transistors of the memory device can be formed. Referring to, for example Figure 4 , the first and second read transistors 124 and 126 of the memory device 400 are formed along the main surface of the front side 403 of the substrate 401 in the FEOL network.

[0100] Method 900 continues to operation 914, where a plurality of front-side interconnect structures are formed according to various embodiments. After forming the read transistors (e.g., 124 and 126), a plurality of middle-end interconnect structures (e.g., VG and MD) are formed above the read transistors. For example, referring to Figure 4 , multiple VGs (e.g., VG1 and VG2) can be formed to couple to the gate terminals of the read transistors 124 and 126, respectively, and multiple MDs (e.g., 422, 424, and 426) can be formed to connect to the source / drain terminals of the read transistors 24 and 126, respectively. In addition, multiple back-end interconnect structures can be formed on the intermediate end interconnect structure. The back-end interconnect structure includes, for example, an M0 metal track in the M0 layer (e.g., 432, 434, and 436), an M1 metal track in the M1 layer (e.g., 442 and 444), and an M2 metal track in the M2 layer (i.e., 452, 454, and 456), as well as other metal tracks in the upper metallization layer (not shown). Each of the read transistors 124 and 126 can be enabled by at least VG. In some embodiments, as Figure 4 As shown, read transistors 124 and 126 are typically gated by read word line WLR1 via metal track 434 , and are typically coupled to bit line BL1 via MD 424 .

[0101] The front-side interconnect structure can be formed of a metal material. The metal material can be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium and combinations thereof. Other metal materials are also within the scope of the present disclosure. The front-side interconnect structure can be formed by covering the front side of the substrate with the above metal materials, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating or a combination thereof.

[0102] The method 900 proceeds to operation 916, where a first programming transistor and a second programming transistor are formed in a first metallization layer of a plurality of metallization layers located above the first read transistor and the second read transistor in the BEOL network. Similarly, at least some of the above processes for forming the read transistor can be used to form the programming transistor. Figure 4 In the memory device 400, the first programming transistor 120 and the second programming transistor 122 are formed in the metallization layer M2 above the first read transistor 124 and the second read transistor 126 in the BEOL network, and the first read transistor 124 and the second read transistor 126 are formed along the main surface of the front side 403 of the substrate 401 in the FEOL network. The first and second programming transistors 120 and 122 are respectively selected to the WLP through the front side interconnect structure. 10 and WLP 11 And through the front-side interconnect structure, the first read transistor 124 and the second read transistor 126 are respectively connected in series to the first programming transistor 120 and the second programming transistor 122. In some embodiments, the source / drain terminals of the first programming transistor 120 and the source / drain terminals of the second programming transistor 122 are commonly connected and floating.

[0103] The method 900 continues to operation 918, where a plurality of backside interconnect structures are formed according to various embodiments. After forming the back-end metal tracks, the substrate is flipped over and a plurality of backside interconnect structures (e.g., BM0, BM1, BM3 tracks) are formed on the back side of the substrate. For example, after flipping the substrate, a polishing process may be performed on the back side of the substrate until the bottom surface of the epitaxial structure (e.g., the source / drain terminals formed in operation 910) is exposed. Next, one or more dielectric layers are formed on the polished backside surface, and then backside via structures are formed, each of which may extend through the one or more dielectric layers to the bottom surface of the corresponding epitaxial structure. Next, the backside interconnect structures may be formed in the corresponding backside metallization layer.

[0104] The backside interconnect structure is formed of a metal material. The metal material can be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium and combinations thereof. Other metal materials are also within the scope of the present disclosure. The backside interconnect structure can be formed by covering the back side of the substrate with the above-mentioned metal material, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating or a combination thereof.

[0105] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes an anti-fuse memory cell configured to present a first logic state or a second logic state. The memory cell is formed on the front side of the substrate and includes at least a first programming transistor, which is formed in a first metallization layer of a plurality of metallization layers disposed above the front side and is gated by a first programming word line; and a first read transistor, which is formed in a second metallization layer of a plurality of metallization layers disposed above the front side or is formed along a main surface on the front side, is coupled in series to the first programming transistor and a first bit line, and is gated by a first read word line.

[0106] In some embodiments, the first read transistor is formed along the main surface, and the memory device further includes: a second programming transistor formed in a first metallization layer among the plurality of metallization layers and enabled by a second programming word line; and a second read transistor formed along the main surface, coupled to the second programming transistor and the first bit line, and enabled by a second read word line.

[0107] In some embodiments, the first gate dielectric layer of the first programming transistor or the second gate dielectric layer of the second programming transistor is configured to be randomly broken down to exhibit the first logic state or the second logic state.

[0108] In some embodiments, the first bit line is formed in a third metallization layer among the plurality of metallization layers, the third metallization layer being different from the first metallization layer and the second metallization layer.

[0109] In some embodiments, the first read transistor is formed in a second metallization layer among the multiple metallization layers, the second metal layer is the same as the first metallization layer among the multiple metallization layers, and the memory device also includes: a second read transistor, formed in the second metallization layer among the multiple metallization layers, coupled to the second bit line, and selected by the second read word line.

[0110] In some embodiments, the first programming transistor is coupled in series between the first read transistor and the second read transistor.

[0111] In some embodiments, the first programming transistor includes a gate metal and a gate dielectric layer below the gate metal, and wherein the gate dielectric layer includes a first dielectric portion and a second dielectric portion.

[0112] In some embodiments, the first dielectric portion is coupled between a gate metal of the first programming transistor and the first read transistor, and wherein the second dielectric portion is coupled between the gate metal of the first programming transistor and the second read transistor.

[0113] In some embodiments, the first dielectric portion or the second dielectric portion is configured to randomly breakdown, wherein the first dielectric portion is broken down to assume a first logic state, and wherein the second dielectric portion is broken down to assume a second logic state.

[0114] In some embodiments, the first bit line and the second bit line are formed on a third metallization layer among the plurality of metallization layers, the third metallization layer being different from the first metallization layer and the second metallization layer.

[0115] In another aspect of the present disclosure, a memory system is disclosed. The memory system includes a memory array and an authentication circuit, the memory array including a plurality of anti-fuse memory cells formed on the front side of a substrate, the authentication circuit being operably coupled to the memory array and configured to generate bits of a physical unclonable function (PUF) signature for each memory cell based on the logic state of each of the memory cells. Each memory cell presents a logic state of a first logic state or a second logic state. Each memory cell includes at least a first programming transistor, which is formed in a first metallization layer of a plurality of metallization layers disposed above the front side and is gated by a first programming word line; and a first read transistor, which is formed in a second metallization layer of a plurality of metallization layers disposed above the front side or is formed along a main surface on the front side, coupled to the first programming transistor and a first bit line, and gated by a first read word line.

[0116] In some embodiments, the first read transistor is formed along the main surface, and each memory cell further includes: a second programming transistor formed in a first metallization layer among the plurality of metallization layers and enabled by a second programming word line; and a second read transistor formed along the main surface, coupled to the second programming transistor and the first bit line, and enabled by a second read word line.

[0117] In some embodiments, the first gate dielectric layer of the first programming transistor or the second gate dielectric layer of the second programming transistor is configured to be randomly broken down to exhibit the first logic state or the second logic state.

[0118] In some embodiments, the memory system also includes an input / output circuit operably coupled to the memory array and configured to: turn on a first read transistor and a second read transistor of one of the memory cells; and simultaneously apply a programming voltage to a first gate terminal of a first programming transistor of the memory cell.

[0119] In some embodiments, the first read transistor is formed in a second metallization layer among the plurality of metallization layers, the second metallization layer is the same as the first metallization layer, and each memory cell further includes: a second read transistor formed in a second metallization layer among the plurality of metallization layers, coupled to the second bit line, and selected by the second read word line.

[0120] In some embodiments, the first programming transistor is coupled in series between the first read transistor and the second read transistor, and wherein the first programming transistor includes a gate metal and a gate dielectric layer below the gate metal, the gate dielectric layer including a first dielectric portion and a second dielectric portion.

[0121] In some embodiments, the first dielectric portion is coupled between a gate metal of the first programming transistor and the first read transistor, and wherein the second dielectric portion is coupled between the gate metal of the first programming transistor and the second read transistor.

[0122] In some embodiments, the first dielectric portion or the second dielectric portion is configured to randomly breakdown, wherein the first dielectric portion is broken down to assume a first logic state, and wherein the second dielectric portion is broken down to assume a second logic state.

[0123] In another aspect of the present disclosure, a method for manufacturing a memory device is disclosed. The method includes: forming a first read transistor along a main surface on a front side of a substrate; forming a first metallization layer of a plurality of metallization layers disposed above the first read transistor to connect a gate of the first read transistor to a first read word line and connect the first read transistor to a first bit line; forming a second metallization layer of a plurality of metallization layers above the first metallization layer of the plurality of metallization layers; forming a first programming transistor in the second metallization layer of the plurality of metallization layers; and forming a third metallization layer of a plurality of metallization layers above the first metallization layer of the plurality of metallization layers to connect a gate of the first programming transistor to a first programming word line and connect the first programming transistor to the first read transistor.

[0124] In some embodiments, the method also includes: forming a second read transistor simultaneously with the first read transistor along the main surface on the front side of the substrate; and forming a second programming transistor simultaneously with the first programming transistor in a second metallization layer among the multiple metallization layers, wherein the first read transistor and the second read transistor are commonly connected to a first bit line, wherein the first bit line is formed in a first metallization layer among the multiple metallization layers, and wherein the first programming transistor and the second programming transistor are commonly connected to each other.

[0125] As used herein, the terms "about" and "approximately" generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0126] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: An anti-fuse memory cell configured to assume a first logic state or a second logic state, wherein the memory cell is formed on a front side of a substrate and comprises at least: a first programming transistor formed in a first metallization layer of a plurality of metallization layers disposed over the front side and gated by a first programming word line; and A first read transistor, formed in a second metallization layer of the plurality of metallization layers disposed over the front side or formed along a major surface on the front side, is coupled in series to the first programming transistor and a first bit line and is gated by a first read word line.

2. The memory device according to claim 1, wherein: The first read transistor is formed along the main surface, and the memory device further includes: a second programming transistor formed in the first of the plurality of metallization layers and gated by a second programming word line; and A second read transistor, formed along the main surface, is coupled to the second programming transistor and the first bit line, and is gated by a second read word line.

3. The memory device according to claim 2, wherein: The first gate dielectric layer of the first programming transistor or the second gate dielectric layer of the second programming transistor is configured to be randomly broken down to exhibit the first logic state or the second logic state.

4. The memory device according to claim 1, wherein: The first bit line is formed in a third metallization layer among the plurality of metallization layers, the third metallization layer being different from the first metallization layer and the second metallization layer among the plurality of metallization layers.

5. The memory device according to claim 1, wherein: The first read transistor is formed in a second metallization layer among the plurality of metallization layers, the second metallization layer being the same as a first metallization layer among the plurality of metallization layers, the memory device further comprising: A second read transistor is formed in a second metallization layer among the plurality of metallization layers, coupled to the second bit line, and gated by a second read word line.

6. The memory device according to claim 5, wherein: The first bit line and the second bit line are formed in a third metallization layer among the plurality of metallization layers, the third metallization layer being different from the first metallization layer and the second metallization layer.

7. A memory system comprising: A memory array comprising a plurality of anti-fuse memory cells formed on a front side of a substrate, each of the memory cells exhibiting a logic state of a first logic state or a second logic state, and comprising at least: a first programming transistor formed in a first metallization layer of a plurality of metallization layers disposed over the front side and gated by a first programming word line; and a first read transistor formed in a second metallization layer of the plurality of metallization layers disposed over the front side or formed along a major surface on the front side, coupled to the first programming transistor and a first bit line, and gated by the first read word line; and An authentication circuit is operably coupled to the memory array and configured to generate bits of a physically unclonable function signature for each of the memory cells based on a logic state of each of the memory cells.

8. The memory system according to claim 7, wherein: The first read transistor is formed along the main surface, and each of the memory cells further comprises: a second programming transistor formed in a first metallization layer of the plurality of metallization layers and gated by a second programming word line; and A second read transistor, formed along the main surface, is coupled to the second programming transistor and the first bit line, and is gated by the second read word line.

9. The memory system according to claim 8, further comprising: An input / output circuit operatively coupled to the memory array and configured to: turning on the first read transistor and the second read transistor of one of the memory cells; as well as A programming voltage is simultaneously applied to the first gate terminal of the first programming transistor of the memory cell.

10. A method for manufacturing a semiconductor device, comprising: forming a first read transistor along a major surface on a front side of the substrate; forming a first metallization layer of a plurality of metallization layers disposed above a first read transistor to connect a gate of the first read transistor to a first read word line and to connect the first read transistor to a first bit line; forming a second metallization layer among the plurality of metallization layers over the first metallization layer among the plurality of metallization layers; forming a first programming transistor in the second metallization layer of the plurality of metallization layers; as well as A third metallization layer of the plurality of metallization layers is formed over the first metallization layer of the plurality of metallization layers to connect a gate of the first programming transistor to a first programming word line and to connect the first programming transistor to the first read transistor.

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