Vertical cavity surface emitting type laser array and forming method thereof
By filling the isolation trench in the vertical cavity surface-based laser array and using fillers of different materials, the problem of difficulty in controlling leakage current and photoresist layer thickness is solved, and the reliability of the vertical cavity surface-based laser array is improved. and performance.
Patent Information
- Application Number
- CN202410869627.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-06
- Filing Date
- 2024-07-01
- Publication Date
- 2025-01-07
AI Technical Summary
The existing vertical cavity surface-based laser arrays are prone to leakage current problems when operating at high voltages, and the thickness of the photoresist layer is difficult to control in subsequent processes, which affects reliability.
By filling isolation trenches between vertical cavity surface-onset lasers and using fillers of different materials, the height difference is reduced and a thinner photoresist layer is used in the etching process to avoid leakage current and improve reliability.
Effectively reduce leakage current, improve the reliability and efficiency of vertical cavity surface-based laser arrays, and use of thinner photoresist layers in the patterning process improves yield.
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Figure CN119275718A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to a vertical-cavity surface-emitting laser (VCSEL) array, and more particularly to a two-dimensional VCSEL array and a method for forming the same. Background Art
[0002] VCSEL is a semiconductor laser diode that emits a laser beam perpendicular to its surface. VCSEL can be tested during the production process. VCSEL is widely used in various fields, such as light detection and ranging (LiDAR), fiber optic communication and biometrics.
[0003] For a two-dimensional VCSEL array, both the anode and cathode can be formed on the top surface of the substrate. A trench can be formed between the VCSELs for isolation. However, this may increase the challenges of subsequent processes. For example, the photoresist layer required to pattern subsequent layers may be too thick, leading to reliability issues. In addition, since the product may operate at high voltage, there may be leakage current at the trench.
[0004] Although existing VCSEL arrays are adequate for their original purpose, they are not satisfactory in all aspects and need to be improved. Summary of the invention
[0005] An embodiment of the present invention provides a vertical cavity surface emitting laser array, comprising: a substrate, an active layer, a contact layer, and an isolation groove. The active layer is formed between a lower mirror and an upper mirror. The contact layer is formed between the active layer and the substrate. The isolation groove extends through the contact layer between a first vertical cavity surface emitting laser and a second vertical cavity surface emitting laser of the vertical cavity surface emitting laser array, and the isolation groove is filled with a filler.
[0006] The embodiment of the present invention also provides a vertical cavity surface emitting laser array, comprising: a substrate, a lower mirror, an active layer, an upper mirror, a contact layer, a first electrode, a second electrode, an isolation groove, and a dielectric layer. The lower mirror has an isolation layer formed on the substrate; an active layer formed on the lower mirror; an upper mirror formed on the active layer; a contact layer formed on the isolation layer; a first electrode formed on the upper mirror; a second electrode formed on the contact layer; an isolation groove surrounding the vertical cavity surface emitting laser of the vertical cavity surface emitting laser array; and a dielectric layer formed on the second electrode, wherein the isolation groove is filled with a filler made of a material different from that of the dielectric layer.
[0007] An embodiment of the present invention further provides a method for forming a vertical cavity surface emitting laser array, comprising: forming a lower mirror and a contact layer on a substrate; forming an active layer on the lower mirror; forming an upper mirror on the active layer; patterning the upper mirror, the active layer, and the lower mirror to form a table on the contact layer; forming a first electrode on the table; forming a second electrode on the contact layer; forming an isolation trench in the contact layer and the lower mirror; and filling the isolation trench with a filler. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] The following will be described in detail with reference to the accompanying drawings. It should be noted that the various characteristic components are not drawn to scale and are only used for illustration. In fact, the size of the components may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.
[0009] Figure 1A-1E are cross-sectional views illustrating various stages of forming a vertical cavity surface emitting laser array according to some embodiments.
[0010] Figure 2 FIG. 1 is a top view of a vertical cavity surface emitting laser array according to some embodiments.
[0011] Figure 3 is an enlarged cross-sectional view of a vertical cavity surface emitting laser array according to some embodiments.
[0012] Figure 4 is an enlarged cross-sectional view illustrating a modified VCSEL array according to some embodiments.
[0013] Figure 5 is a cross-sectional view illustrating a modified VCSEL array according to some embodiments.
[0014] Figure 6 is a cross-sectional view illustrating a modified VCSEL array according to some embodiments.
[0015] Figure 7 is a cross-sectional view illustrating a modified VCSEL array according to some embodiments.
[0016] Figure 8 is a cross-sectional view illustrating a modified VCSEL array according to some embodiments.
[0017] Fig. 9 is a cross-sectional view illustrating a modified VCSEL array according to some embodiments.
[0018] Fig.10 is a cross-sectional view illustrating a modified VCSEL array according to some embodiments.
[0019] Fig.11is a cross-sectional view illustrating a modified VCSEL array according to some embodiments.
[0020] Description of reference numerals:
[0021] 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i: Vertical Cavity Surface Emitting Laser Array
[0022] 100: Vertical Cavity Surface Emitting Laser
[0023] 102:Substrate
[0024] 104: First Mirror
[0025] 104': Middle mirror
[0026] 106: Contact layer
[0027] 107: Active layer
[0028] 107': Semiconductor layer
[0029] 108: Second Mirror
[0030] 110: first electrode
[0031] 112a: first insulating layer
[0032] 112b: second insulating layer
[0033] 112c: third insulating layer
[0034] 112d: fourth insulating layer
[0035] 112e: fifth insulating layer
[0036] 112f: Sixth insulation layer
[0037] 114: Groove
[0038] 115: Countertop
[0039] 116: Oxide layer
[0040] 118: Porosity
[0041] 120: Opening
[0042] 122: Second electrode
[0043] 124: Isolation groove
[0044] 126: Filling
[0045] 126H:Height
[0046] 126D: Depth
[0047] 126a: Angle
[0048] 126W: Bottom width
[0049] 128: Opening
[0050] 130a: first bonding pad layer
[0051] 130b: second bonding pad layer
[0052] 132: Opening
[0053] 134: Opening
[0054] 150: Isolation layer
[0055] 1-1: Line DETAILED DESCRIPTION
[0056] The following disclosure provides many different embodiments or examples to implement the different features of the present invention. The following disclosure describes specific examples of various components and their arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes a first characteristic component formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and may also include an embodiment in which an additional characteristic component is formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the embodiments of the present invention, and do not represent a specific relationship between the different embodiments and / or structures discussed.
[0057] In addition, spatially relative terms may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These spatially relative terms are used to facilitate the description of the relationship between one (or some) elements or features and another (or some) elements or features in the diagram. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the orientation after the rotation.
[0058] Here, the terms "about", "approximately", and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meanings of "about", "approximately", and "generally" can still be implied.
[0059] Although the steps in some of the embodiments described are performed in a particular order, the steps may be performed in other logical orders. In different embodiments, some of the steps described may be replaced or omitted, and other operations may be performed before, during, and / or after the steps described in the embodiments of the present invention. Other features may be added to the semiconductor structures in the embodiments of the present invention. In different embodiments, some features may be replaced or omitted.
[0060] The embodiment of the present invention provides a two-dimensional vertical cavity surface emitting laser array. The grooves between the vertical cavity surface emitting lasers are filled with fillers. The height difference of the vertical cavity surface emitting laser array is reduced, and a thinner photoresist layer can be used in an etching process (e.g., an etching process for forming a guide hole). In addition, leakage current passing through the groove can be avoided.
[0061] Figures 1A-1E FIG. 4 is a cross-sectional view illustrating various stages of forming a vertical cavity surface emitting laser array 10 a according to some embodiments. Figure 2 FIG. 1 is a top view of a VCSEL array 10 a according to some embodiments. Figures 1A-1E Draw along Figure 2 Cross-sectional view taken along the center line 1-1.
[0062] According to some embodiments, Figure 1A As shown, a substrate 102 is provided. The substrate 102 may be a semiconductor substrate. The substrate 102 may include a III-V semiconductor, such as GaAs, GaN, AlGaN, AlN, AlGaAs, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the substrate 102 includes GaAs. In some embodiments, the substrate 102 is n-type doped or p-type doped. In some embodiments, the substrate 102 is a semi-insulating substrate.
[0063] Next, according to some embodiments, Figure 1A As shown, a first mirror 104 is formed on a substrate 102. The first mirror 104 may include an n-type mirror, a p-type mirror, an undoped mirror, or a combination thereof. In some embodiments, the conductivity type of the upper portion of the first mirror 104 is opposite to the conductivity type of the lower portion of the first mirror 104.
[0064] In some embodiments, the first mirror 104 includes a first semiconductor layer and a second semiconductor layer. The first mirror 104 includes a first semiconductor layer and a second semiconductor layer alternately stacked on the substrate 102. The first semiconductor layer and the second semiconductor layer are used in pairs. The first semiconductor layer and the second semiconductor layer may include a III-V semiconductor, such as AlGaAs, GaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. The first semiconductor layer and the second semiconductor layer may be made of different materials with different refractive indices. The first semiconductor layer and the second semiconductor layer may have a first conductivity type. In some embodiments, the first conductivity type is n-type. The first mirror 104 may be referred to as a distributed Bragg reflector of the first conductivity type. The thickness of each of the first semiconductor layer and the second semiconductor layer may depend on the central wavelength of the laser light generated by the vertical cavity surface emitting laser 100 in the vertical cavity surface emitting laser array 10a. The first semiconductor layer and the second semiconductor layer may be formed by a low pressure chemical vapor deposition (LPCVD) process, an epitaxial growth process, other available processes, or a combination thereof. The epitaxial growth process may include molecular-beamepitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE). The total number of pairs of the first semiconductor layer and the second semiconductor layer may depend on design requirements and is not particularly limited.
[0065] According to some embodiments, Figure 1A As shown, a contact layer 106 is formed on the first mirror 104. The contact layer 106 may be an etch stop layer in a subsequent etching process for forming a mesa. The contact layer 106 may be made of a semiconductor layer electrically connected to a subsequently formed electrode. The contact layer 106 may include a III-V semiconductor, such as AlGaAs, GaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, other available materials, or combinations thereof. The contact layer 106 may be formed by a low pressure chemical vapor deposition process, an epitaxial growth process, other available processes, or combinations thereof. The epitaxial growth process may include molecular beam epitaxy, metal organic chemical vapor deposition, or vapor phase epitaxy.
[0066] Next, according to some embodiments, the intermediate mirror 104' is formed on the contact layer 106. The process and materials used to form the intermediate mirror 104' may be similar or the same as the process and materials used to form the first mirror 104, and are not repeated here for the sake of brevity.
[0067] Then, according to some embodiments, Figure 1A As shown, an active layer 107 is formed on the first mirror 104. The active layer 107 may be a multi-layer structure.
[0068] The active layer 107 may include a plurality of quantum wells and quantum well barriers. The quantum wells and quantum well barriers may include III-V semiconductors, such as AlGaAs, GaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. The quantum wells and quantum well barriers may be made of different materials, and the quantum well barriers may have a larger energy band gap than the quantum wells. The active layer 107 may generate the optical power of the VCSEL array 10a.
[0069] In some embodiments, the active layer 107 includes multiple active junction layers, which have tunneling junction layers sandwiched between active junction layers. In some embodiments, the active junction layer of the active layer 107 includes an undoped semiconductor layer sandwiched between a p-type doped semiconductor layer and an n-type doped semiconductor layer. In some embodiments, the tunneling junction layer may include an n-type doped semiconductor layer and a p-type doped semiconductor layer. In some embodiments, the dopant concentration of the tunneling junction layer is greater than that of the p-type doped semiconductor layer and the n-type doped semiconductor layer of the active junction layer.
[0070] The active layer 107 includes a plurality of quantum wells and quantum well barriers, and can be formed by a low pressure chemical vapor deposition process, an epitaxial growth process, other applicable processes, or a combination thereof. The epitaxial growth process may include molecular beam epitaxy, metal organic chemical vapor deposition, or vapor phase epitaxy. The active layer 107 can separate the first mirror 104 below and the second mirror formed subsequently.
[0071] Next, a semiconductor layer 107' is formed on the active layer 107. The semiconductor layer 107' may include a III-V semiconductor, such as GaAs, AlGaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the semiconductor layer 107' includes AlGaAs. The semiconductor layer 107' may be formed by a low pressure chemical vapor deposition process, an epitaxial growth process, other available processes, or a combination thereof. The epitaxial growth process may include molecular beam epitaxy, metal organic chemical vapor deposition, or vapor phase epitaxy.
[0072] Next, according to some embodiments, Figure 1A As shown in FIG. 1 , a second mirror 108 is formed on the semiconductor layer 107 ′. The second mirror 108 may include an n-type mirror, a p-type mirror, an undoped mirror, or a combination thereof. In some embodiments, the conductivity type of the upper portion of the second mirror 108 is opposite to the conductivity type of the lower portion of the second mirror 108 .
[0073] The second mirror 108 may include a third semiconductor layer and a fourth semiconductor layer, which are alternately stacked on the semiconductor layer 107'. The third semiconductor layer and the fourth semiconductor layer may include a III-V semiconductor, such as AlGaAs, GaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. The third semiconductor layer and the fourth semiconductor layer may be made of different materials with different refractive indices. In some embodiments, the third semiconductor layer and the fourth semiconductor layer have a second conductivity type. In some embodiments, the second conductivity type is p-type. The second mirror 108 may be referred to as a distributed Bragg reflector of the second conductivity type. The process used to form the second mirror 108 may be similar or the same as the process used to form the first mirror 104 described above, and for the sake of brevity, it is not repeated here. The number of the third semiconductor layer and the fourth semiconductor layer is not limited thereto and depends on the design requirements.
[0074] Next, according to some embodiments, Figure 1A As shown in FIG. 1 , a first electrode material is formed on the second mirror 108. In some embodiments, an ohmic contact is formed between the first electrode material and the second mirror 108. The first electrode material may include Pt, Ti, Au, Al, Pd, Cu, W, other suitable metals, alloys thereof, or combinations thereof. The first electrode material may be formed on the second mirror 108 by electron beam evaporation, resistance heating evaporation, electroplating, sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, other available methods, or combinations thereof. In some embodiments, the first electrode material is formed by electron beam evaporation. Then, according to some embodiments, as Figure 1A As shown in FIG. 1 , the first electrode material is patterned to form the first electrode 110 on the second mirror 108 .
[0075] Next, according to some embodiments, Figure 1A As shown in FIG. 1 , a first insulating layer 112a is conformally formed on the first electrode 110 and the second mirror 108. The first insulating layer 112a may be made of silicon nitride, aluminum oxide, other suitable insulating materials, or a combination thereof. In some embodiments, the first insulating layer 112a includes silicon nitride. The first insulating layer 112a may be formed by a deposition process. The deposition process may include a chemical vapor deposition process (e.g., low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or flowable chemical vapor deposition), an atomic layer deposition process, other available methods, or a combination thereof.
[0076] Next, according to some embodiments, Figure 1AAs shown in , a groove 114 is formed through the first insulating layer 112a, the second mirror 108, the semiconductor layer 107', the active layer 107, the intermediate mirror 104', and stops on the contact layer 106. In some embodiments, a table 115 is formed on the contact layer 106, and a first electrode 110 is formed on the table 115. A patterning process can be performed to form the groove 114. The patterning process may include a photolithography process and an etching process. Examples of photolithography processes include photoresist coating, soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may be a dry etching process or a wet etching process. In some embodiments, the etching process is reactive ion etching (RIE) using inductively coupled plasma (ICP) as an etchant.
[0077] Then, if Figure 1B As shown in FIG. 1 , a portion of the semiconductor layer 107' is oxidized to form an oxide layer 116. The semiconductor layer 107' may include a high Al component. The Al component may affect the oxidation rate. The oxide layer 116 may include Al2O3. In some embodiments, the oxide layer 116 is formed by a furnace oxidation process.
[0078] In some embodiments, only a portion of the semiconductor layer 107' is oxidized. In some embodiments, the unoxidized portion of the semiconductor layer 107' can serve as the pore 118. The pore 118 can include a III-V semiconductor, such as AlGaAs, GaAs, AlAs, GaN, AlGaN, AlN, InP, InAlAs, InGaAs, or a combination thereof. In some embodiments, the pore 118 is surrounded by an oxide layer 116. In some embodiments, the second mirror 108 is above the pore 118 and the oxide layer 116. The pore 118 can limit the current flowing from the first electrode 110 through the underlying active layer 107, the intermediate mirror 104', the contact layer 106, and the first mirror 104.
[0079] Then, according to some embodiments, Figure 1BAs shown in FIG. 1 , a second insulating layer 112b is conformally formed on the first insulating layer 112a and on the sidewalls and bottom surface of the trench 114. The second insulating layer 112b may cover the top surface and sidewalls of the mesa 115. The second insulating layer 112b may be made of silicon nitride, aluminum oxide, other suitable insulating materials, or a combination thereof. The second insulating layer 112b may be formed by a chemical vapor deposition process (e.g., low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or flowable chemical vapor deposition), an atomic layer deposition process, other available methods, or a combination thereof. In some embodiments, the second insulating layer 112b and the first insulating layer 112a are made of the same material. Therefore, there may be no obvious interface between the second insulating layer 112b and the first insulating layer 112a.
[0080] Then, according to some embodiments, Figure 1B As shown in FIG. 1 , an opening 120 is formed in the second insulating layer 112b covering the contact layer 106. The contact layer 106 at the bottom of the trench 114 may be exposed from the opening 120. In some embodiments, after the opening 120 is formed, a portion of the contact layer 106 at the bottom of the trench 114 is covered by the second insulating layer 112b. The opening 120 may be formed using a patterning process.
[0081] Next, according to some embodiments, a second electrode material is formed on the contact layer 106. In some embodiments, an ohmic contact is formed between the second electrode material and the contact layer 106. The second electrode material may include Pd, Ge, Ti, Pt, Au, other suitable metals, alloys thereof, or combinations thereof. The second electrode material is patterned to form a second electrode 122 in the opening 120 on the contact layer 106. In some embodiments, the second electrode 122 is separated from the second insulating layer 112b.
[0082] Then, according to some embodiments, Figure 1CAs shown in FIG. 1 , a third insulating layer 112c is conformally formed on the second insulating layer 112b, the second electrode 122, and the sidewalls and bottom surfaces of the trench 114. The third insulating layer 112c may cover the second insulating layer 112b and extend into the trench 114. In some embodiments, the third insulating layer 112c covers the upper surface and sidewalls of the second electrode 122. In some embodiments, the third insulating layer 112c directly contacts the contact layer 106 between the second electrode 122 and the mesa 115. The third insulating layer 112c may be made of silicon nitride, aluminum oxide, other suitable insulating materials, or a combination thereof. The third insulating layer 112c may be formed by a chemical vapor deposition process (e.g., low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or flowable chemical vapor deposition), an atomic layer deposition process, other available methods, or a combination thereof. In some embodiments, the third insulating layer 112c, the second insulating layer 112b, and the first insulating layer 112a are made of the same material. Therefore, there may be no obvious interface in between.
[0083] Next, according to some embodiments, Figure 1C As shown in FIG. 1 , an isolation trench 124 is formed through the third insulating layer 112 c, the second insulating layer 112 b, the contact layer 106, the first mirror 104, and the substrate 102. In some embodiments, as Figure 2 As shown, an isolation trench 124 is formed between the VCSELs 100 of the VCSEL array 10a. The isolation trench 124 may be formed using a patterning process. In some embodiments, the VCSEL array 10a includes a plurality of VCSELs 100, and adjacent VCSELs 100 of the VCSEL array 10a are electrically isolated from each other by the isolation trench 124. In some embodiments, the VCSEL array 10a includes a plurality of subgroups of VCSELs 100, and adjacent subgroups of VCSELs 100 in the VCSEL array 10a are electrically isolated from each other by the isolation trench 124.
[0084] Then, according to some embodiments, Figure 1CAs shown in FIG. 1 , a fourth insulating layer 112d is conformally formed on the sidewalls and bottom surfaces of the third insulating layer 112c and the isolation trench 124. The fourth insulating layer 112d may cover the third insulating layer 112c. In some embodiments, the fourth insulating layer 112d is formed to line the isolation trench 124. The fourth insulating layer 112d may be made of silicon nitride, aluminum oxide, other suitable insulating materials, or a combination thereof. The fourth insulating layer 112d may be formed by a chemical vapor deposition process (e.g., low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or flowable chemical vapor deposition), an atomic layer deposition process, other available methods, or a combination thereof. In some embodiments, the fourth insulating layer 112d, the third insulating layer 112c, the second insulating layer 112b, and the first insulating layer 112a are made of the same material. Therefore, there may be no obvious interface therebetween.
[0085] Next, according to some embodiments, Figure 1C As shown in FIG. 1 , a filler 126 is filled in the isolation trench 124. The filler 126 may include a metal material (e.g., Au, Cu, Ti, Ni), a polymer material (e.g., benzocyclobutene (BCB), polybenzoxazoles (PBO), polyimide (PI)), and a dielectric material (e.g., SiNx, SiO2, Al2O3, HFO2), amorphous silicon (a-Si), other suitable materials, or a combination thereof. The filler 126 may be formed by electroplating, electron beam evaporation, resistance heating evaporation, sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, other suitable methods, or a combination thereof. In some embodiments, the filler 126 is made of Au formed by electroplating. In some embodiments, the filler 126 is made of a metal material, which has good mechanical properties (e.g., strength, hardness), and can maintain sufficient mechanical properties after subsequent processes (e.g., high temperature processes such as annealing, deposition processes, flip-chip processes, or cutting processes) of manufacturing a vertical cavity surface emitting laser array. In some embodiments, the filler 126 and the fourth insulating layer 112d are made of different materials. In some embodiments, the filler 126 is electrically isolated from the contact layer 106 by the fourth insulating layer 112d. In some embodiments, the filler 126 is made of metal, and the contact layer 106 is made of a semiconductor layer, and they are electrically isolated from each other by the fourth insulating layer 112d.
[0086] Figure 3FIG. 1 is an enlarged cross-sectional view of a VCSEL 100 of a VCSEL array 10a according to some embodiments. In some embodiments, in the cross-sectional view, the filler 126 is T-shaped. In some embodiments, the middle of the top surface of the filler 126 is lower than both ends of the top surface of the filler 126. In some embodiments, the upper portion of the filler 126 extends laterally out of the isolation trench 124.
[0087] In some embodiments, the filler 126 has a bottom width 126W. The bottom width 126W of the filler 126 is in a range of about 1 μm to about 20 μm. In some embodiments, the filler 126 has a depth 126D in the isolation trench 124. The depth 126D of the filler 126 is in a range of about 1 μm to about 10 μm. In some embodiments, the ratio of the depth 126D of the filler 126 to the bottom width 126W is in a range of about 0.5 to about 20. If the ratio of the depth 126D of the filler 126 to the bottom width 126W is too high, the filler coverage may be poor, or the device reliability may deteriorate. If the ratio of the depth 126D of the filler 126 to the bottom width 126W is too low, the filler coverage may also be poor, or the design flexibility may be limited.
[0088] In some embodiments, the extended portion of the filler 126 outside the isolation trench 124 has a height 126H. The height 126H of the extended portion of the filler 126 is in a range of about 2 μm to about 10 μm. In some embodiments, the ratio of the height 126H of the extended portion to the depth 126D in the isolation trench 124 is in a range of about 0.2 to about 10. If the ratio of the height 126H of the extended portion to the depth 126D in the isolation trench 124 is too high, the shape fluctuation of the subsequent process may be too large. If the ratio of the height 126H of the extended portion to the depth 126D in the isolation trench 124 is too low, the filler coverage may be poor, or the device reliability may be deteriorated.
[0089] In some embodiments, an angle 126a between the sidewall and the bottom surface of the filler 126 is in a range of about 85 degrees to about 110 degrees. If the angle 126a is too large, the device area may become too large. If the angle 126a is too small, it may be difficult to fill the filler in the isolation trench 124.
[0090] Then, according to some embodiments, Figure 1DAs shown in FIG. 1 , a fifth insulating layer 112e is conformally formed on the fourth insulating layer 112d and the filler 126. The fifth insulating layer 112e may be made of silicon nitride, aluminum oxide, other suitable insulating materials, or a combination thereof. The fifth insulating layer 112e may be formed by a chemical vapor deposition process (e.g., low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or flowable chemical vapor deposition), an atomic layer deposition process, other available methods, or a combination thereof. In some embodiments, the fifth insulating layer 112e, the fourth insulating layer 112d, the third insulating layer 112c, the second insulating layer 112b, and the first insulating layer 112a are made of the same material. Therefore, there may be no obvious interface therebetween.
[0091] Then, according to some embodiments, Figure 1D As shown in FIG. 1 , an opening 128 is formed in the fifth insulating layer 112e, the fourth insulating layer 112d, and the third insulating layer 112c covering the second electrode 122. The second electrode 122 may be exposed from the opening 128. In some embodiments, after the opening 128 is formed, a portion of the second electrode 122 is covered by the third insulating layer 112c. The opening 128 may be formed using a patterning process.
[0092] Next, according to some embodiments, Figure 1E As shown in FIG. 1 , a first bonding pad layer 130a is formed in the opening 128 and covers the filler 126. In some embodiments, the mesa 115 on which the first electrode 110 is formed is exposed from the first bonding pad layer 130a. The first bonding pad layer 130a can be formed by electroplating, electron beam evaporation, resistance heating evaporation, sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof.
[0093] Then, according to some embodiments, Figure 1E As shown in the figure, the sixth insulating layer 112f is conformally formed on the first bonding pad layer 130a and the fifth insulating layer 112e. The sixth insulating layer 112f can be made of silicon nitride, aluminum oxide, other suitable insulating materials, or a combination thereof. The sixth insulating layer 112f can be formed by a chemical vapor deposition process (such as low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or flowable chemical vapor deposition), an atomic layer deposition process, other available methods, or a combination thereof. In some embodiments, the sixth insulating layer 112f, the fifth insulating layer 112e, the fourth insulating layer 112d, the third insulating layer 112c, the second insulating layer 112b and the first insulating layer 112a are made of the same material. Therefore, there may be no obvious interface therebetween.
[0094] Then, according to some embodiments, Figure 1EAs shown in FIG. 1 , an opening 132 is formed in the sixth insulating layer 112f on the first bonding pad layer 130a. The first bonding pad layer 130a may be exposed from the opening 132. The opening 132 may be formed using a patterning process.
[0095] Next, according to some embodiments, Figure 1E As shown in FIG. 1 , an opening 134 is formed in the sixth insulating layer 112f, the fifth insulating layer 112e, the fourth insulating layer 112d, the third insulating layer 112c, the second insulating layer 112b, and the first insulating layer 112a on the first electrode 110. The first electrode 110 may be exposed from the opening 134. The opening 134 may be formed using a patterning process.
[0096] Since the filler 126 is formed in the isolation trench 124, a thinner photoresist layer can be used in the etching process for forming the opening 134 and / or the opening 132. In some embodiments, the reliability and yield of the VCSEL array 10a can be improved by using a thinner photoresist layer in the etching process. For example, the thickness of the photoresist layer used in the etching process is less than 10 μm (e.g., in the range of 2 μm and 9 μm).
[0097] Next, according to some embodiments, Figure 1E As shown in FIG. 1 , the second bonding pad layer 130b is formed in the opening 128 on the first electrode 110 and covers the sixth insulating layer 112f. In some embodiments, the second bonding pad layer 130b partially covers the first bonding pad layer 130a, and the first bonding pad layer 130a is exposed from the opening 132. The second bonding pad layer 130b can be formed by electroplating, electron beam evaporation, resistance heating evaporation, sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, other suitable methods, or combinations thereof.
[0098] In some embodiments, the first electrode 110 and the second electrode 122 are formed on the same side of the substrate 102, and thus the VCSEL array 10a can be bonded to another substrate using a flip chip process, a wafer bonding process, or a combination thereof. In some embodiments, the VCSEL array 10a is bonded to a driver integrated circuit, a submount, a printed circuit board (PCB), or a ceramic substrate by a flip chip process or a wafer bonding process.
[0099] Since the filler 126 is formed in the isolation trench 124 between the VCSELs 100 of the VCSEL array 10a, a thinner photoresist layer can be used in a patterning process (e.g., a patterning process for forming a via on the mesa 115), and thus the reliability and / or yield of the VCSEL array 10a can be improved. In addition, the filler 126 in the isolation trench 124 can reduce leakage current, and thus improve the performance of the VCSEL array 10a.
[0100] In some embodiments, the VCSEL array 10 a can be applied to a light detection and ranging system, a three-dimensional sensing system, a data communication system, or a combination thereof.
[0101] Many variations and / or modifications may be made to the embodiments of the present invention. Figure 4 FIG. 1 is an enlarged cross-sectional view of a modified VCSEL array 10b according to some embodiments. Some processes or components are the same or similar to those in the above-mentioned embodiments, and thus these processes and components are not repeated here. Different from the above-mentioned embodiments, according to some other embodiments, such as Figure 4 As shown, the isolation trench 124 and the filling material 126 have sloped sidewalls.
[0102] In some embodiments, Figure 4 As shown, the angle 126a between the sidewall and the bottom surface of the filling material 126 is in the range of about 110 degrees to about 150 degrees. Since it is easier to form the filling material 126 in the isolation trench 124, the quality of the filling material 126 may be better.
[0103] Since the filler 126 is formed in the isolation trench 124 between the VCSELs 100 of the VCSEL array 10b, a thinner photoresist layer can be used in a patterning process (e.g., a patterning process for forming a via on the mesa 115), and thus the reliability and / or yield of the VCSEL array 10b can be improved. In addition, the filler 126 of the isolation trench 124 can reduce leakage current, and thus improve the performance of the VCSEL array 10b. The isolation trench 124 and the filler 126 can have inclined sidewalls, and the quality of the filler 126 can be improved.
[0104] Many variations and / or modifications may be made to the embodiments of the present invention. Figure 5 FIG. 1 is a cross-sectional view of a modified VCSEL array 10c according to some embodiments. Some processes or components are the same or similar to those in the above-mentioned embodiments, and thus these processes and components are not repeated here. Different from the above-mentioned embodiments, according to some other embodiments, such as Figure 5 As shown, an isolation layer 150 is formed between the substrate 102 and the contact layer 106. In some embodiments, the isolation layer 150 is used to prevent or reduce current from flowing from the active layer 107 to the substrate 102 below.
[0105] In some embodiments, the isolation layer 150 includes an inverted p / n junction, an oxide layer, an undoped semiconductor layer, or a combination thereof. In some embodiments, the isolation layer 150 is inserted into the first mirror 104. Therefore, the current cannot pass from the active layer 107 through the isolation layer 150 to the substrate 102 and / or the lower portion of the first mirror 104.
[0106] like Figure 5 As shown, in some embodiments, the isolation trench 124 is formed through the isolation layer 150, and the filling material 126 is formed in the isolation trench 124. In some embodiments, the bottom surface of the filling material 126 is lower than the isolation layer 150. Therefore, the isolation trench 124 can provide lateral isolation, and the isolation layer 150 can provide vertical isolation.
[0107] Figure 6 1 is a cross-sectional view of a modified VCSEL array 10d according to some embodiments. In some embodiments, the isolation trench 124 extends into the substrate 102. In some embodiments, the bottom surface of the filler 126 in the isolation trench 124 is between the top surface and the bottom surface of the substrate 102. In some embodiments, the bottom surface of the filler 126 is higher than the bottom surface of the substrate 102 and lower than the top surface of the substrate 102.
[0108] Figure 7 1 is a cross-sectional view of a modified VCSEL array 10e according to some embodiments. In some other embodiments, the isolation trench 124 extends into the isolation layer 150. In some embodiments, the bottom surface of the isolation trench 124 is between the top surface and the bottom surface of the isolation layer 150. In some embodiments, the bottom surface of the isolation trench 124 is higher than the bottom surface of the isolation layer 150 and lower than the top surface of the isolation layer 150.
[0109] Figure 8 1 is a cross-sectional view of a modified VCSEL array 10f according to some embodiments. In some embodiments, the isolation trench 124 extends to the top surface of the isolation layer 150. In some embodiments, the isolation trench 124 stops at the top surface of the isolation layer 150. In some embodiments, the bottom surface of the isolation trench 124 is substantially flush with the top surface of the isolation layer 150.
[0110] Since the filler 126 is formed in the isolation trench 124 between the VCSELs 100 of the VCSEL arrays 10d, 10e, and 10f, a thinner photoresist layer can be used in a patterning process (e.g., a patterning process for forming a guide hole on the mesa 115), and thus the reliability and / or yield of the VCSEL arrays 10d, 10e, and 10f can be improved. In addition, the filler 126 of the isolation trench 124 can reduce leakage current, and thus improve the performance of the VCSEL arrays 10d, 10e, and 10f. An isolation layer 150 can be formed in the first mirror 104 to provide vertical isolation and reduce leakage current. The bottom surface of the filler 126 can be located between the top surface and the bottom surface of the substrate 102. The bottom surface of the filler 126 can be located between the top surface and the bottom surface of the isolation layer 150. The bottom surface of the filler 126 may be substantially flush with the top surface or the bottom surface of the isolation layer 150 .
[0111] Many variations and / or modifications may be made to the embodiments of the present invention. Fig. 9 FIG. 1 is a cross-sectional view of a modified VCSEL array 10g according to some embodiments. Some processes or components are the same or similar to those in the above-mentioned embodiments, and thus these processes and components are not repeated here. Different from the above-mentioned embodiments, according to some other embodiments, such as Fig. 9 As shown, the mirror formed on the substrate 102 is an undoped mirror 104a.
[0112] In some embodiments, an isolation trench 124 is formed through the undoped mirror 104a. The undoped mirror 104a may provide vertical isolation. In some embodiments, a bottom surface of the isolation trench 124 is higher than a bottom surface of the undoped mirror 104a.
[0113] Fig.10 FIG. 1 is a cross-sectional view of a modified VCSEL 10h according to some embodiments. In some embodiments, the isolation trench 124 extends to the top surface of the substrate 102. In some embodiments, the bottom surface of the isolation trench 124 is substantially flush with the top surface of the substrate 102.
[0114] Fig.11 1 is a cross-sectional view of a modified VCSEL array 10i according to some embodiments. In some embodiments, the isolation trench 124 extends into the substrate 102. In some embodiments, the bottom surface of the filler 126 in the isolation trench 124 is between the top surface and the bottom surface of the substrate 102. In some embodiments, the bottom surface of the filler 126 is higher than the bottom surface of the substrate 102 and lower than the top surface of the substrate 102.
[0115] Since the filler 126 is formed in the isolation trench 124 between the VCSELs 100 of the VCSEL arrays 10g, 10h, and 10i, a thinner photoresist layer can be used in a patterning process (e.g., a patterning process for forming a via on the mesa 115), and thus the reliability and / or yield of the VCSEL arrays 10g, 10h, and 10i can be improved. In addition, the filler 126 of the isolation trench 124 can reduce leakage current, and thus improve the performance of the VCSEL arrays 10g, 10h, and 10i. The undoped mirror 104a formed on the substrate 102 can provide vertical isolation.
[0116] As described above, in an embodiment of the present invention, a VCSEL array and a method for forming the VCSEL array are provided. An isolation groove filled with filler is formed between the VCSELs. A thinner photoresist layer can be used in a patterning process (e.g., a patterning process for forming a guide hole on a table), and thus the reliability and / or yield of the VCSEL array can be improved. In addition, the filling of the isolation groove can reduce leakage current, and thus improve the performance of the VCSEL array.
[0117] It should be noted that although some benefits and effects are described in the above embodiments, not all embodiments need to achieve all benefits and effects.
[0118] The foregoing text summarizes the characteristic components of many embodiments, so that those skilled in the art can better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention, and thereby achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the invention of the embodiments of the present invention. Without departing from the spirit and scope of the invention of the embodiments of the present invention, various changes, substitutions or modifications can be made to the embodiments of the present invention, so the scope of protection of the present invention shall be determined by the scope of the patent application. In addition, although the present invention has been disclosed as above with several preferred embodiments, it is not intended to limit the present invention, and not all advantages have been described in detail herein.
Claims
1. A vertical cavity surface emitting laser array, characterized in that: include: a substrate; An active layer formed between a lower mirror and an upper mirror; a contact layer formed between the active layer and the substrate; as well as An isolation trench extends through the contact layer between a first VCSEL and a second VCSEL of the VCSEL array, and the isolation trench is filled with a filler.
2. The vertical cavity surface emitting laser array according to claim 1, wherein: Also includes: An isolation layer is formed between the substrate and the contact layer.
3. The vertical cavity surface emitting laser array according to claim 2, wherein: The isolation layer is inserted into the lower mirror.
4. The vertical cavity surface emitting laser array according to claim 2, wherein: A bottom surface of the filler is lower than the isolation layer.
5. The vertical cavity surface emitting laser array according to claim 1, wherein: The isolation trench has an inclined sidewall.
6. The vertical cavity surface emitting laser array according to claim 1, wherein: The lower mirror is undoped.
7. The vertical cavity surface emitting laser array according to claim 1, wherein: In a cross-sectional view, the filler is T-shaped.
8. A vertical cavity surface emitting laser array, characterized in that: include: A lower mirror having an isolation layer formed on a substrate; an active layer formed on the lower mirror; an upper mirror formed on the active layer; a contact layer formed on the isolation layer; a first electrode formed on the upper mirror; a second electrode formed on the contact layer; an isolation trench surrounding a VCSEL of the VCSEL array; as well as A dielectric layer is formed on the second electrode, and the isolation trench is filled with a filler made of a material different from that of the dielectric layer.
9. The vertical cavity surface emitting laser array according to claim 8, wherein: Also includes: An insulating layer is lined in the isolation trench.
10. The vertical cavity surface emitting laser array according to claim 9, wherein: The filler is electrically isolated from the contact layer by the insulating layer.
11. The vertical cavity surface emitting laser array according to claim 9, wherein: A top of the filling material extends laterally out of the isolation trench.
12. The vertical cavity surface emitting laser array according to claim 9, wherein: The filler includes metal, polymer, or a combination of metal and polymer.
13. The vertical cavity surface emitting laser array according to claim 8, wherein: The substrate is n-type doped or p-type doped.
14. The vertical cavity surface emitting laser array according to claim 8, wherein: The substrate is a semi-insulating substrate.
15. A method for forming a vertical cavity surface emitting laser array, characterized in that: include: forming a lower mirror and a contact layer on a substrate; forming an active layer on the lower mirror; forming an upper mirror on the active layer; Patterning the upper mirror and the active layer to form a mesa on the contact layer; forming a first electrode on the mesa; forming a second electrode on the contact layer; forming an isolation trench in the contact layer and the lower mirror; and The isolation trench is filled with a filler.
16. The method for forming a vertical cavity surface emitting laser array according to claim 15, wherein: The lower mirror includes an isolation layer.
17. The method for forming a vertical cavity surface emitting laser array according to claim 15, wherein: The active layer includes multiple junction layers, with a tunneling junction layer sandwiched between the active junction layers.
18. The method for forming a vertical cavity surface emitting laser array according to claim 17, wherein: The active junction layer includes an undoped semiconductor layer sandwiched between a p-type doped semiconductor layer and an n-type doped semiconductor layer.
19. The method for forming a vertical cavity surface emitting laser array according to claim 15, wherein: The first electrode and the second electrode are formed on a same side of the substrate.
20. The method for forming a vertical cavity surface emitting laser array according to claim 15, wherein: The substrate is an n-type substrate.