Detection of leakage current in smart semiconductor switches

Abstract

The invention relates to detection of leakage current in smart semiconductor switches. Embodiments relate to a method for a smart semiconductor switch. The method includes activating a semiconductor switch that connects a supply node providing a supply voltage with an output node connected to a connected electrical load. As a result, the output voltage is applied to the electrical load. The method also includes performing a leakage current test. To this end, the semiconductor switch is deactivated in order to separate the electrical load from the power supply node. Further, it is checked whether the time elapsed until the output voltage is below the first voltage level is less than a (time) threshold. Finally, the semiconductor switch is activated again.

Description

Technical Field

[0001] This specification relates to the field of intelligent semiconductor switches. Background Art

[0002] Different types of semiconductor switches are known. For example, metal oxide semiconductor (MOS) field effect transistors (MOSFET) are used in various applications, for example to replace mechanical switches or fuses. One or more MOSFETs can be integrated in a semiconductor chip together with associated drive circuits and control logic, (current and temperature) sensor circuits and further circuits. In this context, people often refer to intelligent semiconductor switches or intelligent switches.

[0003] Intelligent semiconductor switches can be used in a variety of applications. In the automotive sector, such semiconductor switches can not only be used as electronic fuses (so-called e-fuses). Here, the switch is switched on most of the time, even when the connected load is inactive. In this case, the load current flowing through the semiconductor switch can be very small (e.g. in the μA range), whereas in the case of an active load, the load current can be several amperes.

[0004] Intelligent semiconductor switches may have significant internal consumption. Therefore, for some applications, the intelligent semiconductor switch is designed so that it can be operated in an idle mode with low power consumption. In this idle mode, most of the internal circuits of the semiconductor switch (such as sensors and diagnostic functions, charge pumps, etc.) are inactive, while the switch remains connected. When the load current is below a defined threshold value (and if necessary, other conditions are met), the intelligent semiconductor switch usually switches to idle mode. In idle mode, the monitoring and diagnostic functions that are usually available for intelligent semiconductor switches are only limitedly available, so the connected load cannot be fully monitored. Therefore, it is possible, for example, that an impermissibly high leakage current is not detected in the load connected to the semiconductor switch. This example may lead to, for example, too fast discharge of the battery when the car is parked. Summary of the invention

[0005] The inventors had the task of improving the existing concepts of intelligent semiconductor switches with regard to the above-mentioned problems.

[0006] This object is achieved by a method according to claim 1 and a circuit according to claims 9, 10 and 15. Various embodiments and developments are subject matter of the dependent claims.

[0007] Embodiments relate to a method for an intelligent semiconductor switch. The method includes activating a semiconductor switch that connects a power supply node providing a supply voltage to an output node connected to an electrical load. Thus, the output voltage is applied to the electrical load. The method also includes performing a leakage current test. To this end, the semiconductor switch is deactivated (turned off) so as to separate the electrical load from the power supply node. In addition, it is checked whether the time until the output voltage is lower than a first voltage level is less than a (time) threshold. Finally, the semiconductor switch is activated (turned on) again.

[0008] Another embodiment relates to an intelligent semiconductor switch having: at least one transistor connected between a supply node and an output node, and a control circuit configured to switch the transistor on and off. For a leakage current test, the control circuit is configured to switch off the transistor, check whether the time until the output voltage present at the output node is lower than a first voltage level is less than a threshold value, and switch the transistor on again.

[0009] According to a further embodiment, the intelligent semiconductor switch has at least one transistor connected between a power supply node (VS) and an output node and a control circuit configured to switch the transistor on and off. For a leakage current test, the control circuit is configured to switch the transistor off, generate a diagnostic signal including a pulse having a pulse length corresponding to the time until an output voltage output at the output node is lower than a first voltage level, and switch the transistor on again.

[0010] Another embodiment relates to a circuit having at least one transistor connected between a supply node and an output node and a control circuit configured to switch the transistor on and off. The circuit also includes a controller coupled to the control circuit, which is configured to switch the transistor off by means of the control circuit, check whether the time until the output voltage output at the output node is below a first voltage level is less than a threshold value and switch the transistor on again in order to perform a leakage current test. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Subsequently, an exemplary embodiment is explained in detail with the aid of the accompanying drawings. The drawings are not necessarily to scale and the exemplary embodiment is not limited to the aspects shown. Instead, the focus is on the principles on which the exemplary embodiment is based. Among them:

[0012] Figure 1 A simplified circuit diagram showing an intelligent semiconductor switch and a connected load as well as a controller for operating the intelligent semiconductor switch is shown.

[0013] Figure 2 shows an intelligent semiconductor switch having a function for detecting leakage current in a load,

[0014] Figure 3 The function for detecting a leakage current according to an exemplary embodiment is explained with the aid of a timing diagram.

[0015] Figure 4 Shows Figure 3 alternatives,

[0016] Figure 5 Shows Figure 3 Modifications / extensions of the embodiments,

[0017] Figure 6 Shows Figure 5 Modifications / extensions of the embodiments,

[0018] Figure 7 The timing diagram illustrates the Figure 6 The function of the embodiment for detecting leakage current,

[0019] Figure 8 A flow chart illustrating a test for leakage current detection is shown. DETAILED DESCRIPTION

[0020] Figure 1 shows the load Z LOAD The invention discloses a use of an intelligent semiconductor switch 10, wherein the intelligent semiconductor switch is controlled by an external controller 20 (e.g., a microcontroller). Firstly, it is pointed out that "intelligent semiconductor switch" is just a common name, and in this article, the word "intelligent" itself does not imply any specific technical features, but the semiconductor switch has a control circuit 11, and the function of the control circuit is not only to turn on and off the transistor T1.

[0021] according to Figure 1 , the intelligent semiconductor switch 10 (in addition) has a supply node VS and an output node OUT coupled through the transistor T1, so that the nodes VS and OUT are electrically connected when the transistor T1 is turned on, and are separated from each other when the transistor T1 is turned off. S In operation, the power supply node VS is delivered, and the electric load is connected to the output node OUT. Figure 1 Through impedance Z L When transistor T1 is turned on, the load current i LOAD The current flows from the power supply to the load Z via the node VS, the load current path of the transistor T1 and the node OUT. L In the example shown, the load Z L is connected between the node OUT and ground. Therefore, the intelligent semiconductor switch is a high-side switch. In other embodiments, the semiconductor switch 10 can be configured as a low-side switch, wherein in this case, the supply connection is usually connected to ground.

[0022] exist Figure 1 In the example shown, the transistor T1 is a MOS (metal oxide semiconductor) field effect transistor (MOSFET). In other embodiments, other transistor types (e.g. bipolar transistors, insulated gate bipolar transistors, etc.) can also be used. The control electrode of the transistor T1 (in the case of a MOSFET, the control electrode is the gate) is controlled, for example, by means of a so-called gate drive circuit 12. The gate drive circuit is usually designed to generate a corresponding gate voltage V according to the logic signal ON. G , the gate voltage is supplied to the gate of transistor T1. Different variants of gate drive circuits (gate drivers for short) for high-side switches and low-side switches are known per se and are therefore not discussed further here.

[0023] The logic level of the logic signal ON determines whether the transistor T1 should be turned on or off. In the example shown, the logic signal ON is generated by a control circuit 11 included in the intelligent semiconductor switch. The control circuit 11 may include a power supply circuit and is therefore connected to the node VS (supply voltage V S ) and GND (a supply node at ground potential). Different sensor signals or measurement information (e.g., about the magnitude of the load current or temperature) can be supplied to the control circuit 11. Different sensors and measurement circuits for measuring load current and temperature are known per se and are therefore Figure 1 Not shown.

[0024] The intelligent semiconductor switch is usually configured to communicate with other circuits, such as a controller 20 (e.g., a programmable microcontroller). To this end, the control circuit 11 may have a communication interface. For example, the communication interface enables serial data transmission. In practice, SPI (Serial Peripheral Interface) is currently commonly used. Figure 1 In the example shown, the intelligent semiconductor switch 10 has an input node IN for receiving an input signal, which is also a logic signal. For example, an input signal with a high level (IN=1) indicates that the control circuit 11 should turn on the transistor T1. Similarly, an input signal with a low level (IN=0) indicates that the control circuit 11 should turn off the transistor T1. Generally, the level of the logic signal ON corresponds to the input signal at the input node IN, unless the control circuit detects an abnormality such as excessive temperature, excessive current, undervoltage (supply voltage V S is too small), etc. The shutdown conditions may vary depending on the implementation and application, and may also sometimes be configurable (eg, by the controller 20).

[0025] exist Figure 1In the example shown, the intelligent semiconductor switch 10 has a diagnostic input DEN and a diagnostic output IS. A logic signal can be supplied to the diagnostic input DEN, which can activate and deactivate a diagnostic mode of the control circuit 11, wherein the control circuit 11 in the diagnostic mode can output a diagnostic signal i at the output IS. S , which in this example is a current signal. In the example shown, the resistor R S Connected between the diagnostic output terminal IS and ground. The diagnostic current i S The resistor R S The corresponding voltage V D (V D =i S R S ), which voltage can be supplied, for example, to an analog input of the microcontroller 20. The microcontroller can generate a logic signal for the diagnostic input DEN and evaluate the output diagnostic signal i S To monitor the operation of the semiconductor switch and the load connected thereto. The diagnostic signal can, for example, indicate the magnitude of the load current or indicate a fault.

[0026] Figure 2 It is used to detect the load Z LOAD The leakage current i in or parallel to the load LEAK The circuit diagram of the intelligent semiconductor switch with the function of Figure 2 In the case of leakage, the load Z LOAD The resistor R connected in parallel LEAK Even in the case of an inactive load, the load current i LOAD A part of the leakage current i LEAK Flow through resistor R LEAK To understand, the resistor R LEAK Only possible causes of leakage current are indicated. In practice, undesired leakage currents can be caused by various effects. For example, leakage currents can be caused by insufficient insulation in cables or connectors. Figure 2 The capacitor C shown L represents the capacitance at the output terminal OUT. This capacitance can also be included in the load Z LOAD The discrete capacitor structure elements in the output terminal OUT and the load Z LOAD The capacitance between the cable and the connector can also contribute to the capacitance C L .

[0027] Leakage currents can have undesirable effects. In applications in the automotive sector, there is the risk that the vehicle battery will be discharged too quickly and the vehicle may not be able to start after a long time when it is parked. For this reason, it is desirable to detect the leakage current in the simplest possible way and thus to be able to easily identify possible faults in the load or in the supply line to the load. As already mentioned above, the conventional current measurement function of the intelligent semiconductor switch is not available in the idle mode, so that the leakage current cannot be easily detected by means of current measurement.

[0028] Figure 2 The circuit and Figure 1 The circuit is basically the same, where Figure 2 An additional comparator 13 is provided in the circuit, which can detect the condition V DS <V X For example, if this condition is met, the logic signal S OL High level (S OL =1). Here, V X is a predefined or configurable threshold value. Subsequently, it is explained with the aid of a timing diagram how the comparator 13 can be used together with the control circuit 11 in order to be able to detect an undesired leakage current during operation of the intelligent semiconductor switch 10 in the idle mode.

[0029] Figure 3 The first (uppermost) diagram in FIG. 1 shows an example of a signal present at the input terminal IN, which changes from a low level to a high level at a time point t0 and thus indicates the switching on of the transistor T1. In response to the level change of the input signal at the time point t0, the control circuit 11 also sets the logic signal ON from a low level to a high level (ON=1) to switch on the transistor T1. The delay time between the corresponding edges of the input signal and the logic signal ON is negligibly small. The logic signal ON is Figure 3 After switching on transistor T1 , the intelligent semiconductor switch operates in normal mode, ie all diagnostic functions are available.

[0030] As transistor T1 is turned on, the output voltage V OUT Also increases to close to the supply voltage V S The applicable value is V OUT =Vs-V DS =V S -R ON ·i LOAD , where R ON represents the (relatively small) on-resistance of transistor T1. Output voltage V OUT exist Figure 3 The load current i LOAD exist Figure 3 The load current i LOAD Depends on the characteristics of the load. Between time points t0 and t1, the load requires a significant load current i LOAD At time t1, the load current i LOAD The load current i LOAD The cause of the drop is immaterial. For example, it could be caused by the user manually deactivating the load.

[0031] At time point t 10 , the controller triggers leakage current detection (leakage current test) in the following way, that is, a logic signal with a high level is detected at the input terminal DEN, while the transistor T1 is turned on and the intelligent semiconductor switch operates in the idle mode. Figure 3 In order to perform a leakage current test, the transistor T1 is temporarily switched off, for example, in the following manner: the control circuit 11 is switched off at the time point t 10 (or immediately thereafter) sets the signal ON to a low level. Due to the high level at the input terminal DEN, a diagnostic current i is output at the diagnostic output terminal IS. S (i S =i S,OL ), which indicates that the condition V is satisfied DS <V X (corresponding to V S -V OUT <V X or V OUT >V S -V X ).

[0032] After transistor T1 is turned off, the capacitor C at the output terminal OUT L Buffer output voltage V OUT However, when transistor T1 is turned off, the output voltage V OUT decrease (ie, drain-source voltage V DS becomes larger), because the capacitance C L The current i responsible for the discharge of the capacitor LOAD The current flowing through the load (which can be very small in an inactive load) and the leakage current i LEAK The larger the current, the larger the capacitance C L The faster the discharge.

[0033] In the example shown, at time t 11 , voltage V OUT Reaching the threshold V S -V XTherefore, the above condition V is no longer satisfied OUT >V S -V X , and the control circuit 11 changes the diagnostic current from i S =i S,OL Reduce to i S = 0. This enables the microcontroller to measure the time point t 10 and time point t 11 The control circuit 11 receives this information directly from the comparator 13, which responds to the condition V OUT >V S -V X Monitor. Time span t 11 -t 10 With the load Z LOAD The current and leakage current i LEAK If the load is inactive, so that the current through the load is zero or negligibly small, the leakage current i LEAK Basically determine the time span t 11 -t 10 .

[0034] At time point t 11 Soon after, the leakage current test ends, and the control circuit 11 is turned on at time t 12 The transistor T1 is switched on again. At this point in time, the intelligent semiconductor switch is still always in idle mode. In the example shown, the load Z LOAD When activated again (for whatever reason) at any later time (at time point t2), the load current flowing through the load increases to the nominal value, causing the intelligent semiconductor switch to leave the idle mode and switch back to the normal mode.

[0035] The comparator 13 enables the control circuit 11 to detect the time span t 11 -t 10 Is it less than the threshold T? K (t 11 -t 10 <T K ). If the condition t is met 11 -t 10 <T K , then the leakage current i LEAK is likely to be too large. In the example shown, the diagnostic current i S Contains length t 11 -t 10 This also enables the controller 20 to check the condition t 11 -t 10 <T K .

[0036] Threshold TK can be configurable so that it can be tailored to the respective application and according to the capacitance C L and the maximum allowable leakage current to set an appropriate threshold. S The output of is only an example and is not necessarily required. As mentioned, the control circuit 11 can evaluate the condition t by means of the comparator 13 itself. 11 -t 10 <T K The forwarding of information (eg, fault messages) to an external unit such as the controller 20 can also be implemented in other ways, for example, via the SPI interface already mentioned. The specific implementation depends on the specific application.

[0037] The above-mentioned variant in which the leakage test (leakage current test) is not performed and controlled by the intelligent semiconductor switch 10 but is performed and controlled by the controller 20 is Figure 4 Shown in. Figure 4 The second, third, fourth and fifth graphs in Figure 3 The only difference is that the temporary shutdown of transistor T1 is not triggered independently by control circuit 11, but by external controller 20, which actively shuts down the semiconductor switch by means of an input signal at input node IN (at time t10) and after the end of the test (at time t 12 ) actively turns on the semiconductor switch again. In this case, the logic signal ON follows the input signal at the input IN. As mentioned, instead of a logic signal, the corresponding command can also be transmitted via a serial communication interface such as SPI. 11 -t 10 <T K The evaluation is carried out in this case by the controller 20, which can evaluate the current signal i S (or the corresponding voltage signal V D ) and compare it with the threshold value T K This function of the controller 20 can be realized, for example, by means of a processor and appropriate software.

[0038] As mentioned, the capacitor C L are design parameters that may be application dependent. Assumptions (for evaluation of conditions V OUT >V S -V X The value of V X is 1.8V, the maximum allowable current (load current and leakage current) is 75mA, and the threshold T K is 10ms, then the capacitor C LIt must be about 420μF (75mA·10ms / 1.8V=416.67μF). If you want to reduce the capacitance and keep the other parameters unchanged, you will need an additional power supply. Figure 5 In the example, the power supply uses Q P express.

[0039] Figure 5 The circuit in Figure 3 Modification / expansion plan of the circuit. Figure 3 and Figure 5 The only difference between the two is the power supply Q P , which can be switched by an electronic switch SW P Activation and deactivation. The power supply can also be formed via a simple resistor (pull-up resistor). For activating and deactivating the switch SW P (and thus the power supply Q P ) control signal S P It can be generated, for example, by the controller 20. For example, if the power supply is designed so that the power supply provides 37 mA (i P =37mA), then the capacitor C L Instead of discharging at 75 mA (as in the previous example), the capacitor C L It can be reduced from 420 μF to about 210 μF (38 mA·10 ms / 1.8 V=211.1 μF).

[0040] At a given capacitance C L (e.g. 420μF), a given threshold T K (e.g. 10ms) and a given V X (e.g. 1.8V), the maximum current is C L ·V X / T K (75.6mA in the current example). Power Supply Q P The power supply current i P (bias current) and leakage current i LEAK superimposed, and thus (other things remaining the same) changes the maximum current. It is to be understood that the switchable power supply Q P It may also be arranged in the intelligent semiconductor switch 10. In the exemplary embodiment in this case, the control circuit 11 may be designed to activate the power supply (or the pull-up resistor) during the leakage current test and then deactivate it again.

[0041] Figure 6 Shows Figure 5 Modifications / extensions of the embodiments. Figure 6 The circuit and Figure 5 The circuit is basically the same, where Figure 6In the present invention, the diagnostic output IS and the comparator 13 are not required (and can therefore be omitted or not implemented) for the leakage current test. Instead, the controller 20 is configured to measure the output voltage V OUT , that is, the output voltage V OUT A scaled version of V OUT’ The analog input terminal (indicated by A / D in the figure) of the controller 20 is supplied. In the figure, the scaling is achieved by a voltage divider formed by resistors R1 and R2. The resistors are connected in series between the output node OUT and ground. The middle tap of the series circuit of R1 and R2 is connected to the analog input terminal of the controller 20. In addition, Figure 6 In the embodiment, a digital communication interface (specifically, an SPI interface) is implemented instead of the input terminals IN and DEN.

[0042] For example, the controller 20 may evaluate the scaled output voltage V by means of an analog-to-digital converter. OUT’ , in order to obtain the time period t 11 -t 10 , and compare the time period with the threshold T K This feature uses Figure 7 The basic process and Figure 4 Same as in the example. Figure 7 The first timing diagram with Figure 4 The second graph shows the input signal at the input node IN, which the controller 20 can use to temporarily turn off the transistor T1 to perform a leakage current test. P The current provided i P In the current example, the controller activates power supply Q before starting the leakage current test. P At time point t 10 , transistor T1 is turned off and the leakage current test starts; capacitor C L is discharged, where the effective discharge current is i LOAD -i P .

[0043] The third graph shows the voltage V at the center tap of the voltage divider OUT’ , which is delivered to the controller 20. The controller can generate a corresponding digital signal V OUT’ [n] (n is the time index and represents each sample) and compares it with the threshold V TH For comparison (V TH =V S -V X ). In the example shown, at time t 11 Reaching the threshold V TH The controller 20 can determine in a simple manner that at time t 10 +TK Before or after reaching the threshold V TH (T K is the time threshold discussed above), without having to quantitatively determine the time span t 11 -t 10 (This applies to all embodiments.) The fourth diagram shows the course of the load current and is the same as in the previous examples.

[0044] It is to be understood that the embodiments described herein may be modified in different ways without changing the basic functionality of leakage current detection described herein. For example, in the last example ( Figure 6 and Figure 7 ), the diagnostic input terminal DEN is not necessarily required. If a digital communication interface such as SPI is provided in the intelligent semiconductor switch, the input node IN is not required. Power supply Q P Can be arranged inside or outside the intelligent semiconductor switch. Replaces a single power supply Q P In addition, multiple power supplies and / or pull-up resistors can also be used inside and / or outside the intelligent semiconductor switch. In this case, the pull-up resistor is understood as a possible embodiment of the power supply.

[0045] The intelligent semiconductor switch can be integrated in a single semiconductor chip arranged in a chip package. Alternatively, the components of the intelligent semiconductor switch can be integrated into two or more chips, however, the chips are arranged in a single chip package. The input nodes IN and DEN, the output node OUT, the power supply node VS, the diagnostic output terminal IS, and the ground connection GND can be constructed as conventional chip pins, solder balls, etc.

[0046] As mentioned, the controller 20 may be a microcontroller comprising a processor and peripherals, such as an analog-to-digital converter, memory, etc. The memory contains processor instructions that can be implemented by the processor. In this way, the functionality of the controller 20 may be substantially determined by software. But this need not be the case. A combined software and hardware solution with one-time programmable (OTP) logic is also possible.

[0047] The examples described here are summarized below. It should be understood that this does not involve a complete list of important features, but only an exemplary summary.

[0048] A first example relates to a method for an intelligent semiconductor switch, wherein the method Figure 8 Thus, the method comprises activating (turning on) a semiconductor switch (see Figure 8 , step S1), the semiconductor switch connects a supply node providing a supply voltage to an output node connected to an electric load so as to apply an output voltage to the electric load (see Figure 2 , 5 or 6, by switching on transistor T1 so that nodes VS and OUT are electrically connected). When the semiconductor switch is switched on, a test is performed to detect a possible leakage current (leakage current test). This test involves (temporary) deactivation of the semiconductor switch (see Figure 8 , step S2), in order to separate the electrical load from the supply node. Therefore, the output voltage is only buffered by the capacitor at the output node, and the capacitor is discharged (see Figure 3 , 4 or 7). The test also includes checking the time that elapses until the output voltage falls below the first voltage level (see Figure 3 , 4 and the time span t in 7 11 -t 10 ) is less than the threshold (see Figure 8 , step S3). Subsequently, the semiconductor switch is activated again (see Figure 8 , step S4).

[0049] It is not necessary to explicitly measure until the output voltage is below the first voltage level (V OUT ≤V TH ) the time elapsed (e.g. t 11 -t 10 ). Different possibilities for comparing time periods (for example represented by pulse lengths in logic signals) are known to the person skilled in the art. In the example, the time t is explicitly measured. 11 -t 10 and compares it with a threshold value (e.g. digitally in the controller 20, see Figure 6 The threshold may vary with the output capacitance (see, for example, Figure 2 C L ) and / or the maximum permissible leakage current i LEAK,max Related.

[0050] In an exemplary embodiment, the semiconductor switch is activated and deactivated by means of a control circuit, wherein the control circuit (see Figure 2 , 5 or 6) can operate in normal mode and idle mode. "Idle mode" is simply the name of an operating mode with low power consumption, in which several components and functions of the intelligent semiconductor switch are inactive and unavailable. Idle mode generally assumes that the load current is less than a current threshold. When the load consumes no quiescent current or only a very small quiescent current, the performance of a leakage current test makes sense in particular in idle mode, wherein the leakage current test can be performed at any time by a diagnostic command (e.g. via reception of an SPI interface or a level change at the input DEN, see Figure 2 , 5 or 6) trigger leakage current test.

[0051] In some embodiments, a current pulse or a voltage pulse may be output at the diagnostic output, wherein the pulse length corresponds to the time elapsed until the output voltage falls below a first voltage level (see, for example, Figure 3 , the diagnostic current i at the output terminal IS S ).

[0052] Another example relates to an intelligent semiconductor switch having at least one transistor and a control circuit (see Figure 2 , 5 or 6), the at least one transistor being connected between a power supply node and an output node. The control circuit is configured to switch the transistor on and off. The control circuit is configured to perform a leakage current test in response to a diagnostic command. In this case, the transistor is temporarily switched off, and a pulse having a pulse length is output as a diagnostic signal (see, for example, Figure 2 , signal i S ), the pulse length corresponding to the time until the output voltage output at the output node is lower than the first voltage level. Subsequently, the transistor is turned on again. The power supply can be coupled to the output node and configured to output a bias current at the output node (i.e., feed the bias current into the output node). The bias current is superimposed on the load current flowing through the transistor, wherein the maximum allowable leakage current i LEAK,max Can be related to bias current. The power supply can be arranged inside or outside the intelligent semiconductor switch.

[0053] Can be controlled by an external controller (see Figure 5 , the controller 20) performs a check whether the pulse length of the diagnostic signal is less than a threshold value. Alternatively, the check can also be performed by an internal control circuit of the intelligent semiconductor switch. In this case, the output of the diagnostic signal is unnecessary.

Claims

1. A method, comprising: Activate the semiconductor switch (T1), which will provide the supply voltage (V S ) and the connected electrical load (Z LOAD ) is connected to the output node (OUT) so that the output voltage (V OUT ) is applied to the electrical load (Z LOAD )superior; and Performing a leakage current test, the leakage current test comprising: Deactivating the semiconductor switch (T1) to switch the electrical load (Z LOAD ) is separated from the power supply node (VS); Check until the output voltage (V OUT ) is lower than the first voltage level (V TH =V S -V X ) The time (t 11 -t 10 ) is less than the threshold (T K );and The semiconductor switch (T1) is reactivated.

2. The method according to claim 1, wherein: Check the time (t 11 -t 10 ) is less than the threshold value (T K )include: Measure until the output voltage (V OUT ) is lower than the first voltage level (V TH =V S -V X ) the time (t 11 -t 10 ),and The time to be measured (t 11 -t 10 ) and the threshold value (T K )Compare.

3. The method according to claim 1 or 2, wherein: The threshold value (T K ) and the capacitor (C L ) and / or the maximum permissible leakage current.

4. The method according to any one of claims 1 to 3, wherein: The semiconductor switch (T1) is activated and deactivated by means of a control circuit (11) which is operable in a normal mode and an idle mode, wherein the idle mode assumes that a load current (i L ) is less than the current threshold.

5. The method according to claim 4, wherein: The leakage current test is performed during operation of the control circuit (11) in the idle mode.

6. The method according to any one of claims 1 to 5, wherein: In response to receiving the diagnostic command, a leakage current test is initiated.

7. The method according to claim 6, in, The diagnostic command is received via a digital communication interface, or The diagnostic command is a level change in a logic signal received at a diagnostic input terminal (DEN).

8. The method according to claim 6 or 7, further comprising: Output current pulses (i S ) or a voltage pulse, wherein the pulse time corresponds to until the output voltage (V OUT ) is lower than the first voltage level (V TH =V S -V X ) The time (t 11 -t 10 ).

9. An intelligent semiconductor switch having: at least one transistor (T1), the at least one transistor being connected between a supply node (VS) and an output node (OUT); a control circuit (11) configured to switch the transistor (T1) on and off, In order to perform a leakage current test, the control circuit is configured to: The transistor (T1) is turned off and the output voltage (V OUT ) is lower than the first voltage level (V TH =V S -V X ) The time (t 11 -t 10 ) is less than the threshold (T K ), and turns on the transistor (T1) again.

10. An intelligent semiconductor switch having: at least one transistor (T1), the at least one transistor being connected between a supply node (VS) and an output node (OUT); a control circuit (11) configured to switch the transistor (T1) on and off, In order to perform a leakage current test, the control circuit (11) is configured to: Turning off the transistor (T1), Generates a diagnostic signal (i) including a pulse having a pulse length S ), the pulse length corresponds to the output voltage (V OUT ) is lower than the first voltage level (V TH =V S -V DS,OL ) The time (t 11 -t 10 ),and The transistor (T1) is turned on again.

11. The intelligent semiconductor switch according to claim 9 or 10, further comprising: A circuit node (DEN) for receiving a logic signal through the control circuit (11), wherein the diagnostic command is signaled by causing the logic signal to have a predefined level.

12. The intelligent semiconductor switch according to claim 9 or 10, further comprising: A digital communication interface is configured to receive the diagnostic command.

13. The intelligent semiconductor switch according to any one of claims 1 to 12, further comprising: Power supply (Q P ), the power supply is coupled to the output node (OUT) and is configured to output a bias current (i P ), the bias current and the load current (i LOAD ) overlay.

14. The intelligent semiconductor switch according to claim 12, wherein: The maximum allowed leakage current is related to the bias current.

15. A circuit, comprising: at least one transistor (T1), the at least one transistor being connected between a supply node (VS) and an output node (OUT); a control circuit (11) configured to switch the transistor (T1) on and off, A controller (20) coupled to the control circuit (11) is configured to: By means of the control circuit (11), the transistor (T1) is turned off, Check until the output voltage (V OUT ) is lower than the first voltage level (V TH =V S -V X ) The time (t 11 -t 10 ) is less than the threshold (T K ),and The transistor (T1) is turned on again.

16. The circuit of claim 15, wherein: The controller (20) is configured to, when checking that the time (t 11 -t 10 ) is less than the threshold value (T K ) to signal excessive leakage current.

17. A circuit according to claim 15 or 16, wherein: The controller (20) is configured to generate a first logic signal (IN) for the control circuit (11), the first logic signal causing the control circuit to switch the transistor (T1) on and off.

18. A circuit according to any one of claims 14 to 17, wherein: The controller (20) is configured to generate a second logic signal (DEN) for the control circuit (11), the second logic signal causing the control circuit to output a diagnostic signal (i S ), the diagnostic signal and the load current (i LOAD ) related.

19. A circuit according to any one of claims 10 to 18, wherein: The control circuit (11) is capable of operating in a normal mode and an idle mode, and wherein in the idle mode, a load current (i LOAD ) is less than the current threshold.

20. The circuit of claim 19, wherein: The leakage current test is performed during the idle mode and in response to a diagnostic command.

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