Phase-locked loop circuit, chip and electronic equipment

Abstract

The invention provides a phase-locked loop circuit, a chip and an electronic device, the phase-locked loop circuit comprises a phase comparison module, a pulse modulation module, a control module and an oscillation module, the pulse modulation module has a pulse modulation mode, and in the pulse modulation mode, when the width of a first pulse of a phase difference pulse signal is greater than a first preset value, the phase difference pulse signal is output; the width of a second pulse corresponding to the modulation pulse signal and the first pulse is smaller than that of the first pulse. According to the application, the pulse width of the modulation pulse signal is reduced through the pulse modulation module, so that the control module reduces the charge and discharge quantity of the oscillation module, and finally, the phenomenon that the target clock signal rapidly drops due to the large pulse width of the phase difference pulse signal when the reference clock is lost can be avoided.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a phase-locked loop circuit, a chip and an electronic device. Background Art

[0002] Phase-locked loops (PLL) are a technology that uses feedback control principles to achieve frequency and phase synchronization between a reference clock and an output clock. They are widely used in communications, radar, measurement, and automation control.

[0003] However, in some scenarios, the phase-locked loop circuit may lose the reference clock. After the reference clock is lost, the phase-locked loop circuit will quickly follow the changes in the reference clock and quickly reduce the output clock to zero, eventually causing the chip to fail or even burn out due to the loss of the main clock. Summary of the invention

[0004] The present application provides a phase-locked loop circuit, a chip and an electronic device, aiming to solve the above technical problems.

[0005] In the first aspect, the present application provides a phase-locked loop circuit, including: a phase comparison module, which is used to compare the phases of a reference clock signal and a feedback clock signal and output a phase difference pulse signal; a pulse modulation module, which is used to output a modulated pulse signal according to the phase difference pulse signal, and the pulses of the phase difference pulse signal correspond to the pulses of the modulated pulse signal; a control module, which is used to output a control signal according to the modulated pulse signal; and an oscillation module, which is used to output a target clock signal and a feedback clock signal under the control of the control signal; wherein the pulse modulation module has a pulse modulation mode, in which, when the width of a first pulse of the phase difference pulse signal is greater than a first preset value, the width of a second pulse of the modulated pulse signal corresponding to the first pulse is less than the width of the first pulse.

[0006] In some embodiments, when the width of the first pulse of the phase difference pulse signal is less than or equal to a first preset value, the width of the second pulse of the modulated pulse signal corresponding to the first pulse is equal to the width of the first pulse; when the width of the first pulse of the phase difference pulse signal is greater than the first preset value, the width of the second pulse of the modulated pulse signal corresponding to the first pulse is equal to the first preset value.

[0007] In some embodiments, the pulse modulation module further has a pulse restoration mode; in the pulse restoration mode, the width of the first pulse of the phase difference pulse signal is equal to the width of the second pulse of the modulation pulse signal.

[0008] In some embodiments, before the loop of the phase-locked loop circuit is stabilized, the pulse modulation module is in the pulse restoration mode; after the loop of the phase-locked loop circuit is stabilized, the pulse modulation module is in the pulse modulation mode.

[0009] In some embodiments, the pulse modulation module includes a first delay unit, a first NAND gate and a first AND gate; the input end of the first delay unit is connected to the phase difference pulse signal, and the output end of the first delay unit is connected to the first input end of the first NAND gate; the second input end of the first NAND gate is connected to the phase difference pulse signal, and the output end of the first NAND gate is connected to the first input end of the first AND gate; the second input end of the first AND gate is connected to the phase difference pulse signal, and the output end of the first AND gate is connected to the control module.

[0010] In some embodiments, the pulse modulation module also includes a first switch and a second switch; one end of the first switch is connected to the phase difference pulse signal, and the other end is connected to the control module; one end of the second switch is connected to the output end of the first AND gate, and the other end is connected to the control module.

[0011] In some embodiments, the phase-locked loop circuit also includes a steady-state detection module; the steady-state detection module is used to detect whether the loop of the phase-locked loop circuit is stable and control the first switch and the second switch; wherein, before the loop of the phase-locked loop circuit is stable, the first switch is in a closed state and the second switch is in an open state; after the loop of the phase-locked loop circuit is stable, the first switch is in an open state and the second switch is in a closed state.

[0012] In some embodiments, the phase-locked loop circuit also includes a pulse width detection module; the pulse width detection module is used to detect the width of the phase difference pulse signal, and output a first enable signal when the width of the phase difference pulse signal is greater than a second preset value; wherein the first enable signal is used to turn off the control module so that the oscillation module is in a switch self-oscillation state.

[0013] In a second aspect, an embodiment of the present application further provides a chip, comprising the above-mentioned phase-locked loop circuit.

[0014] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the above-mentioned chip or phase-locked loop circuit.

[0015] The present application further sets a pulse modulation module in the phase-locked loop circuit, uses the pulse modulation module to output a modulated pulse signal according to the phase difference pulse signal, and then outputs a control signal through the modulated pulse signal, so that the oscillation module is used to output the target clock signal under the control of the control signal. Due to the pulse modulation mode of the pulse modulation module, when the width of the first pulse of the phase difference pulse signal is less than or equal to the first preset value, the width of the second pulse corresponding to the first pulse of the modulated pulse signal is equal to the width of the first pulse; and when the width of the first pulse of the phase difference pulse signal is greater than the first preset value, the width of the second pulse corresponding to the first pulse of the modulated pulse signal is less than the width of the first pulse, that is, when the pulse width of the phase difference pulse signal is large, the pulse width of the modulated pulse signal will be correspondingly reduced, so that the control module reduces the charge and discharge amount of the oscillation module by using the modulated pulse signal with reduced pulse width, so that the pulse width of the phase difference pulse signal is large when the reference clock is lost, which leads to a rapid decrease in the target clock signal, and finally causes the chip to fail or even burn due to the loss of the main clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic diagram of a phase-locked loop circuit in the related art is shown;

[0018] Figure 2 A schematic diagram showing a signal change when a reference clock is lost;

[0019] Figure 3 is a schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application;

[0020] Figure 4 is another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application;

[0021] Figure 5 is a schematic diagram of phase comparison module related signals provided in an embodiment of the present application;

[0022] Figure 6 is a schematic diagram of phase-locked loop circuit related signals provided in an embodiment of the present application;

[0023] Figure 7 is another schematic diagram of phase-locked loop circuit related signals provided in an embodiment of the present application;

[0024] Figure 8 is another schematic diagram of phase-locked loop circuit related signals provided in an embodiment of the present application;

[0025] Fig. 9 is another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application;

[0026] Fig.10 is a schematic diagram of related signals of the pulse modulation module provided in an embodiment of the present application;

[0027] Fig.11 is another schematic diagram of the pulse modulation module related signals provided in the embodiment of the present application;

[0028] Fig.12 is another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application;

[0029] Fig.13 is another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application;

[0030] Fig.14 is another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application;

[0031] Fig.15 is another schematic diagram of a phase-locked loop circuit provided in an embodiment of the present application.

[0032] Among them, 10 is a phase comparison module, 20 is a pulse modulation module, 21 is a first delay unit, 30 is a control module, 40 is an oscillation module, 50 is a steady-state detection module, and 60 is a pulse width detection module;

[0033] Reference clock signal CLK_Ref, feedback clock signal CLK_Rfb, target clock signal CLK_out, control signal Vc, phase difference pulse signal Pulse_PH, modulation pulse signal Pulse_Limit, first enable signal Clkref_abs;

[0034] A first NAND gate NAND1, a first AND gate AND1, a first switch S1, and a second switch S2. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0036] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0037] In this application, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is given to enable any person skilled in the art to implement and use the invention. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the invention can be implemented without using these specific details. In other instances, well-known structures and processes are not elaborated in detail to avoid obscuring the description of the invention with unnecessary details. Therefore, the present invention is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this application.

[0038] At present, phase-locked loops (PLL) are a technology that uses feedback control principles to achieve frequency and phase synchronization between reference clocks and output clocks. Figure 1 , Figure 1 A schematic diagram of a phase-locked loop circuit in the related art is shown, and the phase-locked loop includes a phase detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider, wherein the frequency divider outputs a feedback clock CLK2 according to the output clock CLKO of the voltage-controlled oscillator, the phase detector can compare the phase difference between the reference clock CLK1 and the feedback clock CLK2 and output a pulse signal containing phase difference information, the charge pump can output a charging current or a discharging current according to the pulse signal containing phase difference information, the low-pass filter allows a low-frequency current signal to pass through and outputs a corresponding low-frequency voltage control signal, and then controls the voltage-controlled oscillator to change its oscillation frequency through the low-frequency voltage control signal, and finally synchronizes the frequency and phase of the feedback clock CLK2 with the reference clock CLK1, and completes the locking process of the output clock CLKO and the reference clock CLK1.

[0039] However, in some scenarios, such as audio signal amplification, the phase-locked loop circuit may experience reference clock loss, for example, see Figure 2 , Figure 2A schematic diagram of signal changes when the reference clock is lost is shown. After the reference clock is lost, the phase-locked loop circuit will quickly follow the changes in the reference clock CLK1 and quickly reduce the frequency of the output clock CLKO to zero, which can easily cause the chip to fail or even burn out due to the loss of the main clock and the failure to activate the protection function in time.

[0040] To this end, the present application provides a phase-locked loop circuit, a chip and an electronic device, which are described in detail below.

[0041] First, see Figure 3 , Figure 3 A schematic diagram of a phase-locked loop circuit in an embodiment of the present application is shown, wherein the phase-locked loop circuit includes a phase comparison module 10, a pulse modulation module 20, a control module 30 and an oscillation module 40.

[0042] Specifically, the phase comparison module 10 can compare the phases of the reference clock signal CLK_Ref and the feedback clock signal CLK_Rfb, so as to determine whether the phases of the feedback clock signal CLK_Rfb and the reference clock signal CLK_Ref are aligned. In some embodiments of the present application, the feedback clock signal CLK_Rfb may refer to a clock signal obtained by dividing the target clock signal CLK_out output by the oscillation module 40 by the frequency divider 70. In some embodiments of the present application, the feedback clock signal CLK_Rfb may also be the target clock signal CLK_out output by the oscillation module 40, that is, the phase comparison module 10 can directly compare the target clock signal CLK_out with the reference clock signal CLK_Ref, so as to determine whether the frequency and phase of the target clock signal CLK_out and the reference clock signal CLK_Ref are locked.

[0043] Generally, the phase comparison module 10 may include a phase detection circuit, which outputs a phase difference pulse signal Pulse_PH by comparing the transition edges (falling edge and / or rising edge) of the reference clock signal CLK_Ref and the feedback clock signal CLK_Rfb, and the phase difference pulse signal Pulse_PH includes the phase difference information between the reference clock signal CLK_Ref and the feedback clock signal CLK_Rfb. In some embodiments of the present application, the phase difference pulse signal Pulse_PH may be a pulse signal. In some embodiments of the present application, the phase difference pulse signal Pulse_PH may also be a group of pulse signals.

[0044] In some embodiments of the present application, for example, for an embodiment in which the phase difference pulse signal Pulse_PH is a pulse signal, the phase comparison module 10 may include an XOR gate. When the levels of the reference clock signal CLK_Ref and the feedback clock signal CLK_Rfb are different, the XOR gate may output a high-level signal as a pulse of the phase difference pulse signal Pulse_PH, thereby determining through the XOR gate whether the phases of the reference clock signal CLK_Ref and the feedback clock signal CLK_Rfb are synchronized and outputting the phase difference pulse signal Pulse_PH.

[0045] In some embodiments of the present application, for example, for an embodiment in which the phase difference pulse signal Pulse_PH is a group of pulse signals, see Figure 4 , Figure 4 Another schematic diagram of the phase-locked loop circuit in the embodiment of the present application is shown, the phase comparison module 10 includes triggers DT1, DT2 and an AND gate AND0, the trigger end of the trigger DT1 is connected to the reference clock signal CLK_Ref, the input end of the trigger DT1 is connected to the power supply voltage VDD, and the output end of the trigger DT1 is connected to the first input end of the AND gate AND0; the trigger end of the trigger DT2 is connected to the feedback clock signal CLK_Rfb, the input end of the trigger DT2 is connected to the power supply voltage VDD, the output end of the trigger DT2 is connected to the second input end of the AND gate AND0, and the output end of the AND gate AND0 is connected to the reset ends of the triggers DT1 and DT2.

[0046] During the operation of the phase comparison module 10, refer to Figure 5 , Figure 5 A schematic diagram of the related signals of the phase comparison module 10 in the embodiment of the present application is shown, the trigger DT1 outputs a first phase difference pulse signal Pulse_PH_up, and the trigger DT1 outputs a second phase difference pulse signal Pulse_PH_dn. The first phase difference pulse signal Pulse_PH_up corresponds to the charging control signal of the oscillation module 40, and the second phase difference pulse signal Pulse_PH_dn corresponds to the discharge control signal of the oscillation module 40. Therefore, when there is a certain phase difference between the reference clock signal CLK_Ref and the feedback clock signal CLK_Rfb, the pulse corresponding to the first phase difference pulse signal Pulse_PH_up will charge the oscillation module 40 and accelerate the oscillation frequency, so that the frequency of the feedback clock signal CLK_Rfb is accelerated and catches up with the frequency of the reference clock signal CLK_Ref.

[0047] It is understandable that the phase comparison module 10 can also use other circuits that can identify the phase difference between the reference clock signal CLK_Ref and the feedback clock signal CLK_Rfb, such as a phase detection circuit implemented by a D flip-flop, a phase detection circuit implemented by a NOR gate, or a phase detection circuit implemented by an inverter.

[0048] The control module 30 is used to output a control signal Vc according to the modulated pulse signal Pulse_Limit of the pulse modulation module 20, so as to control the oscillation module 40 to change the oscillation frequency and lock the frequency and phase of the target clock signal CLK_out with the reference clock signal CLK_Ref. In some embodiments of the present application, the control module 30 may include a charge pump and a low-pass filter, the charge pump outputs a current signal according to the modulated pulse signal Pulse_Limit, and the low-pass filter outputs a low-frequency voltage signal as the control signal Vc after filtering the current signal, so as to control the oscillation module 40 to change its oscillation frequency through the control signal Vc.

[0049] As an example, continue to refer to Figure 4 The charge pump includes current sources I1, I2 and a switch S01, and a low-pass filter is formed by the switch S02, the resistor R0 and the capacitor C0 to filter the voltage of the node M1. The first modulation pulse signal Pulse_Limit_up output by the pulse modulation module 20 corresponds to the first phase difference pulse signal Pulse_PH_up, and the first modulation pulse signal Pulse_Limit_up can control the switch S01. The second modulation pulse signal Pulse_Limit_dn output by the pulse modulation module 20 corresponds to the second phase difference pulse signal Pulse_PH_dn. The second modulation pulse signal Pulse_Limit_dn can control the switch S02. Therefore, under the control of the first modulation pulse signal Pulse_Limit_up, the current source I1 can charge the oscillation module 40 through the switch S01, thereby accelerating the oscillation frequency of the oscillation module 40; and under the control of the second modulation pulse signal Pulse_Limit_dn, the current source I2 can discharge the oscillation module 40 through the switch S02, thereby reducing the oscillation frequency of the oscillation module 40, thereby ultimately enabling the control module 30 to change the oscillation frequency of the oscillation module 40.

[0050] Understandably, Figure 4 The embodiment shown is that the pulse modulation module 20 outputs a group of modulated pulse signals Pulse_Limit according to a group of phase difference pulse signals Pulse_PH. In some other embodiments, for example, for an embodiment in which the phase difference pulse signal Pulse_PH is a pulse signal, the pulse modulation module 20 may also output only one modulated pulse signal Pulse_Limit. At the same time, Figure 4 The charge pump and low-pass filter shown are only exemplary embodiments and should not be construed as limiting the control module 30 of the present application. For example, Figure 4The low-pass filter shown in FIG. 1 is a first-order RC filter. In some possible embodiments, the low-pass filter may also be a second-order RC filter, a third-order RC filter, or an LC filter.

[0051] The oscillation module 40 can change the oscillation frequency according to the control signal Vc to change the frequency of the target clock signal CLK_out. In some embodiments of the present application, for example, for an embodiment in which the control module 30 includes a charge pump and a low-pass filter, the oscillation module 40 may include a voltage-controlled oscillator, and the control end of the voltage-controlled oscillator is connected to the low-pass filter to output a low-frequency voltage signal, and the oscillation frequency of the voltage-controlled oscillator can be changed under the control of the low-frequency voltage signal. Exemplarily, the voltage-controlled oscillator may include but is not limited to a capacitor-tuned voltage-controlled oscillator or an inductor-tuned voltage-controlled oscillator.

[0052] In an embodiment of the present application, the pulse modulation module 20 can output a modulated pulse signal Pulse_Limit according to the phase difference pulse signal Pulse_PH, and the pulse of the phase difference pulse signal Pulse_PH corresponds to the pulse of the modulated pulse signal Pulse_Limit, wherein the pulse modulation module 20 has a pulse modulation mode. In the pulse modulation mode, when the width of the first pulse of the phase difference pulse signal Pulse_PH is greater than the first preset value, the width of the second pulse of the modulated pulse signal Pulse_Limit corresponding to the first pulse is less than the width of the first pulse.

[0053] For example, see Figure 6 , Figure 6 A schematic diagram of the phase-locked loop circuit related signals in the embodiment of the present application is shown. If the reference clock signal CLK_Ref is lost, the second phase difference pulse signal Pulse_PH_dn will generate a wider pulse. If the second phase difference pulse signal Pulse_PH_dn is directly used to discharge the oscillation module 40 through the control module 30, the frequency of the target clock signal CLK_out will be rapidly reduced and the chip will fail or even burn out.

[0054] In the embodiment of the present application, in the pulse modulation mode of the pulse modulation module 20, when the width of the first pulse of the phase difference pulse signal Pulse_PH is greater than the first preset value, the width of the second pulse corresponding to the first pulse of the modulated pulse signal Pulse_Limit is less than the width of the first pulse, that is, when the pulse width of the phase difference pulse signal Pulse_PH is larger, the pulse width of the modulated pulse signal Pulse_Limit will be correspondingly reduced, thereby utilizing the modulated pulse signal Pulse_Limit with reduced pulse width to enable the control module 30 to reduce the charge and discharge amount of the oscillation module 40, thereby avoiding the large pulse width of the phase difference pulse signal Pulse_PH when the reference clock is lost, thereby causing the frequency of the target clock signal CLK_out to drop rapidly, and ultimately causing the chip to fail or even burn due to the loss of the main clock.

[0055] In some embodiments of the present application, in the pulse modulation mode of the pulse modulation module 20, when the width of the first pulse of the phase difference pulse signal Pulse_PH is less than or equal to the first preset value, the width of the second pulse corresponding to the first pulse of the modulated pulse signal Pulse_Limit is equal to the width of the first pulse; when the width of the first pulse of the phase difference pulse signal Pulse_PH is greater than the first preset value, the width of the second pulse corresponding to the first pulse of the modulated pulse signal Pulse_Limit is equal to the first preset value.

[0056] For example, see Figure 7 , Figure 7 Another schematic diagram of the phase-locked loop circuit related signals in the embodiment of the present application is shown. After the reference clock signal CLK_Ref is lost, the second phase difference pulse signal Pulse_PH_dn generates a first pulse less than the first preset value T0 at the beginning, and the second modulation pulse signal Pulse_Limit_dn output by the pulse modulation module 20 generates a second pulse with a width equal to the first pulse, so that the oscillation module 40 discharges normally; and after the second phase difference pulse signal Pulse_PH_dn generates a first pulse wider than the first preset value T0, the second modulation pulse signal Pulse_Limit_dn output by the pulse modulation module 20 generates a second pulse with a pulse width fixed to the first preset value T0, thereby making the width of the second pulse corresponding to the first pulse of the modulated pulse signal Pulse_Limit smaller than the width of the first pulse, and finally reducing the discharge rate of the oscillation module 40 when the reference clock signal CLK_Ref is lost, thereby avoiding the phenomenon of rapid decline of the target clock signal CLK_out.

[0057] In some embodiments of the present application, the pulse modulation module 20 further has a pulse restoration mode; in the pulse restoration mode, the width of the first pulse of the phase difference pulse signal Pulse_PH is equal to the width of the second pulse of the modulation pulse signal Pulse_Limit.

[0058] It should be noted that, see Figure 8 , Figure 8 Another schematic diagram of the phase-locked loop circuit related signals in the embodiment of the present application is shown. In addition to the phase difference pulse signal Pulse_PH having a wider pulse when the reference clock is lost, the phase difference pulse signal Pulse_PH has a wider pulse before the loop of the phase-locked loop circuit is stable. In order to shorten the loop stabilization time of the phase-locked loop circuit, before the loop of the phase-locked loop circuit is stable, the pulse modulation module 20 is in a pulse restoration mode. In the pulse restoration mode of the pulse modulation module 20, no matter how wide the pulse of the phase difference pulse signal Pulse_PH pulse signal is, the modulated pulse signal Pulse_Limit output by the pulse modulation module 20 will retain the pulse width, thereby accelerating the loop stabilization process of the phase-locked loop circuit; and after the loop of the phase-locked loop circuit is stable, the pulse modulation module 20 is in a pulse modulation mode. In the pulse modulation mode of the pulse modulation module 20, the pulse width of the modulated pulse signal Pulse_Limit will be limited, thereby reducing the discharge rate of the oscillation module 40 when the reference clock signal CLK_Ref is lost, and ultimately avoiding the phenomenon of rapid decline of the target clock signal CLK_out.

[0059] In some embodiments of the present application, see Fig. 9 , Fig. 9 Another schematic diagram of the phase-locked loop circuit in the embodiment of the present application is shown, wherein the pulse modulation module 20 includes a first delay unit 21, a first NAND gate NAND1 and a first AND gate AND1; the input end of the first delay unit 21 is connected to the phase difference pulse signal Pulse_PH, and the output end of the first delay unit 21 is connected to the first input end of the first NAND gate NAND1; the second input end of the first NAND gate NAND1 is connected to the phase difference pulse signal Pulse_PH, and the output end of the first NAND gate NAND1 is connected to the first input end of the first AND gate AND1; the second input end of the first AND gate AND1 is connected to the phase difference pulse signal Pulse_PH, and the output end of the first AND gate AND1 is connected to the control module 30.

[0060] For example, taking the pulse width of the second phase difference pulse signal Pulse_PH_dn as being smaller than the first preset value, refer to Fig.10 , Fig.10A schematic diagram of the related signals of the pulse modulation module 20 in the embodiment of the present application is shown. Since the pulse width of the second phase difference pulse signal Pulse_PH_dn is small, the second phase difference pulse signal Pulse_PH_dn does not overlap with the delayed second phase difference pulse signal Pulse_PH_dn. Therefore, the output of the first NAND gate NAND1 remains at a high level, so that the pulse width of the second modulation pulse signal Pulse_Limit_dn output by the first AND gate AND1 is consistent with the second phase difference pulse signal Pulse_PH_dn. Ultimately, in the pulse modulation mode of the pulse modulation module 20, when the width of the first pulse of the phase difference pulse signal Pulse_PH is less than or equal to the first preset value, the purpose of the width of the second pulse corresponding to the first pulse of the modulated pulse signal Pulse_Limit is equal to the width of the first pulse.

[0061] On the contrary, taking the pulse width of the second phase difference pulse signal Pulse_PH_dn as an example, which is greater than the first preset value, refer to Fig.11 , Fig.11 Another schematic diagram of the related signals of the pulse modulation module 20 in the embodiment of the present application is shown. Since the pulse of the second phase difference pulse signal Pulse_PH_dn is wider, there is an overlap between the second phase difference pulse signal Pulse_PH_dn and the delayed second phase difference pulse signal Pulse_PH_dn. Therefore, the first NAND gate NAND1 will output a low-level signal at the overlap. Therefore, the pulse width of the second modulated pulse signal Pulse_Limit_dn output by the first AND gate AND1 is equal to the delay duration of the first delay unit 21. Finally, in the pulse modulation mode of the pulse modulation module 20, when the width of the first pulse of the phase difference pulse signal Pulse_PH is greater than the first preset value, the width of the second pulse corresponding to the first pulse of the modulated pulse signal Pulse_Limit is equal to the first preset value (i.e., the delay duration of the first delay unit).

[0062] In some embodiments of the present application, for example, for an embodiment in which the pulse modulation module 20 also has a pulse restoration mode, see Fig.12 , Fig.12 Another schematic diagram of the phase-locked loop circuit in an embodiment of the present application is shown, where the pulse modulation module 20 also includes a first switch S1 and a second switch S2, where one end of the first switch S1 is connected to the phase difference pulse signal Pulse_PH, and the other end is connected to the control module 30 (for example, the control end of the switch S01), and one end of the second switch S2 is connected to the output end of the first AND gate AND1 (for example, the control end of the switch S01), and the other end is connected to the control module 30.

[0063] It should be noted that before the loop of the phase-locked loop circuit is stabilized, the first switch S1 is in a closed state and the second switch S2 is in an open state. At this time, the pulse modulation module 20 is in a pulse restoration mode. No matter how wide the pulse of the phase difference pulse signal Pulse_PH is, the modulated pulse signal Pulse_Limit output by the pulse modulation module 20 will retain the pulse width, thereby speeding up the loop stabilization process of the phase-locked loop circuit. After the loop of the phase-locked loop circuit is stabilized, the first switch S1 is in an open state and the second switch S2 is in a closed state. At this time, the pulse modulation module 20 is in a pulse modulation mode. In the pulse modulation mode of the pulse modulation module 20, the pulse width of the modulated pulse signal Pulse_Limit will be limited, thereby reducing the discharge rate of the oscillation module 40 when the reference clock signal CLK_Ref is lost, and finally avoiding the phenomenon of the target clock signal CLK_out falling rapidly.

[0064] In some embodiments of the present application, see Fig.13 , Fig.13 Another schematic diagram of the phase-locked loop circuit in the embodiment of the present application is shown, and the phase-locked loop circuit also includes a steady-state detection module 50; the steady-state detection module 50 is used to detect whether the loop of the phase-locked loop circuit is stable and control the first switch S1 and the second switch S2. Specifically, before the loop of the phase-locked loop circuit is stable, the steady-state detection module 50 detects that the loop of the phase-locked loop circuit is not stable, so the steady-state detection module 50 can control the first switch S1 to be in a closed state and the second switch S2 to be in an open state, thereby making the pulse modulation module 20 in a pulse restoration mode to speed up the loop stabilization process of the phase-locked loop circuit; after the loop of the phase-locked loop circuit is stable, the steady-state detection module 50 detects that the loop of the phase-locked loop circuit is stable, so the steady-state detection module 50 can control the first switch S1 to be in an open state and the second switch S2 to be in a closed state, thereby making the pulse modulation module 20 in a pulse modulation mode to reduce the discharge rate of the oscillation module 40 when the reference clock signal CLK_Ref is lost.

[0065] Exemplarily, the steady-state detection module 50 may include, but is not limited to, digital circuits such as counters, triggers, and gate circuits to implement loop stability detection of the phase-locked loop circuit. For example, taking the counter performing loop stability detection on the phase-locked loop circuit as an example, the counter may record the number of cycles of the reference clock signal CLK_Ref and the feedback clock signal CLK_Rfb within a fixed time. When the number of cycles of the reference clock signal CLK_Ref and the feedback clock signal CLK_Rfb within the same time period is close to or equal, it indicates that the reference clock signal CLK_Ref is synchronized with the feedback clock signal CLK_Rfb and the loop of the phase-locked loop circuit is stable.

[0066] In some embodiments of the present application, see Fig.14 , Fig.14 Another schematic diagram of the phase-locked loop circuit in an embodiment of the present application is shown, wherein the phase-locked loop circuit also includes a pulse width detection module 60; the pulse width detection module 60 is used to detect the width of the phase difference pulse signal Pulse_PH, and output a first enable signal Clkref_abs when the width of the phase difference pulse signal Pulse_PH is greater than a second preset value (for example, 100ns), and the first enable signal Clkref_abs is used to turn off the control module 30 so that the oscillation module 40 is in a switch self-oscillation state (free running state).

[0067] It should be noted that after the PLL is stable, if the PLL circuit loses the reference clock, only using the pulse modulation module 20 to reduce the discharge rate of the oscillation module 40 can only reduce the frequency drop speed of the target clock signal CLK_out to a certain extent. In the above embodiment, after the pulse modulation module 20 reduces the discharge rate of the oscillation module 40 and thereby preliminarily reduces the frequency decrease speed of the target clock signal CLK_out, the pulse width detection module 60 can output the first enable signal Clkref_abs and turn off the control module 30 when the width of the phase difference pulse signal Pulse_PH is greater than the second preset value (for example, 100ns), so that the oscillation module 40 is in a switch self-oscillation state. In the switch self-oscillation state, the oscillation module 40 will only slowly reduce the frequency of the target clock signal CLK_out under the action of leakage current. That is to say, the pulse modulation module 20 can preliminarily reduce the frequency decrease speed of the target clock signal CLK_out during the period when the pulse width detection module 60 detects the width of the phase difference pulse signal Pulse_PH, and the pulse width detection module 60 can further reduce the frequency decrease speed of the target clock signal CLK_out after detecting the width of the phase difference pulse signal Pulse_PH, thereby helping to further avoid the phenomenon that the protection timing cannot be turned on due to the loss of the main clock, thereby causing chip failure or even chip burning.

[0068] It can be understood that the implementation of shutting down the control module 30 may include but is not limited to shutting down the charge pump, disconnecting the electrical connection between the charge pump and the low-pass filter, disconnecting the electrical connection between the low-pass filter and the oscillation module 40, etc., and this application does not make specific limitations.

[0069] In some embodiments of the present application, the pulse width detection module 60 can use an analog circuit to detect the width of the phase difference pulse signal Pulse_PH. For example, the pulse width detection module 60 may include a capacitor filtering circuit. Since the capacitor in the filtering circuit can absorb the current of the phase difference pulse signal Pulse_PH, after setting the size of the capacitor, the filtering circuit can output the first enable signal Clkref_abs only when the width of the phase difference pulse signal Pulse_PH is greater than a second preset value.

[0070] In some embodiments of the present application, the pulse width detection module 60 may use a digital circuit to detect the width of the phase difference pulse signal Pulse_PH. For example, the pulse width detection module 60 may include a counter, which records the number of cycles of a pulse in the phase difference pulse signal Pulse_PH, so that it can be determined whether its width is greater than a second preset value by the number of cycles of the pulse.

[0071] It is worth noting that the above contents about the phase-locked loop circuit are intended to clearly illustrate the implementation verification process of the present application. Those skilled in the art can also make equivalent modified designs under the guidance of the present application. For example, refer to Fig.15 , Fig.15 Another schematic diagram of the phase-locked loop circuit in the embodiment of the present application is shown, wherein the first delay unit 21, the first NAND gate NAND1 and the first AND gate AND1 can be set only for the second phase difference pulse signal Pulse_PH_dn to output the second modulated pulse signal Pulse_Limit_dn.

[0072] Furthermore, the embodiment of the present application also provides a chip, which includes the above-mentioned phase-locked loop circuit. A chip (Integrated Circuit, IC) is also called a chip, and the chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. Since the chip in the embodiment of the present application is provided with the phase-locked loop circuit of the above-mentioned embodiment, it has all the beneficial effects of the above-mentioned phase-locked loop circuit, which will not be described in detail here.

[0073] Furthermore, in order to better implement the chip in the embodiment of the present application, based on the chip, the present application also provides an electronic device, wherein the electronic device includes the chip as described above. Since the chip in the electronic device of the present application is provided with the phase-locked loop circuit of the above embodiment, it has all the beneficial effects of the above phase-locked loop circuit, which will not be described in detail here.

[0074] Exemplarily, the electronic device may be, but is not limited to, a car, a smart wearable device, a mobile terminal, a smart home device, etc. Among them, the smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, and a cervical massager. The mobile terminal includes, but is not limited to, a smart phone, a laptop, a tablet computer, and a point of sales terminal (POS). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0075] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0076] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0077] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0078] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more embodiments of the invention, in the above description of the embodiments of this application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0079] Each patent, patent application, patent application publication, and other materials, such as articles, books, specifications, publications, documents, etc., cited in this application is hereby incorporated by reference in its entirety, except for application history documents that are inconsistent with or conflicting with the content of this application, and documents that limit the broadest scope of the claims of this application (currently or later attached to this application). It should be noted that if the descriptions, definitions, and / or use of terms in the accompanying materials of this application are inconsistent or conflicting with the content described in this application, the descriptions, definitions, and / or use of terms in this application shall prevail.

[0080] The above is a detailed introduction to a phase-locked loop circuit, chip and electronic device provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A phase-locked loop circuit, characterized in that: include: A phase comparison module, the phase comparison module is used to compare the phases of the reference clock signal and the feedback clock signal and output a phase difference pulse signal; A pulse modulation module, the pulse modulation module is used to output a modulated pulse signal according to the phase difference pulse signal, the pulses of the phase difference pulse signal and the pulses of the modulated pulse signal correspond to each other; A control module, the control module is used to output a control signal according to the modulated pulse signal; An oscillation module, the oscillation module being used to output a target clock signal and the feedback clock signal under the control of the control signal; The pulse modulation module has a pulse modulation mode. In the pulse modulation mode, when the width of the first pulse of the phase difference pulse signal is greater than a first preset value, the width of the second pulse of the modulated pulse signal corresponding to the first pulse is less than the width of the first pulse.

2. The phase-locked loop circuit according to claim 1, characterized in that: When the width of the first pulse of the phase difference pulse signal is less than or equal to a first preset value, the width of the second pulse of the modulated pulse signal corresponding to the first pulse is equal to the width of the first pulse; When the width of the first pulse of the phase difference pulse signal is greater than the first preset value, the width of the second pulse of the modulated pulse signal corresponding to the first pulse is equal to the first preset value.

3. The phase-locked loop circuit according to claim 1, characterized in that: The pulse modulation module also has a pulse restoration mode; In the pulse restoration mode, the width of the first pulse of the phase difference pulse signal is equal to the width of the second pulse of the modulated pulse signal.

4. The phase-locked loop circuit according to claim 3, characterized in that: Before the loop of the phase-locked loop circuit is stabilized, the pulse modulation module is in the pulse restoration mode; After the loop of the phase-locked loop circuit is stabilized, the pulse modulation module is in the pulse modulation mode.

5. The phase-locked loop circuit according to claim 1, characterized in that: The pulse modulation module includes a first delay unit, a first NAND gate and a first AND gate; The input end of the first delay unit is connected to the phase difference pulse signal, and the output end of the first delay unit is connected to the first input end of the first NAND gate; The second input end of the first NAND gate is connected to the phase difference pulse signal, and the output end of the first NAND gate is connected to the first input end of the first AND gate; The second input end of the first AND gate is connected to the phase difference pulse signal, and the output end of the first AND gate is connected to the control module.

6. The phase-locked loop circuit according to claim 5, characterized in that: The pulse modulation module also includes a first switch and a second switch; One end of the first switch is connected to the phase difference pulse signal, and the other end is connected to the control module; One end of the second switch is connected to the output end of the first AND gate, and the other end of the second switch is connected to the control module.

7. The phase-locked loop circuit according to claim 6, characterized in that: The phase-locked loop circuit also includes a steady-state detection module; The steady-state detection module is used to detect whether the loop of the phase-locked loop circuit is stable and control the first switch and the second switch; Wherein, before the loop of the phase-locked loop circuit is stabilized, the first switch is in a closed state, and the second switch is in an open state; After the loop of the phase-locked loop circuit is stabilized, the first switch is in an open state, and the second switch is in a closed state.

8. The phase-locked loop circuit according to claim 1, characterized in that: The phase-locked loop circuit also includes a pulse width detection module; The pulse width detection module is used to detect the width of the phase difference pulse signal, and output a first enable signal when the width of the phase difference pulse signal is greater than a second preset value; The first enable signal is used to shut down the control module so that the oscillation module is in a switch self-oscillation state.

9. A chip, characterized in that: Comprising the phase-locked loop circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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