Delay testing methods, apparatus, systems, equipment, and media for CXL units

Abstract

This invention relates to the field of CXL technology, specifically disclosing a latency testing method, apparatus, system, device, and medium for CXL units. By using an application message manager, messages are sent and received directly to the CXL unit through the corresponding computer fast interconnect interface module and the timestamps are recorded. The computer fast interconnect interface module includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module. This enables direct hardware-based acquisition of message sending and receiving timestamps from the computer fast interconnect unit, avoiding link errors introduced in system-level testing and achieving direct measurement of the latency performance of the computer fast interconnect unit, thus realizing accurate latency performance testing of the computer fast interconnect unit.

Description

Technical Field

[0001] This invention relates to the field of CXL technology, and in particular to a delay testing method, apparatus, system, device and medium for CXL cells. Background Technology

[0002] Compute Express Link (CXL) is a new open interconnect standard used for memory access and consistent caching between hosts and devices that require shared memory resources. A complete Compute Express Link system may contain one or more CXL-enabled hosts and one or more CXL devices. The performance of each of these CXL units directly affects the overall system performance. Therefore, it is essential to fully understand the performance specifications of each CXL unit in the early stages of system design.

[0003] The current method for testing the latency performance of computer fast interconnect units is to use software tools (such as Intel MLC) in the system to test the latency of the computer fast interconnect device (CXL device). Specifically, the computer fast interconnect device (CXL device) is connected to the test host, and the software tool running on the test host's operating system performs multiple read and write operations on the computer fast interconnect device (CXL device), and then the average value is taken as the final performance indicator.

[0004] However, this system testing method is limited by the performance of the test host itself, such as motherboard wiring parameters, Central Processing Unit (CPU) performance, and the physical path from the CPU socket to the Computer Rapid Root (CXL RP) port (when there are multiple CPU sockets). This leads to significant differences in the latency performance test results of the Computer Rapid Root (CXL) device measured by different test hosts, failing to accurately reflect the performance of the CXL device itself and offering little reference value for the design of Computer Rapid Root systems. Furthermore, this system testing method cannot test the performance of the Computer Rapid Root (CXL) device.

[0005] Providing a more accurate test scheme for the latency performance of computer fast interconnect units is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a delay testing method, apparatus, system, device, and medium for CXL units, which can improve the accuracy of delay performance test results for computer fast interconnect units.

[0007] To address the aforementioned technical problems, this invention provides a latency testing method for a CXL unit, applied to a message manager, comprising:

[0008] The test message is sent to the computer fast interconnection unit corresponding to the computer fast interconnection unit under test, and the sending timestamp of the test message is recorded.

[0009] The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit receives the feedback message of the computer under test fast interconnect unit in response to the test message, and records the timestamp of the received feedback message.

[0010] The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the latency test results of the computer under test fast interconnect unit.

[0011] In some implementations, the computer under test (UTP) quick interconnect unit is a UTP quick interconnect terminal interface device.

[0012] The step of sending a test message to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: sending the test message to the computer fast interconnect terminal interface device under test through the computer fast interconnect root port module;

[0013] The step of receiving the feedback message of the computer fast interconnect unit to the test message through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: receiving the feedback message of the computer fast interconnect terminal interface device to the test message through the computer fast interconnect root port module.

[0014] In some implementations, the computer under test (UTP) fast interconnect unit is a UTP fast interconnect root port device;

[0015] The step of sending a test message to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: sending the test message to the computer fast interconnect root port device under test through the computer fast interconnect terminal interface module;

[0016] Receiving the feedback message of the computer fast interconnect unit to the test message through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: receiving the feedback message of the computer fast interconnect root port device to the test message through the computer fast interconnect terminal interface module.

[0017] In some implementations, the computer under test (UTP) fast interconnect unit is a UTP fast interconnect switch;

[0018] The step of sending a test message to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: sending the test message to the uplink port of the computer fast interconnect switch under test through the computer fast interconnect root port module, and sending the test message to the downlink port of the computer fast interconnect switch under test through the computer fast interconnect terminal interface module.

[0019] The step of receiving the feedback message of the computer fast interconnect unit to the test message through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: receiving the feedback message of the uplink port of the computer fast interconnect switch under test through the computer fast interconnect root port module, and receiving the feedback message of the downlink port of the computer fast interconnect switch under test through the computer fast interconnect terminal interface module.

[0020] In some implementations, this also includes:

[0021] The latency test result of the fast interconnect unit of the computer under test is calculated based on the time difference between the sending timestamp and the receiving timestamp.

[0022] In some implementations, calculating the latency test result of the fast interconnect unit of the computer under test based on the time difference between the sending timestamp and the receiving timestamp includes:

[0023] The average time difference between multiple sets of sending timestamps and receiving timestamps is calculated to obtain the latency test result of the fast interconnect unit of the computer under test.

[0024] In some implementations, this also includes:

[0025] The transmission timestamp and the reception timestamp are sent to the test host via the communication module so that the latency test results of the fast interconnect unit of the computer under test can be calculated on the test host.

[0026] In some implementations, sending test messages to the computer fast interconnect unit (UTU) through the computer fast interconnect interface module corresponding to the UTU includes:

[0027] The message type and the number of times each message type is sent are determined based on the latency test parameters sent by the test host.

[0028] The configuration information of the test message to the fast interconnect unit of the computer under test is determined based on the message type and the number of times each message type is sent.

[0029] According to the configuration information of the message to be tested, the test message is sent to the computer fast interconnection unit under test through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test.

[0030] In some implementations, sending test messages to the computer fast interconnect unit (UTU) through the computer fast interconnect interface module corresponding to the UTU includes:

[0031] The test message is obtained by generating a message in the Computer Fast Interconnect Protocol format based on the message parameter data stream sent by the test host.

[0032] The test message is sent to the computer fast interconnection unit under test through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test.

[0033] In some implementations, at least one of the computer fast interconnect root port module, the computer fast interconnect terminal interface module, and the message manager are built based on a programmable controller.

[0034] In some implementations, the programmable controller includes a field-programmable gate array, a complex programmable logic device, a system-on-a-chip, a digital signal processor, or an application-specific integrated circuit.

[0035] To address the aforementioned technical problems, this invention also provides a latency testing method for a CXL unit, applied to a test host, comprising:

[0036] Using a communication module connected to a message manager, the sending timestamp of the test message sent by the message manager to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and the receiving timestamp of the feedback message of the computer fast interconnect unit under test to the test message received by the message manager through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test;

[0037] The latency test result of the fast interconnect unit of the computer under test is calculated based on the sending timestamp and the receiving timestamp.

[0038] The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module.

[0039] In some implementations, this also includes:

[0040] The latency test parameters are sent to the message manager using the memory-mapped bus in the communication module to complete the register configuration of the message manager;

[0041] The latency test parameters include at least: message type and the number of times each message type is sent.

[0042] In some implementations, this also includes:

[0043] A message parameter data stream is sent to the message manager, so that the message manager generates a message in the Computer Fast Connect Protocol format from the message parameter data stream, thus obtaining the test message.

[0044] To address the aforementioned technical problems, the present invention also provides a latency testing device for a CXL unit, comprising: a message manager, a computer fast interconnect root port module, and a computer fast interconnect terminal interface module;

[0045] The message manager is configured to send test messages to the computer under test (UTP) through a computer fast interconnect interface module corresponding to the UTP, and record the sending timestamp of the test messages; and to receive feedback messages from the UTP in response to the test messages through the computer fast interconnect interface module corresponding to the UTP, and record the receiving timestamp of the feedback messages.

[0046] The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes the computer fast interconnect root port module and / or the computer fast interconnect terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the latency test results of the computer under test fast interconnect unit.

[0047] In some implementations, the message manager includes: a message generator, a log buffer, a time module, a sending module, and a receiving module;

[0048] The message generator is connected to the first end of the sending module, the sending module is connected to the first end of the log buffer, the sending module is connected to the third end of the message manager, the receiving module is connected to the second end of the log buffer, the receiving module is connected to the message manager, and the time module's output is connected to the fourth end of the sending module and the third end of the receiving module.

[0049] The message generator is used to send the test message to the fast interconnect unit of the computer under test through the sending module;

[0050] The sending module is used to cache the sending timestamp obtained from the time module when the test message is sent to the log cache;

[0051] The receiving module is used to cache the receiving timestamp obtained from the time module when the feedback message is received to the log cache.

[0052] In some implementations, a communication module is also included;

[0053] The first end of the communication module is used to connect to the test host, and the second end of the communication module is connected to the register configuration interface of the message manager so that the test host can send latency test parameters to the message manager to complete the register configuration of the message manager; the third end of the communication module is connected to the log transmission interface of the message manager so that the test host can read the test message, the feedback message, the sending timestamp and the receiving timestamp recorded in the message register.

[0054] In some implementations, there are multiple computer fast interconnect root port modules and multiple computer fast interconnect terminal interface modules. Each computer fast interconnect root port module is connected to a different interface of the message manager, and each computer fast interconnect terminal interface module is connected to a different interface of the message manager.

[0055] To address the aforementioned technical problems, the present invention also provides a latency testing system for a CXL unit, comprising: a latency testing device for a computer fast interconnect unit and a test host connected to the latency testing device;

[0056] The latency testing device includes a message manager, a computer fast interconnect root port module, a computer fast interconnect terminal interface module, and a communication module. The message manager is used to send test messages to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and record the sending timestamp of the test messages; and to receive feedback messages from the computer fast interconnect unit under test in response to the test messages through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and record the receiving timestamp of the feedback messages.

[0057] The test host is used to read the sending timestamp and the receiving timestamp through the communication module, and calculate the latency test result of the fast interconnect unit of the computer under test based on the sending timestamp and the receiving timestamp;

[0058] The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes the computer fast interconnect root port module and / or the computer fast interconnect terminal interface module.

[0059] To address the aforementioned technical problems, the present invention also provides a latency testing device for a CXL unit, applied to a message manager, comprising:

[0060] The sending unit is used to send a test message to the computer fast interconnection unit under test through a computer fast interconnection interface module corresponding to the computer fast interconnection unit under test, and to record the sending timestamp of the test message;

[0061] The receiving unit is configured to receive a feedback message from the computer fast interconnection unit under test in response to the test message through a computer fast interconnection interface module corresponding to the computer fast interconnection unit under test, and record the receiving timestamp of the feedback message.

[0062] The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the latency test results of the computer under test fast interconnect unit.

[0063] To address the aforementioned technical problems, the present invention also provides a delay testing device for a CXL unit, which, in some embodiments, is applied to a test host and includes:

[0064] The data reading unit is used to read, using the communication module connected to the message manager, the sending timestamp of the test message sent by the message manager to the computer fast interconnection unit under test through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test, and the receiving timestamp of the feedback message of the computer fast interconnection unit under test to the test message received by the message manager through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test.

[0065] The second calculation unit is used to calculate the latency test result of the fast interconnection unit of the computer under test based on the sending timestamp and the receiving timestamp.

[0066] The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module.

[0067] To address the aforementioned technical problems, the present invention also provides a delay testing device for a CXL unit, comprising:

[0068] Memory, used to store computer programs;

[0069] A processor for executing the computer program, which, when executed by the processor, implements the steps of the delay testing method for the CXL unit as described in any of the above.

[0070] To address the aforementioned technical problems, the present invention also provides a medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the steps of the delay testing method for the CXL unit as described in any of the above claims.

[0071] The latency testing method for the CXL unit provided by this invention sends test messages directly to the computer under test (CUT) via the application message manager through the corresponding computer fast interconnect interface module, and records the sending timestamp of the test messages. Then, it receives feedback messages from the CUT in response to the test messages through the corresponding computer fast interconnect interface module, and records the receiving timestamp of the feedback messages. The computer fast interconnect interface module corresponding to the CUT includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module. This method enables direct acquisition of message sending and receiving timestamps from the CUT based on hardware, bypassing the test host operating system and directly building the system on hardware. This avoids link errors introduced in system-level testing and achieves direct measurement of the latency performance of the computer fast interconnect unit, thus enabling accurate testing of the latency performance of the computer fast interconnect unit.

[0072] The present invention also provides a delay testing method, apparatus, system, device and medium for CXL cells, which have the above-mentioned beneficial effects, and will not be repeated here. Attached Figure Description

[0073] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0074] Figure 1 A connection diagram of a delay testing device for a CXL unit provided in an embodiment of the present invention;

[0075] Figure 2 A connection diagram of another delay testing device for a CXL unit provided in an embodiment of the present invention;

[0076] Figure 3 A flowchart illustrating a delay testing method for a CXL cell provided in an embodiment of the present invention;

[0077] Figure 4 This invention provides a connection diagram for testing a fast interconnect terminal interface device for a computer under test.

[0078] Figure 5 This invention provides a schematic diagram of the connection of a Fast Interconnect root port device for testing a computer under test.

[0079] Figure 6 A connection diagram of a fast interconnect switch for testing a computer under test is provided in an embodiment of the present invention;

[0080] Figure 7 A flowchart of another delay testing method for a CXL unit provided in an embodiment of the present invention;

[0081] Figure 8 This is a schematic diagram of the structure of a delay testing device for a CXL unit provided in an embodiment of the present invention;

[0082] Figure 9 A schematic diagram of the structure of another CXL unit delay testing device provided in an embodiment of the present invention;

[0083] Figure 10 This is a schematic diagram of the structure of a delay testing device for a CXL unit provided in an embodiment of the present invention. Detailed Implementation

[0084] The core of this invention is to provide a delay testing method, apparatus, system, device, and medium for CXL units, which can improve the accuracy of delay performance test results for computer fast interconnect units.

[0085] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0086] The first embodiment of the present invention will be described below.

[0087] Figure 1 A connection diagram of a delay testing device for a CXL unit provided in an embodiment of the present invention; Figure 2 This is a connection diagram of another CXL unit delay testing device provided in an embodiment of the present invention.

[0088] To facilitate understanding, the delay testing device for the CXL unit provided by this invention will be introduced first.

[0089] like Figure 1 As shown, the latency testing device for the CXL unit provided by the present invention includes: a message manager 101, a Computer Fast Interconnect Root Port (CXL RP) module 102, and a Computer Fast Interconnect Terminal Interface (CXL EP) module 103.

[0090] like Figure 2 As shown, in the latency testing device for the CXL unit provided by the present invention, the message output interface of the message manager 101 is connected to the message input interface of the computer fast interconnect root port module 102 and the message input interface of the computer fast interconnect terminal interface module 103, respectively.

[0091] The message manager 101 is used to send test messages to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and record the sending timestamp of the test messages; and to receive feedback messages from the computer fast interconnect unit under test in response to the test messages through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and record the receiving timestamp of the feedback messages.

[0092] The computer fast interconnect interface module corresponding to the computer under test includes a computer fast interconnect root port module 102 and / or a computer fast interconnect terminal interface module 103; the sending timestamp and receiving timestamp are used to calculate the latency test results of the computer under test fast interconnect unit.

[0093] In practical applications, the latency testing device for the CXL unit provided by this invention can be used to test the computer fast interconnect unit of the computer under test, which may include three types of interface devices: computer fast interconnect root port device, computer fast interconnect terminal interface device, and computer fast interconnect switch (CXL switch).

[0094] The CXL (Computer Fast Connect) root port device is a device equipped with a CXL root port (CXL EP). In applications, it needs to connect to the CXL terminal interface (CXL RP) of another device to achieve fast computer interconnection. The CXL terminal interface device is a device equipped with a CXL EP. In applications, it needs to connect to the CXL root port (CXL RP) of another device to achieve fast computer interconnection. The CXL switch is a device with uplink and downlink interfaces. The uplink interface connects to the CXL root port (CXL RP) of another device, and the downlink interface connects to the CXL EP of another device to achieve fast computer interconnection.

[0095] In practical applications, the Computer Fast Connect root port device can be either a Computer Fast Connect host (CXLhost) or a Computer Fast Connect device (CXL device). Similarly, the Computer Fast Connect terminal interface device can also be either a Computer Fast Connect host (CXL host) or a Computer Fast Connect device (CXL device). The role of either a Computer Fast Connect root port device or a Computer Fast Connect terminal interface device can be changed by configuring the type of the Computer Fast Connect interface.

[0096] A Computer Rapid Interconnect (CXL) host is a server that supports the Computer Rapid Interconnect protocol.

[0097] A Computer Fast Interconnect (CXL) device can be a board that supports the Computer Fast Interconnect protocol. A CXL device can include, but is not limited to, CXL Type 1 devices, CXL Type 2 devices, and CXL Type 3 devices. Specifically, a CXL Type 1 device refers to a CXL device that supports the Computer Fast Interconnect Input / Output Protocol (CXL.io) and the Computer Fast Interconnect Cache Protocol (CXL.cache). A CXL Type 2 device refers to a CXL device that supports the Computer Fast Interconnect Input / Output Protocol (CXL.io), the Computer Fast Interconnect Cache Protocol (CXL.cache), and the Computer Fast Interconnect Memory Protocol (CXL.mem). A CXL Type 3 device refers to a CXL device that supports both the Computer Fast Interconnect Input / Output Protocol (CXL.io) and the Computer Fast Interconnect Memory Protocol (CXL.mem).

[0098] The latency testing device for the CXL unit provided by this invention can be implemented based on a programmable logic controller (PLC), including but not limited to Field Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices (CPLDs), System-on-Chips (SoCs), Digital Signal Processors (DSPs), and Application Specific Integrated Circuits (ASICs). By pre-programming the PLC, the hardware functions of the message manager 101, the computer fast interconnect root port module 102, and the computer fast interconnect terminal interface module 103 are implemented. Alternatively, the hardware components of the latency testing device for the CXL unit provided by this invention can be built separately, without limitation. By configuring the register parameters of each hardware component, latency test parameters such as message types and the number of times each message type is sent can be configured. This configuration process can be performed before testing or during testing via an external test host.

[0099] The delay testing device for the CXL unit provided by this invention can be designed to use 220V AC mains power for its power interface.

[0100] The Computer Fast Interconnect Root Port Module 102 implements the Computer Fast Interconnect protocol and provides a Computer Fast Interconnect root port type interface for communication with external Computer Fast Interconnect terminal interface devices. In latency testing, it connects to the uplink port of the Computer Fast Interconnect terminal interface device under test (UTD) or the Computer Fast Interconnect switch under test. The logic circuit of the Computer Fast Interconnect Root Port Module 102 includes a Computer Fast Interconnect transport layer, a Computer Fast Interconnect link layer, a Computer Fast Interconnect arbitration multiplexing layer, a flexible bus physical layer, and a Computer Fast Interconnect root port, which is used to connect to the Computer Fast Interconnect unit under test.

[0101] The Computer Fast Interconnect Terminal Interface Module 103 implements the Computer Fast Interconnect protocol and provides an interface of the Computer Fast Interconnect Terminal Interface type for communication with external Computer Fast Interconnect root port devices. In latency testing, it connects to the downlink port of the Computer Fast Interconnect root port device under test or the Computer Fast Interconnect switch under test. The logic circuit of the Computer Fast Interconnect Terminal Interface Module 103 includes a Computer Fast Interconnect transport layer, a Computer Fast Interconnect link layer, a Computer Fast Interconnect arbitration multiplexing layer, a flexible bus physical layer, and a Computer Fast Interconnect Terminal Interface, which is used to connect to the Computer Fast Interconnect unit under test.

[0102] The computer fast interconnect root port module 102 and the computer fast interconnect terminal interface module 103 can be designed to be compatible with 68B-Flit / 256B-Flit (>32GT / s) protocols, and compatible with fourth-generation interfaces (Gen 4: x16, x8, x4, 16GT / s, 8GT / s), fifth-generation interfaces (Gen 5: x16, x8, x4, 32GT / s, 16GT / s, 8GT / s), and sixth-generation interfaces (Gen 6: x16, x8, x4, 64GT / s, 32GT / s, 16GT / s, 8GT / s), etc. By designing them with high-version interface protocols, they can be backward compatible with the fast interconnect units of the computer under test of various interface versions.

[0103] Both the external interfaces of the computer fast interconnect root port module 102 and the computer fast interconnect terminal interface module 103 can be configured as gold fingers, slots, or cable interfaces. Specifically, multiple computer fast interconnect root port modules 102 with different interface forms and multiple computer fast interconnect terminal interface modules 103 with different interface forms can be set on a latency testing device so that they can be directly connected to the computer under test (DUT) during testing. Shortening the link length of the test loop helps to reduce the latency caused by link components other than the DUT, thereby improving the accuracy of the latency test results of the DUT. Therefore, the external interfaces of the computer fast interconnect root port module 102 and the computer fast interconnect terminal interface module 103 are preferably configured as gold fingers or slots.

[0104] The number of computer fast interconnect root port modules 102 can be one or more, and the number of computer fast interconnect terminal interface modules 103 can be one or more. If both the number of computer fast interconnect root port modules 102 and the number of computer fast interconnect terminal interface modules 103 are multiple, each computer fast interconnect root port module 102 is connected to a different interface of the message manager 101, and each computer fast interconnect terminal interface module 103 is connected to a different interface of the message manager 101. Based on this, the latency testing device for the CXL unit provided by this invention can simultaneously test multiple computer fast interconnect units under test, improving testing efficiency.

[0105] The message manager 101 is used to send test messages, record sending timestamps, receive feedback messages, and record feedback timestamps. In this embodiment of the invention, as... Figure 2 As shown, the message manager 101 may include: a message generator, a log buffer, a time module, a sending module, and a receiving module;

[0106] The message generator's first end is connected to the first end (B) of the sending module, the second end (C) of the sending module is connected to the first end of the log buffer, the third end (E) of the sending module is the message output interface of the message manager 101, the first end (B) of the receiving module is connected to the second end of the log buffer, the second end (D) of the receiving module is the message input interface of the message manager 101, and the output end of the time module is connected to the fourth end (D) of the sending module and the third end (C) of the receiving module, respectively.

[0107] The message generator is used to send test messages to the Fast Interconnect Unit (HIT) of the computer under test via the sending module. Specifically, the message generator generates test messages conforming to the Fast Interconnect Protocol (HIP) format based on latency test parameters and sends these test messages to the sending module.

[0108] The sending module is used to cache the sending timestamp obtained from the time module when sending a test message to the log cache. Specifically, the sending module is connected to the transport layer sending channel of one or more computer fast interconnect root port modules 102, and can also be connected to the transport layer sending channel of one or more computer fast interconnect terminal interface modules 103. The sending module receives test messages from the message generator and sends the test messages to the corresponding computer fast interconnect unit under test according to the specified port information (computer fast interconnect root port module 102 or computer fast interconnect terminal interface module 103). After sending the test message, the sending module caches the test message and the corresponding sending timestamp to the log cache.

[0109] The receiving module is used to cache the received timestamp obtained from the time module when a feedback message is received to the log buffer. Specifically, the receiving module can also be connected to the transport layer transmission channel of one or more computer fast interconnect root port modules 102, and the receiving module can also be connected to the transport layer transmission channel of one or more computer fast interconnect terminal interface modules 103. The receiving module receives feedback messages from the computer fast interconnect root port module 102 and / or computer fast interconnect terminal interface module 103, and after receiving the feedback messages, the receiving module caches the feedback messages and the corresponding received timestamps to the log buffer.

[0110] The time module provides high-precision timestamps for both the transmitting and receiving modules. It can be a precise time module, such as a clock module, to provide clock signals to the various components, enabling the transmitting module to determine the transmission timestamp and the receiving module to record the reception timestamp.

[0111] The log buffer is used to receive message transmission logs from the sending and receiving modules. The message transmission logs from the sending module may include identification information and sending timestamps for test messages. The message transmission logs from the receiving module may include identification information and receiving timestamps for feedback messages.

[0112] To facilitate the configuration of latency test parameters and the display of latency test results, such as Figure 1 As shown, the delay testing device for the CXL unit provided by the present invention may further include a communication module 104.

[0113] The first end of the communication module 104 is used to connect to the test host, and the second end of the communication module 104 is connected to the register configuration interface of the message manager 101 so that the test host can send delay test parameters to the message manager 101 to complete the register configuration of the message manager 101. The third end of the communication module 104 is connected to the log transmission interface of the message manager 101 so that the test host can read the test message, feedback message, sending timestamp and receiving timestamp recorded in the message register.

[0114] In practical applications, as described above, the configuration process of the register parameters of each part of the hardware of the delay test device for the CXL unit provided by the present invention can be performed before the test or can be flexibly adjusted through an external test host during the test.

[0115] In addition, the delay test result of the fast interconnect unit of the computer under test can be calculated based on the sending timestamp and receiving timestamp by configuring the register of the delay test device of the CXL unit. Alternatively, the delay test device of the CXL unit can record only the sending timestamp and receiving timestamp, and the test host can read the sending timestamp and receiving timestamp to calculate the delay test result of the fast interconnect unit of the computer under test. The latter can also be implemented through the communication module 104.

[0116] The communication module 104 can be an Ethernet communication module 104, enabling communication between the latency testing device and an external computer. The test host communicates with the latency testing device according to a specified message format. Two application scenarios are distinguished, such as... Figure 2 As shown, in the latency testing device for the CXL unit provided by this invention, the communication module 104 may include a memory-mapped bus, a data stream bus receiver (RX), and a data stream bus transmitter (TX). The communication module 104 maps received messages according to their headers: data request messages are mapped to the internal memory-mapped bus, while data stream messages are mapped to the internal data stream bus. Data transmitted via the data stream bus transmitter (TX) within the latency testing device is also generated into messages according to a specified format and sent to the test host. The latency testing device uses three buses internally for data stream transmission and register reading from internal modules.

[0117] Based on the memory-mapped bus, when the latency test device receives a Control and Status Register (CSR) read request or Control and Status Register (CSR) write request message sent by the test host, the communication module 104 uses the memory-mapped bus to access the control and status register (CSR) of the internal module. The communication module 104 acts as the master of the memory-mapped bus, and other modules inside the latency test device act as slave devices, responding to the control and status register (CSR) read request or control and status register (CSR) write request of the communication module 104 by using different address segments.

[0118] Based on the data stream bus receiver (RX), when the latency testing device receives a unidirectional data stream sent by the test host, the communication module 104 uses the data stream bus receiver (RX) to send a standard data stream to the internal module. This stream flows to the message generator inside the message manager 101, allowing the message generator to generate test messages in the Computer Fast Interconnect Protocol (CHIPC) format according to the latency testing parameters recorded in the standard data stream. The latency testing parameters can include various parameters such as message types encapsulated in a specific format, the number of transmissions for each message type, and address generation methods. Optionally, the message generator can also generate test messages based on pre-configured latency testing parameters without requiring configuration from the test host.

[0119] like Figure 2 As shown, in conjunction with the data stream bus transmitter (TX), the latency testing device for the CXL unit provided by this invention may further include a log transmission module located between the data stream bus transmitter (TX) and the log buffer. Based on the data stream bus transmitter (TX), the latency testing device transmits latency test-related data from the log transmission module inside the message manager 101 to the test host.

[0120] Different latency test parameters are used depending on the type and even model of the Fast Interconnect Unit (TEU) of the computer under test (UTP). By configuring the latency test device, after the tester connects the TPU to the corresponding interface of the latency test device, the device can send device attribute query messages to the TPU via the Fast Interconnect root port module 102 or the Fast Interconnect terminal interface module 103 through the message manager 101. It also receives and parses the messages from the TPU to obtain the type and model of the TPU, allowing it to switch to the corresponding latency test parameters or carry the type and model of the TPU in the cached test log messages.

[0121] The second embodiment of the present invention will be described below.

[0122] like Figure 2 As shown, this embodiment of the invention provides a latency testing system for a CXL unit, which may include: a latency testing device for a computer fast interconnect unit (such as the latency testing device for CXL described in Embodiment 1 of this invention) and a test host connected to the latency testing device.

[0123] The latency testing device includes a message manager 101, a computer fast interconnect root port module 102, a computer fast interconnect terminal interface module 103, and a communication module 104. The message manager 101 sends test messages to the computer fast interconnect unit under test (UTP) through the corresponding UTP interface module and records the sending timestamp of the test messages. It also receives feedback messages from the UTP through the corresponding UTP interface module and records the receiving timestamp of the feedback messages. The corresponding UTP interface module includes the computer fast interconnect root port module 102 and / or the computer fast interconnect terminal interface module 103.

[0124] The test host is used to read the transmission timestamp and reception timestamp recorded by the latency test device, and calculate the latency test result of the fast interconnect unit of the computer under test based on the transmission timestamp and reception timestamp.

[0125] The test host can also be used to visualize the latency test results of the fast interconnect unit of the computer under test using graphical display templates.

[0126] The specific implementation method of the delay testing device can be found in Embodiment 1 of this invention, and will not be repeated here. The testing host can be any computer device.

[0127] Based on the aforementioned delay testing device for the CXL unit, the delay testing method for the CXL unit provided in this embodiment of the invention will be described below with reference to the accompanying drawings.

[0128] The following describes Embodiment 3 of the present invention.

[0129] Figure 3 This is a flowchart of a delay testing method for a CXL cell provided in an embodiment of the present invention.

[0130] like Figure 3 As shown, the latency testing method for the CXL unit provided in this embodiment of the invention, applied to a message manager, includes:

[0131] S301: Send a test message to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and record the sending timestamp of the test message.

[0132] S302: Receive feedback messages from the computer fast interconnect unit of the computer under test (UTP) on the test message through the computer fast interconnect interface module corresponding to the UTP unit, and record the timestamp of the received feedback message.

[0133] The computer fast interconnect interface module corresponding to the computer under test (UTP) fast interconnect unit includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module; the sending timestamp and receiving timestamp are used to calculate the latency test results of the UTP fast interconnect unit.

[0134] To address the problem that in related technologies, system-level testing schemes are affected by the performance of the test host itself, resulting in inaccurate latency test results for the Computer Fast Interconnect Unit (CXL) under test, and cannot test the Computer Fast Interconnect Host (CXL host) or Computer Fast Interconnect Switch (CXL switch), this invention provides a solution applicable to various types of Computer Fast Interconnect Units under Test (CXL) and significantly reducing the impact of other components in the test loop on latency test results.

[0135] In practical implementation, a test loop for the computer under test (BUT) is constructed based on at least one of the following: a computer fast interconnect root port module, a computer fast interconnect terminal interface module, a message manager, and the BUT unit itself. Specifically, the message manager directly sends and receives messages to and from the BUT unit via the corresponding computer fast interconnect interface module, recording the send and receive timestamps. The computer fast interconnect interface module includes the computer fast interconnect root port module and / or the computer fast interconnect terminal interface module. This allows for direct hardware-based acquisition of the message send and receive timestamps from the BUT unit. Based on the send and receive timestamps, the processing latency of the BUT unit for the test message can be calculated. Since message sending and receiving and timestamp recording in this test loop are implemented by the message manager hardware, it avoids complex transmission links like those of a test host and eliminates errors introduced by the operating system running test software to read test results. This significantly reduces the impact of other components in the test loop on the latency test results, improving the accuracy of the latency performance test results for the computer fast interconnect unit.

[0136] It should be noted that, since some fast interconnect units of the computer under test may also actively send messages, in order to ensure the accuracy of the test results, S302: receive the feedback message of the fast interconnect unit of the computer under test in response to the test message through the fast interconnect interface module corresponding to the fast interconnect unit of the computer under test, and record the receiving timestamp of the feedback message. This may include: when receiving a message sent by the fast interconnect unit of the computer under test through the fast interconnect interface module corresponding to the fast interconnect unit of the computer under test, parsing the message and determining whether it is a feedback message of the fast interconnect unit of the computer under test in response to the test message. If it is, record the receiving timestamp of the feedback message; if not, wait for the fast interconnect unit of the computer under test to send a message.

[0137] At least one of the computer fast interconnect root port module and computer fast interconnect terminal interface module, along with the message manager, can be built based on a programmable logic controller (PLC). The PLC can be a Field Programmable Gate Array (FPGA), Complex Programmable Logic Device (CPLD), System on Chip (SoC), Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), etc. Alternatively, at least one of the computer fast interconnect root port module, computer fast interconnect terminal interface module, and message manager can be assembled separately.

[0138] In the latency test method for the CXL unit provided in this embodiment of the invention, the sending timestamp and receiving timestamp recorded by the message manager can be sent to an external test host to calculate the latency test results of the fast interconnect unit of the computer under test, or the message manager can calculate them itself.

[0139] The latency testing method for the CXL unit provided in this embodiment of the invention may further include: calculating the latency test result of the fast interconnect unit of the computer under test based on the time difference between the sending timestamp and the receiving timestamp. To improve the accuracy of the latency test result, multiple tests are performed on the same item, and the average value is taken. Therefore, calculating the latency test result of the fast interconnect unit of the computer under test based on the time difference between the sending timestamp and the receiving timestamp may include: calculating the average value of the time differences between multiple sets of sending timestamps and receiving timestamps to obtain the latency test result of the fast interconnect unit of the computer under test.

[0140] Alternatively, the latency test method for the CXL unit provided in this embodiment of the invention may further include: sending the transmission timestamp and the reception timestamp to the test host via the communication module so as to calculate the latency test result of the fast interconnect unit of the computer under test on the test host.

[0141] When the message manager is connected to an external test host via a communication module, the test host can also configure the message manager's parameters during testing. Therefore, S301: Sending test messages to the computer under test (UTP) via the computer fast interconnect interface module corresponding to the UTP unit can include: determining the message type and the number of times each message type is sent based on the latency test parameters sent by the test host; determining the configuration information of the test messages to the UTP unit based on the message type and the number of times each message type is sent; and sending the test messages to the UTP unit via the computer fast interconnect interface module corresponding to the UTP unit based on the configuration information of the test messages. Furthermore, latency test parameters may also include address generation methods, etc. By determining the configuration information of the test messages to the UTP unit based on the message type and the number of times each message type is sent, the message manager's registers are configured, completing the latency test configuration of the message manager.

[0142] Based on these latency test parameters, the message manager can generate test messages. Then, S301: Sending test messages to the computer under test (UTP) through the computer fast interconnect interface module corresponding to the UTP unit can include: generating a message in the UTP protocol format based on the message parameter data stream sent by the test host, thus obtaining the test message; and sending the test message to the UTP unit through the computer fast interconnect interface module corresponding to the UTP unit.

[0143] The latency testing method for the CXL unit provided in this invention sends test messages directly to the computer under test (CUT) via the application message manager through the corresponding computer fast interconnect interface module, and records the sending timestamp of the test messages. Then, it receives feedback messages from the CUT in response to the test messages through the same computer fast interconnect interface module, and records the receiving timestamp of the feedback messages. The computer fast interconnect interface module corresponding to the CUT includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module. This method directly obtains the message sending and receiving timestamps of the CUT based on hardware, bypassing the test host operating system and directly building the system on hardware. This avoids link errors introduced in system-level testing and enables direct measurement of the latency performance of the computer fast interconnect unit, thus achieving accurate latency performance testing.

[0144] The following describes Embodiment 4 of the present invention.

[0145] Figure 4This is a connection diagram of a test computer fast interconnect terminal interface device provided in an embodiment of the present invention.

[0146] Based on the above embodiments, when the computer under test (UTP) fast interconnect unit is a UTP fast interconnect terminal interface device, S301: send a test message to the UTP fast interconnect unit through the computer fast interconnect interface module corresponding to the UTP fast interconnect unit, including: sending a test message to the UTP fast interconnect terminal interface device through the computer fast interconnect root port module.

[0147] S302: Receive feedback messages from the computer fast interconnect unit of the computer under test for the test message through the computer fast interconnect interface module corresponding to the computer fast interconnect unit of the computer under test, including: receiving feedback messages from the computer fast interconnect terminal interface device of the computer under test for the test message through the computer fast interconnect root port module.

[0148] The types of test messages sent by the device for the Fast Interconnect Terminal Interface of the computer under test may include, but are not limited to: cache snooping request messages sent by the host to the device when the cache is not hit, cache write pull request messages sent by the host to the device, memory read request messages sent by the host to the device, and memory write request messages sent by the host to the device. The corresponding feedback messages include: cache snooping response messages sent by the device to the host, cache data messages sent by the device to the host, memory data messages sent by the device to the host, and no data response messages sent by the device to the host.

[0149] like Figure 4 As shown, by connecting the computer fast interconnect terminal interface of the computer under test (UTP) to the external interface of the computer fast interconnect root port module, a first test loop is formed for the UTP. Based on this first test loop, message transmission and reception related to the UTP are performed.

[0150] The following is combined with Figure 2 This document describes a single test procedure for the latency of the fast interconnect terminal interface device of the computer under test in responding to cached snooping messages.

[0151] The test host sends a request message to test the cache snooping latency. After the communication module parses the message, it configures the control and status registers of the message generator through the memory-mapped bus.

[0152] The message generator generates a cache snoop request (H2D Req Snoop) message sent to the device by a host with a random specified address when the cache is not hit. This message is then sent to the transport layer of the computer fast interconnect root port module via the sending module. Finally, it is sent to the fast interconnect terminal interface device of the computer under test through the external interface of the computer fast interconnect root port module. When the sending module finishes sending, it queries the current timestamp Ts1 as the sending timestamp and sends the H2D ReqSnoop message and the sending timestamp Ts1 together to the log cache for caching.

[0153] Both the message generator and the sending module have entered an idle state.

[0154] When the receiving module receives a message sent by the Fast Interconnect Terminal Interface device of the computer under test, it queries the current timestamp Ts2 and parses the received message. If it is not a D2H Resp Snoop Response message sent by the device to the host, the current timestamp Ts2 is discarded; if it is a D2H Resp Snoop Response message, the D2H Resp Snoop Response message and the corresponding receiving timestamp Ts2 are sent to the log buffer for caching.

[0155] When the log transmission module detects that the data validity signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the external test host.

[0156] The test host calculates the latency of the Fast Interconnect Terminal Interface device of the computer under test responding to the cached snooping message by calculating Ts2-Ts1.

[0157] The following is combined with Figure 2 This document describes the single-pass test procedure for the latency of writing and fetching messages to the response cache of the fast interconnect terminal interface device of the computer under test.

[0158] The test host sends a request message for test cache write-to-fetch latency. After the communication module parses the message, it configures the control and status registers of the message generator through the memory-mapped bus.

[0159] The message generator generates a single cache write pull request (H2D Resp WritePull) message from a host at a randomly specified address to the device and sends it to the transport layer of the computer fast interconnect root port module through the message sending module. Finally, it is sent to the fast interconnect terminal interface device of the computer under test through the external interface of the computer fast interconnect root port module. When the sending module finishes sending, it queries the current timestamp Ts1 as the sending timestamp and sends the H2D RespWritePull message and the Ts1 sending timestamp together to the log cache.

[0160] Both the message generator and the sending module have entered an idle state.

[0161] The receiving module receives the message returned by the Fast Interconnect Terminal Interface device of the computer under test and queries the current timestamp Ts2. The receiving module parses the received message. If it is not a cached data (D2HData) message sent by the device to the host, the current timestamp Ts2 is discarded. If it is a D2H Data message, the receiving module sends the message message D2H Data and the corresponding received timestamp Ts2 to the log buffer.

[0162] When the log transmission module detects that the data validity signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the test host.

[0163] The test host calculates the latency of the fast interconnect terminal interface device of the computer under test to respond to the cache write and pull messages by calculating Ts2-Ts1.

[0164] The following is combined with Figure 2 This document describes the single-pass test procedure for the latency of the fast interconnect terminal interface device of the computer under test responding to the host's memory read message.

[0165] The test host sends a request message to test the memory read latency. After the communication module parses the message, it configures the message generator control and status register through the memory-mapped bus.

[0166] The message generator generates a single memory read request (M2S Req MemRd) message sent from a host at a randomly specified address to the device. This message is then sent to the transport layer of the computer fast interconnect root port module via the message sending module. Finally, it is sent to the fast interconnect terminal interface device of the computer under test through the external interface of the computer fast interconnect root port module. When the sending module finishes sending, it queries the current timestamp Ts1 as the sending timestamp and sends the M2S Req MemRd message and the sending timestamp Ts1 together to the log buffer.

[0167] Both the message generator and the sending module have entered an idle state.

[0168] The receiving module receives a message from the Fast Interconnect Terminal Interface (HIT) device of the computer under test and queries the current timestamp Ts2. The receiving module parses the received message. If it is not a memory data (S2M DRSMemData) message sent by the device to the host, the current timestamp Ts2 is discarded. If it is an S2MDRS MemData message, the message S2M DRSMemData and the corresponding receive timestamp Ts2 are sent to the log buffer.

[0169] When the log transmission module detects that the data validity signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the test host.

[0170] The test host calculates the latency of the Fast Interconnect Terminal Interface device of the computer under test responding to read memory messages by calculating Ts2-Ts1.

[0171] The following is combined with Figure 2 This document describes a single test procedure for the latency of the fast interconnect terminal interface device of the computer under test responding to a host write-to-memory message.

[0172] The test host sends a request message to test the write latency to memory. After the communication module parses the message, it configures the message generator control and status register through the memory-mapped bus.

[0173] The message generator generates a single memory write request (M2S RwD MemWr) message sent from a host at a randomly specified address to the device. This message is then sent to the transport layer of the computer fast interconnect root port module via the message sending module. Finally, it is sent to the fast interconnect terminal interface device of the computer under test through the external interface of the computer fast interconnect root port module. When the sending module finishes sending, it queries the current timestamp Ts1 as the sending timestamp and sends the M2S RwD MemWr message and the sending timestamp Ts1 together to the log buffer.

[0174] Both the message generator and the sending module have entered an idle state.

[0175] The receiving module receives the message returned by the Fast Interconnect Terminal Interface device of the computer under test and queries the current timestamp Ts2. The receiving module parses the received message. If it is not a No Data Response (S2MNDR Cmp) message sent by the device to the host, the current timestamp Ts2 is discarded. If it is an S2M NDR Cmp message, the message message S2M NDRCmp and the corresponding receive timestamp Ts2 are sent to the log buffer.

[0176] When the log transmission module detects that the data validity signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the test host.

[0177] The test host calculates the latency of the Fast Interconnect Terminal Interface device of the computer under test responding to the write-to-memory message by calculating Ts2-Ts1.

[0178] The fifth embodiment of the present invention will be described below.

[0179] Figure 5 This is a schematic diagram of a connection for testing a fast interconnect root port device of a computer under test, provided as an embodiment of the present invention.

[0180] Based on the above embodiments, when the computer under test (UTP) fast interconnect unit is the UTP fast interconnect root port device, S301: send a test message to the UTP fast interconnect unit through the computer fast interconnect interface module corresponding to the UTP fast interconnect unit, including: sending a test message to the UTP fast interconnect root port device through the computer fast interconnect terminal interface module.

[0181] S302: Receive feedback messages from the computer fast interconnect unit of the computer under test (UTP) on the test message through the computer fast interconnect interface module corresponding to the UTP unit, including: receiving feedback messages from the UTP root port device on the test message through the computer fast interconnect terminal interface module.

[0182] The types of test messages sent by the device on the fast interconnect root port of the computer under test may include, but are not limited to: reverse failure snooping request messages sent by the device to the host, and the corresponding feedback messages include: reverse failure response messages sent by the host to the device.

[0183] like Figure 5 As shown, by connecting the computer fast interconnect root port of the computer under test (UTP) to the external interface of the computer fast interconnect terminal interface module of the latency test device, a second test loop is formed for the UTP root port device. Based on this second test loop, message transmission and reception related to the UTP root port device are performed.

[0184] The following is combined with Figure 2 This document describes a single test procedure for the latency of the fast interconnect root port device of the computer under test responding to reverse failure snooping messages.

[0185] The test host sends a request message to test the reverse failure snooping latency. After the communication module parses the message, it configures the message generator control and status register through the memory-mapped bus.

[0186] The message generator generates a single random address device to send a (memory) reverse fail-through request (S2M BISnp) message to the host and sends it to the transport layer of the computer fast interconnect terminal interface module through the message sending module. Finally, it sends the message to the computer fast interconnect root port device under test through the external interface of the computer fast interconnect terminal interface module. When the sending module finishes sending, it queries the current timestamp Ts1 as the sending timestamp and sends the S2M BISnp message and the sending timestamp Ts1 to the log buffer.

[0187] Both the message generator and the sending module have entered an idle state.

[0188] The receiving module receives the message returned by the Fast Interconnect root port device of the computer under test and queries the current timestamp Ts2. It parses the received message. If it is not a (memory) reverse failure response (M2S BIRsp) message sent by the host to the device, the current timestamp Ts2 is discarded. If it is an M2S BIRsp message, the message message M2S BIRsp and the corresponding receive timestamp Ts2 are sent to the log buffer.

[0189] When the log transmission module detects that the data validity signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the test host.

[0190] The test host calculates the latency of the Fast Interconnect root port device of the computer under test responding to the reverse failure snooping message by calculating Ts2-Ts1.

[0191] The following describes Embodiment Six of the present invention.

[0192] Figure 6 This is a connection diagram of a fast interconnect switch for testing a computer under test, provided as an embodiment of the present invention.

[0193] Based on the above embodiments, when the computer under test (UTP) fast interconnect unit is a UTP fast interconnect switch, S301: send test messages to the UTP fast interconnect unit through the computer fast interconnect interface module corresponding to the UTP fast interconnect unit, including: sending test messages to the uplink port of the UTP fast interconnect switch through the computer fast interconnect root port module, and sending test messages to the downlink port of the UTP fast interconnect switch through the computer fast interconnect terminal interface module.

[0194] S302: Receive feedback messages from the computer fast interconnect unit under test for the test message through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, including: receiving feedback messages from the uplink port of the computer fast interconnect switch under test through the computer fast interconnect root port module, and receiving feedback messages from the downlink port of the computer fast interconnect switch under test through the computer fast interconnect terminal interface module.

[0195] The types of test messages sent by the Fast Interconnect switch to the computer under test may include, but are not limited to: Fast Interconnect root port device messages and Fast Interconnect terminal interface device messages.

[0196] like Figure 4As shown, by connecting the uplink interface of the computer under test (UTP) fast interconnect switch to the external interface of the computer fast interconnect root port module of the latency test device, and connecting the downlink interface of the UTP fast interconnect switch to the external interface of the computer fast interconnect terminal interface module of the latency test device, a third test loop is formed for the UTP fast interconnect switch, and message transmission and reception related to the UTP fast interconnect switch are performed based on this third test loop.

[0197] The latency performance test of the computer under test fast interconnect switch is mainly divided into testing the latency of the computer under test fast interconnect switch forwarding computer fast interconnect root port device messages and testing the latency of the computer under test fast interconnect switch forwarding computer fast interconnect terminal interface device messages.

[0198] The following is combined with Figure 2 This section describes the single-pass latency of the Fast Interconnect switch forwarding messages from the Fast Interconnect root port device.

[0199] The test host sends a request message to enumerate the ports of the computer's Fast Interconnect switch. After the communication module parses the message, it controls the message generator and status register through the memory-mapped bus.

[0200] The message generator generates a message to read the extended DVSEC register of the computer's Fast Interconnect switch, and sends it to the uplink port of the Fast Interconnect switch of the computer under test through the external interface of the computer's Fast Interconnect root port module via the message sending module.

[0201] The receiving module listens for messages returned by the computer's Fast Interconnect root port module.

[0202] The test host sends a request message to read the port information of the computer's Fast Interconnect switch. After the communication module parses the message, it reads the control and status registers of the message receiving module through the memory-mapped bus. The reading process is blocked until the receiving module hears the message returned by the computer's Fast Interconnect root port module.

[0203] The test host sends a message indicating the forwarding delay from the uplink port to the downlink port of the computer fast interconnect switch. The message contains the downlink port information of the computer fast interconnect switch corresponding to the interface of the computer fast interconnect terminal interface module of the delay test device. After parsing the message, the communication module controls the message generator and the status register through the memory-mapped bus.

[0204] The message generator generates a memory read request (M2S Req MemRd) message from the host to the device according to specified port information and other parameters. This M2S Req MemRd message is then sent by the sending module to the uplink port of the computer under test's fast interconnect switch via the external interface of the computer fast interconnect root port module. Simultaneously, this M2S Req MemRd message, along with the current timestamp Ts1, is sent to the log buffer. Because the message contains port information, it is forwarded by the computer under test's fast interconnect switch to the corresponding downlink port of the latency test device's computer fast interconnect terminal interface module.

[0205] The receiving module listens for the computer fast interconnect terminal interface module. When it detects an M2S Req MemRd message, it obtains the current timestamp Ts2 and transmits it along with the message to the log buffer. It should be noted that the computer fast interconnect terminal interface module will randomly generate test data and return a memory data (S2M DRS MemData) message sent by the device to the host.

[0206] When the log transmission module detects that the data validity signal of the log buffer is true, it reads the data and sends it to the communication module, and finally uploads it to the test host.

[0207] The test host calculates Ts2-Ts1 to determine the latency of the Fast Interconnect switch forwarding the Fast Interconnect root port device message from the uplink port to the downlink port of the computer under test.

[0208] The following is combined with Figure 2 This section describes the single-pass latency of the Fast Interconnect switch forwarding messages from the Fast Interconnect terminal interface device of the computer under test.

[0209] The latency testing device sends a computer fast interconnect message to the downlink port of the computer fast interconnect switch under test through the computer fast interconnect terminal interface module. This message specifies the external interface of the computer fast interconnect root port module of the latency testing device corresponding to the uplink port.

[0210] The following describes Embodiment Seven of the present invention.

[0211] Figure 7 A flowchart of another delay testing method for a CXL unit provided in an embodiment of the present invention.

[0212] like Figure 7 As shown, when applied to a test host, the latency testing method for the CXL unit provided in this embodiment of the invention may include:

[0213] S701: Using the communication module connected to the message manager, read the sending timestamp of the test message sent by the message manager to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and the receiving timestamp of the feedback message of the computer fast interconnect unit under test to the test message received by the message manager through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test.

[0214] S702: Calculate the latency test result of the fast interconnect unit of the computer under test based on the sending timestamp and receiving timestamp.

[0215] The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module.

[0216] In a specific implementation, the latency testing method for the CXL unit provided in this embodiment of the invention may further include: sending latency test parameters to the message manager using the memory-mapped bus in the communication module to complete the register configuration of the message manager. The latency test parameters include at least: the message type and the number of times each message type is sent.

[0217] The latency testing method for the CXL unit provided in this embodiment of the invention may further include: sending a message parameter data stream to a message manager, so that the message manager generates a message in the Computer Fast Interconnect Protocol format from the message parameter data stream to obtain a test message.

[0218] The latency testing method for the CXL unit provided in this embodiment of the invention may further include: using a graphical display template to visualize the latency test results of the fast interconnect unit of the computer under test.

[0219] For the latency testing method applied to the CXL unit of the test host, please refer to the method description in the above embodiments that include the test host, which will not be repeated here.

[0220] The above details various embodiments of the delay testing method for CXL cells. Based on this, the present invention also discloses a delay testing apparatus, device, and medium for CXL cells corresponding to the above methods.

[0221] The following describes Embodiment 8 of the present invention.

[0222] Figure 8 This is a schematic diagram of the delay testing device for a CXL unit provided in an embodiment of the present invention.

[0223] like Figure 8 As shown, the latency testing device for the CXL unit provided in this embodiment of the invention, applied to a message manager, includes:

[0224] The sending unit 801 is used to send test messages to the computer fast interconnection unit under test through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test, and record the sending timestamp of the test messages;

[0225] The receiving unit 802 is used to receive the feedback message of the computer fast interconnect unit to the test message through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and record the receiving timestamp of the feedback message.

[0226] The computer fast interconnect interface module corresponding to the computer under test (UTP) fast interconnect unit includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module; the sending timestamp and receiving timestamp are used to calculate the latency test results of the UTP fast interconnect unit.

[0227] In some implementations, the computer under test (UTP) fast interconnect unit is a UTP fast interconnect terminal interface device; the sending unit 801 sends test messages to the UTP fast interconnect unit through the computer fast interconnect interface module corresponding to the UTP fast interconnect unit, including: sending test messages to the UTP fast interconnect terminal interface device through the computer fast interconnect root port module;

[0228] The receiving unit 802 receives the feedback message of the computer under test (UTP) to the test message through the computer fast interconnect interface module corresponding to the UTP fast interconnect unit, including: receiving the feedback message of the UTP fast interconnect terminal interface device to the test message through the computer fast interconnect root port module.

[0229] In some implementations, the computer under test (UTP) fast interconnect unit is the UTP fast interconnect root port device; the sending unit 801 sends test messages to the UTP fast interconnect unit through the computer fast interconnect interface module corresponding to the UTP fast interconnect unit, including: sending test messages to the UTP fast interconnect root port device through the computer fast interconnect terminal interface module;

[0230] The receiving unit 802 receives the feedback message of the computer under test (UTP) to the test message through the computer fast interconnect interface module corresponding to the UTP fast interconnect unit, including: receiving the feedback message of the UTP fast interconnect root port device to the test message through the computer fast interconnect terminal interface module.

[0231] In some implementations, the computer under test (UTP) fast interconnect unit is a UTP fast interconnect switch; the sending unit 801 sends test messages to the UTP fast interconnect unit through the computer fast interconnect interface module corresponding to the UTP fast interconnect unit, including: sending test messages to the uplink port of the UTP fast interconnect switch through the computer fast interconnect root port module, and sending test messages to the downlink port of the UTP fast interconnect switch through the computer fast interconnect terminal interface module;

[0232] The receiving unit 802 receives feedback messages from the computer fast interconnect unit under test (UTP) to the test message through the computer fast interconnect interface module corresponding to the UTP fast interconnect unit. This includes receiving feedback messages from the uplink port of the UTP fast interconnect switch through the computer fast interconnect root port module, and receiving feedback messages from the downlink port of the UTP fast interconnect switch through the computer fast interconnect terminal interface module.

[0233] In some implementations, the delay testing apparatus for the CXL unit provided in this embodiment of the invention may further include:

[0234] The first calculation unit is used to calculate the latency test result of the fast interconnect unit of the computer under test based on the time difference between the sending timestamp and the receiving timestamp.

[0235] In some implementations, the computing unit calculates the latency test result of the fast interconnect unit of the computer under test based on the time difference between the sending timestamp and the receiving timestamp, including: calculating the average of the time differences between multiple sets of sending timestamps and receiving timestamps to obtain the latency test result of the fast interconnect unit of the computer under test.

[0236] Alternatively, the delay testing apparatus for the CXL unit provided in this embodiment of the invention may further include:

[0237] The output unit is used to send the transmission timestamp and reception timestamp to the test host via the communication module so that the delay test results of the fast interconnect unit of the computer under test can be calculated on the test host.

[0238] In some implementations, the sending unit 801 sends test messages to the computer fast interconnect unit under test through a computer fast interconnect interface module corresponding to the computer fast interconnect unit under test. This may include: determining the message type and the number of times each message type is sent based on the latency test parameters sent by the test host; determining the configuration information of the test message to the computer fast interconnect unit under test based on the message type and the number of times each message type is sent; and sending the test message to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test based on the configuration information of the test message.

[0239] In some implementations, the sending unit 801 sends a test message to the computer under test (UTP) through a computer fast interconnect interface module corresponding to the UTP unit. This may include: generating a message in the UTP protocol format based on the message parameter data stream sent by the test host to obtain the test message; and sending the test message to the UTP unit through the computer fast interconnect interface module corresponding to the UTP unit.

[0240] In some implementations, at least one of the computer fast interconnect root port module, computer fast interconnect terminal interface module, and message manager is built on a programmable controller, complex programmable logic device, system-on-a-chip, digital signal processor, or application-specific integrated circuit.

[0241] In some implementations, the programmable controller includes a field-programmable gate array (FPGA).

[0242] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0243] The following describes Embodiment Nine of the present invention.

[0244] Figure 9 This is a schematic diagram of another delay testing device for a CXL unit provided in an embodiment of the present invention.

[0245] like Figure 9 As shown, the latency testing device for the CXL unit provided in this embodiment of the invention, applied to a test host, includes:

[0246] The data reading unit 901 is used to read, using the communication module connected to the message manager, the sending timestamp of the test message sent by the message manager to the computer fast interconnection unit under test through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test, and the receiving timestamp of the feedback message of the computer fast interconnection unit under test to the test message received by the message manager through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test.

[0247] The second calculation unit 902 is used to calculate the latency test result of the fast interconnection unit of the computer under test based on the sending timestamp and the receiving timestamp.

[0248] The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module.

[0249] In some implementations, the delay testing apparatus for the CXL unit provided in this embodiment of the invention may further include:

[0250] The first configuration unit is used to send the latency test parameters to the message manager via the memory-mapped bus in the communication module to complete the register configuration of the message manager. The latency test parameters include at least: message type and the number of times each message type is sent.

[0251] In some implementations, the delay testing apparatus for the CXL unit provided in this embodiment of the invention may further include:

[0252] The second configuration unit is used to send a message parameter data stream to the message manager, so that the message manager can generate a message in the Computer Fast Interconnect Protocol format from the message parameter data stream to obtain a test message.

[0253] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0254] The tenth embodiment of the present invention will be described below.

[0255] Figure 10 This is a schematic diagram of the structure of a delay testing device for a CXL unit provided in an embodiment of the present invention.

[0256] like Figure 10 As shown, the delay testing device for the CXL unit provided in this embodiment of the invention includes:

[0257] Memory 1010 is used to store computer program 1011;

[0258] Processor 1020 is configured to execute computer program 1011, which, when executed by processor 1020, implements the steps of the delay test method of CXL unit as described in any of the above embodiments.

[0259] The processor 1020 may include one or more processing cores, such as a 3-core processor or an 8-core processor. The processor 1020 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 1020 may also include a main processor and a coprocessor. The main processor, also known as a Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 1020 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 1020 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.

[0260] The memory 1010 may include one or more media, which may be non-transitory. The memory 1010 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 1010 is used to store at least the following computer program 1011, wherein, after being loaded and executed by the processor 1020, the computer program 1011 is able to implement the relevant steps in the latency testing method of the CXL unit disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 1010 may also include an operating system 1012 and data 1013, etc., and the storage method may be temporary storage or permanent storage. The operating system 1012 may be Windows. The data 1013 may include, but is not limited to, the data involved in the above methods.

[0261] In some embodiments, the delay test device for the CXL unit may further include a display screen 1030, a power supply 1040, a communication interface 1050, an input / output interface 1060, a sensor 1070, and a communication bus 1080.

[0262] Those skilled in the art will understand that Figure 10 The structure shown does not constitute a limitation on the delay test equipment for the CXL unit and may include more or fewer components than shown.

[0263] The latency testing device for CXL units provided in this embodiment of the invention includes a memory and a processor. When the processor executes the program stored in the memory, it can implement the latency testing method for CXL units as described above, with the same effect.

[0264] The following describes embodiment eleven of the present invention.

[0265] It should be noted that the device and equipment embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or modules may be electrical, mechanical, or other forms. Modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0266] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0267] If the integrated modules are implemented as software functional modules and sold or used as independent products, they can be stored in a medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present invention.

[0268] Therefore, embodiments of the present invention also provide a medium storing a computer program, which, when executed by a processor, implements the steps of a latency testing method such as the CXL unit.

[0269] The medium can include various media that can store program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0270] The computer program contained in the medium provided in this embodiment can implement the steps of the delay test method of the CXL unit as described above when executed by the processor, with the same effect.

[0271] The foregoing has provided a detailed description of a delay testing method, apparatus, system, device, and medium for a CXL cell provided by the present invention. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus, device, and medium disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0272] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A delay testing method for a CXL cell, characterized in that, Applied to message managers, including: The test message is sent to the computer fast interconnection unit corresponding to the computer fast interconnection unit under test, and the sending timestamp of the test message is recorded. The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit receives the feedback message of the computer under test fast interconnect unit to the test message, and records the receiving timestamp of the feedback message; The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the latency test results of the computer under test fast interconnect unit; The external interface of the computer fast interconnect interface module is a gold finger or a slot; The message manager and the computer fast interconnect interface module are both implemented based on a programmable controller. The configuration of the latency test parameters required for the latency test of the computer under test fast interconnect unit is achieved by configuring the register parameters of the hardware. The message manager includes: a message generator, a log cache, a time module, a sending module, and a receiving module; The message generator is connected to the first end of the sending module, the sending module is connected to the first end of the log buffer, the sending module is connected to the third end of the message manager, the receiving module is connected to the second end of the log buffer, the receiving module is connected to the message manager, and the time module's output is connected to the fourth end of the sending module and the third end of the receiving module. The step of sending test messages to the computer fast interconnection unit under test through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test, and recording the sending timestamp of the test messages, includes: The message generator is used to send the test message to the fast interconnect unit of the computer under test through the sending module; The sending module is used to cache the sending timestamp obtained from the time module when the test message is sent to the log cache; The step of receiving the feedback message from the computer fast interconnection interface module corresponding to the computer under test (UTP) in response to the test message, and recording the timestamp of the received feedback message, includes: The receiving module is used to cache the receiving timestamp obtained from the time module when the feedback message is received to the log cache.

2. The delay testing method for the CXL unit according to claim 1, characterized in that, The fast interconnect unit of the computer under test is a fast interconnect terminal interface device for the computer under test. The step of sending a test message to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: sending the test message to the computer fast interconnect terminal interface device under test through the computer fast interconnect root port module; The step of receiving the feedback message of the computer fast interconnect unit to the test message through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: receiving the feedback message of the computer fast interconnect terminal interface device to the test message through the computer fast interconnect root port module.

3. The delay testing method for the CXL unit according to claim 1, characterized in that, The fast interconnect unit of the computer under test is the fast interconnect root port device of the computer under test; The step of sending a test message to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: sending the test message to the computer fast interconnect root port device under test through the computer fast interconnect terminal interface module; Receiving the feedback message of the computer fast interconnect unit to the test message through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: receiving the feedback message of the computer fast interconnect root port device to the test message through the computer fast interconnect terminal interface module.

4. The delay testing method for the CXL unit according to claim 1, characterized in that, The fast interconnect unit of the computer under test is a fast interconnect switch for the computer under test; The step of sending a test message to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: sending the test message to the uplink port of the computer fast interconnect switch under test through the computer fast interconnect root port module, and sending the test message to the downlink port of the computer fast interconnect switch under test through the computer fast interconnect terminal interface module. The step of receiving the feedback message of the computer fast interconnect unit to the test message through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: receiving the feedback message of the uplink port of the computer fast interconnect switch under test through the computer fast interconnect root port module, and receiving the feedback message of the downlink port of the computer fast interconnect switch under test through the computer fast interconnect terminal interface module.

5. The delay testing method for the CXL unit according to claim 1, characterized in that, Also includes: The latency test result of the fast interconnect unit of the computer under test is calculated based on the time difference between the sending timestamp and the receiving timestamp.

6. The delay testing method for the CXL unit according to claim 5, characterized in that, The step of calculating the latency test result of the fast interconnect unit of the computer under test based on the time difference between the sending timestamp and the receiving timestamp includes: The average time difference between multiple sets of sending timestamps and receiving timestamps is calculated to obtain the latency test result of the fast interconnect unit of the computer under test.

7. The delay testing method for the CXL unit according to claim 1, characterized in that, Also includes: The transmission timestamp and the reception timestamp are sent to the test host via the communication module so that the latency test results of the fast interconnect unit of the computer under test can be calculated on the test host.

8. The delay testing method for the CXL unit according to claim 1, characterized in that, The step of sending a test message to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: The message type and the number of times each message type is sent are determined based on the latency test parameters sent by the test host. The configuration information of the test message to the fast interconnect unit of the computer under test is determined based on the message type and the number of times each message type is sent. According to the configuration information of the test message, the test message is sent to the computer fast interconnection unit under test through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test.

9. The delay testing method for the CXL unit according to claim 1, characterized in that, The step of sending a test message to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: The test message is obtained by generating a message in the Computer Fast Interconnect Protocol format based on the message parameter data stream sent by the test host. The test message is sent to the computer fast interconnection unit under test through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test.

10. The delay testing method for the CXL unit according to claim 1, characterized in that, The programmable controller includes field-programmable gate arrays, complex programmable logic devices, system-on-a-chip, digital signal processors, or application-specific integrated circuits.

11. A delay testing method for a CXL cell, characterized in that, Applied to test hosts, including: Using a communication module connected to a message manager, the sending timestamp of the test message sent by the message manager to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and the receiving timestamp of the feedback message of the computer fast interconnect unit under test to the test message received by the message manager through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test; The latency test result of the fast interconnect unit of the computer under test is calculated based on the sending timestamp and the receiving timestamp. The computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module. The external interface of the computer fast interconnect interface module is a gold finger or a slot; The message manager and the computer fast interconnect interface module are both implemented based on a programmable controller. The configuration of the latency test parameters required for the latency test of the computer under test fast interconnect unit is achieved by configuring the register parameters of the hardware. The message manager includes: a message generator, a log cache, a time module, a sending module, and a receiving module; The message generator is connected to the first end of the sending module, the sending module is connected to the first end of the log buffer, the sending module is connected to the third end of the message manager, the receiving module is connected to the second end of the log buffer, the receiving module is connected to the message manager, and the time module's output is connected to the fourth end of the sending module and the third end of the receiving module. The step of obtaining the sending timestamp of the test message sent by the message manager to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: The message generator is used to send the test message to the fast interconnect unit of the computer under test through the sending module; The sending module is used to cache the sending timestamp obtained from the time module when the test message is sent to the log cache; The message manager receives the timestamp of the feedback message from the computer fast interconnection unit corresponding to the computer fast interconnection unit under test (UTP) through the computer fast interconnection interface module, including: The receiving module is used to cache the receiving timestamp obtained from the time module when the feedback message is received to the log cache.

12. The delay testing method for the CXL unit according to claim 11, characterized in that, Also includes: The latency test parameters are sent to the message manager using the memory-mapped bus in the communication module to complete the register configuration of the message manager; The latency test parameters include at least: message type and the number of times each message type is sent.

13. The delay testing method for the CXL unit according to claim 12, characterized in that, Also includes: A message parameter data stream is sent to the message manager, so that the message manager generates a message in the Computer Fast Connect Protocol format from the message parameter data stream, thus obtaining the test message.

14. A delay testing device for a CXL cell, characterized in that, include: Message Manager, Computer Fast Connect Root Port Module, and Computer Fast Connect Terminal Interface Module; The message manager is configured to send test messages to the computer under test (UTP) through a computer fast interconnect interface module corresponding to the UTP, and record the sending timestamp of the test messages; and to receive feedback messages from the UTP in response to the test messages through the computer fast interconnect interface module corresponding to the UTP, and record the receiving timestamp of the feedback messages. The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes the computer fast interconnect root port module and / or the computer fast interconnect terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the latency test results of the computer under test fast interconnect unit; The external interface of the computer fast interconnect interface module is a gold finger or a slot; The message manager and the computer fast interconnect interface module are both implemented based on a programmable controller. The configuration of the latency test parameters required for the latency test of the computer under test fast interconnect unit is achieved by configuring the register parameters of the hardware. The message manager includes: a message generator, a log cache, a time module, a sending module, and a receiving module; The message generator is connected to the first end of the sending module, the sending module is connected to the first end of the log buffer, the sending module is connected to the third end of the message manager, the receiving module is connected to the second end of the log buffer, the receiving module is connected to the message manager, and the time module's output is connected to the fourth end of the sending module and the third end of the receiving module. The message manager is used to send test messages to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and to record the sending timestamp of the test message, including: The message generator is used to send the test message to the fast interconnect unit of the computer under test through the sending module; The sending module is used to cache the sending timestamp obtained from the time module when the test message is sent to the log cache; The step of receiving the feedback message from the computer fast interconnection interface module corresponding to the computer under test (UTP) in response to the test message, and recording the timestamp of the received feedback message, includes: The receiving module is used to cache the receiving timestamp obtained from the time module when the feedback message is received to the log cache.

15. The delay testing apparatus for the CXL unit according to claim 14, characterized in that, It also includes a communication module; The first end of the communication module is used to connect to the test host, and the second end of the communication module is connected to the register configuration interface of the message manager so that the test host can send latency test parameters to the message manager to complete the register configuration of the message manager; the third end of the communication module is connected to the log transmission interface of the message manager so that the test host can read the test message, the feedback message, the sending timestamp and the receiving timestamp recorded in the message register.

16. The delay testing apparatus for the CXL unit according to claim 14, characterized in that, The number of computer fast interconnect root port modules and the number of computer fast interconnect terminal interface modules are both multiple. Each computer fast interconnect root port module is connected to a different interface of the message manager, and each computer fast interconnect terminal interface module is connected to a different interface of the message manager.

17. A delay testing system for a CXL cell, characterized in that, include: A latency testing device for a computer fast interconnect unit and a test host connected to the latency testing device; The latency testing device includes a message manager, a computer fast interconnect root port module, a computer fast interconnect terminal interface module, and a communication module. The message manager is used to send test messages to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and record the sending timestamp of the test messages; and to receive feedback messages from the computer fast interconnect unit under test in response to the test messages through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and record the receiving timestamp of the feedback messages. The test host is used to read the sending timestamp and the receiving timestamp through the communication module, and calculate the latency test result of the fast interconnect unit of the computer under test based on the sending timestamp and the receiving timestamp; The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes the computer fast interconnect root port module and / or the computer fast interconnect terminal interface module. The external interface of the computer fast interconnect interface module is a gold finger or a slot; The message manager and the computer fast interconnect interface module are both implemented based on a programmable controller. The configuration of the latency test parameters required for the latency test of the computer under test fast interconnect unit is achieved by configuring the register parameters of the hardware. The message manager includes: a message generator, a log cache, a time module, a sending module, and a receiving module; The message generator is connected to the first end of the sending module, the sending module is connected to the first end of the log buffer, the sending module is connected to the third end of the message manager, the receiving module is connected to the second end of the log buffer, the receiving module is connected to the message manager, and the time module's output is connected to the fourth end of the sending module and the third end of the receiving module. The message manager is used to send test messages to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and to record the sending timestamp of the test message, including: The message generator is used to send the test message to the fast interconnect unit of the computer under test through the sending module; The sending module is used to cache the sending timestamp obtained from the time module when the test message is sent to the log cache; The system receives feedback messages from the computer fast interconnect interface module corresponding to the computer under test (UTP) in response to the test message, and records the timestamp of the received feedback messages, including: The receiving module is used to cache the receiving timestamp obtained from the time module when the feedback message is received to the log cache.

18. A delay testing device for a CXL cell, characterized in that, Applied to message managers, including: The sending module is used to send test messages to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and record the sending timestamp of the test messages; The receiving module is used to receive the feedback message of the computer under test (UTP) to the test message through the computer fast interconnect interface module corresponding to the UTP of the computer under test, and to record the receiving timestamp of the feedback message. The computer fast interconnect interface module corresponding to the computer under test fast interconnect unit includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module; the sending timestamp and the receiving timestamp are used to calculate the latency test results of the computer under test fast interconnect unit; The external interface of the computer fast interconnect interface module is a gold finger or a slot; The message manager and the computer fast interconnect interface module are both implemented based on a programmable controller. The configuration of the latency test parameters required for the latency test of the computer under test fast interconnect unit is achieved by configuring the register parameters of the hardware. The message manager includes: a message generator, a log cache, a time module, a sending module, and a receiving module; The message generator is connected to the first end of the sending module, the sending module is connected to the first end of the log buffer, the sending module is connected to the third end of the message manager, the receiving module is connected to the second end of the log buffer, the receiving module is connected to the message manager, and the time module's output is connected to the fourth end of the sending module and the third end of the receiving module. The sending module is used to send test messages to the computer fast interconnect unit under test through a computer fast interconnect interface module corresponding to the computer fast interconnect unit under test, and to record the sending timestamp of the test messages, including: The sending module is used to send the test message generated by the message generator, and cache the sending timestamp obtained from the time module when sending the test message to the log cache. The receiving module is used to receive a feedback message from the computer fast interconnect unit under test (UTP) in response to the test message through a computer fast interconnect interface module corresponding to the UTP, and to record the timestamp of the received feedback message, including: The receiving module is used to cache the receiving timestamp obtained from the time module when the feedback message is received to the log cache.

19. A delay testing device for a CXL cell, characterized in that, Applied to test hosts, including: The data reading unit is used to read, using the communication module connected to the message manager, the sending timestamp of the test message sent by the message manager to the computer fast interconnection unit under test through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test, and the receiving timestamp of the feedback message of the computer fast interconnection unit under test to the test message received by the message manager through the computer fast interconnection interface module corresponding to the computer fast interconnection unit under test. The second calculation unit is used to calculate the latency test result of the fast interconnection unit of the computer under test based on the sending timestamp and the receiving timestamp. The computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes a computer fast interconnect root port module and / or a computer fast interconnect terminal interface module. The external interface of the computer fast interconnect interface module is a gold finger or a slot; The message manager and the computer fast interconnect interface module are both implemented based on a programmable controller. The configuration of the latency test parameters required for the latency test of the computer under test fast interconnect unit is achieved by configuring the register parameters of the hardware. The message manager includes: a message generator, a log cache, a time module, a sending module, and a receiving module; The message generator is connected to the first end of the sending module, the sending module is connected to the first end of the log buffer, the sending module is connected to the third end of the message manager, the receiving module is connected to the second end of the log buffer, the receiving module is connected to the message manager, and the time module's output is connected to the fourth end of the sending module and the third end of the receiving module. The step of obtaining the sending timestamp of the test message sent by the message manager to the computer fast interconnect unit under test through the computer fast interconnect interface module corresponding to the computer fast interconnect unit under test includes: The message generator is used to send the test message to the fast interconnect unit of the computer under test through the sending module; The sending module is used to cache the sending timestamp obtained from the time module when the test message is sent to the log cache; The message manager receives the timestamp of the feedback message from the computer fast interconnection unit corresponding to the computer fast interconnection unit under test (UTP) through the computer fast interconnection interface module, including: The receiving module is used to cache the receiving timestamp obtained from the time module when the feedback message is received to the log cache.

20. A delay testing device for a CXL unit, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program, which, when executed by the processor, implements the steps of the delay testing method for the CXL unit as described in any one of claims 1 to 12.

21. A medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the delay testing method for the CXL unit as described in any one of claims 1 to 12.

Images