Storage unit, storage structure and preparation method thereof

Abstract

The present disclosure relates to a memory cell, a memory structure, and a method for preparing the same. The memory cell comprises: a write transistor comprising a write word line, a write gate dielectric layer, and a write channel layer, wherein the write word line extends in a first direction, the write gate dielectric layer is located on the sidewall of the write word line, and the write channel layer is located on the sidewall of the write gate dielectric layer; a shared wire extending in a third direction; a first electrode arranged along the first direction with the shared wire, the first electrode and the shared wire being located on the same side of the write channel layer; a read transistor comprising a read gate dielectric layer, a read channel layer, and a read bit line, the read gate dielectric layer being located between the shared wire and the first electrode and extending to the sidewall of the first electrode, the read channel layer comprising a read channel portion, the read channel portion being located on the sidewall of the read gate dielectric layer, and one end of the read channel portion being connected to the shared wire and the other end being connected to the read bit line. The present disclosure can effectively improve storage density in an embodiment.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a memory cell, a memory structure, and a preparation method thereof. Background Art

[0002] With the development of storage technology, people have increasingly higher demands on the integration and density of storage devices.

[0003] Traditionally, storage density has been increased through fabrication methods such as the 6F2 layout and buried word lines. However, further scaling at smaller sizes using these methods can significantly degrade device electrical performance. This makes further scaling very difficult, limiting further increases in storage density.

[0004] The 2T0C architecture memory cell consists of two transistors (a read transistor and a write transistor) without a capacitor, effectively reducing the area occupied by the memory cell and thus helping to increase storage density. However, the storage density of existing 2T0C architecture memory cells still cannot meet the growing demand. Summary of the Invention

[0005] Based on this, the embodiments of the present disclosure provide a storage unit, a storage structure and a preparation method thereof that can further improve storage density.

[0006] A storage unit, comprising:

[0007] A write transistor, comprising a write word line, a write gate dielectric layer, and a write channel layer, wherein the write word line extends along a first direction, the write gate dielectric layer is located on a sidewall of the write word line in a second direction, and the write channel layer is located on a sidewall of the write gate dielectric layer in the second direction, the second direction intersects the first direction, and a plane defined by the first and second directions is a first plane;

[0008] a shared conductive line extending along a third direction, wherein the third direction intersects the first plane;

[0009] a first electrode, arranged along a first direction with the shared conductive line; and in a second direction, the first electrode and the shared conductive line are located on a same side of the write channel layer away from the write gate dielectric layer;

[0010] A read transistor includes a read gate dielectric layer, a read channel layer, and a read bit line. The read gate dielectric layer is located between the shared wire and the first electrode, and extends from between the shared wire and the first electrode to the side wall of the first electrode along the first direction and the side wall of the first electrode along the second direction. The read channel layer includes a read channel portion. The read channel portion is located on the side wall of the read gate dielectric layer away from the write channel layer, and one end of the read channel portion is connected to the shared wire, and the other end is connected to the read bit line.

[0011] In one embodiment, the memory cell further includes a second electrode, and the second electrode is located between the shared conductive line and the write channel layer.

[0012] In one embodiment, the write word line includes a word line portion and a gate portion, the word line portion extends along a first direction, and the same word line portion connects multiple gate portions arranged at intervals along the first direction, and the write gate dielectric layer is located on the side wall of the gate portion in the second direction.

[0013] In one embodiment,

[0014] The size of the gate portion in the third direction is smaller than the size of the word line portion in the third direction,

[0015] The write gate dielectric layer extends from the sidewall of the gate portion to the surface of the write word line along the third direction, and the write channel layer extends from the sidewall of the write gate dielectric layer to the surface of the write gate dielectric layer on the gate portion along the third direction.

[0016] In one embodiment,

[0017] An electrode isolation structure is provided between the shared wire and the first electrode, the electrode isolation structure is located on a sidewall of the write channel layer in the second direction, and a size of the first electrode in the second direction is larger than a size of the electrode isolation structure in the second direction;

[0018] The read gate dielectric layer extends along a sidewall of the electrode isolation structure in the second direction, a sidewall of the first electrode in the first direction, and a sidewall of the first electrode in the second direction.

[0019] In one embodiment, the read bit line extends along a first direction and is disposed opposite to the write word line along a second direction, and the shared conductive line is located between the read bit line and the write word line.

[0020] In one embodiment, the read channel layer further includes a read conductive portion, the read conductive portion extends along the first direction and is located at two ends of the read bit line in the third direction, and the read channel portion is connected to the read conductive portion.

[0021] In one embodiment, the read bit line is spaced apart from the read channel portion.

[0022] In one embodiment, the shared conductive line is connected to a sidewall of the reading channel portion in the second direction.

[0023] A storage structure comprising:

[0024] substrate;

[0025] Multiple memory cell layers are located on the substrate, each of the memory cell layers includes multiple memory cells as described in any one of the above items, the multiple memory cell layers are stacked along the third direction, and the shared conductive line passes through each of the memory cell layers along the third direction and is shared by the relevant memory cells of each of the memory cell layers.

[0026] A method for preparing a storage structure, comprising:

[0027] A substrate is provided, the substrate comprising a stacked structure including an isolation dielectric layer and a sacrificial layer alternately stacked, the stacked structure having a first region, a shared region, and a second region extending along a first direction and arranged along a second direction, the second direction intersecting the first direction, a first isolation structure and a second isolation structure being provided in the shared region and penetrating the stacked structure, the first isolation structure and the second isolation structure being spaced apart in the first direction;

[0028] Removing the sacrificial layer located in the first area and the shared area to form a first hollow cavity, wherein the first hollow cavity includes a first sub-cavity and a second sub-cavity, wherein the first sub-cavity is located in the first area, and the second sub-cavity is located in the shared area and between the first isolation structure and the second isolation structure;

[0029] forming a first electrode in the second sub-cavity;

[0030] forming a write channel layer, a write gate dielectric layer, and a write word line in the first sub-cavity, wherein one end of the write channel layer in the first direction is located on a sidewall of the first electrode, the write gate dielectric layer is located on a sidewall of the write channel layer, and the write word line is located on a sidewall of the write gate dielectric layer and extends along the first direction;

[0031] forming a device through hole on a side of the second isolation structure close to the first isolation structure, and removing the sacrificial layer located in the second region to form a second hollow cavity, wherein the second hollow cavity is connected to the device through hole;

[0032] forming a read gate dielectric layer and a read channel layer in the device through hole and the second hollow cavity, and forming a read bit line, wherein the read gate dielectric layer is located on a sidewall of the device through hole close to the first region, a sidewall of the device through hole close to the first isolation structure, and a sidewall of the second hollow cavity close to the shared region, the read channel layer includes a read channel portion, the read channel portion is formed on a sidewall of the read gate dielectric layer, and the read bit line is connected to the read channel portion;

[0033] A shared wire extending along a third direction is formed through the second isolation structure. The shared wire and the first electrode are arranged along the first direction, and the shared wire is electrically connected to the read channel portion and the write channel layer. The plane determined by the first direction and the second direction is a first plane, and the third direction intersects with the first plane.

[0034] In one embodiment, the second isolation structure includes a first isolation portion and a second isolation portion, the second isolation portion is located between the first isolation portion and the second region, and a size of the second isolation portion in the first direction is larger than a size of the first isolation portion in the first direction.

[0035] When the sacrificial layer located in the first area and the shared area is removed, the first hollow cavity formed further includes a third sub-cavity, the first isolation portion and the second isolation portion surround the third sub-cavity, and a first electrode is formed in the second sub-cavity while a second electrode is formed in the third sub-cavity.

[0036] When a shared conductive line extending along the third direction is formed through the second isolation structure, a shared conductive line connected to the second electrode is formed.

[0037] In one embodiment, forming a write channel layer, a write gate dielectric layer, and a write word line in the first sub-cavity includes:

[0038] forming a write channel material layer and a write gate dielectric material layer in sequence on a sidewall of the first sub-cavity close to the shared area, and forming a write word line material layer to fill the first sub-cavity;

[0039] In the first direction, each pair of the first isolation structure and the second isolation structure serves as an isolation group, and the write channel material layer, the write gate dielectric material layer and the write word line material layer between adjacent isolation groups are etched to form the write channel layer, the write gate dielectric layer and the write word line, wherein the write word line includes a word line portion and a gate portion, the gate portion is connected to the write gate dielectric layer, the word line portion extends along the first direction, and the same word line portion is connected to multiple gate portions arranged at intervals along the first direction.

[0040] In one embodiment, the first area includes a first sub-area and a second sub-area, and the second sub-area is located between the first sub-area and the shared area.

[0041] The step of sequentially forming a write channel material layer and a write gate dielectric material layer on a sidewall of the first sub-cavity close to the shared area, and forming a write word line material layer to fill the first sub-cavity includes:

[0042] In the second sub-region, forming the writing channel material layer on the top wall of the first sub-cavity, the bottom wall of the first sub-cavity and the sidewalls of the first sub-cavity;

[0043] forming the write gate dielectric material layer on the top wall of the first sub-cavity in the first sub-region, the bottom wall of the first sub-cavity in the first sub-region, and the surface of the write channel material layer;

[0044] The write word line material layer is formed on the surface of the write gate dielectric material layer.

[0045] In one embodiment, when a device through hole is formed on a side of the second isolation structure close to the first isolation structure, the device through hole is spaced apart from the first region.

[0046] The shared conductive line extending along the third direction by penetrating the second isolation structure includes:

[0047] A shared through hole is formed in the second isolation structure, the shared through hole isolates the second isolation structure, and the second isolation structure located on a side of the device through hole away from the second region in the second direction forms an electrode isolation structure.

[0048] In one embodiment, forming a read gate dielectric layer and a read channel layer in the device through hole and the second hollow cavity, and forming a read bit line, includes:

[0049] forming a read gate dielectric material layer, a read channel material layer, and a first dielectric material layer in sequence along the inner walls of the device through hole and the second hollow cavity, wherein the first dielectric material layer fills the device through hole and the second hollow cavity;

[0050] removing the read gate dielectric material layer and the read channel material layer located on the sidewall of the device through hole away from the first isolation structure, so that the remaining read gate dielectric material layer forms a read gate dielectric layer, and the remaining read channel material layer forms a read channel layer;

[0051] Filling the remaining space in the device through hole with a second dielectric layer;

[0052] removing a portion of the first dielectric material layer located in the second hollow cavity and away from the shared area, so that the remaining first dielectric material layer forms a first dielectric layer;

[0053] The read bit line is formed in the second hollow cavity.

[0054] The aforementioned memory cell, memory structure, and fabrication method thereof share a conductive line that serves as both the write bit line of the write transistor and the read word line of the read transistor, thereby effectively saving the wiring area of ​​the memory cell and thereby effectively increasing the memory cell density. Furthermore, this simplifies the wiring process and reduces power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0056] Figure 1 is a flow chart of a method for preparing a storage structure provided in one embodiment;

[0057] Figures 2 to 23 Schematic diagram of the structure obtained during the preparation of the storage structure provided in one embodiment, wherein: Figures 8 to 12 for Figure 7 Schematic diagram of the screenshot structure along the AA' direction;

[0058] Figure 24 is a circuit diagram of a storage unit in a storage structure provided in one embodiment;

[0059] Figure 25 A schematic structural diagram of a storage unit provided in one embodiment;

[0060] Figure 26 A schematic structural diagram of a storage unit provided in another embodiment.

[0061] Description of reference numerals:

[0062] 100-base, 110-stacked structure, 111-isolation dielectric layer, 1111-isolation dielectric material layer, 112-sacrificial layer, 121-first isolation structure, 122-second isolation structure, 122a-device through hole, 1221-first isolation portion, 1222-second isolation portion, 1121-sacrificial material layer, 120-substrate, 100a-first sub-cavity, 100b-second hollow cavity, 210-first electrode, 220-second electrode, 2001-electrode material layer, 300-write transistor, 310-write channel layer, 3101-write channel material layer, 320-write gate dielectric layer, 3201-write gate dielectric material layer, 330-write word line, 3301-write word line material layer, 340-sacrificial filling layer, 400-read transistor, 410-read gate dielectric layer, 4101-read gate dielectric material layer, 420-read channel layer, 4201-read channel material layer, 430-read bit line, 500-shared wire, 500a-shared through hole, 6001-first dielectric material layer, 600-first dielectric layer, 700-second dielectric layer. DETAILED DESCRIPTION

[0063] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0065] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0066] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0067] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0068] In one embodiment, see Figure 1 , provides a method for preparing a storage structure, comprising the following steps:

[0069] Step S10, see Figure 3A substrate 100 is provided. The substrate 100 includes a stacked structure 110. The stacked structure 110 includes an isolation dielectric layer 111 and a sacrificial layer 112 alternately stacked. The stacked structure 110 includes a first area A1, a shared area A2, and a second area A3 extending along a first direction and arranged along a second direction. The second direction intersects the first direction. A first isolation structure 121 and a second isolation structure 122 are provided in the shared area A2, penetrating the stacked structure 110. The first isolation structure 121 and the second isolation structure 122 are spaced apart in the first direction.

[0070] Step S20: remove the sacrificial layer 112 in the first area A1 and the shared area A2 to form a first hollow cavity (not shown). The first hollow cavity includes a first sub-cavity 100a (see Figure 6 ) and a second sub-cavity (not shown), the first sub-cavity 100a is located in the first area A1, and the second sub-cavity is located in the shared area A2 and is located between the first isolation structure 121 and the second isolation structure 122;

[0071] Step S30, see Figure 6 , forming a first electrode 210 in the second sub-cavity;

[0072] Step S40, see Figure 7 as well as Figure 23 A write channel layer 310, a write gate dielectric layer 320, and a write word line 330 are formed in the first sub-cavity 100a. One end of the write channel layer 310 in the first direction is located on a sidewall of the first electrode 210. The write gate dielectric layer 320 is located on a sidewall of the write channel layer 310. The write word line 330 is located on a sidewall of the write gate dielectric layer 320 and extends along the first direction.

[0073] Step S50, see Figure 14 , forming a device through hole 122a on a side of the second isolation structure 122 close to the first isolation structure 121, and removing the sacrificial layer 112 located in the second area A3 to form a second hollow cavity 100b, the second hollow cavity 100b communicating with the device through hole 122a;

[0074] Step S60, see Figure 20 A read gate dielectric layer 410 and a read channel layer 420 are formed in the device through hole 122a and the second hollow cavity 100b, and a read bit line 430 is formed. The read gate dielectric layer 410 is located on the sidewall of the device through hole 122a close to the first area A1, the sidewall of the device through hole 122a close to the first isolation structure 121, and the sidewall of the second hollow cavity 100b close to the shared area A2. The read channel layer 420 includes a read channel portion 421 formed on the sidewall of the read gate dielectric layer 410. The read bit line 430 is connected to the read channel portion 421.

[0075] Step S70, see Figure 22 , passes through the second isolation structure 122 to form a shared wire 500 extending along the third direction. The shared wire 500 and the first electrode 210 are arranged along the first direction. The shared wire 500 is electrically connected to the read channel portion 421 and the write channel layer 310. The plane determined by the first direction and the second direction is the first plane, and the third direction intersects with the first plane.

[0076] In step S10, refer to Figure 3 , the substrate 100 includes a stacked structure 110. Figure 2 The base 100 may further include a substrate 120 . The substrate 120 may support the stacked structure 110 .

[0077] The substrate 120 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 120 can be a single-layer structure or a multi-layer structure. For example, the substrate can include a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate can include a Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator substrate. The type of substrate should not limit the scope of protection of this disclosure.

[0078] When forming the stacked structure 110 on the substrate 120, refer to Figure 2 First, isolation dielectric material layers 1111 and sacrificial material layers 1121 made of different materials can be alternately formed on substrate 120 through a deposition process or other means. The material of isolation dielectric material layer 1111 can include, but is not limited to, silicon oxide. The material of sacrificial material layer 1121 can include, but is not limited to, silicon nitride.

[0079] As an example, at least one sacrificial material layer 1121 may be formed, and isolation dielectric material layers 1111 may be formed on both sides of each sacrificial material layer 1121, thereby facilitating the subsequent formation of a memory cell structure between adjacent isolation dielectric material layers 1111. Furthermore, when the number of sacrificial material layers 1121 is greater than two, multiple stacked memory cell layers may be formed, thereby increasing storage density.

[0080] Then, see Figure 3The isolation dielectric material layer 1111 and the sacrificial material layer 1121 can be etched using a photolithography process to form a first isolation trench 121a and a second isolation trench 121b that penetrate the isolation dielectric material layer 1111 and the sacrificial material layer 1121. The first isolation trench 121a and the second isolation trench 121b are spaced apart in the first direction. After etching, the remaining isolation dielectric material layer 1111 can form the isolation dielectric layer 111, and the remaining sacrificial material layer 1121 can form the sacrificial layer 112.

[0081] Afterwards, see Figure 4 An isolation material may be formed in the first isolation trench 121a, the second isolation trench 121b, and on the top surface of the topmost isolation dielectric layer 111. The isolation material is then subjected to a chemical mechanical polishing (CMP) process to form a first isolation structure 121 filling the first isolation trench 121a and a second isolation structure 122 filling the second isolation trench 121b.

[0082] The isolation material may be different from the material of the sacrificial layer 112. Therefore, when the sacrificial layer 112 is subsequently removed, the first isolation structure 121, the second isolation structure 122, and the isolation dielectric layer 111 may be retained. As an example, the isolation material may be the same as the material of the isolation dielectric layer 111.

[0083] In step S20 , the sacrificial layer 112 in the first area A1 and the sacrificial layer 112 in the shared area A2 may be removed simultaneously, thereby forming a first hollow cavity.

[0084] After removing the sacrificial layer 112 located in the shared area A2, the sacrificial layer 112 located between the second isolation structure 122 and the first isolation structure 121 in the shared area A2 is removed, and the second isolation structure 122, the first isolation structure 121 and the adjacent isolation dielectric layer 111 located on both sides of the sacrificial layer 112 can be surrounded to form a second sub-cavity.

[0085] At the same time, after the sacrificial layer 112 in the first area A1 is removed, the space between the adjacent isolation dielectric layers 111 on both sides of the sacrificial layer 112 in the first area A1 is hollowed out, thereby forming the first sub-cavity 100a connected to the second sub-cavity.

[0086] In step S30, refer to Figure 5 The electrode material layer 2001 may be filled in the first hollow cavity by electroplating or chemical vapor deposition. The material of the electrode material layer 2001 may include but is not limited to metal materials.

[0087] Then, see Figure 6The electrode material layer 2001 in the first area A1 may be removed to form a first electrode 210. The first electrode 210 may serve as a source or drain of the write transistor 300 and also as a gate of the read transistor 400.

[0088] In the first direction, the first electrode 210 may be isolated from the second isolation structure 122 by the first isolation structure 121 located on both sides thereof.

[0089] In step S40 , a write channel layer 310 and a write gate dielectric layer 320 may be sequentially formed on the cavity wall of the first sub-cavity 100 a and the surface of the first electrode 210 , and then a write word line 330 may be formed to fill the first sub-cavity 100 a .

[0090] After forming the write channel layer 310 , the write gate dielectric layer 320 , and the write word line 330 in the first sub-cavity 100 a , the write transistor 300 may be formed.

[0091] After a gate voltage signal for turning on the write transistor is applied to the write word line 330, a conductive channel may be formed in the write channel layer 310. The two ends of the write channel layer 310 may serve as a source region and a drain region, respectively.

[0092] The material of the write channel layer 310 may include, but is not limited to, indium gallium zinc oxide (IGZO). IGZO has excellent leakage resistance, thereby improving transistor performance. Furthermore, IGZO material is relatively low in cost and its manufacturing process is relatively simple, effectively reducing process costs.

[0093] The material of the write gate dielectric layer 320 may include, but is not limited to, high dielectric constant materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0094] The write word line 330 can serve as the gate of the write transistor 300. The material of the write word line 330 can include, but is not limited to, tungsten (W). For example, the material of the write word line 330 can also include cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), copper (Cu), or aluminum (Al).

[0095] The write word line 330 extends along the first direction and can connect the write gate dielectric layers 320 of multiple write transistors 300 arranged along the first direction, so that the multiple write transistors 300 arranged along the first direction share the same write word line 330 .

[0096] In step S50, refer to Figure 13The second isolation structure 122 may be etched first to form a device through hole 122a penetrating the second isolation structure 122. The device through hole 122a may extend along the third direction.

[0097] Then, see Figure 14 The sacrificial layer 112 in the second area A3 can be removed, so that the space between the adjacent isolation dielectric layers 111 on both sides of the sacrificial layer 112 is hollowed out to form a second hollow cavity 100b. The second hollow cavity 100b can extend along the first direction and communicate with the device through hole 122a.

[0098] In step S60, refer to Figure 20 After forming a read gate dielectric layer 410 and a read channel layer 420 in the device through hole 122 a and the second hollow cavity 100 b and forming a read bit line 430 , the read transistor 400 may be formed.

[0099] The material of the read gate dielectric layer 410 may include, but is not limited to, a high-k dielectric material such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). The material of the read gate dielectric layer 410 may be the same as or different from the material of the write gate dielectric layer 320.

[0100] The material of the read channel layer 420 may include, but is not limited to, indium gallium zinc oxide (IGZO). IGZO has excellent leakage resistance, thereby improving transistor performance. Furthermore, IGZO material is relatively low in cost and its manufacturing process is relatively simple, effectively reducing process costs.

[0101] When the device through hole 122 a may extend along the third direction, the portions of the read gate dielectric layer 410 and the read channel layer 420 located in the device through hole 122 a may also extend along the third direction.

[0102] Meanwhile, the device through hole 122 a is located on a side of the second isolation structure 122 close to the first isolation structure 121 , so the read gate dielectric layer 410 may be located on a sidewall of the first isolation structure 121 .

[0103] See also Figure 20 The read gate dielectric layer 410 located on the sidewall of the device through hole 122a near the first area A1 is referred to as the first gate dielectric portion 411. The read gate dielectric layer 410 located on the sidewall of the device through hole 122a near the first isolation structure 121 is referred to as the second gate dielectric portion 412. The read gate dielectric layer 410 located on the sidewall of the second hollow cavity 100b near the shared area A2 is referred to as the third gate dielectric portion 413.

[0104] The read channel portion 421 located on the sidewalls of the second gate dielectric portion 412 can form the channel region of the read transistor 400. The read channel portion 421 located on the sidewalls of the first gate dielectric portion 411 and the read channel portion 421 located on the sidewalls of the third gate dielectric portion 413 can serve as the source and drain regions of the read transistor, respectively. Furthermore, the read channel portion 421 located on the sidewalls of the third gate dielectric portion 413 can be connected to the read bit line 430, thereby connecting the read bit line 430 to the source or drain region of the read transistor 400.

[0105] Meanwhile, the first gate dielectric portion 411 , the read channel portion 421 located at the sidewall of the first gate dielectric portion 411 , the second gate dielectric portion 412 , and the read channel portion 421 located at the sidewall of the second gate dielectric portion 412 may extend along the third direction.

[0106] In step S70, refer to Figure 21 , a shared through hole 500a can be formed in the second isolation structure 122, penetrating the second isolation structure 122 and extending along the third direction. Figure 22 , the shared conductive line 500 is filled in the shared through hole 500 a.

[0107] As an example, the shared through hole 500a may expose a portion of the read channel portion 421 located on the sidewall of the first gate dielectric portion 411. In this case, the shared conductive line 500 formed in the shared through hole 500a may be in good contact with the sidewall of the portion of the read channel portion 421 in the second direction, thereby enabling the shared conductive line 500 to be in good contact with the source region or drain region of the read transistor 400.

[0108] Of course, the shared through hole 500 a may also be provided only at the end of the reading channel portion 421 in the first direction, which is not limited here.

[0109] The shared conductive line 500 and the first electrode 210 are arranged along the first direction. The shared conductive line 500 is connected to the read channel portion 421 , thereby connecting to the drain region or source region of the read transistor 400 , thereby serving as a read word line of the read transistor 400 .

[0110] At the same time, the shared conductive line 500 is connected to the write channel layer 310 , thereby serving as a write bit line of the write transistor 300 .

[0111] In this embodiment, a memory cell with a 2TOC architecture can be formed. Meanwhile, the shared conductor 500 serves as both the write bit line of the write transistor 300 and the read word line of the read transistor 400, thereby effectively saving the wiring area of ​​the memory cell and effectively increasing the memory cell density. Furthermore, this simplifies the wiring process and reduces power consumption.

[0112] In one embodiment, see Figure 6 The second isolation structure 122 includes a first isolation portion 1221 and a second isolation portion 1222. The second isolation portion 1222 is located between the first isolation portion 1221 and the second area A3, and the size of the second isolation portion 1222 in the first direction is larger than the size of the first isolation portion 1221 in the first direction.

[0113] At this time, in step S20, when the sacrificial layer 112 located in the first area A1 and the shared area A2 is removed to form the first hollow cavity, a third sub-cavity can be formed on the side of the second isolation portion 1222 close to the first area A1. The third sub-cavity is also located on the side of the first isolation portion 1221 away from the first isolation structure 121. The first isolation portion 1221 and the second isolation portion 1222 can form an L-shape surrounding the third sub-cavity.

[0114] At the same time, in step S30, refer to Figure 6 , while forming the first electrode 210 in the second sub-cavity, the second electrode 220 is also formed in the third sub-cavity.

[0115] For example, after filling the first hollow cavity with an electrode material layer 2001 by electroplating or chemical vapor deposition, the electrode material layer 2001 in the first area A1 is removed, thereby simultaneously forming the first electrode 210 and the second electrode 220. The second electrode 220 and the first electrode 210 can serve as the source and drain of the write transistor 300, respectively.

[0116] Furthermore, in step S70, when forming the shared conductive line 500 extending along the third direction through the second isolation structure 122, a shared through hole 500a with a side surface exposing the second electrode 220 can be formed in the second isolation structure 122. Then, the shared through hole 500a is filled with the shared conductive line 500, thereby forming the shared conductive line 500 connected to the second electrode 220. At this point, the shared conductive line 500 is connected to the write channel layer 310 through the second electrode 220.

[0117] In this embodiment, the second electrode 220 is formed simultaneously with the first electrode 210. Therefore, when forming the write channel layer 310, the write channel layer 310 is formed simultaneously on the surfaces of the first electrode 210 and the second electrode 220. Therefore, when subsequently fabricating the shared conductive line 500, the shared via 500a does not need to expose the write channel layer 310; instead, it only needs to expose the second electrode 220. This effectively protects the write channel layer 310.

[0118] Of course, in other embodiments, the second electrode 220 may not be formed. In this case, as an example, the orthographic projection shape of the second isolation structure 122 on the first plane determined by the first direction and the second direction may be a rectangle, so that when the sacrificial layer 112 is removed to form the first hollow cavity, no third sub-cavity is formed. In addition, when preparing the shared conductive line 500, a shared through hole 500a that exposes the write channel layer 310 may be formed, and then the shared conductive line 500 is filled in the shared through hole 500a, thereby forming a shared conductive line 500 directly connected to the write channel layer 310 (see Figure 25 ).

[0119] In one embodiment, step S40 includes:

[0120] Step S41, please refer to Figure 7 , forming a write channel material layer 3101 and a write gate dielectric material layer 3201 in sequence on the sidewall of the first sub-cavity 100a near the shared area A2, and forming a write word line material layer 3301 to fill the first sub-cavity 100a;

[0121] Step S42, see Figure 23 In the first direction, each pair of first isolation structures 121 and second isolation structures 122 is considered an isolation group. The write channel material layer 3101, write gate dielectric material layer 3201, and write word line material layer 3301 between adjacent isolation groups are etched to form a write channel layer 310, a write gate dielectric layer 320, and a write word line 330. The write word line 330 includes a word line portion 331 and a gate portion 332. The gate portion 332 is connected to the write gate dielectric layer 320. The word line portion 331 extends along the first direction, and the same word line portion 331 connects to multiple gate portions 332 spaced apart along the first direction.

[0122] In step S41, a write channel material layer 3101 and a write gate dielectric material layer 3201 can be sequentially formed on the sidewalls of the first sub-cavity 100a by processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). Then, a write word line material layer 3301 filling the first sub-cavity 100a can be formed by processes such as electroplating.

[0123] Furthermore, the write channel material layer 3101 and the write gate dielectric material layer 3201 can be formed only on the sidewall of the first sub-cavity 100a near the shared area A2, or can extend from the sidewall of the first sub-cavity 100a near the shared area A2. Furthermore, the write channel material layer 3101 and the write gate dielectric material layer 3201 can extend in different ways, which is not limited herein.

[0124] In step S42, a patterned photoresist may be first formed on the top isolation dielectric layer 111. The openings of the patterned photoresist may be opposite to the write channel material layer 3101, the write gate dielectric material layer 3201, and the write word line material layer 3301 between adjacent isolation groups.

[0125] Then, based on patterned photoresist etching, the isolation dielectric layer 111 located in the first area and the write channel material layer 3101, the write gate dielectric material layer 3201 and the write word line material layer 3301 between the adjacent isolation dielectric layers 111 are etched to form a write channel layer 310, a write gate dielectric layer 320 and a write word line 330.

[0126] Meanwhile, as an example, step S42 can be performed after step S70 is completed. Of course, step S42 can also be performed in other steps, for example, it can be performed immediately after step S41. In this case, after the etching step of step S42, the etched area is filled with insulating material, and then subsequent steps such as step S50 are performed.

[0127] In this embodiment, after etching the write channel material layer 3101 and the write gate dielectric material layer 3201 , the write channel layer 310 and the write gate dielectric layer 320 of different write transistors 300 can be separated, thereby separating the different write transistors 300 .

[0128] Furthermore, when the write channel material layer 3101 and the write gate dielectric material layer 3201 are only formed on the sidewall of the first sub-cavity 100a close to the shared area A2, while the write channel material layer 3101 and the write gate dielectric material layer 3201 are etched, the write word line material layer 3301 is also etched, so that the formed write word line 330 includes a word line portion 331 and a gate portion 332, thereby effectively reducing the difficulty of the photolithography process.

[0129] Of course, in some embodiments, when the write channel material layer 3101 and the write gate dielectric material layer 3201 can be formed only on the sidewall of the first sub-cavity 100a close to the shared area A2, if the process conditions are feasible, only the write channel material layer 3101 and the write gate dielectric material layer 3201 can be etched, or only the write channel material layer 3101 can be etched to separate different write transistors 300.

[0130] In one embodiment, see Figure 12 The first area A1 includes a first sub-area A11 and a second sub-area A12, and the second sub-area A12 is located between the first sub-area A11 and the shared area A2.

[0131] Step S41 includes:

[0132] Step S411, please refer to Figure 10 , in the second sub-area A12, a write channel material layer 3101 is formed on the top wall of the first sub-cavity 100a, the bottom wall of the first sub-cavity 100a, and the sidewalls of the first sub-cavity 100a;

[0133] Step S412, please refer to Figure 11 , forming a write gate dielectric material layer 3201 on the top wall of the first sub-cavity 100a in the first sub-area A11, the bottom wall of the first sub-cavity 100a in the first sub-area A11, and the surface of the write channel material layer 3101;

[0134] Step S413, please refer to Figure 12 , a write word line material layer 3301 is formed on the surface of the write gate dielectric material layer 3201.

[0135] In step S411, refer to Figure 9 , a write channel material layer 3101 can be formed on the top wall, bottom wall and sidewall of the first sub-cavity 100a in the first sub-area A11 and the second sub-area A12 by a deposition process. Then, refer to Figure 10 , remove the writing channel material layer 3101 located in the first sub-area A11.

[0136] When removing the write channel material layer 3101 in the first sub-area A11, a sacrificial filling layer 340 may be formed on the surface of the write channel material layer 3101 in the first sub-cavity 100a. The sacrificial filling layer 340 fills the first sub-cavity 100a. Then, the write channel material layer 3101 in the first sub-area A11 and the sacrificial filling layer 340 are removed together by side etching. Figure 11 , remove the sacrificial filling layer 340.

[0137] In step S412, refer to Figure 11 , a write gate dielectric material layer 3201 may be formed on the inner wall of the first sub-cavity 100a having the write channel material layer 3101 formed in the second sub-area A12 through a deposition process.

[0138] In step S413, refer to Figure 12 The write word line material layer 3301 may be formed on the surface of the write gate dielectric material layer 3201 by electroplating or chemical vapor deposition. Furthermore, the write word line material layer 3301 may fill the first sub-cavity 100a.

[0139] Meanwhile, as an example, during the etching step S42, the write channel material layer 3101, the write gate dielectric material layer 3201, and the write word line material layer 3301 located between adjacent isolation groups in the second sub-area A12 may be removed by etching to form the write channel layer 310, the write gate dielectric layer 320, and the write word line 330. At this point, the gate portion 332 of the write word line 330 is located in the second sub-area A12.

[0140] At this time, after step S42 , the size of the gate portion 332 in the third direction is smaller than the size of the word line portion 331 in the third direction.

[0141] At the same time, the write gate dielectric layer 320 extends from the side wall of the gate portion 332 to the surface of the write word line 330 (including the gate portion 332 and the word line portion 331) along the third direction, and the write channel layer 310 extends from the side wall of the write gate dielectric layer 320 to the surface of the write gate dielectric layer 320 along the third direction located in the second sub-area A12 (that is, located on the gate portion 332).

[0142] Of course, in other examples, during the etching step S42, based on the above example, the write channel material layer 3101, the write gate dielectric material layer 3201, and the write word line material layer 3301 located between adjacent isolation groups in the local first sub-area A11 may also be etched away. In this case, the gate portion 332 of the write word line 330 is located in the second sub-area A12 and extends into the local first sub-area A11 adjacent to the second sub-area A12.

[0143] In this embodiment, the write channel layer 310 extends from the side wall of the write gate dielectric layer 320 to the surface of the write gate dielectric layer 320 along the third direction located in the second sub-area A12, thereby effectively increasing the channel width of the write transistor 300, thereby effectively increasing the gate control capability of the write transistor 300.

[0144] In one embodiment, in step S50, see Figure 14 When the device through hole 122 a is formed on a side of the second isolation structure 122 close to the first isolation structure 121 , the device through hole 122 a is spaced apart from the first area A1 .

[0145] Step S70 includes:

[0146] Step S71, see Figure 21 A shared through hole 500a is formed in the second isolation structure 122, and the shared through hole 500a separates the second isolation structure 122. The second isolation structure 122 located on the side of the device through hole 122a away from the second area A3 in the second direction forms an electrode isolation structure 123.

[0147] As an example, the electrode isolation structure 123 may include a first isolation portion 1221 and a portion of a second isolation portion 1222. Alternatively, the electrode isolation structure 123 may include only the first isolation structure 121.

[0148] At this time, the read gate dielectric layer 410 may extend along the sidewalls of the electrode isolation structure 123 in the second direction, the sidewalls of the first electrode 210 in the first direction, and the sidewalls of the first electrode 210 in the second direction.

[0149] In this embodiment, the electrode isolation structure 123 can effectively isolate the first electrode 210 from the shared conductive line 500, and can also effectively isolate the read channel portion 421 formed in the device through-hole 122a from the write channel layer 310, thereby effectively isolating the read transistor 400 from the write transistor 300. When the second electrode 220 is formed simultaneously with the first electrode 210, the electrode isolation structure 123 can also effectively isolate the first electrode 210 from the second electrode 220.

[0150] In one embodiment, step S60 includes:

[0151] Step S61, see Figure 15 as well as Figure 16 , a read gate dielectric material layer 4101, a read channel material layer 4201, and a first dielectric material layer 6001 are sequentially formed along the inner wall of the device through hole 122a and the second hollow cavity 100b, and the first dielectric material layer 6001 fills the device through hole 122a and the second hollow cavity 100b;

[0152] Step S62, see Figure 17 , removing the read gate dielectric material layer 4101 and the read channel material layer 4201 located on the sidewall of the device through hole 122 a away from the first isolation structure 121 , and the remaining read gate dielectric material layer 4101 forms the read gate dielectric layer 410 , and the remaining read channel material layer forms the read channel layer 420 ;

[0153] Step S63, see Figure 18 , filling the remaining space in the device through hole 122a with a second dielectric layer 700;

[0154] Step S64, see Figure 19 , removing a portion of the first dielectric material layer 6001 located in the second hollow cavity 100 b away from the shared area A2 , and the remaining first dielectric material layer 6001 forms the first dielectric layer 600 ;

[0155] Step S65, see Figure 20 , a read bit line 430 is formed in the second hollow cavity 100b.

[0156] In step S61, refer to Figure 15 as well as Figure 16 The read gate dielectric material layer 4101 , the read channel material layer 4201 and the first dielectric material layer 6001 can be formed sequentially through a deposition process.

[0157] The material of the first dielectric material layer 6001 is different from the material of the isolation dielectric layer 111. For example, the material of the first dielectric material layer 6001 may include but is not limited to silicon nitride.

[0158] In step S62, refer to Figure 17 After removing the read gate dielectric material layer 4101 and the read channel material layer 4201 located on the sidewalls of the device through hole 122a away from the first isolation structure 121, the formed read gate dielectric 410 can be located not only on the sidewalls of the device through hole 122a and the sidewalls of the second hollow cavity 100b, but also on the top and bottom walls of the second hollow cavity 100b; the formed read channel layer 420 can also include a read conductive portion 422 in addition to the read channel portion 421. The read channel portion 421 is formed on the sidewalls of the read gate dielectric layer 410, and the read conductive portion 422 is formed on the surface of the read gate dielectric layer 410 located on the top and bottom walls of the second hollow cavity 100b. At the same time, since the second hollow cavity 100b extends along the first direction, the formed read conductive portion 422 also extends along the first direction.

[0159] At this time, the read conductive portion 422 can effectively connect the read channel portion 421 with the subsequently formed read bit line 430 , thereby connecting the source region or the drain region of the read transistor 400 with the read bit line 430 .

[0160] At the same time, as an example, while removing the read gate dielectric material layer 4101 and the read channel material layer 4201 located on the side wall of the device through hole 122a away from the first isolation structure 121, part of the first dielectric material layer 6001 located in the device through hole 122a away from the first isolation structure 121 can also be removed to facilitate process processing.

[0161] In step S63, refer to Figure 18 The material of the second dielectric layer 700 may include, but is not limited to, silicon nitride. The material of the second dielectric layer 700 may be the same as or different from that of the first dielectric material layer 6001.

[0162] At this time, see Figure 21 When forming the shared through hole 500 a in a subsequent step, the second dielectric layer 700 can be etched while etching the second isolation structure 122 , thereby exposing the read channel portion 421 , so that the formed shared conductive line 500 can be connected to the read channel portion 421 .

[0163] In step S64, refer to Figure 19 After removing the portion of the first dielectric material layer 6001 located in the second hollow cavity 100b away from the shared area A2, a portion of the second hollow cavity 100b is hollowed out again. The remaining first dielectric layer 600 includes the unremoved portion of the first dielectric material layer 6001 located in the second hollow cavity 100b and the unremoved portion of the first dielectric material layer 6001 located in the device through hole 122a.

[0164] In step S65, refer to Figure 20 The read bit line 430 can be formed by processes such as electroplating or chemical vapor deposition.

[0165] At this time, the read bit line 430 extends along the first direction and has read conductive portions 422 at both ends in the third direction. The read bit line 430 and the write word line 330 are disposed opposite each other along the second direction, with the shared conductor 500 located between them.

[0166] In this embodiment, the read bit line 430 and the read channel portion 421 are separated by the first dielectric layer 600 , thereby effectively reducing the parasitic capacitance between the read bit line 430 and the first electrode 210 .

[0167] In other embodiments, during step S64, all first dielectric material layers 6001 within the second hollow cavity 100b may be removed. Subsequently, in step S65, the second hollow cavity 100b may be filled with a read bit line 430. In this case, the formed read bit line 430 may be directly connected to the read channel portion 421. The read conductive portions 422 at both ends of the read bit line 430 may also be removed.

[0168] Alternatively, in other embodiments, the read bit line 430 may be formed in other ways. The read bit line 430 may also extend in other directions, which are not limited herein.

[0169] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0170] In one embodiment, see Figure 23 , also provides a storage structure, which can be but is not limited to being prepared by the above-mentioned storage structure preparation method.

[0171] The memory structure includes a substrate 100, a plurality of memory cell layers located on the substrate 100, and each memory cell layer includes a plurality of memory cells 10. The plurality of memory cell layers are stacked along a third direction. The memory cell 10 includes a write transistor 300, a shared conductor 500, a first electrode 210, and a read transistor 400. Figure 24 The shared conductive line 500 serves as both a read word line for the read transistor 400 and a write bit line for the write transistor 300. The shared conductive line 500 penetrates each memory cell layer along the third direction and is shared by the related memory cells 10 of each memory cell layer.

[0172] In one embodiment, see Figure 25 or Figure 26 , a memory cell 10 is also provided, including a write transistor 300 , a shared conductor 500 , a first electrode 210 and a read transistor 400 .

[0173] The write transistor 300 includes a write word line 330 , a write gate dielectric layer 320 , and a write channel layer 310 .

[0174] The write word line 330 extends along a first direction and can serve as the gate of the write transistor 300. The material of the write word line 330 can include, but is not limited to, tungsten (W). For example, the material of the write word line 330 can also include cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), copper (Cu), or aluminum (Al).

[0175] The write gate dielectric layer 320 is located on the sidewall of the write word line 330 in the second direction. The second direction intersects the first direction. As an example, the second direction can be perpendicular to the first direction. Of course, the second direction can also be non-perpendicular to the first direction, and the angle between the second direction and the first direction can be set according to actual needs.

[0176] The sidewall of the same write word line 330 extending along the first direction may be provided with the write gate dielectric layer 320 of multiple write transistors 300 arranged along the first direction, so that the multiple write transistors 300 arranged along the first direction share the same write word line 330 .

[0177] The material of the write gate dielectric layer 320 may include, but is not limited to, high dielectric constant materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0178] The write channel layer 310 is located on the sidewall of the write gate dielectric layer 320 in the second direction. When a gate voltage signal is applied to the write word line 330 to turn on the write transistor 300, a conductive channel is formed in the write channel layer 310. The two ends of the write channel layer 310 can serve as the source region and the drain region.

[0179] The material of the write channel layer 310 may include, but is not limited to, indium gallium zinc oxide (IGZO). IGZO has excellent leakage resistance, which can improve device performance. Furthermore, IGZO material is relatively low in cost and its manufacturing process is relatively simple, effectively reducing process costs.

[0180] The shared conductor 500 extends along a third direction. The plane defined by the first and second directions is the first plane. The third direction intersects the first plane. As an example, the third direction may be perpendicular to the first plane. Of course, the third direction may not be perpendicular to the first plane, and the angle between the third direction and the first plane may be set according to actual needs.

[0181] The first electrode 210 and the shared conductive line 500 are arranged along a first direction. Furthermore, in a second direction, the first electrode 210 and the shared conductive line 500 are located on the same side of the write channel layer 310, away from the write gate dielectric layer 320. The shared conductive line 500 and the first electrode 210 can respectively connect two ends of the write channel layer 310, thereby connecting the source and drain regions of the write channel layer 310. In this case, the shared conductive line 500 can serve as a write bit line for the write transistor 300.

[0182] The material of the first electrode 210 and / or the material of the shared wire 500 may include, but is not limited to, a metal material. As an example, the material of the first electrode 210 is the same as the material of the shared wire 500. Of course, the two materials may also be different.

[0183] The read transistor 400 includes a read gate dielectric layer 410 , a read channel layer 420 , and a read bit line 430 .

[0184] The read gate dielectric layer 410 is located between the shared conductive line 500 and the first electrode 210 , and extends from between the shared conductive line 500 and the first electrode 210 to the sidewalls of the first electrode 210 along the first direction and the sidewalls of the first electrode 210 along the second direction.

[0185] The material of the read gate dielectric layer 410 may include, but is not limited to, a high-k dielectric material such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). The material of the read gate dielectric layer 410 may be the same as or different from the material of the write gate dielectric layer 320.

[0186] The read channel layer 420 includes a read channel portion 421 . The read channel portion 421 is located on a sidewall of the read gate dielectric layer 410 away from the write channel layer 310 . One end of the read channel portion 421 is connected to the shared conductive line 500 , and the other end is connected to the read bit line 430 .

[0187] See also Figure 25 The read gate dielectric layer 410 located between the shared conductive line 500 and the first electrode 210 is referred to as a first gate dielectric portion 411. The read gate dielectric layer 410 located on the sidewall of the first electrode 210 along the first direction is referred to as a second gate dielectric portion 412, and the read gate dielectric layer 410 located on the sidewall of the first electrode 210 along the second direction is referred to as a third gate dielectric portion 413.

[0188] The read channel portion 421 located on the sidewalls of the second gate dielectric portion 412 can form the channel region of the read transistor 400. The read channel portion 421 located on the sidewalls of the first gate dielectric portion 411 and the read channel portion 421 located on the sidewalls of the third gate dielectric portion 413 can serve as the source and drain regions of the read transistor 400, respectively. Furthermore, the read channel portion 421 located on the sidewalls of the first gate dielectric portion can be connected to the shared conductive line 500, while the read channel portion 421 located on the sidewalls of the third gate dielectric portion can be connected to the read bit line 430, thereby connecting the shared conductive line 500 and the read bit line 430 to the source and drain regions of the read transistor 400, respectively. In this case, the shared conductive line 500 also serves as the read word line for the read transistor 400.

[0189] The material of the read channel layer 420 may include, but is not limited to, indium gallium zinc oxide (IGZO). IGZO material has good anti-leakage characteristics, which can improve device performance. In addition, IGZO material cost is relatively low and the process is relatively simple, which can effectively reduce process costs.

[0190] In this embodiment, the memory cell utilizes a 2T0C architecture. The shared conductor 500 serves as both the write bit line for the write transistor 300 and the read word line for the read transistor 400, effectively saving the memory cell wiring area and thereby increasing the memory cell density. This also simplifies the wiring process and reduces power consumption.

[0191] In one embodiment, see Figure 26 The memory cell 10 further includes a second electrode 220 , which is located between the shared conductive line 500 and the write channel layer 310 .

[0192] The material of the second electrode 220 may be the same as or different from that of the first electrode 210 .

[0193] In one embodiment, see Figure 25 or Figure 26 The write word line 330 includes a word line portion 331 and a gate portion 332. The word line portion 331 extends along the first direction. The same word line portion 331 connects multiple gate portions 332 spaced apart along the first direction. The write gate dielectric layer 320 is located on the sidewalls of the gate portion 332 in the second direction.

[0194] In one embodiment, a dimension of the gate portion 332 in the third direction is smaller than a dimension of the word line portion 331 in the third direction.

[0195] The write gate dielectric layer 320 extends from the sidewall of the gate portion 332 to the surface of the write word line 330 along the third direction. In this case, the write gate dielectric layer 320 may extend from the sidewall of the gate portion 332 to the surface of the gate portion 332 along the third direction, or may extend to the surfaces of the gate portion 332 and the word line portion 331 along the third direction.

[0196] The write channel layer 310 extends from the sidewall of the write gate dielectric layer 320 to the surface of the write gate dielectric layer 320 located on the gate portion 332 along the third direction.

[0197] At this time, the channel width of the write transistor 300 can be effectively increased, thereby effectively increasing the gate control capability of the write transistor 300.

[0198] In one embodiment, see Figure 25 or Figure 26 An electrode isolation structure 123 is provided between the shared conductive line 500 and the first electrode 210. The electrode isolation structure 123 is located on a sidewall of the write channel layer 310 in the second direction, and a dimension of the first electrode 210 in the second direction is larger than a dimension of the electrode isolation structure 123 in the second direction;

[0199] The read gate dielectric layer 410 extends along the sidewall of the electrode isolation structure 123 in the second direction, the sidewall of the first electrode 210 in the first direction, and the sidewall of the first electrode 210 in the second direction.

[0200] At this time, the electrode isolation structure 123 can effectively isolate the first electrode 210 from the shared conductive line 500, and can also effectively isolate the read channel portion 421 from the write channel layer 310, thereby effectively isolating the read transistor 400 from the write transistor 300. When the memory cell 10 further includes the second electrode 220, the electrode isolation structure 123 can also effectively isolate the first electrode 210 from the second electrode 220.

[0201] In one embodiment, see Figure 25 or Figure 26 The read bit line 430 extends along the first direction and is arranged opposite to the write word line 330 along the second direction. The shared conductive line 500 is located between the read bit line 430 and the write word line 330 .

[0202] In one embodiment, see Figure 26 The read channel layer 420 further includes a read conductive portion 422 , which extends along the first direction and is located at both ends of the read bit line 430 in the third direction, and the read channel portion 421 is connected to the read conductive portion 422 .

[0203] At this time, the read bit line 430 may be connected to the read channel portion 421 through the read conductive portion 422 .

[0204] In one embodiment, see Figure 25 or Figure 26 The read bit line 430 and the read channel portion 421 are spaced apart from each other, thereby effectively reducing the parasitic capacitance between the read bit line 430 and the first electrode 210 .

[0205] In one embodiment, see Figure 25 or Figure 26 The shared conductive line 500 is connected to the sidewall of the read channel portion 421 in the second direction, thereby increasing the contact area between the shared conductive line 500 and the read channel portion 421 and reducing the contact resistance therebetween.

[0206] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0207] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A storage unit, characterized in that: include: A write transistor, comprising a write word line, a write gate dielectric layer, and a write channel layer, wherein the write word line extends along a first direction, the write gate dielectric layer is located on a sidewall of the write word line in a second direction, and the write channel layer is located on a sidewall of the write gate dielectric layer in the second direction, the second direction intersects the first direction, and a plane defined by the first and second directions is a first plane; a shared conductive line extending along a third direction, wherein the third direction intersects the first plane; a first electrode, arranged along a first direction with the shared conductive line; and in a second direction, the first electrode and the shared conductive line are located on a same side of the write channel layer away from the write gate dielectric layer; A read transistor includes a read gate dielectric layer, a read channel layer, and a read bit line. The read gate dielectric layer is located between the shared wire and the first electrode, and extends from between the shared wire and the first electrode to the side wall of the first electrode along the first direction and the side wall of the first electrode along the second direction. The read channel layer includes a read channel portion. The read channel portion is located on the side wall of the read gate dielectric layer away from the write channel layer, and one end of the read channel portion is connected to the shared wire, and the other end is connected to the read bit line.

2. The storage unit according to claim 1, wherein The write word line includes a word line portion and a gate portion, the word line portion extends along a first direction, and the same word line portion connects multiple gate portions arranged at intervals along the first direction, and the write gate dielectric layer is located on the side wall of the gate portion in the second direction.

3. The storage unit according to claim 2, wherein: The size of the gate portion in the third direction is smaller than the size of the word line portion in the third direction, The write gate dielectric layer extends from the sidewall of the gate portion to the surface of the write word line along the third direction, and the write channel layer extends from the sidewall of the write gate dielectric layer to the surface of the write gate dielectric layer on the gate portion along the third direction.

4. The storage unit according to claim 1, wherein: An electrode isolation structure is provided between the shared wire and the first electrode, the electrode isolation structure is located on a sidewall of the write channel layer in the second direction, and a size of the first electrode in the second direction is larger than a size of the electrode isolation structure in the second direction; The read gate dielectric layer extends along a sidewall of the electrode isolation structure in the second direction, a sidewall of the first electrode in the first direction, and a sidewall of the first electrode in the second direction. The storage unit according to claim 1 , wherein: The read bit line extends along a first direction and is arranged opposite to the write word line along a second direction. The shared conductive line is located between the read bit line and the write word line. The storage unit according to claim 5 , wherein: The read channel layer further includes a read conductive portion extending along the first direction and located at both ends of the read bit line in the third direction, and the read channel portion is connected to the read conductive portion.

7. The storage unit according to claim 6, wherein: The read bit line is spaced apart from the read channel portion.

8. The storage unit according to claim 1, wherein: The shared conductive line connects sidewalls of the reading channel portion in the second direction.

9. A storage structure, characterized in that: include: substrate; A plurality of memory cell layers are located on the substrate, each of the memory cell layers includes a plurality of memory cells according to any one of claims 1 to 8, the plurality of memory cell layers are stacked along the third direction, and the shared conductive line penetrates each of the memory cell layers along the third direction and is shared by related memory cells of each of the memory cell layers.

10. A method for preparing a storage structure, characterized in that: include: A substrate is provided, the substrate comprising a stacked structure including an isolation dielectric layer and a sacrificial layer alternately stacked, the stacked structure having a first region, a shared region, and a second region extending along a first direction and arranged along a second direction, the second direction intersecting the first direction, a first isolation structure and a second isolation structure being provided in the shared region and penetrating the stacked structure, the first isolation structure and the second isolation structure being spaced apart in the first direction; Removing the sacrificial layer located in the first area and the shared area to form a first hollow cavity, wherein the first hollow cavity includes a first sub-cavity and a second sub-cavity, wherein the first sub-cavity is located in the first area, and the second sub-cavity is located in the shared area and between the first isolation structure and the second isolation structure; forming a first electrode in the second sub-cavity; forming a write channel layer, a write gate dielectric layer, and a write word line in the first sub-cavity, wherein one end of the write channel layer in the first direction is located on a sidewall of the first electrode, the write gate dielectric layer is located on a sidewall of the write channel layer, and the write word line is located on a sidewall of the write gate dielectric layer and extends along the first direction; forming a device through hole on a side of the second isolation structure close to the first isolation structure, and removing the sacrificial layer located in the second region to form a second hollow cavity, wherein the second hollow cavity is connected to the device through hole; forming a read gate dielectric layer and a read channel layer in the device through hole and the second hollow cavity, and forming a read bit line, wherein the read gate dielectric layer is located on a sidewall of the device through hole close to the first region, a sidewall of the device through hole close to the first isolation structure, and a sidewall of the second hollow cavity close to the shared region, the read channel layer includes a read channel portion, the read channel portion is formed on a sidewall of the read gate dielectric layer, and the read bit line is connected to the read channel portion; A shared wire extending along a third direction is formed through the second isolation structure. The shared wire and the first electrode are arranged along the first direction, and the shared wire is electrically connected to the read channel portion and the write channel layer. The plane determined by the first direction and the second direction is a first plane, and the third direction intersects with the first plane.

11. The method for preparing a storage structure according to claim 10, characterized in that: The second isolation structure includes a first isolation portion and a second isolation portion, the second isolation portion is located between the first isolation portion and the second region, and a size of the second isolation portion in the first direction is larger than a size of the first isolation portion in the first direction. When the sacrificial layer located in the first area and the shared area is removed, the first hollow cavity formed further includes a third sub-cavity, the first isolation portion and the second isolation portion surround the third sub-cavity, and a first electrode is formed in the second sub-cavity while a second electrode is formed in the third sub-cavity. When a shared conductive line extending along the third direction is formed through the second isolation structure, a shared conductive line connected to the second electrode is formed.

12. The method for preparing a storage structure according to claim 10, characterized in that: Forming a write channel layer, a write gate dielectric layer, and a write word line in the first sub-cavity, including: forming a write channel material layer and a write gate dielectric material layer in sequence on a sidewall of the first sub-cavity close to the shared area, and forming a write word line material layer to fill the first sub-cavity; In the first direction, each pair of the first isolation structure and the second isolation structure serves as an isolation group, and the write channel material layer, the write gate dielectric material layer and the write word line material layer between adjacent isolation groups are etched to form the write channel layer, the write gate dielectric layer and the write word line, wherein the write word line includes a word line portion and a gate portion, the gate portion is connected to the write gate dielectric layer, the word line portion extends along the first direction, and the same word line portion is connected to multiple gate portions arranged at intervals along the first direction.

13. The method for preparing the storage structure according to claim 12, characterized in that: The first area includes a first sub-area and a second sub-area, and the second sub-area is located between the first sub-area and the shared area. The step of sequentially forming a write channel material layer and a write gate dielectric material layer on a sidewall of the first sub-cavity close to the shared area, and forming a write word line material layer to fill the first sub-cavity includes: In the second sub-region, forming the writing channel material layer on the top wall of the first sub-cavity, the bottom wall of the first sub-cavity and the sidewalls of the first sub-cavity; forming the write gate dielectric material layer on the top wall of the first sub-cavity in the first sub-region, the bottom wall of the first sub-cavity in the first sub-region, and the surface of the write channel material layer; The write word line material layer is formed on the surface of the write gate dielectric material layer.

14. The method for preparing the storage structure according to claim 10, characterized in that: When a device through hole is formed on a side of the second isolation structure close to the first isolation structure, the device through hole is spaced apart from the first region. The shared conductive line extending along the third direction by penetrating the second isolation structure includes: A shared through hole is formed in the second isolation structure, the shared through hole separates the second isolation structure, and the second isolation structure located on a side of the device through hole away from the second region in the second direction forms an electrode isolation structure.

15. The method for preparing the storage structure according to claim 10, characterized in that: The step of forming a read gate dielectric layer and a read channel layer in the device through hole and the second hollow cavity, and forming a read bit line, includes: forming a read gate dielectric material layer, a read channel material layer, and a first dielectric material layer in sequence along the inner walls of the device through hole and the second hollow cavity, wherein the first dielectric material layer fills the device through hole and the second hollow cavity; removing the read gate dielectric material layer and the read channel material layer located on the sidewall of the device through hole away from the first isolation structure, so that the remaining read gate dielectric material layer forms a read gate dielectric layer, and the remaining read channel material layer forms a read channel layer; Filling the remaining space in the device through hole with a second dielectric layer; removing a portion of the first dielectric material layer located in the second hollow cavity and away from the shared area, so that the remaining first dielectric material layer forms a first dielectric layer; The read bit line is formed in the second hollow cavity.

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