A memory and a manufacturing method thereof

Abstract

The present disclosure relates to the field of semiconductor, and provides a memory and a manufacturing method thereof. The memory comprises: a memory array comprising a plurality of vertical transistors and a plurality of memory cells; a plurality of bit lines located at a side of the vertical transistors away from the memory cells; a first interconnection structure located at a side of the bit lines away from the memory array; a second interconnection structure located at a side of the first interconnection structure away from the bit lines; a bonding interface located between the first interconnection structure and the second interconnection structure; a peripheral circuit located at a side of the second interconnection structure away from the first interconnection structure. Wherein the bit lines are correspondingly coupled with the peripheral circuit through the first interconnection structure, the bonding interface and the second interconnection structure. Wherein the first interconnection structure comprises a first interconnection layer, the first interconnection layer comprises a plurality of first pads and a plurality of first leads, the plurality of first pads are correspondingly coupled with the plurality of bit lines through the plurality of first leads and a plurality of first contact plugs, and for the plurality of first leads, the greater the extension length is, the greater the width is.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory and a method for manufacturing the same. Background Technology

[0002] With the development of the semiconductor field, the density of memory cells using planar memory is approaching its limit. Currently, three-dimensional memory architectures can solve the density limitations of planar memory cells. In a three-dimensional memory architecture, the memory cell array and peripheral circuitry are located on different wafers and bonded together face-to-face. However, in the wafer on which the memory cell array is located, bit line contact plugs have the problems of small size and layout limitations, which are not conducive to the coupling of bit lines with peripheral circuitry. Summary of the Invention

[0003] In view of the above, this disclosure provides a memory and a method for manufacturing the same to solve or improve the technical problems existing in the prior art.

[0004] This disclosure provides a memory, including: a memory array, comprising a plurality of vertical transistors arranged in an array and a plurality of memory cells coupled to each of the plurality of vertical transistors, wherein the active region of each vertical transistor extends along a first direction, and a first end of each vertical transistor is coupled to a first end of a memory cell; a plurality of bit lines located on the side of the plurality of vertical transistors away from the plurality of memory cells, extending along a second direction perpendicular to the first direction, and respectively coupled to the second ends of the plurality of vertical transistors; a first interconnect structure located on the side of the plurality of bit lines away from the memory array; a second interconnect structure located on the side of the first interconnect structure away from the plurality of bit lines; and a bonding interface located on the... Between the first interconnect structure and the second interconnect structure; peripheral circuitry, located on the side of the second interconnect structure away from the first interconnect structure, wherein the plurality of bit lines are correspondingly coupled to the peripheral circuitry through the first interconnect structure, the bonding interface, and the second interconnect structure; wherein the first interconnect structure includes a plurality of interconnect layers, the plurality of interconnect layers including a first interconnect layer close to the plurality of bit lines, the first interconnect layer including a plurality of first pads and a plurality of first leads, the plurality of first pads being correspondingly coupled to the plurality of bit lines through the plurality of first leads and a plurality of first contact plugs, the plurality of first pads having the same size, the plurality of first contact plugs having the same size, and for the plurality of first leads, the greater the extension length, the greater the width.

[0005] In some embodiments, the resistance of the plurality of first leads is substantially the same.

[0006] In some embodiments, the plurality of first contact plugs are staggered on both sides of the perpendicular bisector of the plurality of bit lines, the extension direction of the perpendicular bisector is perpendicular to the first direction and the second direction respectively, and the plurality of first contact plugs are equidistant from the perpendicular bisector; the first contact plug located on one side of the perpendicular bisector is coupled to the bit line of odd number, and the first contact plug located on the other side of the perpendicular bisector is coupled to the bit line of even number.

[0007] In some embodiments, the first pad coupled to the first contact plug located on the same side of the vertical line is also located on the same side of the vertical line and is staggered along the extension direction of the vertical line.

[0008] In some embodiments, the plurality of first contact plugs are arranged sequentially along the perpendicular bisector of the plurality of bit lines, the extension direction of the perpendicular bisector being perpendicular to the first direction and the second direction, respectively; the first pad located on one side of the perpendicular bisector is coupled to the odd-numbered first contact plugs, and the first pad located on the other side of the perpendicular bisector is coupled to the even-numbered first contact plugs.

[0009] In some embodiments, the first pads located on the same side of the vertical line are staggered along the extension direction of the vertical line.

[0010] In some embodiments, the plurality of interconnect layers further includes a second interconnect layer located away from the plurality of bit lines. The second interconnect layer includes a plurality of uniformly distributed second pads, which are correspondingly coupled to the plurality of bit lines via a plurality of second contact plugs and other interconnect layers besides the second interconnect layer.

[0011] In some embodiments, the plurality of interconnect layers further includes at least one intermediate interconnect layer located between the first interconnect layer and the second interconnect layer. The intermediate interconnect layer includes a plurality of intermediate pads and a plurality of intermediate leads. The plurality of intermediate pads are correspondingly coupled to the plurality of bit lines through the plurality of intermediate leads, a plurality of intermediate contact plugs, and other interconnect layers located between the intermediate interconnect layer and the plurality of bit lines. The area occupied by the intermediate pads is larger than the area occupied by the first pads, and the area occupied by the second pads is larger than the area occupied by the intermediate pads.

[0012] In some embodiments, the memory further includes: a plurality of word lines extending along a third direction and respectively covering a portion of the sidewall of the active region of the plurality of vertical transistors, wherein the third direction is perpendicular to the first direction and intersects with the second direction; a plurality of word line contact plugs located between the plurality of word lines and the first interconnect structure; wherein the plurality of word lines are correspondingly coupled to the peripheral circuitry through the plurality of word line contact plugs, the first interconnect structure, the bonding interface, and the second interconnect structure.

[0013] In some embodiments, the plurality of word line contact plugs are distributed at opposite ends of the plurality of word lines, with the word line contact plug at one end of the plurality of word lines coupled to the odd-numbered word lines, and the word line contact plug at the other end of the plurality of word lines coupled to the even-numbered word lines.

[0014] This disclosure also provides a method for manufacturing a memory, comprising: forming a first semiconductor structure, wherein the first semiconductor structure includes a memory array, a plurality of bit lines, and a first interconnect structure; the memory array includes a plurality of vertical transistors arranged in an array and a plurality of memory cells coupled to the plurality of vertical transistors in a one-to-one correspondence, the active region of each vertical transistor extends along a first direction, and a first end of each vertical transistor is coupled to a first end of each memory cell; the plurality of bit lines are located on the side of the plurality of vertical transistors away from the plurality of memory cells, the plurality of bit lines extend along a second direction perpendicular to the first direction, and are respectively coupled to the second ends of the plurality of vertical transistors; the first interconnect structure is located on the side of the plurality of bit lines away from the memory array; forming a second semiconductor structure, wherein the second semiconductor... The body structure includes a peripheral circuit and a second interconnect structure located on the peripheral circuit. The first semiconductor structure and the second semiconductor structure are bonded by forming a bonding interface between the first interconnect structure and the second interconnect structure, so that the multiple bit lines are correspondingly coupled to the peripheral circuit through the first interconnect structure, the bonding interface, and the second interconnect structure. The first interconnect structure includes multiple interconnect layers, the multiple interconnect layers including a first interconnect layer close to the multiple bit lines. The first interconnect layer includes multiple first pads and multiple first leads. The multiple first pads are correspondingly coupled to the multiple bit lines through the multiple first leads and multiple first contact plugs. The multiple first pads are of the same size, the multiple first contact plugs are of the same size, and for the multiple first leads, the longer the extension length, the larger the width.

[0015] In some embodiments, forming the first semiconductor structure includes: etching a substrate from a first surface to form a plurality of active regions arranged in an array and a trench structure defining the plurality of active regions, each of the active regions extending along a first direction perpendicular to the substrate; forming an isolation structure within the trench structure; etching a portion of the isolation structure from the first surface to form a plurality of word line trenches extending along a third direction, each of the word line trenches exposing a portion of each of the active regions arranged along the third direction, the third direction being perpendicular to the first direction; sequentially forming a gate dielectric layer and a word line within each of the word line trenches; and etching the first surface from the first surface to form a plurality of active regions. The first end of the active region is doped to form a first source / drain region; the plurality of memory cells are formed on the first surface, and the first end of each memory cell is coupled to a first source / drain region; the substrate is thinned from the second surface to expose the second end of each of the active regions; the second end of each of the active regions is doped from the second surface to form a second source / drain region; a plurality of bit lines extending along a second direction are formed on the second surface, and the plurality of bit lines are respectively coupled to the second source / drain regions of the plurality of active regions, the second direction being perpendicular to the first direction and intersecting the third direction; a first interconnect structure is formed on the second surface.

[0016] In some embodiments, forming a first interconnect structure on the second surface includes: forming a first interconnect layer on the second surface, the first interconnect layer being located on the plurality of bit lines; forming at least one intermediate interconnect layer on the first interconnect layer, the intermediate interconnect layer including a plurality of intermediate pads and a plurality of intermediate leads, the plurality of intermediate pads being correspondingly coupled to the plurality of bit lines through the plurality of intermediate leads, a plurality of intermediate contact plugs, and other interconnect layers located between the intermediate interconnect layer and the plurality of bit lines; wherein the area occupied by the intermediate pads is larger than the area occupied by the first pads.

[0017] In some embodiments, forming a first interconnect structure on the second surface further includes: forming a second interconnect layer on the intermediate interconnect layer, the second interconnect layer including a plurality of uniformly distributed second pads, the plurality of second pads being coupled to the plurality of bit lines through a plurality of second contact plugs and other interconnect layers other than the second interconnect layer; wherein the area occupied by the second pads is larger than the area occupied by the intermediate pads.

[0018] In some embodiments, forming the first semiconductor structure further includes: forming a plurality of word line contact plugs, the plurality of word line contact plugs being located between the plurality of word lines and the first interconnect structure; wherein the plurality of word lines are correspondingly coupled to the peripheral circuitry through the plurality of word line contact plugs, the first interconnect structure, the bonding interface, and the second interconnect structure.

[0019] Therefore, this disclosure provides a memory and a method for manufacturing the same. The memory includes: a memory array comprising a plurality of vertical transistors arranged in an array and a plurality of memory cells coupled one-to-one with each of the vertical transistors, wherein the active region of each vertical transistor extends along a first direction, and a first end of each vertical transistor is coupled to a first end of a memory cell; a plurality of bit lines located on the side of the plurality of vertical transistors away from the plurality of memory cells, extending along a second direction perpendicular to the first direction, and respectively coupled to the second ends of the plurality of vertical transistors; a first interconnect structure located on the side of the plurality of bit lines away from the memory array; a second interconnect structure located on the side of the first interconnect structure away from the plurality of bit lines; and a bonding interface, bit... Between the first interconnect structure and the second interconnect structure; peripheral circuitry, located on the side of the second interconnect structure away from the first interconnect structure, wherein multiple bit lines are correspondingly coupled to the peripheral circuitry through the first interconnect structure, the bonding interface, and the second interconnect structure; wherein the first interconnect structure includes multiple interconnect layers, the multiple interconnect layers including a first interconnect layer close to the multiple bit lines, the first interconnect layer including multiple first pads and multiple first leads, the multiple first pads being correspondingly coupled to the multiple bit lines through the multiple first leads and multiple first contact plugs, the multiple first pads having the same size, the multiple first contact plugs having the same size, and for the multiple first leads, the greater the extension length, the greater the width. On the one hand, this disclosure solves or improves the problem of small first contact plug size hindering bit line coupling by setting a first interconnect structure, in which multiple first pads and multiple first leads are set in the first interconnect layer of the first interconnect structure and coupled to multiple bit lines through multiple first contact plugs. Simultaneously, the greater the extension length of the multiple first leads, the greater their width, which can compensate for the difference in resistance value of the transmission path caused by the distance difference when multiple first pads are coupled to multiple bit lines. On the other hand, this disclosure also sets a second interconnect structure and forms a bonding interface between the first interconnect structure and the second interconnect structure, allowing multiple bit lines to be coupled to peripheral circuits through the first interconnect structure, the bonding interface, and the second interconnect structure. This further improves the stability of bit line coupling to peripheral circuits, enhancing memory performance and yield.

[0020] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1A schematic diagram of a wafer bonding method provided for related technologies;

[0023] Figure 2 A three-dimensional schematic diagram of a memory provided for related technologies;

[0024] Figure 3 A three-dimensional schematic diagram of a memory provided in an embodiment of this disclosure;

[0025] Figure 4 A top view schematic diagram of a memory provided in an embodiment of this disclosure;

[0026] Figure 5 This is a schematic vertical cross-sectional view of a memory provided in an embodiment of the present disclosure, wherein (a) is a view along... Figure 4 (a) is a schematic diagram of the vertical cross-section of line a-a' in Figure (b). Figure 4 A schematic diagram of the vertical cross-section of line c-c' in the diagram;

[0027] Figure 6 A schematic diagram of a first interconnection structure provided in an embodiment of this disclosure;

[0028] Figure 7 A schematic diagram of a first interconnect layer provided in an embodiment of this disclosure;

[0029] Figure 8 A schematic diagram of the layout of a first contact plug provided for related technologies;

[0030] Figure 9 A schematic diagram of the layout of a first contact plug provided in an embodiment of this disclosure;

[0031] Figure 10 This is a schematic diagram of the layout of a first pad and a first lead provided in an embodiment of the present disclosure;

[0032] Figure 11 A schematic diagram of the layout of yet another first contact plug provided in an embodiment of this disclosure;

[0033] Figure 12 A schematic diagram of the layout of another first pad and first lead provided in an embodiment of this disclosure;

[0034] Figure 13 A schematic diagram of a second interconnect layer provided in an embodiment of this disclosure;

[0035] Figure 14 A schematic diagram illustrating the coupling between a first contact plug and a second interconnect layer, provided in an embodiment of this disclosure;

[0036] Figure 15 A schematic diagram of the layout of a contact plug provided in an embodiment of this disclosure;

[0037] Figure 16 A schematic flowchart illustrating a method for manufacturing a memory according to an embodiment of this disclosure;

[0038] Figures 17 to 28 This is a schematic diagram of the structure of the memory during the manufacturing process provided in an embodiment of the present disclosure, wherein, Figures 17 to 20 For along Figure 4 A schematic diagram of the vertical cross-section of line a-a' in the diagram. Figures 21 to 23 , Figure 25 This is a three-dimensional schematic diagram of the memory manufacturing process. Figure 24 , Figures 26 to 28 For along Figure 4 A schematic diagram of the vertical cross-section of line c-c' in the diagram. Detailed Implementation

[0039] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0040] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0041] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items. All numerical ranges herein include endpoint values.

[0045] In related technologies, heterogeneous integration technology on chip (HITOC) allows memory cell arrays with vertical transistors and peripheral circuits to be formed on a first wafer and a second wafer, respectively, and bonded face-to-face to form a three-dimensional memory (such as...). Figure 1 As shown). Due to face-to-face bonding, bit line contact plugs and word line contact plugs in the first wafer can only be placed at the edges of the bit lines and word lines (e.g., Figure 2 (As shown). Therefore, the layout of multiple contact plugs in the first wafer has certain limitations, which is not conducive to the bonding of the first wafer and the second wafer.

[0046] Furthermore, during the fabrication of the first wafer, bit line trenches can be formed on the substrate first, and metal material can be deposited within the trenches to form bit lines; then, vertical transistors are formed on the bit lines. In this fabrication process, the large depth of the bit line trenches within the substrate makes metal material filling difficult, resulting in a complex bit line fabrication process. Moreover, the doping end of the subsequently formed vertical transistor near the bit line presents a doping challenge. Alternatively, vertical transistors can be formed on the substrate first, and then the bottom of the vertical transistor can be doped using an ion implantation process to form bit lines. The disadvantage of this process is that the bit line doping region is a heavily doped region, which can easily lead to high leakage current through the substrate.

[0047] Based on this, the present disclosure proposes the following technical solutions:

[0048] This disclosure provides a memory, Figure 3 A three-dimensional schematic diagram of a memory provided in an embodiment of this disclosure; Figure 4 A top view schematic diagram of a memory provided in an embodiment of this disclosure; Figure 5 This is a schematic vertical cross-sectional view of a memory provided in an embodiment of the present disclosure, wherein (a) is a view along... Figure 4 (a) is a schematic diagram of the vertical cross-section of line a-a' in Figure (b). Figure 4 A schematic diagram of the vertical cross-section of line c-c' in the diagram; Figure 6 A schematic diagram of a first interconnection structure provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of a first interconnect layer provided in an embodiment of the present disclosure.

[0049] See Figures 3 to 5The memory includes: a memory array 11, including a plurality of vertical transistors 12 arranged in an array and a plurality of memory cells 13 coupled one-to-one with the plurality of vertical transistors 12, wherein the active region 120 of each vertical transistor 12 extends along a first direction x, and the first end A1 of each vertical transistor 12 is coupled to the first end B1 of a memory cell 13.

[0050] Multiple bit lines 14 are located on the side of multiple vertical transistors 12 away from multiple memory cells 13, extend along a second direction y perpendicular to the first direction x, and are respectively coupled to the second end A2 of the multiple vertical transistors 12.

[0051] The first interconnect structure 21 is located on the side of the multiple bit lines 14 away from the memory array 11;

[0052] The second interconnect structure 41 is located on the side of the first interconnect structure 21 that is away from the multiple bit lines 14;

[0053] The bonding interface 40 is located between the first interconnect structure 21 and the second interconnect structure 41;

[0054] The peripheral circuit 42 is located on the side of the second interconnect structure 41 away from the first interconnect structure 21, wherein multiple bit lines 14 are correspondingly coupled to the peripheral circuit 42 through the first interconnect structure 21, the bonding interface 40 and the second interconnect structure 41.

[0055] The first interconnect structure 21 includes multiple interconnect layers 210, and the multiple interconnect layers 210 include a first interconnect layer 211 close to multiple bit lines 14 (such as...). Figure 6 and Figure 7 As shown), the first interconnect layer 211 includes a plurality of first pads 2112 and a plurality of first leads 2111 (as shown). Figure 10 As shown, multiple first pads 2112 are coupled to multiple bit lines 14 via multiple first leads 2111 and multiple first contact plugs 31. The multiple first pads 2112 are of the same size, and the multiple first contact plugs 31 are of the same size.

[0056] For multiple first leads 2111, the greater the extension length, the greater the width.

[0057] It should be noted that, in order to clearly illustrate the content of this embodiment, Figure 3 Only a portion of the memory components are shown in the image. Figure 4 and Figure 5 The second direction y and the third direction z shown are both perpendicular to the first direction x. The second direction y and the third direction z can be perpendicular to each other or form any angle. The following explanation uses the second direction y being perpendicular to the third direction z as an example, and will not be repeated below.

[0058] In this embodiment of the disclosure, see Figure 4 The size of storage array 11 meets the 4F requirement. 2 (F: Minimum pattern size achievable under given process conditions). That is, the distance between the center points of two adjacent vertical transistors 12 in the second direction y is 2F, and the distance between the center points of two adjacent vertical transistors 12 in the third direction z is also 2F. Thus, by using vertical transistors instead of planar transistors, the integration density of the memory is improved.

[0059] In this embodiment of the disclosure, see Figure 5 Figure (b) shows that the storage array 11 includes a dynamic random access memory (DRAM) cell array.

[0060] It should be noted that the memory array 11 is not limited to a DRAM cell array, but may also include other suitable memory arrays that can use transistors as switching and selection devices. For example, static random access memory (SRAM) cell arrays, resistive memory cell arrays, and magnetic memory cell arrays.

[0061] In this embodiment of the disclosure, see Figure 5 In Figure (b), storage cell 13 is a capacitor used to store charge as binary information stored by the corresponding DRAM cell. Specifically, storage cell 13 is a vertical capacitor.

[0062] In this embodiment of the disclosure, see Figure 5 In Figure (a), the first terminal A1 and the second terminal A2 of the vertical transistor 12 are opposite to each other along the first direction x. Furthermore, a first source-drain region and a second source-drain region are formed at the first terminal A1 and the second terminal A2 of the vertical transistor 12, respectively. The first source-drain region and the second source-drain region can be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)).

[0063] In this embodiment of the disclosure, see Figure 5 In Figure (a), both the first interconnect structure 21 and the second interconnect structure 41 may include multiple interconnect layers, which can be connected to each other via multiple contact plugs. Here, the materials of the interconnect layers include, but are not limited to, tungsten, cobalt, copper, aluminum, titanium nitride, tungsten nitride, or any combination thereof.

[0064] In this embodiment of the disclosure, see Figure 5 In Figure (b), the bonding interface 40 (Hybrid Bonding Interface) can be a bonding layer of a certain thickness formed by the hybrid bonding of the first interconnect structure 21 and the second interconnect structure 41.

[0065] It is understandable that by setting up the first interconnect structure 21 and the second interconnect structure 41, and forming a bonding interface 40 between the first interconnect structure 21 and the second interconnect structure 41, multiple bit lines 14 can be coupled to the peripheral circuit 42 through the first interconnect structure 21, the bonding interface 40, and the second interconnect structure 41. This improves the stability of the coupling between the bit lines 14 and the peripheral circuit 42, thereby increasing the performance and yield of the memory.

[0066] In this embodiment of the disclosure, see Figure 5 As shown in Figure (a), the peripheral circuitry 42 may include one or more of the following: a page buffer, a decoder, a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any part of the aforementioned functional circuitry (e.g., a sub-circuit), or any active or passive component of the circuitry (e.g., a transistor, diode, resistor, or capacitor).

[0067] Figure 8 A schematic diagram of the layout of a first contact plug provided for related technologies; Figure 9 A schematic diagram of the layout of a first contact plug provided in an embodiment of this disclosure; Figure 10 This is a schematic diagram of the layout of a first pad and a first lead provided in an embodiment of the present disclosure; Figure 11 A schematic diagram of the layout of yet another first contact plug provided in an embodiment of this disclosure; Figure 12 This is a schematic diagram of the layout of another first pad and first lead provided in an embodiment of the present disclosure.

[0068] See Figure 8 As can be seen, the first contact plug 31 is located at the edge of the bit line 14. In this case, there is a problem of large transmission resistance between the first contact plug 31 and the memory cell on the bit line 14 that is far away from the first contact plug 31, which leads to a reduction in the sensing margin of the memory.

[0069] In the embodiments disclosed herein, see Figure 9 and Figure 11 The first contact plug 31 can be disposed in the middle region of the bit line 14 (i.e., the region between the two ends of the bit line). This is because the first contact plug 31 is located on the side of the bit line 14 away from the vertical transistor 12, that is, between the bit line 14 and the first interconnect structure 21. Therefore, the layout of the first contact plug 31 is not limited by devices such as vertical transistors and word lines. In this way, the problem of the limitation of the layout of the first contact plug 31 is improved. At the same time, the transmission resistance between the first contact plug 31 and the memory cells at both ends of the bit line 14 can be reduced, thereby improving the sensing margin of the memory.

[0070] In this embodiment of the disclosure, see Figure 10 and Figure 12 The size of the first pad 2112 is much larger than the size of the first contact plug 31. In this way, multiple first pads and multiple first leads are coupled to multiple bit lines through multiple first contact plugs, which can improve the problem of the small size of the first contact plug 31 and facilitate the coupling of bit line 14 with the peripheral circuit 42.

[0071] In some embodiments of this disclosure, see Figure 10 and Figure 12 The resistances of the multiple first leads 2111 are basically the same.

[0072] It should be noted that the statement that the resistance of multiple first leads 2111 is basically the same can be understood as meaning that the resistance of multiple first leads 2111 can be equal, but a certain degree of difference is allowed within a certain error range. Specifically, this resistance error range can include minor design errors that do not affect the electrical performance of the memory, provided that multiple first pads 2112 are coupled to multiple bit lines 14 through multiple first leads 2111 and multiple first contact plugs 31. This resistance error range can also include differences caused by manufacturing errors. This resistance error range includes, but is not limited to, the above two situations.

[0073] It is understandable that the resistance of the first lead 2111 is R = ρL / S. Here, ρ is the resistivity of the first lead material, L is the length of the first lead, and S is the cross-sectional area of ​​the first lead. According to the resistance calculation formula, the resistance increases with the length of the first lead. Therefore, the greater the extension length of the multiple first leads 2111, the greater their width. This can compensate for the resistance difference in the transmission path caused by distance differences, improving the stability of the coupling between bit line 14 and peripheral circuit 42.

[0074] In order to facilitate the fabrication of multiple first pads 2112 and multiple first leads 2111, and at the same time ensure that the resistance values ​​of bit lines 14 and peripheral circuits 42 are consistent when they are coupled, the layout of multiple first pads 2112 and multiple first leads 2111 and their coupling with multiple first contact plugs 31 can be designed in a standardized manner.

[0075] In some embodiments of this disclosure, see Figure 9 and Figure 10 Multiple first contact plugs 31 are staggered on both sides of the perpendicular 140 of multiple bit lines 14. The extension direction of the perpendicular 140 is perpendicular to the first direction x and the second direction y, respectively. The distances of the multiple first contact plugs 31 to the perpendicular 140 are equal. The first contact plugs 31 located on one side of the perpendicular 140 are coupled to the bit lines 14 of odd number, and the first contact plugs 31 located on the other side of the perpendicular 140 are coupled to the bit lines 14 of even number.

[0076] Here, the perpendicular bisector 140 refers to the straight line that divides the multiple position lines 14 extending along the second direction y into two ends.

[0077] It is understandable that setting multiple first contact plugs 31 staggered on both sides of the vertical line 140 of multiple bit lines 14 is beneficial to increasing the setting space of the first contact plugs 31, thereby increasing the size of the first contact plugs 31, increasing the contact area between the first contact plugs 31 and the bit lines 14, and thus reducing the contact resistance between the first contact plugs 31 and the bit lines 14.

[0078] Furthermore, when multiple first contact plugs 31 are staggered on both sides of the vertical line 140 of multiple bit lines 14, the first pads 2112 coupled to the first contact plugs 31 located on the same side of the vertical line 140 are also located on the same side of the vertical line 140, and are staggered along the extension direction of the vertical line 140. Here, the staggered arrangement of the first pads 2112 can increase the placement space of the first pads 2112, thereby increasing the size of the first pads 2112 and further improving the problem of the small size of the first contact plugs 31.

[0079] In other embodiments of this disclosure, see Figure 11 and Figure 12 Multiple first contact plugs 31 are arranged sequentially along the perpendicular 140 of multiple position lines 14, and the extension direction of the perpendicular 140 is perpendicular to the first direction x and the second direction y, respectively.

[0080] The first pad 2112 located on one side of the vertical line 140 is coupled to the odd-numbered first contact plugs 31, and the first pad 2112 located on the other side of the vertical line 140 is coupled to the even-numbered first contact plugs 31. Furthermore, the first pads 2112 on the same side of the vertical line 140 are staggered along the extension direction of the vertical line 140. Here, the first contact plugs 31 are arranged sequentially along the vertical line 140, simplifying the fabrication process of the multiple first contact plugs 31; simultaneously, the staggered arrangement of the first pads 2112 ensures that the multiple first pads have ample space, which is beneficial for reducing the contact resistance between the bit line 14 and the peripheral circuit 42 when connecting to other interconnect layers later.

[0081] Figure 13 This is a schematic diagram of the layout of a second interconnect layer provided in an embodiment of the present disclosure; Figure 14 This is a schematic diagram showing the coupling of a first contact plug and a second interconnect layer according to an embodiment of the present disclosure.

[0082] In some embodiments of this disclosure, see Figure 13 and Figure 14The multiple interconnect layers 210 also include a second interconnect layer 212 located away from the multiple bit lines 14. The second interconnect layer 212 includes a plurality of uniformly distributed second pads 2121, which are connected by a plurality of second contact plugs 32 (e.g., Figure 6 As shown, the first interconnect structure 21 and the other interconnect layers besides the second interconnect layer 212 are coupled to the multiple bit lines 14. Here, the multiple second pads 2121 are evenly distributed on the second interconnect layer 212, which is beneficial to the bonding of the first interconnect structure 21 and the second interconnect structure 41, thereby improving the stability of the coupling between the multiple bit lines 14 and the peripheral circuit 42.

[0083] In this embodiment of the disclosure, see Figure 14 Multiple second pads 2121 are evenly distributed on both sides of the vertical line, and multiple first contact plugs 31 located on one side of the vertical line are correspondingly coupled to multiple second pads 2121 on the same side.

[0084] In this embodiment of the disclosure, the second pad 2121 can also be coupled to the word line, memory cell 13 and other structures through a plurality of second contact plugs 32 and other interconnect layers other than the second interconnect layer 212.

[0085] In some embodiments of this disclosure, see Figure 6 The multiple interconnect layers 210 also include at least one intermediate interconnect layer 213 located between the first interconnect layer 211 and the second interconnect layer 212, the intermediate interconnect layer 213 including multiple intermediate pads and multiple intermediate leads. Figure 6 (Not shown), multiple intermediate pads are coupled to multiple bit lines 14 via multiple intermediate leads, multiple intermediate contact plugs 33, and other interconnect layers located between the intermediate interconnect layer 213 and the multiple bit lines 14.

[0086] The area occupied by the middle pad is larger than that occupied by the first pad 2112, and the area occupied by the second pad 2121 is larger than that occupied by the middle pad.

[0087] Understandably, the area occupied by the intermediate pad is set to be larger than that of the first pad 2112, and the area occupied by the second pad 2121 is larger than that of the intermediate pad. This can further reduce the contact resistance of the bit line 14 coupled to the peripheral circuit 42.

[0088] In some embodiments of this disclosure, see Figure 5 In diagram (b), the memory also includes:

[0089] Multiple word lines 15 extend along the third direction z, respectively covering part of the sidewalls of the active region 120 of multiple vertical transistors 12;

[0090] Multiple word line contact plugs 34 are located between multiple word lines 15 and the first interconnection structure 21;

[0091] Among them, multiple word lines 15 are coupled to the peripheral circuit 42 through multiple word line contact plugs 34, the first interconnection structure 21, the bonding interface 40 and the second interconnection structure 41.

[0092] Figure 15 This is a schematic diagram of the layout of a contact plug provided in an embodiment of this disclosure.

[0093] In some embodiments of this disclosure, see Figure 15 Multiple word line contact plugs 34 are distributed at opposite ends of multiple word lines 15. The word line contact plugs 34 located at one end of the multiple word lines 15 are coupled to the odd-numbered word lines 15, and the word line contact plugs 34 located at the other end of the multiple word lines 15 are coupled to the even-numbered word lines 15. In this way, the arrangement space of the word line contact plugs 34 can be further increased, and the contact resistance between the word line contact plugs 34 and the word lines 15 can be reduced.

[0094] In this embodiment of the disclosure, see Figure 15 The spacing between the multiple first contact plugs 31 is D1 = 1 * BL pitch (i.e., one bit line pitch), and the spacing between the multiple word line contact plugs 34 is D2 = 2 * WL pitch (i.e., twice the word line pitch).

[0095] In this embodiment of the disclosure, see Figure 15 The memory also includes capacitive contact plugs 30 for correspondingly coupling multiple memory cells 13 to peripheral circuits 42 through a first interconnect structure 21, a bonding interface 40, and a second interconnect structure 41.

[0096] This disclosure also provides a method for manufacturing a memory. Figure 16 This is a schematic flowchart of a method for manufacturing a memory according to an embodiment of the present disclosure, as shown below. Figure 16 As shown, the method includes the following steps:

[0097] Step S101: Form a first semiconductor structure, wherein the first semiconductor structure includes a memory array 11, multiple bit lines 14, and a first interconnect structure 21; the memory array 11 includes multiple vertical transistors 12 arranged in an array and multiple memory cells 13 coupled one-to-one with the multiple vertical transistors 12, the active region 120 of each vertical transistor 12 extends along a first direction x, and the first end A1 of each vertical transistor 12 is coupled to the first end B1 of each memory cell 13; the multiple bit lines 14 are located on the side of the multiple vertical transistors 12 away from the multiple memory cells 13, the multiple bit lines 14 extend along a second direction y perpendicular to the first direction x, and are respectively coupled to the second end A2 of the multiple vertical transistors 12; the first interconnect structure 21 is located on the side of the multiple bit lines 14 away from the memory array 11;

[0098] Step S102: Form a second semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit 42 and a second interconnect structure 41 located on the peripheral circuit 42;

[0099] Step S103: The first semiconductor structure and the second semiconductor structure are bonded by forming a bonding interface 40 between the first interconnect structure 21 and the second interconnect structure 41, so that multiple bit lines 14 are correspondingly coupled to the peripheral circuit 42 through the first interconnect structure 21, the bonding interface 40 and the second interconnect structure 41; wherein, the first interconnect structure 21 includes multiple interconnect layers 210, the multiple interconnect layers 210 include a first interconnect layer 211 close to the multiple bit lines 14, the first interconnect layer 211 includes multiple first pads 2112 and multiple first leads 2111, the multiple first pads 2112 are correspondingly coupled to the multiple bit lines 14 through the multiple first leads 2111 and multiple first contact plugs 31, the multiple first pads 2112 are the same size, the multiple first contact plugs 31 are the same size, and for the multiple first leads 2111, the longer the extension length, the wider the width.

[0100] Figures 17 to 28 This is a schematic diagram of the structure of the memory during the manufacturing process according to an embodiment of the present disclosure, wherein, Figures 17 to 20 For along Figure 4 A schematic diagram of the vertical cross-section of line a-a' in the diagram. Figures 21 to 23 , Figure 25 This is a three-dimensional schematic diagram of the memory manufacturing process. Figure 24 , Figures 26 to 28 For along Figure 4 A schematic diagram of the vertical cross-section of line c-c' in the diagram. The following is combined with... Figures 17 to 28 The method for manufacturing a memory provided in the embodiments of this disclosure will be further described.

[0101] It should be noted that, in order to clearly illustrate the content of this embodiment, Figures 21 to 23 , Figure 25 Only some components, such as vertical transistor 12, word line 15, and bit line 14, are shown in the diagram.

[0102] First, step S101 is performed: forming a first semiconductor structure.

[0103] In some embodiments of this disclosure, see Figures 17 to 28 Forming a first semiconductor structure, comprising:

[0104] The substrate 50 is etched from the first surface 501 to form a plurality of active regions 120 arranged in an array and a trench structure T1 defining the plurality of active regions 120. Each active region 120 extends along a first direction x perpendicular to the substrate 50 (e.g., ...). Figure 17 (as shown);

[0105] An isolation structure 51 is formed within the trench structure T1 (e.g., Figure 18 (as shown);

[0106] The isolation structure 51 is partially etched from the first surface 501 to form a plurality of word line trenches extending along the third direction z, each word line trench exposing a portion of each active region 120 arranged along the third direction z, the third direction z being perpendicular to the first direction x;

[0107] Within each word line trench, a gate dielectric layer 52 and a word line 15 are sequentially formed (e.g., Figure 19 (as shown);

[0108] Doping is performed on the first end C1 of each active region 120 from the first surface 501 to form the first source / drain region;

[0109] Multiple memory cells 13 are formed on the first surface 501, and the first end B1 of each memory cell 13 is coupled to a first source-drain region (e.g., Figure 20 (as shown);

[0110] Thinning of substrate 50 from the second surface 502 (e.g.) Figure 22 As shown), to expose the second end C2 of each active region 120; doping is performed on the second end C2 of each active region 120 from the second surface 502 to form a second source / drain region (as shown). Figure 23 , 24 (as shown);

[0111] Multiple bit lines 14 extending along the second direction y are formed on the second surface 502. These bit lines 14 are respectively coupled to the second source / drain regions of multiple active regions 120. The second direction y is perpendicular to the first direction x and intersects with the third direction z (e.g., ...). Figure 25 (as shown);

[0112] A first interconnect structure 21 is formed on the second surface 502.

[0113] In this embodiment of the disclosure, see Figure 20 The first surface 501 and the second surface 502 are two surfaces of the substrate 50 that are opposite each other along the first direction x. The first end C1 and the second end C2 of the active region 120 are two ends that are opposite each other along the first direction x.

[0114] In this embodiment of the disclosure, see Figure 20 The substrate 50 may include at least one of the semiconductor materials, such as group IV elements such as silicon (Si), germanium (Ge), and silicon-germanium (SiGe), or group III-V compounds such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), indium arsenide (InAs), and indium gallium arsenide (InGaAs). The following description exemplifies the inclusion of silicon in the substrate 50.

[0115] In this embodiment of the disclosure, see Figure 20 The isolation structure 51 may include materials such as silicon oxide and silicon nitride; the material of the gate dielectric layer 52 includes, but is not limited to, silicon oxide, silicon nitride, or high-k dielectric materials; the material of the word line 15 includes, but is not limited to, tungsten, cobalt, copper, titanium nitride, polysilicon, silicides, or any combination thereof.

[0116] In this embodiment of the disclosure, the first end C1 and the second end C2 of the active region 120 can be doped using ion implantation and / or thermal diffusion processes to form a first source / drain region and a second source / drain region. The first source / drain region and the second source / drain region can be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)).

[0117] In this embodiment of the disclosure, see Figures 26 to 28 The specific steps for forming multiple bit lines 14 after doping the second end C2 of each active region 120 from the second surface 502 include: depositing and etching bit line connection material 53 and bit line conductive material 54 on the second surface 502, and the remaining bit line connection material 53 and bit line conductive material 54 located on the second end C2 are respectively formed as bit line connection layer 141 and bit line conductive layer 142 in bit line 14.

[0118] In this embodiment of the disclosure, the material of the bit line interconnect layer 141 may include polysilicon, and the material of the bit line conductive layer 142 may include titanium nitride.

[0119] In this embodiment of the disclosure, after forming multiple bit lines 14, the method further includes: forming multiple first contact plugs 31 on the multiple bit lines 14 (e.g., Figure 5 (As shown in Figure (a)). Since the first contact plug 31 is located on the side of bit line 14 away from memory array 11, that is, the first contact plug 31 is the backside contact plug of bit line 14. Here, backside refers to the side of bit line 14 away from memory array 11.

[0120] In this embodiment of the disclosure, see Figure 9 The first contact plug 31 can be located in the middle section of the bit line 14 (i.e., the area between the two ends of the bit line). The layout of the first contact plug 31 is not limited by devices such as vertical transistors and word lines. In this way, the problem of the limitation of the layout of the first contact plug 31 is improved. At the same time, the transmission resistance between the first contact plug 31 and the memory cells at both ends of the bit line 14 can be reduced, thereby improving the sensing margin of the memory.

[0121] In this embodiment of the disclosure, see Figure 10 and Figure 12The size of the first pad 2112 is much larger than the size of the first contact plug 31. This improves the problem of the small size of the first contact plug 31 and facilitates the coupling of the bit line 14 with the peripheral circuit 42.

[0122] It is understandable that the bit line 14 can be fabricated from the second surface 502 of the substrate 50 by thinning the second surface 502 of the substrate 50. In this way, the fabrication of the bit line 14 can be performed at the end of the entire process, thus simplifying the bit line fabrication process.

[0123] In some embodiments of this disclosure, forming the first semiconductor structure further includes:

[0124] Forming multiple word line contact plugs 34 (e.g.) Figure 5 As shown in Figure (b), multiple word line contact plugs 34 are located between multiple word lines 15 and the first interconnect structure 21; wherein, the multiple word lines 15 are correspondingly coupled to the peripheral circuit 42 through the multiple word line contact plugs 34, the first interconnect structure 21, the bonding interface 40 and the second interconnect structure 41.

[0125] In this embodiment, the word line contact plug 34 is also the back contact plug of the word line 15. Here, "back" refers to the side of the word line 15 away from the storage cell 13.

[0126] In this embodiment of the disclosure, see Figure 15 Multiple word line contact plugs 34 are distributed at opposite ends of multiple word lines 15. The word line contact plug 34 located at one end of the multiple word lines 15 is coupled to the odd-numbered word lines 15, and the word line contact plug 34 located at the other end of the multiple word lines 15 is coupled to the even-numbered word lines 15.

[0127] In some embodiments of this disclosure, a first interconnect structure 21 is formed on the second surface 502, including:

[0128] A first interconnect layer 211 is formed on the second surface 502 (e.g.) Figure 6 As shown), the first interconnect layer 211 is located on multiple bit lines 14;

[0129] At least one intermediate interconnect layer 213 is formed on the first interconnect layer 211 (e.g. Figure 6 As shown), the intermediate interconnect layer 213 includes multiple intermediate pads and multiple intermediate leads. Figure 6 (Not shown), multiple intermediate pads are coupled to multiple bit lines 14 via multiple intermediate leads, multiple intermediate contact plugs 33, and other interconnect layers located between the intermediate interconnect layer 213 and the multiple bit lines 14; wherein, the area occupied by the intermediate pads is greater than the area occupied by the first pad 2112.

[0130] In this embodiment of the disclosure, the specific method for forming the first interconnect layer 211 includes: forming a dielectric layer on the first contact plug 31; and forming a plurality of first pads 2112 and a plurality of first leads 2111 in the dielectric layer. Here, the material of the dielectric layer includes, but is not limited to, one or more of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide; the materials of the first pads 2112 and the first leads 2111 include conductive materials, such as copper, aluminum, tungsten, or tin.

[0131] In this embodiment of the disclosure, the first interconnect layer 211 can be formed by depositing conductive materials through one or more thin film deposition processes (including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof). The fabrication process for forming the interconnect layer may also include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process.

[0132] It should be noted that the same materials and processes used to form other interconnect layers as those used to form the first interconnect layer 211 can be employed, and will not be elaborated upon further below.

[0133] In this embodiment of the disclosure, the resistance of the multiple first leads 2111 is basically the same.

[0134] In one embodiment of this disclosure, see [link to embodiment]. Figure 9 and Figure 10 Multiple first contact plugs 31 are staggered on both sides of the perpendicular 140 of multiple bit lines 14. The extension direction of the perpendicular 140 is perpendicular to the first direction x and the second direction y, respectively. The distances of the multiple first contact plugs 31 to the perpendicular 140 are equal. The first contact plugs 31 located on one side of the perpendicular 140 are coupled to the bit lines 14 of odd number, and the first contact plugs 31 located on the other side of the perpendicular 140 are coupled to the bit lines 14 of even number.

[0135] It is understandable that setting multiple first contact plugs 31 staggered on both sides of the vertical line 140 of multiple bit lines 14 is beneficial to increasing the setting space of the first contact plugs 31, thereby increasing the size of the first contact plugs 31, increasing the contact area between the first contact plugs 31 and the bit lines 14, and thus reducing the contact resistance between the first contact plugs 31 and the bit lines 14.

[0136] In this embodiment, when multiple first contact plugs 31 are staggered on both sides of the vertical line 140 of multiple bit lines 14, the first pads 2112 coupled to the first contact plugs 31 located on the same side of the vertical line 140 are also located on the same side of the vertical line 140 and are staggered along the extension direction of the vertical line 140. Here, the staggered arrangement of the first pads 2112 can increase the placement space of the first pads 2112, thereby increasing the size of the first pads 2112 and further improving the problem of the small size of the first contact plugs 31.

[0137] In another embodiment of this disclosure, see Figure 11 and Figure 12 Multiple first contact plugs 31 are arranged sequentially along the perpendicular 140 of multiple position lines 14, and the extension direction of the perpendicular 140 is perpendicular to the first direction x and the second direction y, respectively.

[0138] The first pad 2112 located on one side of the perpendicular 140 is coupled to the odd-numbered first contact plug 31, and the first pad 2112 located on the other side of the perpendicular 140 is coupled to the even-numbered first contact plug 31. Furthermore, the first pads 2112 located on the same side of the perpendicular 140 are staggered along the extension direction of the perpendicular 140.

[0139] In some embodiments of this disclosure, a first interconnect structure 21 is formed on the second surface 502, and the method further includes:

[0140] A second interconnect layer 212 is formed on the intermediate interconnect layer 213 (e.g., ...). Figure 13 As shown, the second interconnect layer 212 includes a plurality of uniformly distributed second pads 2121, and the plurality of second pads 2121 are coupled to a plurality of bit lines 14 through a plurality of second contact plugs 32 and other interconnect layers other than the second interconnect layer 212; wherein, the area occupied by the second pads 2121 is larger than the area occupied by the middle pads.

[0141] Here, multiple second pads 2121 are evenly distributed on the second interconnect layer 212, which is beneficial to the bonding of the first interconnect structure 21 and the second interconnect structure 41, thereby improving the stability of the coupling between multiple bit lines 14 and the peripheral circuit 42.

[0142] Then, step S102 is performed: forming a second semiconductor structure, wherein the second semiconductor structure includes a peripheral circuit 42 and a second interconnect structure 41 located on the peripheral circuit 42 (e.g., Figure 5 (as shown in Figure (a)).

[0143] In this embodiment of the disclosure, forming the second interconnect structure 41 includes forming multiple interconnect layers. The method for forming the second interconnect structure 41 is similar to the method for forming the first interconnect structure 21, and will not be described again here.

[0144] Finally, step S103 is executed: the first semiconductor structure and the second semiconductor structure are bonded by forming a bonding interface 40 between the first interconnect structure 21 and the second interconnect structure 41, so that multiple bit lines 14 are correspondingly coupled to the peripheral circuit 42 through the first interconnect structure 21, the bonding interface 40 and the second interconnect structure 41 (e.g., Figure 5 (as shown in Figure (b)).

[0145] In this embodiment of the disclosure, a hybrid bonding technique can be used to form the bonding interface 40. Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)) and can simultaneously achieve metal-to-metal (e.g., copper-to-copper) bonding and dielectric-to-dielectric (e.g., silicon oxide-to-silicon oxide) bonding.

[0146] In this embodiment of the disclosure, see Figure 5 In Figures (a) and (b), the first contact plug 31 and the word line contact plug 34 are both back contact plugs of the bit line 14 and the word line 15. Therefore, the first semiconductor structure and the second semiconductor structure can be mixed-bonded in a back-to-face manner.

[0147] It is understandable that after the bonding interface 40 is formed between the first interconnect structure 21 and the second interconnect structure 41, multiple bit lines 14 can be coupled to the peripheral circuit 42 through the first interconnect structure 21, the bonding interface 40, and the second interconnect structure 41. This improves the stability of the coupling between the bit lines 14 and the peripheral circuit 42, thereby increasing the performance and yield of the memory.

[0148] It should be noted that the memory provided in the embodiments of this disclosure can be applied to DRAM structures or other semiconductor devices, and is not limited thereto. The technical features described in the various embodiments of the memory provided in this disclosure can be arbitrarily combined without conflict.

[0149] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory, characterized in that, include: A memory array includes a plurality of vertical transistors arranged in an array and a plurality of memory cells coupled one-to-one with the plurality of vertical transistors, wherein the active region of each vertical transistor extends along a first direction and the first end of each vertical transistor is coupled to the first end of a memory cell. Multiple bit lines are located on the side of the multiple vertical transistors away from the multiple memory cells, extend along a second direction perpendicular to the first direction, and are respectively coupled to the second end of the multiple vertical transistors; a first interconnect structure is located on the side of the multiple bit lines away from the memory array; The second interconnect structure is located on the side of the first interconnect structure that is away from the plurality of bit lines; A bonding interface is located between the first interconnect structure and the second interconnect structure; The peripheral circuit is located on the side of the second interconnect structure away from the first interconnect structure, wherein the plurality of bit lines are correspondingly coupled to the peripheral circuit through the first interconnect structure, the bonding interface and the second interconnect structure; The first interconnect structure includes multiple interconnect layers, each including a first interconnect layer adjacent to the multiple bit lines. Each first interconnect layer includes multiple first pads and multiple first leads. The multiple first pads are coupled to the multiple bit lines via the multiple first leads and multiple first contact plugs. The multiple first pads and the multiple first contact plugs are of the same size. For the multiple first leads, the greater the extension length, the greater the width.

2. The memory according to claim 1, characterized in that, The resistance of the multiple first leads is the same.

3. The memory according to claim 1 or 2, characterized in that, The plurality of first contact plugs are arranged alternately on both sides of the perpendicular line of the plurality of position lines, the extension direction of the perpendicular line is perpendicular to the first direction and the second direction respectively, and the plurality of first contact plugs are equidistant from the perpendicular line; The first contact plug located on one side of the vertical line is coupled to the bit line of odd number, and the first contact plug located on the other side of the vertical line is coupled to the bit line of even number.

4. The memory according to claim 3, characterized in that, The first pad coupled to the first contact plug located on the same side of the vertical line is also located on the same side of the vertical line and is staggered along the extension direction of the vertical line.

5. The memory according to claim 1 or 2, characterized in that, The plurality of first contact plugs are arranged sequentially along the perpendicular bisector of the plurality of position lines, and the extension direction of the perpendicular bisector is perpendicular to the first direction and the second direction, respectively; The first pad located on one side of the vertical line is coupled to the first contact plug of odd number, and the first pad located on the other side of the vertical line is coupled to the first contact plug of even number.

6. The memory according to claim 5, characterized in that, The first pads located on the same side of the vertical line are staggered along the extension direction of the vertical line.

7. The memory according to claim 1 or 2, characterized in that, The plurality of interconnect layers further include a second interconnect layer located away from the plurality of bit lines. The second interconnect layer includes a plurality of uniformly distributed second pads, which are coupled to the plurality of bit lines via a plurality of second contact plugs and other interconnect layers besides the second interconnect layer.

8. The memory according to claim 7, characterized in that, The plurality of interconnect layers further includes at least one intermediate interconnect layer located between the first interconnect layer and the second interconnect layer. The intermediate interconnect layer includes a plurality of intermediate pads and a plurality of intermediate leads. The plurality of intermediate pads are correspondingly coupled to the plurality of bit lines through the plurality of intermediate leads, a plurality of intermediate contact plugs, and other interconnect layers located between the intermediate interconnect layer and the plurality of bit lines. The area occupied by the intermediate pad is greater than that occupied by the first pad, and the area occupied by the second pad is greater than that occupied by the intermediate pad.

9. The memory according to claim 1 or 2, characterized in that, The memory also includes: Multiple word lines extend along a third direction, respectively covering a portion of the sidewalls of the active regions of the multiple vertical transistors, wherein the third direction is perpendicular to the first direction and intersects with the second direction; Multiple word line contact plugs are located between the multiple word lines and the first interconnect structure; The multiple word lines are coupled to the peripheral circuit via the multiple word line contact plugs, the first interconnect structure, the bonding interface, and the second interconnect structure.

10. The memory according to claim 9, characterized in that, The plurality of word line contact plugs are distributed at opposite ends of the plurality of word lines. The word line contact plug at one end of the plurality of word lines is coupled to the word lines of odd numbered sequence, and the word line contact plug at the other end of the plurality of word lines is coupled to the word lines of even numbered sequence.

11. A method for manufacturing a memory, characterized in that, include: A first semiconductor structure is formed, wherein the first semiconductor structure includes a memory array, multiple bit lines, and a first interconnect structure; the memory array includes multiple vertical transistors arranged in an array and multiple memory cells coupled to the multiple vertical transistors one-to-one; the active region of each vertical transistor extends along a first direction, and a first end of each vertical transistor is coupled to a first end of each memory cell; the multiple bit lines are located on the side of the multiple vertical transistors away from the multiple memory cells, the multiple bit lines extend along a second direction perpendicular to the first direction, and are respectively coupled to the second ends of the multiple vertical transistors; the first interconnect structure is located on the side of the multiple bit lines away from the memory array; A second semiconductor structure is formed, wherein the second semiconductor structure includes a peripheral circuit and a second interconnect structure located on the peripheral circuit; The first semiconductor structure and the second semiconductor structure are bonded by forming a bonding interface between the first interconnect structure and the second interconnect structure, so that the multiple bit lines are correspondingly coupled to the peripheral circuit through the first interconnect structure, the bonding interface, and the second interconnect structure; wherein, the first interconnect structure includes multiple interconnect layers, the multiple interconnect layers include a first interconnect layer close to the multiple bit lines, the first interconnect layer includes multiple first pads and multiple first leads, the multiple first pads are correspondingly coupled to the multiple bit lines through the multiple first leads and multiple first contact plugs, the multiple first pads are of the same size, the multiple first contact plugs are of the same size, and for the multiple first leads, the longer the extension length, the larger the width.

12. The method for manufacturing a memory according to claim 11, characterized in that, Forming the first semiconductor structure includes: The substrate is etched from the first surface to form a plurality of said active regions arranged in an array and a trench structure defining said plurality of active regions, each said active region extending along a first direction perpendicular to said substrate; An isolation structure is formed within the trench structure; The isolation structure is partially etched from the first surface to form a plurality of word line trenches extending along a third direction, each of the word line trenches exposing a portion of each of the active regions arranged along the third direction, the third direction being perpendicular to the first direction; A gate dielectric layer and a word line are sequentially formed within each of the word line trenches; Doping is performed from the first end of each of the active regions on the first surface to form the first source / drain regions; The plurality of memory cells are formed on the first surface, and the first end of each memory cell is coupled to a first source-drain region; The substrate is thinned from the second side to expose the second ends of each of the active regions; the second ends of each of the active regions are doped from the second side to form second source / drain regions; Multiple bit lines extending along the second direction are formed on the second surface, and the multiple bit lines are respectively coupled to the second source and drain regions of the multiple active regions. The second direction is perpendicular to the first direction and intersects with the third direction. A first interconnect structure is formed on the second surface.

13. The method for manufacturing a memory according to claim 12, characterized in that, A first interconnect structure is formed on the second surface, including: The first interconnect layer is formed on the second surface, and the first interconnect layer is located on the plurality of bit lines; At least one intermediate interconnect layer is formed on the first interconnect layer. The intermediate interconnect layer includes a plurality of intermediate pads and a plurality of intermediate leads. The plurality of intermediate pads are coupled to the plurality of bit lines through the plurality of intermediate leads, a plurality of intermediate contact plugs, and other interconnect layers located between the intermediate interconnect layer and the plurality of bit lines. The area occupied by the intermediate pads is larger than the area occupied by the first pads.

14. The method for manufacturing a memory according to claim 13, characterized in that, The first interconnect structure is formed on the second surface, and the method further includes: A second interconnect layer is formed on the intermediate interconnect layer. The second interconnect layer includes a plurality of uniformly distributed second pads. The plurality of second pads are coupled to the plurality of bit lines through a plurality of second contact plugs and other interconnect layers other than the second interconnect layer. The area occupied by the second pads is larger than that occupied by the intermediate pads.

15. The method for manufacturing a memory according to claim 12, characterized in that, Forming the first semiconductor structure further includes: Multiple word line contact plugs are formed, and the multiple word line contact plugs are located between multiple word lines and the first interconnect structure; wherein, the multiple word lines are correspondingly coupled to the peripheral circuit through the multiple word line contact plugs, the first interconnect structure, the bonding interface and the second interconnect structure.

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