Semiconductor device and data storage system including the same

Abstract

The invention discloses a semiconductor device and a data storage system. The semiconductor device includes: a plate layer; gate electrodes stacked on the plate layer and spaced apart from each other, and including a first gate electrode and a second gate electrode on the first gate electrode; a first channel structure extending in the first gate electrode; and second channel structures extending in the second gate electrode and electrically connected to the first channel structures, respectively, in which the second gate electrode includes a metal material, and in which the first channel structures are electrically connected to the second gate electrode. Each of the second channel structures includes a second channel layer, a second gate dielectric layer between the second channel layer and the second gate electrode, a second channel buried insulating layer on an inner side surface of the second channel layer, a second channel pad on the second channel buried insulating layer, and a second gate electrode on the second channel pad. And a second pad oxide layer on the second channel pad and the second channel layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0087296 filed in the Korean Intellectual Property Office on July 5, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to a semiconductor device and a data storage system including the semiconductor device. Background Art

[0004] Semiconductor devices capable of storing high-capacity data in data storage systems requiring data storage have become necessary. Therefore, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as a method for increasing the data storage capacity of semiconductor devices, a semiconductor device including a memory cell arranged three-dimensionally instead of a memory cell arranged two-dimensionally has been proposed. Summary of the invention

[0005] Example embodiments of the present disclosure are directed to providing a semiconductor device having improved electrical properties and reliability.

[0006] Example embodiments of the present disclosure are directed to providing a data storage system including a semiconductor device having improved electrical properties and reliability.

[0007] According to an example embodiment of the present disclosure, a semiconductor device includes: a first semiconductor structure, which includes a substrate, a circuit device on the substrate, and a circuit interconnection line on the circuit device; and a second semiconductor structure, which is located on the first semiconductor structure, wherein the second semiconductor structure includes: a board layer; a gate electrode, which includes a lower selection gate electrode, a memory gate electrode and an upper selection gate electrode sequentially stacked on the board layer, wherein the gate electrodes are spaced apart from each other in a first direction perpendicular to an upper surface of the board layer; a first isolation region, which extends in the lower selection gate electrode and the memory gate electrode in a second direction perpendicular to the first direction; a second isolation region, which extends in the upper selection gate electrode in the second direction; a horizontal insulating layer, which is located between the memory gate electrode and the upper selection gate electrode; a first channel structure, which extends in the lower selection gate electrode and the memory gate electrode in the first direction; a second channel structure, which extends in the upper selection gate electrode and the horizontal insulating layer and is electrically connected to the first channel structure, respectively; and a gate barrier layer, which is located on the side surface and the lower surface of the upper selection gate electrode, wherein the upper selection gate electrode includes a metal material.

[0008] According to an example embodiment of the present disclosure, a semiconductor device includes: a board layer; gate electrodes stacked on the board layer in a first direction perpendicular to an upper surface of the board layer and spaced apart from each other, wherein the gate electrodes include a first gate electrode and a second gate electrode on the first gate electrode; a first channel structure extending in the first direction in the first gate electrode; and a second channel structure extending in the first direction in the second gate electrode, wherein the second channel structures are electrically connected to the first channel structures, respectively, wherein the second gate electrode includes a metal material, and wherein each of the second channel structures includes a second channel layer, a second gate dielectric layer between the second channel layer and the second gate electrode, a second channel buried insulating layer on an inner side surface of the second channel layer, a second channel pad on the second channel buried insulating layer, and a second channel pad and a second pad oxide layer on the second channel layer.

[0009] According to an example embodiment of the present disclosure, a data storage system includes: a semiconductor memory device, which includes a first semiconductor structure, a second semiconductor structure on the first semiconductor structure, and an input / output pad, wherein the first semiconductor structure includes a circuit device and the input / output pad is electrically connected to the circuit device; and a controller, which is electrically connected to the semiconductor memory device through the input / output pad and is configured to control the semiconductor memory device, wherein the second semiconductor structure includes: a board layer; gate electrodes, which are stacked on the board layer in a first direction perpendicular to an upper surface of the board layer and spaced apart from each other, wherein the gate electrodes include a first gate electrode and a second gate electrode on the first gate electrode; a first channel structure, which extends in the first gate electrode in the first direction; and a second channel structure, which extends in the second gate electrode in the first direction, wherein the second channel structures are electrically connected to the first channel structures, respectively, wherein the second gate electrode includes a metal material, and wherein each of the second channel structures includes a second channel layer, a second gate dielectric layer between the second channel layer and the second gate electrode, a second channel pad on an inner side surface of the second channel layer, and a second pad oxide layer on the second channel pad and the second channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure;

[0012] Figure 2 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0013] Figure 3A and Figure 3Bis an enlarged view showing a portion of a semiconductor device according to an example embodiment of the present disclosure;

[0014] Figure 4 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure;

[0015] Figure 5A and Figure 5B is an enlarged view showing a portion of a semiconductor device according to an example embodiment of the present disclosure;

[0016] Figure 6 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0017] Figure 7 is a cross-sectional view showing a semiconductor device according to an example embodiment of the present disclosure;

[0018] FIG. 8A to FIG. 8S is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure;

[0019] Fig. 9 is a diagram illustrating a data storage system including a semiconductor device according to an example embodiment of the present disclosure;

[0020] Fig.10 is a perspective view illustrating a data storage system including a semiconductor device according to an example embodiment of the present disclosure; and

[0021] Fig.11 is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings as follows.

[0023] Figure 1 is a plan view illustrating a semiconductor device according to example embodiments.

[0024] Figure 2 It is shown along Figure 1 2 is a cross-sectional view of a semiconductor device according to example embodiments taken along line II′ in FIG.

[0025] Figure 3A and Figure 3B are enlarged views illustrating some portions of a semiconductor device according to example embodiments. Figure 3A It is shown Figure 2 Magnified view of area "A" in FIG. Figure 3B It is shown Figure 2 Magnified view of area "B" in FIG.

[0026] Figure 4 It is shown along Figure 3A FIG. 1 is a plan view of a semiconductor device according to example embodiments taken along line II-II′ in FIG.

[0027] Reference Figures 1 to 4 , the semiconductor device 100 may include a peripheral circuit region PERI as a first semiconductor structure including a substrate 201, and a memory cell region CELL as a second semiconductor structure including a plate layer 101. The memory cell region CELL may be disposed on the peripheral circuit region PERI. In an example embodiment, on the contrary, the memory cell region CELL may be disposed below the peripheral circuit region PERI. For ease of description, spatially relative terms such as "under ...", "under ...", "under ...", "above ...", "above ...", "higher", etc. may be used herein to describe the relationship between an element or feature and another (one or more) element or feature as shown in the drawings. It will be understood that in addition to the orientations depicted in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is flipped, the element described as "under" or "under" other elements or features will then be oriented to "above" the other elements or features. Therefore, the term "under ..." may include both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0028] The peripheral circuit region PERI may include a substrate 201, an impurity region 205 and a device isolation layer 210 in the substrate 201, a circuit device 220 disposed on the substrate 201, a peripheral region insulating layer 290, a circuit contact plug 270, and a circuit interconnection line 280. The peripheral region insulating layer 290, the circuit contact plug 270, and the circuit interconnection line 280 may be located on the substrate 201.

[0029] The substrate 201 may have an upper surface extending in an X direction and a Y direction. The X direction and the Y direction may be parallel to the upper surface of the substrate 201 and intersect each other. The X direction and the Y direction may be perpendicular to each other. In the substrate 201, the active region may be defined by the device isolation layer 210. For example, the active region may be adjacent to the device isolation layer 210 (e.g., located between the device isolation layers 210). An impurity region 205 including impurities may be disposed in a portion of the active region. The substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, and / or a group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0030] The circuit devices 220 may include planar transistors. Each of the circuit devices 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The impurity region 205 may be provided as a source / drain region located in the substrate 201 on both sides (e.g., opposite sides) of the circuit gate electrode 225.

[0031] The peripheral region insulating layer 290 may be disposed on the circuit device 220 on the substrate 201. The peripheral region insulating layer 290 may include a plurality of insulating layers formed in different processes. The peripheral region insulating layer 290 may include an insulating material.

[0032] The circuit contact plug 270 and the circuit interconnection line 280 may form a circuit interconnection structure electrically connected to the circuit device 220 and the impurity region 205. It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, the element or layer may be directly on the other element or layer, directly connected to or directly coupled to the other element or layer, or one or more intermediate elements or layers may exist. In contrast, when an element is referred to as being "directly coupled to", "directly connected to" or "directly responsive to" another element, or "directly on" another element, there is no intermediate element. In addition, "electrical connection" conceptually includes physical connection and physical disconnection. For example, the "electrical connection" between element A and element B may include a direct physical connection between element A and element B and / or an indirect physical connection between element A and element B with one or more intermediate elements between element A and element B. The circuit contact plug 270 may have a cylindrical shape, and the circuit interconnection line 280 may have a linear shape, but is not limited thereto. An electrical signal may be applied to the circuit device 220 through the circuit contact plug 270 and the circuit interconnection line 280. In an area not shown, the circuit contact plug 270 may also be connected (e.g., electrically connected) to the circuit gate electrode 225. The circuit interconnection line 280 may be connected (e.g., electrically connected) to the circuit contact plug 270, may have a line shape, and may be provided in a plurality of layers. The circuit contact plug 270 and the circuit interconnection line 280 may include a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), etc., and each component may also include a diffusion barrier layer. In example embodiments, the number of layers of the circuit contact plug 270 and the circuit interconnection line 280 may vary.

[0033] The memory cell region CELL may include a source structure SS (on the peripheral circuit region PERI or on the peripheral region insulating layer 290), a gate electrode 130 stacked on the source structure SS, an interlayer insulating layer 120 alternately stacked with the gate electrode 130, a first channel structure CH and a second channel structure SH extending in at least a portion of the gate electrode 130 (e.g., penetrating at least a portion of the gate electrode 130), a first isolation region MS extending in at least a portion of the gate electrode 130 (e.g., extending through at least a portion of the gate electrode 130), a second isolation region US extending in a first upper gate electrode 130U1 of the gate electrode 130 (e.g., penetrating the first upper gate electrode 130U1 of the gate electrode 130), a horizontal insulating layer 150 disposed between the first channel structure CH and the second channel structure SH, and a pillar 180 on the second channel structure SH. The memory cell region CELL may also include (in a plan view) a gate barrier layer 135 extending around at least a portion of the gate electrode 130 (e.g., surrounding at least a portion of the gate electrode 130), and a first cell region insulating layer 192, a second cell region insulating layer 194, and a third cell region insulating layer 196 on the gate electrode 130.

[0034] The source structure SS may include a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104 stacked in sequence. However, in example embodiments, the number of conductive layers included in the source structure SS may vary.

[0035] The plate layer 101 may have a plate shape and may be used as at least a portion of a common source line of the semiconductor device 100. The plate layer 101 may have an upper surface extending in the X direction and the Y direction. The plate layer 101 may include a conductive material. For example, the plate layer 101 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, and / or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, and / or silicon germanium. The plate layer 101 may also include impurities. The plate layer 101 may be provided as a polycrystalline semiconductor layer such as a polysilicon layer or an epitaxial layer.

[0036] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be stacked in order on the upper surface of the plate layer 101. For example, the first horizontal conductive layer 102 may be used as a part of a common source line of the semiconductor device 100 and may be used as a common source line together with the plate layer 101. Figure 3B As shown in , the first horizontal conductive layer 102 may be directly connected to the first channel layer 140 around the first channel layer 140 .

[0037] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may include a semiconductor material such as polysilicon. In this case, at least the first horizontal conductive layer 102 may be doped with impurities having the same conductivity as that of the plate layer 101, and the second horizontal conductive layer 104 may be a doped layer or a layer including impurities diffused from the first horizontal conductive layer 102. However, the material of the second horizontal conductive layer 104 is not limited to a semiconductor material, and may be replaced with an insulating layer.

[0038] A portion of the gate electrode 130 (e.g., the gate electrode 130 other than the first upper gate electrode 130U1) may be vertically stacked and spaced apart from each other on the plate layer 101, and may form a stacked structure together with the interlayer insulating layer 120. The stacked structure may include a lower stacked structure and an upper stacked structure stacked vertically. Alternatively, in an example embodiment, the stacked structure may be configured as a single stacked structure. The vertical direction may be a Z direction perpendicular to the X direction and the Y direction. The vertical direction may be perpendicular to the upper surface of the substrate 201.

[0039] The gate electrode 130 may include a first upper gate electrode 130U1 included in a string selection transistor, a second upper gate electrode 130U2 included in an erase transistor, a memory gate electrode 130M included in a plurality of memory cells, a first lower gate electrode 130L1 included in an erase transistor, and a second lower gate electrode 130L2 included in a ground selection transistor. The number of memory gate electrodes 130M included in a memory cell may be determined according to the capacity of the semiconductor device 100. In example embodiments, each of the number of second upper gate electrodes 130U2, the number of first lower gate electrodes 130L1, and the number of second lower gate electrodes 130L2 may be one to four or more. In some example embodiments, the positions of the first lower gate electrode 130L1 and the second lower gate electrode 130L2 may be interchanged. In some example embodiments, the second upper gate electrode 130U2 and / or the first lower gate electrode 130L1 may be omitted. In some example embodiments, a portion of the memory gate electrode 130M may be a dummy gate electrode.

[0040] The first upper gate electrode 130U1 and the second lower gate electrode 130L2 may also be referred to as an upper selection gate electrode and a lower selection gate electrode, respectively. In addition, the second lower gate electrode 130L2, the first lower gate electrode 130L1, the memory gate electrode 130M, and the second upper gate electrode 130U2, which are arranged in order upward, may be referred to as a first gate electrode, and the first upper gate electrode 130U1 may be referred to as a second gate electrode. The thickness of the first upper gate electrode 130U1 (i.e., the second gate electrode) (in the Z direction) may be greater than the thickness of each of the first gate electrodes (in the Z direction).

[0041] The gate electrode 130 may include a conductive material such as a metal material. For example, the gate electrode 130 may include tungsten (W), molybdenum (Mo), tantalum (Ta), ruthenium (Ru), niobium (Nb), osmium (Os), zirconium (Zr), iridium (Ir), rhenium (Re), and / or titanium (Ti). All of the gate electrodes 130 (e.g., each of the gate electrodes 130) may include a metal material, or at least the first upper gate electrode 130U1 may include a metal material. For example, (each of) the gate electrodes 130 may include the same metal material. In some embodiments, the first upper gate electrode 130U1 may include a different material and / or have a material composition different from the material composition of other gate electrodes (e.g., the second upper gate electrode 130U2, the memory gate electrode 130M, the first lower gate electrode 130L1, and / or the second lower gate electrode 130L2) in the gate electrode 130.

[0042] The first upper gate electrode 130U1 may include a gap VD therein. Figure 4 As shown in , the first upper gate electrode 130U1 may be located on the side surface of the second channel structure SH and the side surface of the second isolation region US (for example, deposited from the side surface of the second channel structure SH and the side surface of the second isolation region US). Therefore, the gap VD may be provided between the second channel structures SH and between the second channel structure SH and the second isolation region US. In example embodiments, the relative size and shape of the gap VD may be changed. The gap VD may include air or gas. The first upper gate electrode 130U1 may have an inclined side surface so that the width of the first upper gate electrode 130U1 (for example, in the X direction and / or the Y direction) may increase toward the plate layer 101. For example, the side surface and the lower surface of the first upper gate electrode 130U1 may have an inclination of less than 90 degrees. For example, the side surface and the lower surface of the first upper gate electrode 130U1 may meet each other at an acute angle.

[0043] When the first upper gate electrode 130U1 includes a metal material (e.g., more metal material), the resistivity of the first upper gate electrode 130U1 can be reduced, compared to a comparative example in which the first upper gate electrode 130U1 includes a semiconductor material (e.g., more semiconductor material or only semiconductor material), so that the thickness of the first upper gate electrode 130U1 (in the Z direction) can be reduced. Therefore, the vertical level of the contact plug (in the Z direction) connected (e.g., electrically connected) to the gate electrode 130 on the end of the gate electrode 130 (e.g., the first upper gate electrode 130U1) can be reduced together, so that the process difficulty of the semiconductor device 100 can be reduced, and the overall height of the semiconductor device 100 (in the Z direction) can be reduced (e.g., lowered). The vertical level can be a relative position (e.g., distance) from the lower surface of the substrate 201 in the vertical direction (e.g., Z direction). A distance farther from the lower surface of the substrate 201 can be a higher vertical level. A distance closer to the lower surface of the substrate 201 can be a lower vertical level. In addition, in a comparative example where the first upper gate electrode 130U1 includes a semiconductor material (e.g., more semiconductor material or only semiconductor material), a heat treatment process may be performed to improve (e.g., reduce) the resistivity of the first upper gate electrode 130U1. In contrast, in the previous example embodiment, the heat treatment process may not be performed for improving the resistivity by the first upper gate electrode 130U1 including a metal material (e.g., more metal material), so that defects such as cracks and warpage caused by the heat treatment process may be reduced (e.g., prevented).

[0044] The thickness of the first upper gate electrode 130U1 (in the Z direction) may be, for example, approximately To about (For example, to ) or approximately To about (For example, to However, the embodiments of the present disclosure are not limited to the thickness of the first upper gate electrode 130U1.

[0045] like Figure 3A and Figure 3BAs shown in , the gate barrier layer 135 may extend around (e.g., surround) the gate electrode 130 (in a plan view). The gate barrier layer 135 may be on the upper surface, lower surface, and side surface of the gate electrode 130 except the first upper gate electrode 130U1 (e.g., around or around the upper surface, lower surface, and side surface of the gate electrode 130 except the first upper gate electrode 130U1). The gate barrier layer 135 may expose the upper surface of the first upper gate electrode 130U1, and may be on the lower surface and side surface of the first upper gate electrode 130U1 (e.g., around or around the lower surface and side surface of the first upper gate electrode 130U1). The arrangement of the gate barrier layer 135 may be due to the following reference to Figure 8Q and Figure 8R The process of manufacturing the first upper gate electrode 130U1 is described in more detail. The gate barrier layer 135 on the first upper gate electrode 130U1 (e.g., covering the first upper gate electrode 130U1 or overlapping the first upper gate electrode 130U1) may contact the side surface of the second channel structure SH and the side surface of the second isolation region US (e.g., the upper isolation insulating layer 103 described below). The gate barrier layer 135 may include, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN) and / or a combination thereof. In some example embodiments, the gate barrier layer 135 may not be disposed on the first gate electrode. As used herein, "element A overlaps element B in direction X" (or similar language) means that there is at least one line extending in direction X and intersecting both element A and element B.

[0046] The interlayer insulating layer 120 may be disposed between the gate electrodes 130 except the first upper gate electrode 130U1. Similar to the gate electrode 130, the interlayer insulating layers 120 may also be spaced apart from each other in a direction (e.g., Z direction) perpendicular to the upper surface of the plate layer 101. The interlayer insulating layer 120 may include an insulating material such as silicon oxide and / or silicon nitride. In example embodiments, the thickness of each of the interlayer insulating layers 120 (in the Z direction) may vary.

[0047] The first channel structure CH may extend in the gate electrode 130 other than the first upper gate electrode 130U1 in the Z direction (e.g., penetrate the gate electrode 130 other than the first upper gate electrode 130U1), and may be connected (e.g., electrically connected) to the plate layer 101. The second channel structure SH may extend in the first upper gate electrode 130U1 in the Z direction (e.g., penetrate the first upper gate electrode 130U1), and may be physically and electrically connected to the first channel structure CH, respectively. The first channel structure CH may form a memory cell string together with the second channel structure SH, and may be spaced apart from each other while forming rows and columns on the plate layer 101.

[0048] like Figure 1 As shown in , the first channel structure CH may be arranged to form a grid pattern in the XY plane, or may be arranged in a zigzag pattern in one direction (for example, in the X direction and / or the Y direction). The second channel structure SH may be arranged on the first channel structure CH, respectively. In example embodiments, at least a portion of the second channel structure SH may not be aligned with the first channel structure CH, and may be offset or misaligned in one direction (for example, in the X direction and / or the Y direction). For example, the second channel structure SH may overlap with the corresponding first channel structure CH in the Z direction. In this article, misalignment may mean that the center of an element and the center of another element are (basically) arranged at different positions in one direction. For example, if the center of element A and the center of element B are (basically) located at different positions in the X direction, element A and element B may be referred to as being misaligned in the X direction. The degree of misalignment of the second channel structure SH relative to the corresponding first channel structure CH may be different from each other. For example, the distance between the center of the second channel structure SH and the center of the corresponding first channel structure CH in the X direction may be different from each other. For example, referring to Figure 1 , the degree of misalignment (for example, the length of the offset or the distance between the centers) of the first channel structure CH and the corresponding second channel structure SH arranged in the leftmost region of the semiconductor device 100 defined by the second isolation region US may be greater than the degree of misalignment (for example, the length of the offset or the distance between the centers) of the first channel structure CH and the corresponding second channel structure SH in the central region of other regions (defined by the second isolation region US) of the semiconductor device 100, wherein the other regions may be adjacent to the leftmost region.

[0049] Each of the first channel structure CH and the second channel structure SH may have a columnar shape and may have an inclined side surface whose width decreases toward the plate layer 101. The first diameter of the first channel structure CH may be greater than the second diameter of the second channel structure SH. For example, the first diameter may be in a range of about 60 nm to 100 nm (e.g., 60 nm to 100 nm), and the second diameter may be in a range of about 40 nm to 80 nm (e.g., 40 nm to 80 nm).

[0050] like Figure 3A and Figure 3B As shown in , each of the first channel structures CH may include a first channel layer 140, a first gate dielectric layer 145, a first channel buried insulating layer 147, a first channel pad 148, and a first pad oxide layer 149. The first channel layer 140 may be formed in a ring shape extending around (e.g., surrounding) the first channel buried insulating layer 147 (in a plan view), but in an example embodiment, the first channel layer 140 may have a columnar shape such as a cylindrical or prism shape in which the first channel buried insulating layer 147 is absent. The first channel layer 140 may be connected (e.g., electrically connected) to the first horizontal conductive layer 102 in a lower portion. The first channel layer 140 may include, for example, a semiconductor material such as polysilicon and / or single crystal silicon.

[0051] The first gate dielectric layer 145 may be disposed between the gate electrode 130 and the first channel layer 140. Although not specifically shown, the first gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer stacked in order on (from) the first channel layer 140. The tunneling layer may tunnel charges into the charge storage layer, and may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), and / or a combination thereof. The charge storage layer may be configured as a charge trapping layer or a floating gate conductive layer. The blocking layer may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), a high-κ dielectric material, and / or a combination thereof. In example embodiments, at least a portion of the first gate dielectric layer 145 may extend along the gate electrode 130 in a horizontal direction (eg, an X direction and / or a Y direction).

[0052] The first channel pad 148 may be disposed at the upper end of the upper channel structure CH2. The first channel pad 148 may include, for example, doped polysilicon. The first pad oxide layer 149 may be disposed on the upper surface of the first channel layer 140 and the first channel pad 148 and may include, for example, silicon oxide.

[0053] The first channel structure CH may include a lower channel structure CH1 and an upper channel structure CH2 stacked vertically (e.g., stacked in the Z direction). The first channel structure CH may include a lower channel structure CH1 and an upper channel structure CH2 connected to each other (e.g., physically connected and / or electrically connected), and may have a curved portion due to a difference in the width of a connection region between the lower channel structure CH1 and the upper channel structure CH2. However, in example embodiments, the number of channel structures stacked in the Z direction in the first channel structure CH may vary. The first channel layer 140, the first gate dielectric layer 145, and the first channel buried insulating layer 147 may extend continuously between the lower channel structure CH1 and the upper channel structure CH2.

[0054] like Figure 3AAs shown in , each of the second channel structures SH may include a second channel layer 160, a second gate dielectric layer 165, a second channel buried insulating layer 167, a second channel pad 168, and a second pad oxide layer 169. The second channel layer 160 may be formed in a ring shape extending around the second channel buried insulating layer 167 therein (e.g., surrounding the second channel buried insulating layer 167 therein). The second channel layer 160 may extend in the horizontal insulating layer 150 (e.g., penetrate the horizontal insulating layer 150). In some embodiments, the lower portion of the second channel layer 160 may extend in the horizontal insulating layer 150 (e.g., penetrate the horizontal insulating layer 150). The second channel layer 160 may have a pad portion PR extending horizontally in the horizontal insulating layer 150. For example, the second channel layer 160 may protrude horizontally toward the horizontal insulating layer 150. The second channel layer 160 (e.g., the pad portion PR of the second channel layer 160) may be disposed in a horizontal recessed region of the horizontal insulating layer 150. The second channel layer 160 (e.g., a portion of the second channel layer 160 located below the pad portion PR) may be disposed in the first channel pad 148 of the first channel structure CH. For example, the second channel layer 160 may partially extend into the first channel pad 148. The second channel layer 160 may be connected (e.g., electrically connected) to the first channel pad 148. The second channel layer 160 may be disposed in a recessed region of the first channel pad 148 below the pad portion PR. The second pad oxide layer 169 may overlap the second channel pad 168 and the second channel layer 160 (in the Z direction). For example, the second pad oxide layer 169 may cover at least a portion of the upper surface of the second channel pad 168 and the upper surface of the second channel layer 160. The second pad oxide layer 169 may be disposed on the inner side (e.g., the inner side surface) of the second gate dielectric layer 165 and may contact the second gate dielectric layer 165 through its side surface.

[0055] The description of the materials of the first channel layer 140, the first channel buried insulating layer 147, the first channel pad 148, and the first pad oxide layer 149 may be applied to the description of the materials of the second channel layer 160, the second channel buried insulating layer 167, the second channel pad 168, and the second pad oxide layer 169, respectively. The second gate dielectric layer 165 may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), high dielectric constant (high κ) dielectric materials and / or combinations thereof.

[0056] The horizontal insulating layer 150 may be disposed between the first channel structure CH and the second channel structure SH and may extend horizontally. In some embodiments, the horizontal insulating layer 150 may overlap the second channel structure SH in a horizontal direction (e.g., X direction and / or Y direction) and may be disposed on the first channel structure CH. The horizontal insulating layer 150 may be disposed between the first upper gate electrode 130U1 and the second upper gate electrode 130U2. The horizontal insulating layer 150 may be used as an etching stop layer when forming the second channel structure SH, and the horizontal insulating layer 150 may also be used when forming the pad portion PR of the second channel layer 160.

[0057] The horizontal insulating layer 150 may include an insulating material, and may include a material different from that of the first and second cell region insulating layers 192 and 194. The horizontal insulating layer 150 may include a nitride, and may include, for example, SiN, SiON, SiCN, and / or SiOCN.

[0058] The first isolation region MS may extend in the gate electrode 130 other than the first upper gate electrode 130U1 (eg, penetrate the gate electrode 130 other than the first upper gate electrode 130U1), and may extend in the Y direction. Figure 1 As shown in , the first isolation regions MS may be arranged parallel to each other. Figure 2 As shown in FIG. 1 , the first isolation region MS may extend in the gate electrode 130 stacked on the plate layer 101 (e.g., penetrate the gate electrode 130 stacked on the plate layer 101), may also extend in the first horizontal conductive layer 102 and the second horizontal conductive layer 104 (e.g., penetrate the first horizontal conductive layer 102 and the second horizontal conductive layer 104), and may be connected to the plate layer 101. Each side surface of the first isolation region MS may have a region protruding toward the gate electrode 130 other than the first upper gate electrode 130U1.

[0059] Each of the first isolation regions MS may include a gate isolation insulating layer 105. The gate isolation insulating layer 105 may have a shape whose width may generally decrease toward the plate layer 101 due to a high aspect ratio. The width of the gate isolation insulating layer 105 may not gradually decrease toward the plate layer 101 due to a protruding region of the first isolation region MS toward the gate electrode 130. In some embodiments, the width of a portion of the gate isolation insulating layer 105 protruding toward the gate electrode 130 may decrease toward the plate layer 101. The gate isolation insulating layer 105 may include an insulating material, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0060] like Figure 1As shown in , a plurality of second isolation regions US may be disposed between first isolation regions MS adjacent to each other and may extend in the Y direction. The second isolation region US may extend in the first upper gate electrode 130U1 disposed at the uppermost portion of the gate electrode 130 (e.g., penetrate the first upper gate electrode 130U1 disposed at the uppermost portion of the gate electrode 130). The second isolation region US may divide the first upper gate electrode 130U1 in the Y direction. The second isolation region US may be spaced apart from the first isolation region MS in a plan view and may not overlap with the first isolation region MS in the Z direction. In the X direction, the width of the second isolation region US may be smaller than the width of the first isolation region MS and may be smaller than the diameter of the second channel structure SH. For example, the width of the second isolation region US may be in the range of about 30 nm to about 50 nm (e.g., 30 nm to 50 nm).

[0061] The upper surface of the second isolation region US may be disposed at substantially the same level (e.g., the same vertical level) as the upper surface of the second channel structure SH. For example, the upper surface of the second isolation region US may be disposed at the same distance from the slab 101 in the Z direction as the upper surface of the second channel structure SH. The side surface of the second isolation region US may have a shape different from that of the first isolation region MS. Specifically, the side surface of the second isolation region US may extend toward the slab 101 at a constant slope without having a region protruding horizontally toward the first upper gate electrode 130U1. The side surface of the second isolation region US may be substantially flat. The side surface of the second isolation region US may be formed as above, because the second isolation region US may be formed before the first upper gate electrode 130U1, which will be described below with reference to Figure 8G to Figure 8R Describe in more detail.

[0062] Each of the second isolation regions US may include an upper isolation insulating layer 103. The upper isolation insulating layer 103 may include an insulating material, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0063] The column 180 may be included in a cell interconnect structure electrically connected to a memory cell in the memory cell region CELL. The column 180 may be connected (e.g., electrically and physically connected) to the second channel structure SH, and may be electrically connected to the first channel structure CH. The column 180 may have a hole shape, may extend in the second pad oxide layer 169 of the second channel structure SH (e.g., penetrate the second pad oxide layer 169 of the second channel structure SH), and may be (at least partially) disposed in a recessed region of the second channel pad 168. However, whether the second channel pad 168 is recessed and its recessed depth may be changed in an example embodiment. The column 180 may electrically connect the first channel structure CH and the second channel structure SH to a bit line not shown. The column 180 may include a metal, e.g., tungsten (W), copper (Cu), or aluminum (Al).

[0064] The first cell region insulating layer 192, the second cell region insulating layer 194, and the third cell region insulating layer 196 may be disposed on the gate electrode 130. The first cell region insulating layer 192 may be located on the second upper gate electrode 130U2 (e.g., covering the second upper gate electrode 130U2 or overlapping the second upper gate electrode 130U2), the second cell region insulating layer 194 may be located on the horizontal insulating layer 150 (e.g., covering the horizontal insulating layer 150 or overlapping the horizontal insulating layer 150), and the third cell region insulating layer 196 may be located on the first upper gate electrode 130U1 (e.g., covering the first upper gate electrode 130U1 or overlapping the first upper gate electrode 130U1). The first cell region insulating layer 192, the second cell region insulating layer 194, and the third cell region insulating layer 196 may include insulating materials, and each of these layers may include a plurality of insulating layers.

[0065] Figure 5A and Figure 5B is an enlarged view illustrating a portion of a semiconductor device according to example embodiments. Figure 5A and Figure 5B Each shows Figure 3A The corresponding area.

[0066] Reference Figure 5A In the semiconductor device 100a, the gate barrier layer 135 extending around (eg, surrounding) the first upper gate electrode 130U1 may be omitted (see Figure 3A ). Therefore, the first upper gate electrode 130U1 may be in contact with the side surface of the second channel structure SH and the side surface of the second isolation region US. In example embodiments, the gate barrier layer 135 disposed on the gate electrode 130 below the first upper gate electrode 130U1 may be omitted (see Figure 3B ).

[0067] Reference Figure 5B In the semiconductor device 100b, the first upper gate electrode 130U1 may not include a gap VD (see Figure 3A Depending on the distance between the second channel structures SH, the material of the first upper gate electrode 130U1, and the deposition conditions of the first upper gate electrode 130U1, the gap VD may not be formed as in the example embodiment.

[0068] Figure 6 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0069] Reference Figure 6 In the semiconductor device 100c, the arrangement relationship between the first isolation region MS and the second isolation region US and the arrangement relationship between the first channel structure CH and the second channel structure SH may be the same as Figure 2 Different from those in the example embodiments in .

[0070] At least one of the second isolation regions US may be disposed on the first isolation region MS and may overlap the first isolation region MS in the Z direction. In some example embodiments, the first isolation region MS may also extend upward to extend in the first upper gate electrode 130U1 (e.g., penetrate the first upper gate electrode 130U1). In this case, the second isolation region US on the first isolation region MS may be omitted.

[0071] In some embodiments, a second channel structure SH among the second channel structures SH may be misaligned relative to the corresponding first channel structure CH in one direction, and other second channel structures SH among the second channel structures SH may be misaligned relative to other corresponding first channel structures CH in another direction (e.g., the opposite direction). For example, a second channel structure SH among the second channel structures SH may be misaligned on the left side of the corresponding first channel structure CH among the first channel structures CH, and other second channel structures SH among the second channel structures SH may be misaligned on the right side of other corresponding first channel structures CH among the first channel structures CH.

[0072] In example embodiments, the arrangement of the first isolation region MS and the second isolation region US and the misalignment of the first channel structure CH and the second channel structure SH may vary.

[0073] Figure 7 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0074] Reference Figure 7 , the semiconductor device 100d may include a first semiconductor structure S1 and a second semiconductor structure S2 bonded by a wafer bonding method.

[0075] Reference above Figure 1 and Figure 2 The description of the peripheral circuit region PERI described can be applied to the first semiconductor structure S1. However, the first semiconductor structure S1 may also include a first bonding via 295, a first bonding metal layer 298, and a first bonding insulating layer 299 as a bonding structure. The first bonding via 295 may be disposed above the uppermost circuit interconnection line 280 and may be connected (e.g., electrically connected) to the circuit interconnection line 280. At least a portion of the first bonding metal layer 298 may be connected (e.g., electrically connected) to the first bonding via 295 on the first bonding via 295. The first bonding metal layer 298 may be connected (e.g., electrically connected) to the second bonding metal layer 198 of the second semiconductor structure S2. The first bonding metal layer 298 together with the second bonding metal layer 198 may provide an electrical connection path according to the bonding between the first semiconductor structure S1 and the second semiconductor structure S2. A portion of the first bonding metal layer 298 may be connected to the circuit interconnection line 280 below and may be provided only for bonding. The first bonding via 295 and the first bonding metal layer 298 may include a conductive material such as copper (Cu). The first bonding insulating layer 299 may be disposed around (e.g., may extend around) the first bonding metal layer 298. The first bonding insulating layer 299 may also be configured to serve as a diffusion barrier layer for the first bonding metal layer 298, and may include, for example, SiN, SiON, SiCN, SiOC, SiOCN, and / or SiO.

[0076] Unless otherwise stated, the above references Figures 1 to 4 The description of the memory cell region CELL described above can be applied to the second semiconductor structure S2. The second semiconductor structure S2 can also include a bit line 185, a lower contact plug 182, and a cell interconnection line 184 as a cell interconnection structure, and can also include a second bonding via 195, a second bonding metal layer 198, and a second bonding insulating layer 199 as a bonding structure. The second semiconductor structure S2 can also include a passivation layer 106 located on the upper surface of the plate layer 101 (e.g., covering the upper surface of the plate layer 101 or overlapping the upper surface of the plate layer 101).

[0077] The bit line 185 may be connected (e.g., electrically connected) to the pillar 180, the lower contact plug 182 may be connected (e.g., electrically connected) to the bit line 185, and the cell interconnection line 184 may be connected (e.g., electrically connected) to the lower contact plug 182. However, in example embodiments, the number of layers of contact plugs and cell interconnection lines included in the cell interconnection structure and their arrangement may vary. The bit line 185, the lower contact plug 182, and the cell interconnection line 184 may include a conductive material, and may include, for example, tungsten (W), aluminum (Al), and / or copper (Cu).

[0078] The second bonding via 195 and the second bonding metal layer 198 may be disposed below the lowermost cell interconnect line 184. The second bonding via 195 may connect (e.g., electrically connect) the cell interconnect line 184 to the second bonding metal layer 198, and the second bonding metal layer 198 may be bonded to the first bonding metal layer 298 of the first semiconductor structure S1. The second bonding insulating layer 199 may be bonded and connected to the first bonding insulating layer 299 of the first semiconductor structure S1. The second bonding via 195 and the second bonding metal layer 198 may include a conductive material such as copper (Cu). The second bonding insulating layer 199 may include, for example, SiO, SiN, SiCN, SiOC, SiON, and / or SiOCN.

[0079] The first semiconductor structure S1 and the second semiconductor structure S2 may be joined by a bonding between the first bonding metal layer 298 and the second bonding metal layer 198 and a bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199. The bonding between the first bonding metal layer 298 and the second bonding metal layer 198 may be, for example, a copper (Cu) to copper (Cu) bonding, and the bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199 may be, for example, a dielectric to dielectric bonding (such as a SiCN to SiCN bonding). The first semiconductor structure S1 and the second semiconductor structure S2 may be joined by a hybrid bonding including a copper (Cu) to copper (Cu) bonding and a dielectric to dielectric bonding.

[0080] The passivation layer 106 may be disposed on an upper surface of the board layer 101 and may protect the semiconductor device 100d. The passivation layer 106 may include an insulating material (eg, silicon oxide, silicon nitride, and / or silicon carbide), and may include a plurality of insulating layers in example embodiments.

[0081] In example embodiments, the second semiconductor structure S2 may not include the first horizontal conductive layer 102 and the second horizontal conductive layer 104 (see Figure 2 The upper end of the first channel structure CH may expose the first channel layer 140 (see Figure 3B ), and the first channel structure CH (first channel layer 140) may be directly connected (eg, electrically connected) to the plate layer 101. However, the electrical connection between the first channel structure CH and the common source line may be changed in example embodiments, and the first channel structure CH and the source structure SS may have the same Figure 2 The same structure as in the example embodiment.

[0082] FIG. 8A to FIG. 8S is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments. FIG. 8A to FIG. 8F and Figure 8S Shown with Figure 2corresponding area, and Figure 8G to Figure 8R Shown with Figure 3A The corresponding area.

[0083] Reference Fig. 8A , a circuit device 220 , a circuit interconnection structure (eg, a circuit contact plug 270 and a circuit interconnection line 280 ), and a peripheral region insulating layer 290 included in the peripheral circuit region PERI may be formed on the substrate 201 .

[0084] First, a device isolation layer 210 may be formed in a substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 may be sequentially formed on the substrate 201. The device isolation layer 210 may be formed by, for example, a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 may be formed using an atomic layer deposition (ALD) process and / or a chemical vapor deposition (CVD) process. The circuit gate dielectric layer 222 may include, for example, silicon oxide, and the circuit gate electrode 225 may include, for example, polysilicon and / or a metal silicide layer, but example embodiments thereof are not limited thereto. Thereafter, a spacer layer 224 and an impurity region 205 may be formed on two (e.g., opposite) side surfaces of the circuit gate dielectric layer 222 and the circuit gate electrode 225. In example embodiments, the spacer layer 224 may include a plurality of layers. The impurity region 205 may be formed by performing an ion implantation process.

[0085] In the circuit interconnection structure, the circuit contact plug 270 may be formed by partially forming the peripheral region insulating layer 290, removing a portion by etching, and filling a conductive material therein. The circuit interconnection line 280 may be formed, for example, by depositing a conductive material and patterning the material.

[0086] The peripheral region insulating layer 290 may include a plurality of insulating layers. The peripheral region insulating layer 290 may be formed as part of each process of forming other elements of the circuit interconnect structure (eg, circuit contact plugs 270 and circuit interconnect lines 280). Thus, a peripheral circuit region PERI may be formed.

[0087] Reference Figure 8B, a memory cell region CELL including a plate layer 101, a horizontal sacrificial layer 110, and a second horizontal conductive layer 104 may be formed on the peripheral circuit region PERI. The plate layer 101, the horizontal sacrificial layer 110, and the second horizontal conductive layer 104 may be sequentially formed on the peripheral region insulating layer 290. A lower mold structure may be formed by alternately stacking a lower sacrificial insulating layer 118 and an interlayer insulating layer 120 on the second horizontal conductive layer 104. A lower channel sacrificial layer 119 may be formed in the lower mold structure, and an upper mold structure may be formed by alternately stacking a lower sacrificial insulating layer 118 and an interlayer insulating layer 120 on the lower mold structure and / or the lower channel sacrificial layer 119.

[0088] The plate layer 101 may be formed on the peripheral region insulating layer 290. The plate layer 101 may include, for example, polysilicon, and may be formed by a CVD process. The polysilicon included in the plate layer 101 may include impurities.

[0089] The horizontal sacrificial layer 110 may include a first horizontal insulating layer 111 and a second horizontal insulating layer 112. The first horizontal insulating layer 111 and the second horizontal insulating layer 112 may be alternately stacked on the board layer 101. The horizontal sacrificial layer 110 may be formed by a subsequent process. Figure 2 The first horizontal insulating layer 111 may include a material different from that of the second horizontal insulating layer 112. For example, the first horizontal insulating layer 111 may include the same material as that of the interlayer insulating layer 120, and the second horizontal insulating layer 112 may include the same material as that of the lower sacrificial insulating layer 118. The second horizontal conductive layer 104 may be formed on the horizontal sacrificial layer 110.

[0090] The first channel structure CH (see Figure 2 ) of the lower channel structure CH1 (see Figure 2 ) is formed on the second horizontal conductive layer 104. For example, the vertical level of the upper surface of the lower molding structure may be (substantially) the same as the vertical level of the upper surface of the lower channel structure CH1.

[0091] The lower sacrificial insulating layer 118 can be formed by a gate electrode 130 (see Figure 2) is replaced by a portion of the interlayer insulating layer 120. The lower sacrificial insulating layer 118 may include a material different from that of the interlayer insulating layer 120, and may have an etching selectivity relative to the interlayer insulating layer 120 (at least under certain etching conditions). For example, the interlayer insulating layer 120 may include silicon oxide and / or silicon nitride, and the lower sacrificial insulating layer 118 may include a material different from that of the interlayer insulating layer 120. For example, the lower sacrificial insulating layer 118 may include silicon, silicon oxide, silicon carbide and / or silicon nitride. In example embodiments, the interlayer insulating layer 120 may not have the same thickness. The thickness of the interlayer insulating layer 120 and the lower sacrificial insulating layer 118 and the number of the interlayer insulating layer 120 and the lower sacrificial insulating layer 118 may be different from the example shown.

[0092] A lower channel sacrificial layer 119 may be formed in a position corresponding to the lower channel structure CH1. The lower channel sacrificial layer 119 may be formed by forming a hole to extend in the lower molding structure (e.g., penetrate the lower molding structure), depositing a material forming the lower channel sacrificial layer 119 in the hole, and performing a planarization process. The lower channel sacrificial layer 119 may include, for example, polysilicon.

[0093] The upper channel structure CH2 (see Figure 2 ) is formed on the lower molded structure at a vertical level of . For example, the vertical level of the upper surface of the upper molded structure may be (substantially) the same as the vertical level of the upper surface of the upper channel structure CH2. The upper molded structure may be formed by alternately stacking lower sacrificial insulating layers 118 and interlayer insulating layers 120 in the same manner as the lower molded structure. The first unit region insulating layer 192 may be formed on the uppermost lower sacrificial insulating layer 118.

[0094] Reference Figure 8C , a first channel structure CH extending in (eg, penetrating) the lower molding structure and the upper molding structure may be formed.

[0095] First, an upper channel sacrificial layer extending in the upper mold structure (eg, penetrating the upper mold structure) may be formed. The upper channel sacrificial layer may be formed in a position corresponding to the upper channel structure CH2. The upper channel sacrificial layers may be formed to be connected to the lower channel sacrificial layers 119, respectively.

[0096] The first channel structure CH may be formed by the following steps: a lower channel hole is formed by removing a portion of the lower channel sacrificial layer 119 and the upper channel sacrificial layer, a first gate dielectric layer 145, a first channel layer 140, at least a portion of the first channel buried insulating layer 147, and a first channel pad 148 are sequentially deposited in the lower channel hole, and a first pad oxide layer 149 is formed.

[0097] The first gate dielectric layer 145 may be formed to have a uniform thickness (e.g., thickness in the X direction or the Y direction) using an ALD and / or CVD process. In the process, all or a portion of the first gate dielectric layer 145 may be formed, and a portion extending (substantially) perpendicular to the plate layer 101 along the first channel structure CH (e.g., along the inner side surface of the lower channel hole) may be formed in the process. The first channel layer 140 may be formed on the first gate dielectric layer 145 in the lower channel hole. The first channel buried insulating layer 147 may be formed to fill the rest of the lower channel hole, and may include, for example, an insulating material. The first channel pad 148 may be formed after partially removing the first channel buried insulating layer 147. The first channel pad 148 may include a conductive material such as polysilicon. The first pad oxide layer 149 may be formed by oxidizing the first channel pad 148 and the first channel layer 140 exposed upward.

[0098] Reference Fig.8D , the first opening OP1 may be formed, the first horizontal conductive layer 102 may be formed, and the lower sacrificial insulating layer 118 may be removed.

[0099] In the first isolation region MS (see Figure 2 ). The first opening OP1 may extend in the lower sacrificial insulating layer 118 and the interlayer insulating layer 120 (e.g., penetrate the lower sacrificial insulating layer 118 and the interlayer insulating layer 120), and may extend to the plate layer 101. When the sacrificial spacer layer is formed in the first opening OP1, by performing an etch-back process, the horizontal sacrificial layer 110 may be selectively removed, and a portion of the exposed first gate dielectric layer 145 may also be removed together. After the first horizontal conductive layer 102 is formed by depositing a conductive material in the region where the horizontal sacrificial layer 110 is removed, the sacrificial spacer layer may be removed from the first opening OP1.

[0100] The lower sacrificial insulating layer 118 may be selectively removed with respect to the interlayer insulating layer 120, the second horizontal conductive layer 104, and the first channel structure CH using, for example, a wet etching process. A tunnel portion TL may be formed in a region where the lower sacrificial insulating layer 118 is removed.

[0101] Reference Fig. 8E , the second lower gate electrode 130L2 , the first lower gate electrode 130L1 , the memory gate electrode 130M, and the second upper gate electrode 130U2 may be formed, and the first isolation region MS may be formed.

[0102] In this process, a first gate electrode (e.g., a second lower gate electrode 130L2, a first lower gate electrode 130L1, a memory gate electrode 130M, and a second upper gate electrode 130U2) extending around (e.g., surrounding) the first channel structure CH in a plan view may be formed. The first gate electrode may be formed by depositing a conductive material in the tunnel portion TL. Before forming the first gate electrode, Figure 3B As shown in FIG. 1 , the gate barrier layer 135 is first formed. In some example embodiments, a portion of the first gate dielectric layer 145 may be preferentially formed before forming the gate barrier layer 135. After forming the first gate electrode, the first isolation region MS may be formed by forming a gate isolation insulating layer 105 in the first opening OP1.

[0103] Reference Figure 8F , a horizontal insulating layer 150 may be formed, and an upper sacrificial insulating layer 178 and an upper interlayer insulating layer 179 may be formed on the horizontal insulating layer 150 .

[0104] A horizontal insulating layer 150 may be formed on the upper surface of the first channel structure CH and the upper surface of the first isolation region MS (e.g., the horizontal insulating layer 150 may be formed to cover or overlap the upper surface of the first channel structure CH and the upper surface of the first isolation region MS). Thereafter, a second cell region insulating layer 194 may be formed on the horizontal insulating layer 150.

[0105] The upper sacrificial insulating layer 178 may include a material different from that of the second cell region insulating layer 194 and the upper interlayer insulating layer 179. For example, the second cell region insulating layer 194 and the upper interlayer insulating layer 179 may include silicon oxide, and the upper sacrificial insulating layer 178 may include silicon nitride.

[0106] Reference Figure 8G , a second isolation region US can be formed.

[0107] First, in a position corresponding to the second isolation region US, a trench may be formed by partially removing the upper sacrificial insulating layer 178 and the upper interlayer insulating layer 179, the insulating material included in the upper isolation insulating layer 103 may be filled in the trench, and a planarization process such as chemical mechanical polishing (CMP) may be performed to remove the entire upper interlayer insulating layer 179. During the planarization process, the upper sacrificial insulating layer 178 may be used as a planarization stop layer. Therefore, second isolation regions US each including the upper isolation insulating layer 103 may be formed.

[0108] Reference Figure 8HAfter forming a hard mask layer HM on the upper sacrificial insulating layer 178 and forming the upper channel hole SHH, a second gate dielectric layer 165 and a spacer layer SP may be formed in the upper channel hole SHH (eg, on side and lower surfaces of the upper channel hole SHH).

[0109] can be connected to the second channel structure SH (see Figure 3A ) is formed in a position corresponding to the upper channel hole SHH. The upper channel hole SHH may extend in the upper sacrificial insulating layer 178 (e.g., penetrate the upper sacrificial insulating layer 178), and the second cell region insulating layer 194 may be exposed through a lower surface and / or a side surface of the upper channel hole SHH. In some example embodiments, the upper channel hole SHH may be formed such that the horizontal insulating layer 150 is exposed through a lower surface and / or a side surface of the upper channel hole SHH.

[0110] The second gate dielectric layer 165 and the spacer layer SP may be sequentially formed in the upper channel hole SHH. In this process, the spacer layer SP may also be formed on the lower surface and / or the side surface of the upper channel hole SHH. The spacer layer SP may be formed into the second channel layer 160 (see Figure 3A ). The spacer layer SP may include a semiconductor material such as polysilicon.

[0111] Reference Figure 8I , the upper channel hole SHH may further extend downward to expose the first channel pad 148 .

[0112] The upper channel hole SHH may extend downward by performing an etch-back process using the spacer layer SP. The upper channel hole SHH may penetrate the spacer layer SP, the second gate dielectric layer 165, the second unit region insulating layer 194, and the horizontal insulating layer 150, and may also penetrate the first pad oxide layer 149 of the first channel structure CH, and may partially recess the first channel pad 148. However, whether the first channel pad 148 is recessed and the recess depth of the first channel pad 148 may vary in example embodiments.

[0113] Reference Figure 8J , the oxide layer PO may be formed by oxidizing the semiconductor material layer exposed by the upper channel hole SHH.

[0114] The semiconductor material layer exposed by the upper channel hole SHH may include a spacer layer SP and a first channel pad 148. The oxide layer PO may include, for example, a silicon oxide layer.

[0115] Reference Figure 8K , portions of the horizontal insulating layer 150 exposed by the upper channel holes SHH may be removed.

[0116] The horizontal insulating layer 150 may be selectively removed by, for example, a wet etching process to form a pad tunnel portion PL. Therefore, the upper channel hole SHH may have a pad tunnel portion PL extending horizontally on the first channel pad 148. During this process, the oxide layer PO may prevent the semiconductor material layer (e.g., the spacer layer SP and the first channel pad 148) from being damaged by the etchant.

[0117] Reference Figure 8L , the oxide layer PO can be removed.

[0118] The oxide layer PO may be selectively removed by, for example, a wet etching process. In this process, the first pad oxide layer 149 and the second cell region insulating layer 194 may be partially removed together with the oxide layer PO. Thus, the height (vertical level) of the pad tunnel portion PL may be increased (raised). However, the degree of change in the height of the pad tunnel portion PL may vary in example embodiments.

[0119] Reference Figure 8M , a second channel layer 160 may be formed.

[0120] The second channel layer 160 may be formed by depositing a semiconductor material such as polysilicon on the first channel pad 148 exposed through the upper channel hole SHH (e.g., the second channel layer 160 may be formed to cover the first channel pad 148 exposed through the upper channel hole SHH or overlap the first channel pad 148 exposed through the upper channel hole SHH). A semiconductor material may also be formed on the spacer layer SP on the inner side surface of the upper channel hole SHH, and the spacer layer SP may form the second channel layer 160 together with the semiconductor material. The semiconductor material may fill the pad tunnel portion PL, and thus, the second channel layer 160 may have a pad portion PR. Subsequently, a heat treatment process may be performed so that the crystallinity of the second channel layer 160 may be improved.

[0121] Reference Figure 8N , a second channel buried insulating layer 167 and a second channel pad 168 may be formed.

[0122] A second channel buried insulating layer 167 may be formed in the upper channel hole SHH (to fill the remaining portion of the upper channel hole SHH). Thereafter, the second channel buried insulating layer 167 may be partially removed from the upper end, a second channel pad 168 may be formed on the second channel buried insulating layer 167, and a CMP process may be performed. In the CMP process, the upper sacrificial insulating layer 178 may be used as a CMP stop layer.

[0123] Reference Fig.8O , a second pad oxide layer 169 may be formed.

[0124] The second pad oxide layer 169 may be formed by oxidizing the exposed upper portions (eg, upper surfaces) of the second channel pad 168 and the second channel layer 160. The thickness of the second pad oxide layer 169 may be, for example, about 1000 Å. To about (For example, to ). Therefore, the second channel structure SH can be finally formed.

[0125] Reference Figure 8P , the second opening OP2 may be formed by removing the upper sacrificial insulating layer 178 .

[0126] The upper sacrificial insulating layer 178 may be removed by, for example, a wet etching process, and may be removed selectively with respect to the second isolation region US, the second channel structure SH, and the second cell region insulating layer 194. When the upper sacrificial insulating layer 178 is removed, the second pad oxide layer 169 may protect the second channel pad 168 and the second channel layer 160 from being damaged by the etchant.

[0127] Reference Figure 8Q , a preliminary gate barrier layer 135p and a first preliminary upper gate electrode 130U1p may be formed.

[0128] An initial gate barrier layer 135p may be formed on the side surface and the upper surface of the second channel structure SH exposed by the second opening OP2 and the side surface and the upper surface of the second isolation region US (for example, the initial gate barrier layer 135p may be formed to cover or overlap the side surface and the upper surface of the second channel structure SH exposed by the second opening OP2 and the side surface and the upper surface of the second isolation region US). The first upper gate electrode 130U1 may be deposited on the initial gate barrier layer 135p (see Figure 3A ) to form the first preliminary upper gate electrode 130U1p. The material included in the first upper gate electrode 130U1 may be a metal material. A void VD may be formed in the first preliminary upper gate electrode 130U1p. In example embodiments, the size and shape of the void VD may vary.

[0129] Reference Figure 8R , a gate barrier layer 135 and a first upper gate electrode 130U1 may be formed.

[0130] The gate barrier layer 135 and the first upper gate electrode 130U1 may be formed by partially removing the initial gate barrier layer 135p and the first initial upper gate electrode 130U1p from their upper portions using, for example, a wet etching process. Thus, the upper regions of the second isolation region US and the second channel structure SH may protrude above the upper surface of the first upper gate electrode 130U1 (protrude upward from the upper surface of the first upper gate electrode 130U1). A portion of the gate barrier layer 135 may be removed, and a portion of the gate barrier layer 135 may remain only on the side surface and the lower surface of the first upper gate electrode 130U1.

[0131] In example embodiments, since the first upper gate electrode 130U1 includes a metal material, unlike a case where a gate electrode is formed of a semiconductor material, a thermal treatment process may not be performed after deposition. Therefore, structural defects caused by the thermal treatment process may be prevented.

[0132] Reference Figure 8S , a third unit region insulating layer 196 may be formed.

[0133] A third cell region insulating layer 196 may be formed on the first upper gate electrode 130U1, the second isolation region US, and the second channel structure SH (e.g., the third cell region insulating layer 196 may be formed to cover the first upper gate electrode 130U1, the second isolation region US, and the second channel structure SH or to overlap with the first upper gate electrode 130U1, the second isolation region US, and the second channel structure SH). The third cell region insulating layer 196 may have a flat upper surface through a planarization process.

[0134] Afterwards, refer to Figure 2 , the semiconductor device 100 may be manufactured by forming the pillar 180 connected (eg, electrically connected) to the upper end of the second channel structure SH.

[0135] Fig. 9 is a diagram illustrating a data storage system including a semiconductor device according to example embodiments.

[0136] Reference Fig. 9 , the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid state drive device (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0137] The semiconductor device 1100 may be implemented as a nonvolatile memory device, such as in Figures 1 to 7 The NAND flash memory device described in the aforementioned example embodiment is taken as an example. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an example embodiment, the first structure 1100F may be disposed on one side of the second structure 1100S. The first structure 1100F may be implemented as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be implemented as a memory cell structure, the memory cell structure including a bit line BL, a common source line CSL, a word line WL disposed between the bit line BL and the common source line CSL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR.

[0138] In the second structure 1100S, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary in example embodiments.

[0139] In example embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The gate lower lines LL1 and LL2 may be configured as gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be configured as a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be configured as gate electrodes of the upper transistors UT1 and UT2, respectively.

[0140] In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series (e.g., electrically connected) to each other. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series (e.g., electrically connected) to each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation for erasing data stored in the memory cell transistor MCT using a GIDL phenomenon.

[0141] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through the first connection interconnection 1115 extending between the first structure 1100F and the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through the second connection interconnection 1125 extending between the first structure 1100F and the second structure 1100S.

[0142] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through the input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through the input / output connection line 1135 extending between the first structure 1100F and the second structure 1100S.

[0143] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface (I / F) 1230 . In example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0144] The processor 1210 may control the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a controller interface 1221 that processes communication with the semiconductor device 1100. Through the controller interface 1221, a control command for controlling the semiconductor device 1100, data to be written to the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100 may be transmitted. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command from an external host is received through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command. As used hereinafter, the terms “external / external configuration,” “external / external device,” “external / external power,” “external / external signal,” or “external” are intended to broadly refer to devices, circuits, blocks, modules, power, and / or signals that reside externally (e.g., outside the functional or physical boundaries) relative to a given circuit, block, module, system, or device.

[0145] Fig.10 is a perspective view illustrating a data storage system including a semiconductor device according to example embodiments.

[0146] Reference Fig.10 , the data storage system 2000 in the example embodiment may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected (e.g., electrically connected) to the controller 2002 through an interconnection pattern 2005 formed on the main board 2001.

[0147] The mainboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may be changed according to the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host according to one of the interfaces among the universal serial bus (USB), the peripheral component interconnect high speed (PCI-Express), the serial advanced technology attachment (SATA), and the M-Phy (UFS) for universal flash storage. In an example embodiment, the data storage system 2000 may be operated by power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0148] The controller 2002 may write data to the semiconductor package 2003 or may read data from the semiconductor package 2003 , and may improve the operation speed of the data storage system 2000 .

[0149] The DRAM 2004 may be configured as a buffer memory for alleviating a speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 may operate as a cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003. When the data storage system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0150] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 respectively disposed on the lower surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 located on the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100 (e.g., covering the semiconductor chip 2200 and the connection structure 2400 or overlapping the semiconductor chip 2200 and the connection structure 2400).

[0151] The package substrate 2100 may be configured as a printed circuit board including the package pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may be connected to Fig. 9 Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. Figures 1 to 7 The semiconductor device described in the aforementioned example embodiments.

[0152] In example embodiments, the connection structure 2400 may be configured as a bonding wire that electrically connects the input / output pad 2210 to the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. In example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through-hole electrode (TSV) instead of the connection structure 2400 of the bonding wire method.

[0153] In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate different from the mainboard 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other (e.g., electrically connected) through an interconnect formed on the interposer substrate.

[0154] Fig.11 is a cross-sectional view showing a semiconductor package according to an example embodiment, which shows a cross-sectional view taken along line III-III'. Fig.10 An example embodiment of a semiconductor package 2003 in FIG.

[0155] Reference Fig.11In the semiconductor package 2003, the package substrate 2100 may be implemented as a printed circuit substrate. The package substrate 2100 may include a package substrate body portion 2120, a package upper pad 2130 disposed on an upper surface of the package substrate body portion 2120, a lower pad 2125 disposed on a lower surface of the package substrate body portion 2120 or exposed through the lower surface of the package substrate body portion 2120, and an internal interconnection 2135 electrically connecting the package upper pad 2130 to the lower pad 2125 in the package substrate body portion 2120. The lower pad 2125 may be connected (e.g., electrically connected) to an interconnection pattern 2005 of a main board 2001 of the data storage system 2000 through a conductive connection portion 2800, such as Fig.10 as shown in .

[0156] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region having a peripheral interconnect 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 and an insulating junction 3230 extending in the gate stack structure 3210 (e.g., penetrating the gate stack structure 3210), and a bit line 3240 electrically connected to the channel structure 3220. As described above with reference to Figures 1 to 7 As described, in each of the semiconductor chips 2200, the first upper gate electrode 130U1 may include a metal material, and the gate barrier layer 135 may expose the upper surface of the first upper gate electrode 130U1, and may be located on the side surface and the lower surface of the first upper gate electrode 130U1 (for example, covering the side surface and the lower surface of the first upper gate electrode 130U1 or overlapping with the side surface and the lower surface of the first upper gate electrode 130U1).

[0157] Each of the semiconductor chips 2200 may include a through interconnect 3245, which is electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extends into the second structure 3200. The through interconnect 3245 may also be provided on the outside of the gate stack structure 3210, and may be provided to extend in the gate stack structure 3210 (e.g., penetrate the gate stack structure 3210). Each of the semiconductor chips 2200 may also include an input / output connection interconnect 3265 and an input / output pad 2210, which is electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extends into the second structure 3200, and the input / output pad 2210 is electrically connected to the input / output connection interconnect 3265.

[0158] According to the aforementioned example embodiments, by optimizing the material of the upper selection gate electrode, the arrangement of the gate barrier layer, and the structure of the second channel structure extending in (e.g., penetrating) the upper selection gate electrode, a semiconductor device with improved electrical properties and reliability and a data storage system including the semiconductor device can be provided.

[0159] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device comprising: A first semiconductor structure comprising a substrate, a circuit device on the substrate, and a circuit interconnection line on the circuit device; as well as a second semiconductor structure located on the first semiconductor structure, Wherein, the second semiconductor structure comprises: Lamellar; a gate electrode comprising a lower selection gate electrode, a memory gate electrode, and an upper selection gate electrode sequentially stacked on the plate layer, wherein the gate electrodes are spaced apart from each other in a first direction perpendicular to an upper surface of the plate layer; a first isolation region extending in the lower selection gate electrode and the memory gate electrode in a second direction perpendicular to the first direction; a second isolation region extending in the upper selection gate electrode in the second direction; a horizontal insulating layer located between the memory gate electrode and the upper selection gate electrode; a first channel structure extending in the lower selection gate electrode and the memory gate electrode in the first direction; second channel structures extending in the upper selection gate electrode and the horizontal insulating layer and electrically connected to the first channel structures, respectively; and a gate barrier layer located on the side surface and the lower surface of the upper selection gate electrode, Wherein, the upper selection gate electrode comprises a metal material.

2. The semiconductor device according to claim 1, wherein The gate barrier layer contacts a side surface of the second isolation region.

3. The semiconductor device according to claim 1, wherein Each of the second channel structures includes a second gate dielectric layer, a second channel layer, and a second channel buried insulating layer sequentially disposed on the upper selection gate electrode, and The second channel layer has a pad portion protruding toward the horizontal insulating layer.

4. The semiconductor device according to claim 3, wherein: Each of the second channel structures includes a second channel pad located on the second channel buried insulating layer and a pad oxide layer overlapping at least a portion of an upper surface of the second channel pad and a portion of an upper surface of the second channel layer in the first direction.

5. The semiconductor device according to claim 1, wherein The upper selection gate electrode includes a gap between the second channel structures and / or between the second channel structure and the second isolation region.

6. The semiconductor device according to claim 1, wherein The thickness of the upper selection gate electrode is to within the range.

7. The semiconductor device according to claim 1, wherein A side surface of the first isolation region has a region protruding toward the lower selection gate electrode and the memory gate electrode, and Wherein, a side surface of the second isolation region extends toward the board layer at a constant slope.

8. The semiconductor device according to claim 1, wherein The first isolation region and the second isolation region are spaced apart from each other in a plan view, and The first isolation region does not overlap with the second isolation region in the first direction.

9. The semiconductor device according to claim 1, wherein: An upper surface of each of the second isolation regions and an upper surface of each of the second channel structures are located at the same distance from the plate layer in the first direction.

10. The semiconductor device according to claim 1, wherein The upper selection gate electrode, the lower selection gate electrode, and the memory gate electrode include the same material.

11. The semiconductor device according to claim 1, in, A first offset channel structure among the second channel structures is offset by a first length relative to a first corresponding channel structure among the first channel structures in a third direction perpendicular to the first direction and the second direction, and A second offset channel structure among the second channel structures is offset by a second length in the third direction relative to a second corresponding channel structure among the first channel structures, and the second length is different from the first length.

12. The semiconductor device according to claim 1, wherein The first channel structure has a first diameter, and the second channel structure has a second diameter that is smaller than the first diameter.

13. A semiconductor device comprising: Lamellar; Gate electrodes are stacked on the plate layer in a first direction perpendicular to the upper surface of the plate layer and are spaced apart from each other, wherein the gate electrodes include a first gate electrode and a second gate electrode on the first gate electrode; a first channel structure extending in the first direction in the first gate electrode; and second channel structures extending in the second gate electrode in the first direction, wherein the second channel structures are electrically connected to the first channel structures, respectively, Wherein, the second gate electrode comprises a metal material, and Wherein, each of the second channel structures includes a second channel layer, a second gate dielectric layer between the second channel layer and the second gate electrode, a second channel buried insulating layer on the inner surface of the second channel layer, a second channel pad on the second channel buried insulating layer, and a second pad oxide layer on the second channel pad and the second channel layer.

14. The semiconductor device according to claim 13, wherein: The second gate dielectric layer contacts a side surface of the second pad oxide layer.

15. The semiconductor device according to claim 13, further comprising: A gate barrier layer is located on the side surface and the lower surface of the second gate electrode.

16. The semiconductor device according to claim 13, wherein: The second gate electrode has an inclined side surface, and Wherein, the width of the second gate electrode increases toward the plate layer.

17. The semiconductor device according to claim 13, in, Each of the first channel structures includes a first channel layer, a first gate dielectric layer between the first channel layer and the first gate electrode, a first channel buried insulating layer on an inner side surface of the first channel layer, and a first channel pad on the first channel buried insulating layer, and The second channel layer partially extends into the first channel pad and is electrically connected to the first channel pad.

18. The semiconductor device according to claim 13, further comprising: A pillar is located on each of the second channel structures, wherein the pillar extends into the second pad oxide layer and the second channel pad and is electrically connected to the second channel layer.

19. A data storage system comprising: A semiconductor memory device comprising a first semiconductor structure, a second semiconductor structure on the first semiconductor structure, and an input / output pad, wherein the first semiconductor structure comprises a circuit device and the input / output pad is electrically connected to the circuit device; and a controller electrically connected to the semiconductor memory device through the input / output pad and configured to control the semiconductor memory device, Wherein, the second semiconductor structure comprises: Lamellar; Gate electrodes are stacked on the plate layer in a first direction perpendicular to the upper surface of the plate layer and are spaced apart from each other, wherein the gate electrodes include a first gate electrode and a second gate electrode on the first gate electrode; a first channel structure extending in the first direction in the first gate electrode; and second channel structures extending in the second gate electrode in the first direction, wherein the second channel structures are electrically connected to the first channel structures, respectively, wherein the second gate electrode comprises a metal material, and Each of the second channel structures includes a second channel layer, a second gate dielectric layer between the second channel layer and the second gate electrode, a second channel pad on an inner surface of the second channel layer, and a second pad oxide layer on the second channel pad and the second channel layer.

20. The data storage system according to claim 19, wherein: The second gate electrode and the first gate electrode include different materials.

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