Display driver thread runtime scheduling

Abstract

Aspects presented herein relate to methods and apparatus for display processing, including devices, such as a CPU or DPU. The apparatus may monitor at least one display task associated with a set of display software threads. The device can also detect that the loading time of the at least one display task is smaller than a loading time threshold value or the panel frame rate is smaller than a frame rate threshold value. Further, the apparatus may obtain a first configuration for at least one thread of the set of display software threads and a second configuration for the at least one thread. The apparatus may also adjust execution of the at least one display task from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread.

Description

Technical Field

[0001] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for display processing. Background Art

[0002] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones (such as smart phones), embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, and each application may need to utilize the GPU during execution. The display processor is configured to convert digital information received from the CPU into analog values, and may issue commands to the display panel to display visual content. A device that provides content for visual presentation on a display may utilize a GPU and / or a display processor.

[0003] The GPU of a device may be configured to perform processes in a graphics processing pipeline. Additionally, a display processor or display processing unit (DPU) may be configured to perform processes for display processing. However, with the advent of wireless communications and smaller handheld devices, the need for improved graphics or display processing continues to increase. Summary of the invention

[0004] The following presents the summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify the key or important elements of all aspects, nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description presented later.

[0005] In one aspect of the present disclosure, a method, a computer-readable medium, and a device are provided. The device may be a display processing unit (DPU) or any device that can perform display processing. The device may monitor at least one display task associated with a display software thread set, wherein the display software thread set corresponds to a display feature set. The device may also detect that the load time of the at least one display task is less than a load time threshold or the panel frame rate is less than a frame rate threshold. Additionally, the device may adjust the panel frame rate based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold. The device may also adjust the frame buffer cache from a double data rate (DDR) memory to an on-chip cache during a display processing unit (DPU) control task handover, wherein the frame buffer cache is adjusted based on detecting that the load time of the at least one display task is less than the load time threshold or the panel frame rate is less than the frame rate threshold. In addition, the device may also detect the lack of update to the frame buffer cache based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold; and update the previous frame content back to the current frame based on the detection of the lack of update to the frame buffer cache. The device may also obtain a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold. The device may also adjust the execution of the at least one display task from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread.

[0006] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an example content generation system.

[0008] Figure 2 An example graphics processing unit (GPU) is illustrated.

[0009] Figure 3 An example display framework including a display processor and a display is illustrated.

[0010] Figure 4 is a diagram illustrating an example mask layer for display processing.

[0011] Figure 5 is a diagram illustrating an example display thread procedure for a display device in display processing.

[0012] Figure 6 is a diagram illustrating an example display thread procedure for a display device in display processing.

[0013] Figure 7 is a diagram illustrating an example display thread procedure for a display device in display processing.

[0014] Figure 8 is a communication flow diagram illustrating example communications between the CPU, display driver, and DPU.

[0015] Fig. 9 is a flow chart showing an example method of processing.

[0016] Fig.10 is a flow chart showing an example method of processing. DETAILED DESCRIPTION

[0017] Some aspects of display processing can utilize different types of display panels, such as video mode panels or command mode panels. When the display does not provide internal memory for display data, the video mode panel can be utilized, and when the display has access to the internal frame buffer memory, the command mode panel can be utilized. Certain types of video mode panels can support multiple refresh rates (e.g., refresh rates of 1Hz to 120Hz). This may cause the host chip that is controlling the video mode to experience a considerable amount of power consumption. For example, the host chip may need to refresh at a certain frame rate (e.g., 1 frame per second (FPS)). In some aspects, certain frame rates can be used for different types of content and different levels of light. As smart phones and user equipment (UE) become more advanced, any advantages of command mode panels may be reduced, and the disadvantages of command mode panels may become more obvious. For example, compared with video mode panels, command mode panels may be more expensive. In addition, if the power consumption advantage compared to video mode panels disappears, the command mode panel may become less ideal. In addition, the increased utilization of certain types of display panels may cause video mode panels to become more suitable. Therefore, compared to command mode panels, there are more and more reasons to utilize video mode panels. Some types of static displays can be designed to use a controller to cache images from memory. In some instances, if content update idle occurs, a certain buffer can be written to the controller to reduce the amount of access at the DDR memory. By doing so, compared with conventional frame refresh, the display driver software (SW) thread at the CPU can be greatly reduced when running. This may be due to reducing the amount of programming and / or reducing the amount of software event control. However, the thread running as a real-time thread in the CPU may still increase power consumption. The lightweight display thread can still be a CPU real-time task, which may keep the CPU awake and may increase the CPU power consumed. In one example, the display software thread may increase a large amount of CPU power utilization because they frequently run on the real-time thread in the CPU. As indicated herein, some video mode static display solutions may keep the CPU active when running software threads. By doing so, a large amount of power may be utilized at the CPU. In addition, these video mode static display solutions may experience a large amount of DDR memory access. Various aspects of the present disclosure can utilize methods to reduce the amount of power used for display driver software threads at the CPU. For example, aspects of the present disclosure may reduce the amount of power used at the CPU for a display driver software thread during a static display (i.e., video mode). For example, aspects of the present disclosure may provide software vendors with a solution for reducing the amount of power used at the CPU for a display driver software thread. Additionally, in some instances, aspects of the present disclosure may allow for a reduction in the amount of DDR memory accesses associated with a display driver software thread.In addition, the various aspects presented herein can schedule display software threads to solve the aforementioned power consumption problem. For example, the various aspects presented herein can schedule display software threads at CPU and digital signal processor (DSP) (e.g., low power DSP) for static display and other scenarios.

[0018] Various aspects of the system, device, computer program product and method will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether it is implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein may be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functions, or structures and functions other than or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of the claims.

[0019] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some potential benefits and advantages of various aspects of the present disclosure are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or objectives. On the contrary, various aspects of the present disclosure are intended to be widely applicable to different wireless technologies, system configurations, networks and transmission protocols, some of which are illustrated by way of example in the drawings and the description below. The specific embodiments and drawings merely illustrate the present disclosure rather than limit it, and the scope of the present disclosure is defined by the attached claims and their equivalent technical solutions.

[0020] Several aspects are presented with reference to various devices and methods. These devices and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0021] For example, an element or any part of an element or any combination of elements may be implemented as a "processing system" including one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on chips (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic devices, discrete hardware circuits, and other suitable hardware configured to perform the various functions described in this disclosure. One or more processors in a processing system may execute software. Software may be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, processes, functions, etc., whether expressed in software, firmware, middleware, microcode, hardware description languages, or other terms. The term "application" may refer to software. As described herein, one or more technologies may refer to an application, i.e., software, configured to perform one or more functions. In such examples, the application may be stored in a memory (e.g., an on-chip memory of a processor, a system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute an application. For example, an application may be described as including a code that, when executed by hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access the code from the memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in the present disclosure. In such examples, the components may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0022] Therefore, in one or more examples described herein, the described functions can be implemented in hardware, software, or any combination thereof. If implemented with software, the functions can be stored or encoded on a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media. Storage media can be any available media that can be accessed by a computer. As an example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage device, magnetic disk storage device, other magnetic storage devices, a combination of computer-readable media of the above types, or any other medium that can be used to store instructions or data structure forms of computer executable code that can be accessed by a computer.

[0023] In summary, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices to improve rendering of graphics content and / or reduce load on a processing unit (i.e., any processing unit, such as a GPU, configured to perform one or more of the techniques described herein). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0024] As used herein, instances of the term "content" may refer to "graphic content," "images," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphic content" may refer to content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphic content" may refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphic content" may refer to content produced by a graphics processing unit.

[0025] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphics content may be processed to become display content. For example, a graphics processing unit may output graphics content (such as a frame) to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphics content (such as one or more frames) from the buffer and perform one or more display processing techniques thereon to generate display content. For example, the display processing unit may be configured to perform synthesis on one or more rendering layers to generate a frame. For another example, the display processing unit may be configured to synthesize, mix or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling on the frame, such as zooming in or out. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been mixed together to form the frame, that is, the frame includes two or more layers, and the frame including two or more layers may be subsequently mixed.

[0026] Figure 11 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of a SOC. The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include several components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frame for presentation thereon. In further examples, the results of the graphics processing may not be displayed on the device, for example, the first display and the second display may not receive any frames for presentation thereon. Instead, the frames or graphics processing results may be passed to another device. In some aspects, this may be referred to as split rendering.

[0027] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor (such as display processor 127) to perform one or more display processing techniques on one or more frames generated by processing unit 120 before being presented by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head mounted display, or any other type of display device.

[0028] Memory external to the processing unit 120 and the content encoder / decoder 122, such as the system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to the external memory, such as the system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 via a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other via the bus or a different connection.

[0029] The content encoder / decoder 122 may be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphics content.

[0030] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, or optical storage media, or any other type of memory.

[0031] According to some examples, the internal memory 121 or the system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagation signal. However, the term "non-transitory" should not be interpreted to mean that the internal memory 121 or the system memory 124 is non-removable or that its contents are static. For example, the system memory 124 may be removed from the device 104 and moved to another device. For another example, the system memory 124 may not be removable from the device 104.

[0032] The processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into the motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0033] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into the mainboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0034] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving functions described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or positioning information. The transmitter 130 may be configured to perform any sending functions described herein with respect to the device 104. For example, the transmitter 130 may be configured to send information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving functions and / or sending functions described herein with respect to the device 104.

[0035] See again Figure 1 In certain aspects, the display processor 127 may include an adjustment component 198 configured to monitor at least one display task associated with a display software thread set, wherein the display software thread set corresponds to a display feature set. The adjustment component 198 may also be configured to detect that a load time of the at least one display task is less than a load time threshold or a panel frame rate is less than a frame rate threshold. The adjustment component 198 may also be configured to adjust the panel frame rate based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold. The adjustment component 198 may also be configured to adjust a frame buffer cache from a double data rate (DDR) memory to an on-chip cache during a display processing unit (DPU) control task handover, wherein the frame buffer cache is adjusted based on detecting that the load time of the at least one display task is less than the load time threshold or the panel frame rate is less than the frame rate threshold. The adjustment component 198 may also be configured to detect a lack of update to the frame buffer cache based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold; and to update the previous frame content back to the current frame based on the detection of the lack of update to the frame buffer cache. The adjustment component 198 may also be configured to obtain a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold. The adjustment component 198 may also be configured to adjust the execution of the at least one display task from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread. Although the following description may focus on display processing, the concepts described herein may be applicable to other similar processing techniques.

[0036] As described herein, a device such as device 104 may refer to any device, apparatus or system configured to perform one or more technologies described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation or a mainframe computer), a final product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smart watch, an augmented reality device or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an onboard computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more technologies described herein. The process herein may be described as being performed by a specific component (e.g., a GPU), but in further embodiments, other components (e.g., a CPU) consistent with the disclosed embodiments may be used to perform.

[0037] The GPU may process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU may process two types of data or data packets, such as context register packets and draw call data. The context register packet may be a collection of global state information, such as information about global registers, shaders, or constant data, which may adjust how the graphics context is to be processed. For example, the context register packet may include information about the color format. In some aspects of the context register packet, there may be a bit indicating which workload belongs to the context register. In addition, there may be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program may describe an operation, such as a color mode or color format. Therefore, the context register may define multiple states of the GPU.

[0038] The context state may be used to determine how a single processing unit (e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor) operates and / or in which mode the processing unit operates. To this end, the GPU may use context registers and programming data. In some aspects, the GPU may generate workloads (e.g., vertex or pixel workloads) in a pipeline based on context register definitions of a mode or state. Certain processing units (e.g., VFDs) may use these states to determine certain functions, such as how to assemble vertices. Since these modes or states may change, the GPU may need to change the corresponding context. Additionally, the workload corresponding to the mode or state may follow the changed mode or state.

[0039] Figure 2 An example GPU 200 is illustrated in accordance with one or more techniques of this disclosure. Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z pass engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering back end (RB) 236, a second level (L2) cache (UCHE) 238, and a system memory 240. Although Figure 2 GPU 200 is shown to include processing units 220 to 238, but GPU 200 may include multiple additional processing units. Additionally, processing units 220 to 238 are merely examples, and any combination or order of processing units may be used with a GPU according to the present disclosure. GPU 200 also includes command buffer 250, context register group 260, and context state 261.

[0040] like Figure 2 As shown, the GPU may parse the command buffer into context register packets (e.g., context register packets 260) and / or draw call data packets (e.g., draw call packets 212) using a CP (e.g., CP 210) or a hardware accelerator. Subsequently, the CP 210 may transmit the context register packets 260 or the draw call packets 212 to a processing unit or block in the GPU through a separate path. In addition, the command buffer 250 may alternate different states of context registers and draw calls. For example, the command buffer may be constructed in the following manner: context registers of context N, draw calls of context N, context registers of context N+1, and draw calls of context N+1.

[0041] The GPU can render images in a variety of different ways. In some instances, the GPU can use rendering and / or tile rendering to render images. In a tile rendering GPU, the image can be divided or split into different parts or tiles. After the image is divided, each part or tile can be rendered separately. The tile rendering GPU can divide the computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects, during the binning process, the image can be divided into different boxes or tiles. In some aspects, during the binning process, a visibility stream can be constructed in which visible primitives or drawing calls can be identified. In contrast to tile rendering, direct rendering does not divide the frame into smaller boxes or tiles. On the contrary, in direct rendering, the entire frame is rendered at once. Additionally, some types of GPUs may allow both tile rendering and direct rendering.

[0042] Figure 3is a block diagram 300 illustrating an example display framework including a processing unit 120 , a system memory 124 , a display processor 127 , and a display 131 , as may be identified in connection with device 104 .

[0043] The GPU may be included in a device that provides content for visual presentation on a display. For example, the processing unit 120 may include a GPU 310 configured to render graphics data for display on a computing device (e.g., device 104), which may be a computer workstation, a mobile phone, a smart phone or other smart device, an embedded system, a personal computer, a tablet computer, a video game console, etc. The operation of the GPU 310 may be controlled based on one or more graphics processing commands provided by the CPU 315. The CPU 315 may be configured to execute multiple applications concurrently. In some cases, each of the multiple applications executed concurrently may utilize the GPU 310 at the same time. The processing technology may be performed by outputting frames via the processing unit 120 over a physical or wireless communication channel.

[0044] System memory 124, which may be executed by processing unit 120, may include user space 320 and kernel space 325. User space 320 (sometimes referred to as "application space") may include software applications and / or application frameworks. For example, software applications may include operating systems, media applications, graphics applications, workspace applications, etc. The application framework may include a framework used by one or more software applications, such as libraries, services (e.g., display services, input services, etc.), application program interfaces (APIs), etc. Kernel space 325 may further include a display driver 330. Display driver 330 may be configured to control display processor 127. For example, display driver 330 may cause display processor 127 to synthesize a frame and send data of the frame to a display.

[0045] Display processor 127 includes display control block 335 and display interface 340. Display processor 127 may be configured to manipulate functions of display 131 (e.g., based on input received from display driver 330). Display control block 335 may be further configured to output image frames to display 131 via display interface 340. In some examples, display control block 335 may additionally or alternatively perform post-processing of image data provided based on execution of processing unit 120 on system memory 124.

[0046] The display interface 340 may be configured to cause the display 131 to display an image frame. The display interface 340 may output image data to the display 131 according to an interface protocol such as, for example, MIPIDSI (Mobile Industry Processor Interface, Display Serial Interface). That is, the display 131 may be configured according to the MIPIDSI standard. The MIPIDSI standard supports a video mode and a command mode. In an example where the display 131 operates in the video mode, the display processor 127 may continuously refresh the graphics content of the display 131. For example, the entire graphics content may be refreshed at each refresh cycle (e.g., line by line). In an example where the display 131 operates in the command mode, the display processor 127 may write the graphics content of the frame to the buffer 350.

[0047] In some such examples, display processor 127 may not continuously refresh the graphics content of display 131. Instead, display processor 127 may use vertical synchronization (Vsync) pulses to coordinate the rendering and consumption of graphics content at buffer 350. For example, when a Vsync pulse is generated, display processor 127 may output new graphics content to buffer 350. Thus, the generation of a Vsync pulse may indicate that current graphics content has been rendered at buffer 350.

[0048] Based on the display controller 345, the display client 355, and the buffer 350, the frame is displayed at the display 131. The display controller 345 may receive image data from the display interface 340 and store the received image data in the buffer 350. In some examples, the display controller 345 may output the image data stored in the buffer 350 to the display client 355. Thus, the buffer 350 may represent a local memory to the display 131. In some examples, the display controller 345 may output the image data received from the display interface 340 directly to the display client 355.

[0049] The display client 355 may be associated with a touch panel that senses interactions between a user and the display 131. When a user interacts with the display 131, one or more sensors in the touch panel may output a signal to the display controller 345 indicating which of the one or more sensors has sensor activity, the duration of the sensor activity, the pressure applied to the one or more sensors, etc. The display controller 345 may use the sensor output to determine the manner in which the user is interacting with the display 131. The display 131 may further be associated with / include other devices that operate in conjunction with the display client 355, such as a camera, a microphone, and / or a speaker.

[0050] Some processing techniques of device 104 may be performed through three stages (e.g., stage 1: rendering stage; stage 2: composition stage; and stage 3: display / delivery stage). However, other processing techniques may combine the composition stage and the display / delivery stage into a single stage, such that the processing technique may be performed based on a total of two stages (e.g., stage 1: rendering stage; and stage 2: composition / display / delivery stage). During the rendering stage, GPU 310 may process a content buffer based on the execution of an application that generates content on a pixel-by-pixel basis. During the composition and display stages, pixel elements may be assembled to form a frame that is delivered to a physical display panel / subsystem (e.g., display 131) that displays the frame.

[0051] Instructions (e.g., software instructions) executed by a CPU or instructions executed by a display processor may cause the CPU or display processor to search and / or generate a synthesis strategy for synthesizing a frame based on dynamic priorities and runtime statistics associated with one or more synthesis strategy groups. A frame to be displayed by a physical display device (such as a display panel) may include multiple layers. In addition, the synthesis of a frame may be based on combining multiple layers into a frame (e.g., based on a frame buffer). After combining multiple layers into a frame, the frame may be provided to a display panel for display on the display panel. The process of combining each layer in a plurality of layers into a frame may be referred to as synthesis, frame synthesis, synthesis procedure, synthesis process, etc.

[0052] The frame synthesis procedure or synthesis strategy may correspond to a technique for synthesizing different layers in a plurality of layers into a single frame. The plurality of layers may be stored in a double data rate (DDR) memory. Each layer in the plurality of layers may further correspond to a separate buffer. A synthesizer or hardware synthesizer (HWC) associated with a block or function may determine the input of each layer / buffer and execute the frame synthesis procedure to generate an output indicating a synthesized frame. That is, the input may be a layer, and the output may be a frame synthesis procedure for synthesizing a frame to be displayed on a display panel.

[0053] Some aspects of display processing may utilize different types of mask layers, such as shape mask layers. A mask layer is a layer that can represent a portion of a display or display panel. For example, an area of ​​a mask layer may correspond to an area of ​​a display, but the entire mask layer may depict a portion of the content that is actually displayed at the display or panel. For example, a mask layer may include a top portion and a bottom portion of a display area, but the middle portion of the mask layer may be empty. In some examples, there may be multiple mask layers to represent different portions of the display area. In addition, for certain portions of the display area, the content of different mask layers may overlap with each other. Thus, a mask layer may represent a portion of a display area that may or may not overlap with other mask layers.

[0054] Figure 44 is a diagram illustrating an example mask layer for display processing. More specifically, diagram 400 depicts one type of mask layer that can represent portions of a display panel. Figure 4 As shown, diagram 400 includes a mask layer 402, which includes a top region 410 and a bottom region 420. The top region 410 includes regions 411, 412, 413, and 414, and the bottom region 420 includes regions 421, 422, 423, and 424. Figure 4 As depicted, mask layer 402 may represent different areas displayed on the display panel.

[0055] Some types of displays may use a certain type of mask layer (e.g., a shape mask layer) to reshape the display frame. For example, the mask layer may reshape the display frame to provide a more optimized visual shape at the display panel (e.g., improved rounded corners, improved circular shape, improved rectangular shape, etc.). These types of mask layers (e.g., shape mask layers) may be processed by software (e.g., graphics processing unit (GPU) software or central processing unit (CPU) software), or by hardware (e.g., display processing unit (DPU) hardware). In addition, these mask layers may be processed by other specific types of hardware logic modules (e.g., modules in display driver integrated circuits (DDICs) or bridge chips). In some aspects, these types of mask layers (e.g., shape mask layers) may be based on a certain unit, such as a pixel. That is, the shape generation base unit of the shape mask layer may be a single pixel.

[0056] Some aspects of display processing can utilize different types of display panels, such as video mode panels or command mode panels. When the display does not provide internal memory for display data, the video mode panel can be utilized, and when the display has access to the internal frame buffer memory, the command mode panel can be utilized. Both the video mode panel and the command mode panel can be used with a high-speed interface and / or a low-power interface. Video mode panels (e.g., video mode low temperature polycrystalline oxide (LTPO) organic light emitting diode (OLED) panels) have been utilized in display processing for many years. Certain types of video mode panels (e.g., LTPO OLED panels) can support multiple refresh rates (e.g., refresh rates of 1 Hz to 120 Hz). This may cause the host chip that is controlling the video mode to experience a considerable amount of power consumption. For example, the host chip may need to refresh at a certain frame rate (e.g., a frame per second (FPS) of 1). In some aspects, certain frame rates can be used for different types of content and different levels of light. For example, a 1 Hz frame rate may be used for static content frames with high ambient light, a 15 Hz frame rate may be used for static content frames with low ambient light, and a 120 Hz frame rate may be used for user interface (UI) animations or games. 30 Hz, 60 Hz, or 90 Hz frame rates may be used for a number of different scenarios.

[0057] As smartphones and user equipment (UE) become more advanced, any advantages of command mode panels may be reduced, and the disadvantages of command mode panels may become more apparent. For example, command mode panels may be more expensive than video mode panels. In addition, command mode panels may include larger physical dimensions for display driver integrated circuits (DDICs). In addition, if the power consumption advantage compared to video mode panels disappears, command mode panels may become less ideal. In addition, the increased utilization of certain types of display panels (e.g., LTPO OLED display panels) may cause video mode panels to become more suitable. Therefore, there are more and more reasons to utilize video mode panels compared to command mode panels.

[0058] Some types of static displays (e.g., screen door effect (SDE) static displays) can be designed to use a controller (e.g., a last level cache controller (LLCC)) to cache images from a memory (e.g., a double data rate (DDR) memory). In some instances, if a content update idle occurs, a buffer (e.g., a buffer for GPU synthesis results) can be written to the controller (e.g., LLCC) to reduce the amount of access at the DDR memory. By doing so, the display driver software (SW) thread runtime at the CPU can be greatly reduced (e.g., from 3ms to 0.8ms) compared to conventional frame refreshes. This may be due to a reduced amount of programming (e.g., pipeline programming) and / or a reduced amount of software (SW) event control. However, a thread running as a real-time thread in the CPU may still increase power consumption (e.g., 10mA to 20mA of power consumption). The lightweight display thread can still be a CPU real-time task, which may keep the CPU awake and may increase the CPU power consumed. In one instance, the display software threads may increase a lot of CPU power utilization because they frequently run on real-time threads in the CPU.

[0059] Figure 5 5 is a diagram 500 illustrating an example of a display thread procedure for a display device. More specifically, diagram 500 depicts a display thread at a CPU during static display (ie, video mode). Figure 5 As shown, diagram 500 includes a display device 502, an on-chip cache 510 (e.g., an LLCC on-chip cache), a static display 512, a display driver software thread 520, a CPU 530 (e.g., a system on chip (SOC) CPU), a DPU and a display serial interface (DSI) 540, and a video mode panel 550 (e.g., a video mode LTPO OLED panel). Figure 5 A display device 502 is depicted that includes an on-chip cache 510 when operating a static display. In addition, Figure 5 The display driver software thread 520 is depicted running on the CPU 530 prior to processing at the DPU and DSI 540. After processing at the DPU and DSI 540, the video mode panel 550 may display the output. Figure 5 The display driver software thread 520 is illustrated as utilizing a significant amount of power at the CPU 530 during static display 512 (ie, video mode) at the display device 502 .

[0060] As indicated herein, some video mode static display solutions (e.g., video mode static display on-chip LLCC cache solutions) may keep the CPU active while running software threads. By doing so, a large amount of power may be utilized at the CPU. In addition, these video mode static display solutions may experience a large amount of DDR memory accesses. Based on the above, it may be beneficial to determine how to reduce the amount of power used for display driver software threads at the CPU. For example, it may be beneficial to determine how to reduce the amount of power used for display driver software threads at the CPU during static display (i.e., video mode). For example, for smartphone vendors, it may be beneficial to reduce the amount of power used for display driver software threads at the CPU. It may also be beneficial to reduce the amount of DDR memory accesses associated with display driver software threads.

[0061] Various aspects of the present disclosure may utilize methods to reduce the amount of power used for display driver software threads at the CPU. For example, various aspects of the present disclosure may reduce the amount of power used for display driver software threads at the CPU during static display (i.e., video mode). For example, various aspects of the present disclosure may provide software vendors with solutions for reducing the amount of power used for display driver software threads at the CPU. Additionally, in some instances, various aspects of the present disclosure may allow for reducing the amount of DDR memory accesses associated with display driver software threads. In addition, various aspects presented herein may schedule display software threads to address the aforementioned power consumption issues. For example, various aspects presented herein may schedule display software threads at CPUs and digital signal processors (DSPs) (e.g., low-power DSPs) for static display and other scenarios.

[0062] In some instances, aspects of the present disclosure can solve the aforementioned power consumption problem by utilizing a static display scheduling flow. For example, if the content of a frame is not updated within a threshold time period, a static display may have occurred. If a static display occurs, the last frame content may be written back to a controller (e.g., LLCC) or memory (e.g., DDR) as a frame cache. If this happens, the host (e.g., a display driver or controller) may switch the display panel to a lower frame rate or FPS. Next, the host (e.g., a display driver or controller) may switch control of the display software thread from the CPU to the DSP (e.g., a low-power DSP). This control switch may occur in multiple procedures. For example, during the boot of the host system, multiple groups (e.g., two groups) of display software driver threads may be established separately in the CPU and the DSP. During the runtime of the host system, the display subsystem control task may be handed over from the CPU thread group to the DSP thread group, or vice versa. Additionally, a static display (i.e., an idle timeout) may trigger a handover of the display subsystem control task from the CPU to the DSP.

[0063] In some aspects, if the frame content is updated or starts (restarts) updating, the host (e.g., display driver or controller) may schedule or switch control of the display software thread from the DSP to the CPU. In addition, the host (e.g., display driver or controller) may switch the frame rate of the display panel from the current frame rate (e.g., current FPS) to a higher frame rate (e.g., higher FPS). After switching the frame rate, the host (e.g., display driver or controller) may synthesize multiple frames or layers associated with the display software thread (e.g., newly updated frames or layers). That is, the host (e.g., display driver or controller) may synthesize multiple frames or layers based on the switching frame rate.

[0064] Figure 6 600 is a diagram illustrating an example of a display thread procedure for a display device. More specifically, diagram 600 depicts the display threads at the CPU and DSP during static display (ie, video mode). Figure 6 As shown, diagram 600 includes a display device 602, an on-chip cache 610 (e.g., an LLCC on-chip cache), a static display 612, a display driver software thread group 620, a CPU 630 (e.g., a system on chip (SOC) CPU), a DPU and DSI 640, a video mode panel 650 (e.g., a video mode LTPO OLED panel), a display driver software thread group 660, a digital signal processor (DSP) 670, and a DPU control handover 680. Figure 6 A display device 602 is depicted that includes an on-chip cache 610 when operating a static display 612. In addition, Figure 6 The display driver software thread group 620 is depicted as running on the CPU 630 and the display driver software thread group 660 is depicted as running on the DSP 670. There may be a DPU control handoff 680 for transferring or switching control of one or both of the thread groups (e.g., the display driver software thread group 620 and / or the display driver software thread group 660). For example, the DPU control handoff 680 may allow the display driver software thread group 620 to run on the DSP 670. Additionally, the DPU control handoff 680 may allow the display driver software thread group 660 to run on the CPU 630. The display driver software thread group 620 and the display driver software thread group 660 may then be passed to the DPU and DSI 640. After processing at the DPU and DSI 640, the video mode panel 650 may display the output. Thus, Figure 6It is illustrated that the display driver software thread group 620 and / or the display driver software thread group 660 may be scheduled to run on the CPU 630 and / or the DSP 670. By doing so, this may help reduce the amount of power at the CPU 630 during a static display 612 (i.e., video mode) at the display device 602.

[0065] Additionally, aspects of the present disclosure may schedule control of display driver software threads on the CPU and DSP via multiple measures. For example, aspects presented herein may schedule control of display driver software threads via a general display software thread cross-processor runtime scheduling policy. To this end, the host (e.g., a display driver or controller) may monitor the load time of the current display software thread task. For example, the host (e.g., a display driver or controller) may monitor the load time of the layer number, display feature / function number, and other tasks. If the load time of the current display software thread is low and the execution time specification is not strict (e.g., low frame rate or FPS), the host (e.g., a display driver or controller) may schedule or switch control of the display software thread from the CPU to the DSP, or vice versa. For example, the host (e.g., a display driver or controller) may schedule or switch control of the display software thread based on the following: (1) single-layer video playback without complex runtime tone mapping; (2) static display; or (3) low frame rate or FPS (e.g., 1 Hz or less). Display software control switching may be triggered by multiple events. For example, a touch event at the display device, a system performance lock at the display device, a system application specification change, or a display software task load time change may trigger a switch of display software control from the CPU to the DSP or from the DSP to the CPU. Furthermore, display software tasks may be dynamically scheduled at the CPU and DSP. Furthermore, execution of display software tasks may be divided between the CPU and the DSP.

[0066] Figure 7 700 is a diagram illustrating an example of a display thread procedure for a display device. More specifically, diagram 700 depicts the display threads at the CPU and DSP during static display (ie, video mode). Figure 7 As shown, diagram 700 includes display driver software tasks 710, runtime frame, layer and display function analysis 720, display driver software thread group 730, CPU 740 (e.g., system on chip (SOC) CPU), DPU control handoff 750, display driver software thread group 760, DSP 770, and DPU and DSI 780. Figure 7 A display driver software task 710 is depicted running for a display device having a static display. In addition, a runtime frame, layer, and display function analysis 720 may be performed on the display driver software task 710. In addition, Figure 7The display driver software thread group 730 is depicted as running on the CPU 740 and the display driver software thread group 760 is depicted as running on the DSP 770. There may be a DPU control handoff 750 for transferring or switching control of the display driver software thread group 730 or the display driver software thread group 760. For example, the DPU control handoff 750 may allow the display driver software thread group 730 to run on the DSP 770. Additionally, the DPU control handoff 750 may allow the display driver software thread group 760 to run on the CPU 740. The display driver software thread group 730 and the display driver software thread group 760 may then be passed to the DPU and DSI 780. After processing at the DPU and DSI 780, the video mode panel may display the output from the processing. Thus, Figure 7 It is illustrated that display driver software thread group 730 and / or display driver software thread group 760 may be scheduled to run on CPU 740 and / or DSP 770. By doing so, this may help reduce the amount of power consumed at CPU 740 during static display (i.e., video mode) at the display device.

[0067] Aspects of the present disclosure may include multiple benefits or advantages. For example, the various aspects presented herein may transfer or switch the control of the display driver software thread to the DSP to reduce the power consumption burden of the CPU. By doing so, the various aspects of the present disclosure can reduce the power consumption at the CPU without causing any performance loss. Additionally, the various aspects presented herein may execute the display driver software thread via multiple separate threads (e.g., two threads) at multiple devices (e.g., CPU and DSP). In addition, the various aspects presented herein may execute software for static display via the display software thread running on the DSP. In addition, the various aspects presented herein may execute DPU hardware programming via runtime scheduling at the CPU, DSP and / or other processors.

[0068] Figure 8 FIG. 8 is a communication flow diagram 800 showing a process according to one or more techniques of the present disclosure. Figure 8 As shown, diagram 800 includes example communications between a display driver 802 (e.g., software running on a CPU for controlling a DPU or a processor for controlling a DPU), a CPU 804 (or other central processing unit), and a DPU 806 (or other display processor) in accordance with one or more techniques of this disclosure.

[0069] At 810, the display driver 802 may monitor at least one display task associated with a display software thread set, wherein the display software thread set corresponds to a display feature set. When monitoring the at least one display task associated with the display software thread set, the display driver 802 may receive an indication of the at least one display task (e.g., receiving an indication 812 from the CPU 804). In some aspects, the display software thread set may include a first group of display software threads and a second group of display software threads, and monitoring the at least one display task may include monitoring the first group of display software threads and the second group of display software threads. The at least one display task may be associated with at least one of the following: a frame layer, a frame geometry, or a hardware display link. In addition, the at least one display task may correspond to at least one first task for one or more of the following: display hardware, a display processing unit (DPU), or a display serial interface (DSI).

[0070] At 820, the display driver 802 may detect that the loading time of the at least one display task is less than a loading time threshold or the panel frame rate is less than a frame rate threshold. The loading time threshold or the frame rate threshold may be associated with at least one of the following: (1) a single layer frame or a limited layer frame, (2) a static display, or (3) a frame per second (FPS) lower than a FPS threshold.

[0071] At 830, the display driver 802 may adjust the panel frame rate based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold. In the case where the load time of the at least one display task is less than the load time threshold, the panel frame rate may be reduced from a current frames per second (FPS) to a lower FPS, and in the case where the panel frame rate is less than the frame rate threshold, the panel frame rate may be increased from the current FPS to a higher FPS. In some examples, the lower FPS may be 1 Hz, 5 Hz, 10 Hz, 15 Hz, or 30 Hz, and the higher FPS may be 30 Hz, 60 Hz, 90 Hz, or 120 Hz.

[0072] At 840, the display driver 802 may adjust the frame buffer cache from the double data rate (DDR) memory to the on-chip cache during a display processing unit (DPU) controlled task handover, wherein the frame buffer cache is adjusted based on detecting that the load time of the at least one display task is less than the load time threshold or the panel frame rate is less than the frame rate threshold.

[0073] At 850, the display driver 802 may detect a lack of update to the frame buffer cache based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold. Additionally, at 850, the display driver 802 may write back a previous frame content update to the current frame based on detecting the lack of update to the frame buffer cache.

[0074] At 860, the display driver 802 may obtain a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold. In some instances, the first configuration of the at least one thread may be associated with a low-power processor or a digital signal processor (DSP), and obtaining the first configuration of the at least one thread may include receiving an indication to adjust the first configuration from a central processing unit (CPU) to the low-power processor or the DSP. Additionally, the first configuration of the at least one thread may be associated with a low-power processor or a digital signal processor (DSP), and the second configuration of the at least one thread may be associated with a central processing unit (CPU).

[0075] At 870, the display driver 802 may adjust the execution of the at least one display task from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread. In some instances, adjusting the execution of the at least one display task may include dividing the execution of the at least one display task between being associated with the first configuration for the at least one thread and being associated with the second configuration for the at least one thread. The execution of the at least one display task may be adjusted based on at least one of the following: a touch event, a system performance lock, one or more system application specifications, a change in the display software task load time, or a change in the panel frame rate. Additionally, the execution of the at least one display task may be dynamically scheduled for at least one of the following: a low power processor, a digital signal processor (DSP), or a central processing unit (CPU). After the execution of the at least one display task is adjusted from being associated with the first configuration to being associated with the second configuration, the display driver 802 may send an indication of the execution adjustment (e.g., sending an indication 872 to the DPU 806).

[0076] Fig. 9900 is a flowchart of an example method of display processing according to one or more techniques of the present disclosure. The method may be implemented by a display driver (e.g., software running on a CPU for controlling a DPU or a processor for controlling a DPU), a CPU (or other central processing unit), a DPU (or other display processor), a DDIC, an apparatus for display processing, a wireless communication device, and / or a combination thereof. Figures 1 to 8 The examples are performed using any device that can perform display processing.

[0077] At 902, the display driver may monitor at least one display task associated with a set of display software threads, wherein the set of display software threads corresponds to a set of display features, such as in conjunction with Figures 1 to 8 For example, Figure 8 As described in step 810, the display driver 802 may monitor at least one display task associated with a display software thread set, wherein the display software thread set corresponds to a display feature set. In addition, step 902 may be performed by Figure 1 , executed by the display processor 127 in. When monitoring the at least one display task associated with the display software thread set, the display driver may receive an indication of the at least one display task. In some aspects, the display software thread set may include a first group of display software threads and a second group of display software threads, and monitoring the at least one display task may include: monitoring the first group of display software threads and the second group of display software threads. The at least one display task may be associated with at least one of the following: a frame layer, a frame geometry, or a hardware display link. In addition, the at least one display task may correspond to at least one first task for one or more of the following: display hardware, a display processing unit (DPU), or a display serial interface (DSI).

[0078] At 904, the display driver may detect that the loading time of the at least one display task is less than a loading time threshold or the panel frame rate is less than a frame rate threshold, such as in combination with Figures 1 to 8 For example, Figure 8 As described in 820 of step 802, the display driver 802 may detect that the loading time of the at least one display task is less than the loading time threshold or the panel frame rate is less than the frame rate threshold. In addition, step 904 may be performed by Figure 1 The display processor 127 in the embodiment of the present invention is executed. The loading time threshold or the frame rate threshold may be associated with at least one of the following: (1) a single layer frame or a limited layer frame, (2) a static display, or (3) a frame per second (FPS) lower than a FPS threshold.

[0079] At 912, the display driver may obtain a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold, such as in combination with Figures 1 to 8 For example, Figure 8 As described in 860 of step 860, the display driver 802 may obtain a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold. In addition, step 912 may be performed by Figure 1 127 in the display processor 127. In some examples, the first configuration of the at least one thread may be associated with a low-power processor or a digital signal processor (DSP), and obtaining the first configuration of the at least one thread may include: receiving an indication to adjust the first configuration from a central processing unit (CPU) to the low-power processor or the DSP. In addition, the first configuration of the at least one thread may be associated with a low-power processor or a digital signal processor (DSP), and the second configuration of the at least one thread may be associated with a central processing unit (CPU).

[0080] At 914, the display driver may adjust the execution of the at least one display task from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread, such as in conjunction with Figures 1 to 8 For example, Figure 8 As described in 870 of , the display driver 802 may adjust the execution of the at least one display task from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread. In addition, step 914 may be performed by Figure 1 127 in the display processor 127. In some instances, adjusting the execution of the at least one display task may include dividing the execution of the at least one display task between being associated with the first configuration of the at least one thread and being associated with the second configuration of the at least one thread. The execution of the at least one display task may be adjusted based on at least one of the following: a touch event, a system performance lock, one or more system application specifications, a change in the display software task load time, or a change in the panel frame rate. Additionally, the execution of the at least one display task may be dynamically scheduled for at least one of the following: a low-power processor, a digital signal processor (DSP), or a central processing unit (CPU). After the execution of the at least one display task is adjusted from being associated with the first configuration to being associated with the second configuration, the display driver may send an indication of the execution adjustment.

[0081] Fig.10 1000 is a flowchart of an example method of display processing according to one or more techniques of the present disclosure. The method may be implemented by a display driver (e.g., software running on a CPU for controlling a DPU or a processor for controlling a DPU), a CPU (or other central processing unit), a DPU (or other display processor), a DDIC, an apparatus for display processing, a wireless communication device, and / or a combination thereof. Figures 1 to 8 The examples are performed using any device that can perform display processing.

[0082] At 1002, the display driver may monitor at least one display task associated with a set of display software threads, wherein the set of display software threads corresponds to a set of display features, such as in conjunction with Figures 1 to 8 For example, Figure 8 As described in 810 of , the display driver 802 may monitor at least one display task associated with a display software thread set, wherein the display software thread set corresponds to a display feature set. In addition, step 1002 may be performed by Figure 1 , executed by the display processor 127 in. When monitoring the at least one display task associated with the display software thread set, the display driver may receive an indication of the at least one display task. In some aspects, the display software thread set may include a first group of display software threads and a second group of display software threads, and monitoring the at least one display task may include: monitoring the first group of display software threads and the second group of display software threads. The at least one display task may be associated with at least one of the following: a frame layer, a frame geometry, or a hardware display link. In addition, the at least one display task may correspond to at least one first task for one or more of the following: display hardware, a display processing unit (DPU), or a display serial interface (DSI).

[0083] At 1004, the display driver may detect that the loading time of the at least one display task is less than a loading time threshold or the panel frame rate is less than a frame rate threshold, such as in combination with Figures 1 to 8 For example, Figure 8 As described in 820 of FIG. 8 , the display driver 802 may detect that the loading time of the at least one display task is less than the loading time threshold or the panel frame rate is less than the frame rate threshold. In addition, step 1004 may be performed by Figure 1 The display processor 127 in the embodiment of the present invention is executed. The loading time threshold or the frame rate threshold may be associated with at least one of the following: (1) a single layer frame or a limited layer frame, (2) a static display, or (3) a frame per second (FPS) lower than a FPS threshold.

[0084] At 1006, the display driver may adjust the panel frame rate based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold, such as in combination with Figures 1 to 8 For example, Figure 8 As described in 830 of step 1006, the display driver 802 may adjust the panel frame rate based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold. In addition, step 1006 may be performed by Figure 1 The display processor 127 in the embodiment of the present invention is executed. When the loading time of the at least one display task is less than the loading time threshold, the panel frame rate can be reduced from the current frames per second (FPS) to a lower FPS, and when the panel frame rate is less than the frame rate threshold, the panel frame rate can be increased from the current FPS to a higher FPS. In some examples, the lower FPS can be 1 Hz, 5 Hz, 10 Hz, 15 Hz, or 30 Hz, and the higher FPS can be 30 Hz, 60 Hz, 90 Hz, or 120 Hz.

[0085] At 1008, the display driver may adjust the frame buffer cache from the double data rate (DDR) memory to the on-chip cache during the display processing unit (DPU) control task handover, wherein the frame buffer cache is adjusted based on detecting that the load time of the at least one display task is less than the load time threshold or the panel frame rate is less than the frame rate threshold, such as in combination with Figures 1 to 8 For example, Figure 8 As described in 840 of , the display driver 802 may adjust the frame buffer cache from the double data rate (DDR) memory to the on-chip cache during the display processing unit (DPU) control task handover, wherein the frame buffer cache is adjusted based on detecting that the load time of the at least one display task is less than the load time threshold or the panel frame rate is less than the frame rate threshold. In addition, step 1008 may be performed by Figure 1 The display processor 127 in is executed.

[0086] At 1010, the display driver may detect a lack of update to the frame buffer cache based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold. Additionally, at 1010, the display driver may update the previous frame content back to the current frame based on detecting the lack of update to the frame buffer cache, such as in conjunction with Figures 1 to 8 For example, Figure 8As described in 850 of the embodiment, the display driver 802 may detect the lack of update to the frame buffer cache based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold; and update the previous frame content back to the current frame based on the lack of update to the frame buffer cache detected. In addition, step 1010 may be performed by Figure 1 The display processor 127 in is executed.

[0087] At 1012, the display driver may obtain a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold, such as in combination with Figures 1 to 8 For example, Figure 8 As described in 860 of step 1010, the display driver 802 may obtain a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold. In addition, step 1012 may be performed by Figure 1 127 in the display processor 127. In some examples, the first configuration of the at least one thread may be associated with a low-power processor or a digital signal processor (DSP), and obtaining the first configuration of the at least one thread may include: receiving an indication to adjust the first configuration from a central processing unit (CPU) to the low-power processor or the DSP. In addition, the first configuration of the at least one thread may be associated with a low-power processor or a digital signal processor (DSP), and the second configuration of the at least one thread may be associated with a central processing unit (CPU).

[0088] At 1014, the display driver may adjust the execution of the at least one display task from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread, such as in conjunction with Figures 1 to 8 For example, Figure 8 As described in 870 of , the display driver 802 may adjust the execution of the at least one display task from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread. In addition, step 1014 may be performed by Figure 1127 in the display processor 127. In some instances, adjusting the execution of the at least one display task may include dividing the execution of the at least one display task between being associated with the first configuration of the at least one thread and being associated with the second configuration of the at least one thread. The execution of the at least one display task may be adjusted based on at least one of the following: a touch event, a system performance lock, one or more system application specifications, a change in the display software task load time, or a change in the panel frame rate. Additionally, the execution of the at least one display task may be dynamically scheduled for at least one of the following: a low-power processor, a digital signal processor (DSP), or a central processing unit (CPU). After the execution of the at least one display task is adjusted from being associated with the first configuration to being associated with the second configuration, the display driver may send an indication of the execution adjustment.

[0089] In various configurations, a method or apparatus for display processing is provided. The apparatus may be a display driver (e.g., software running on a CPU for controlling a DPU or a processor for controlling a DPU), a CPU (or other central processing unit), a DPU (or other display processor), a DDIC, an apparatus for display processing, and / or some other processor that can perform display processing. In various aspects, the apparatus may be a display processor 127 within a device 104, or may be some other hardware within a device 104 or another device. The apparatus (e.g., a display processor 127) may include a component for monitoring at least one display task associated with a display software thread set, wherein the display software thread set corresponds to a display feature set. The apparatus (e.g., a display processor 127) may include a component for detecting that a load time of the at least one display task is less than a load time threshold or a panel frame rate is less than a frame rate threshold. The apparatus (e.g., a display processor 127) may include a component for obtaining a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold. The device (e.g., display processor 127) may include means for adjusting execution of the at least one display task from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread. The device (e.g., display processor 127) may include means for adjusting the panel frame rate based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold. The device (e.g., display processor 127) may include means for adjusting a frame buffer cache from a double data rate (DDR) memory to an on-chip cache during a display processing unit (DPU) control task handover, wherein the frame buffer cache is adjusted based on detecting that the load time of the at least one display task is less than the load time threshold or the panel frame rate is less than the frame rate threshold. The device (e.g., display processor 127) may include means for detecting a lack of update to the frame buffer cache based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold. The apparatus (eg, display processor 127) may include means for writing back a previous frame content update to a current frame based on detecting the lack of the update to the frame buffer cache.

[0090] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the display processing techniques described can be used by a display driver, a CPU, a DPU, a display processor, or some other processors that can perform display processing to implement the display driver thread runtime scheduling techniques described herein. Compared with other display processing techniques, this can also be implemented at a low cost. In addition, the display processing techniques of this article can improve or accelerate data processing or execution. In addition, the display processing techniques of this article can improve resource or data utilization and / or resource efficiency. Additionally, various aspects of the present disclosure can utilize display driver thread runtime scheduling techniques to improve memory bandwidth efficiency and / or increase processing speed at the CPU or DPU.

[0091] It should be understood that the specific order or hierarchy of the blocks in the disclosed process / flowchart is merely an illustration of an exemplary method. It should be understood that the specific order or hierarchy of the blocks in the process / flowchart may be rearranged based on design preferences. In addition, some blocks may be combined or omitted. The attached method claims provide the elements of each block in a sample order, but are not meant to be limited to the specific order or hierarchy provided.

[0092] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein unless otherwise specified, reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be interpreted as being preferred or having advantages over other aspects.

[0093] Unless specifically stated otherwise, the term “some” refers to one or more, and the term “or” may be interpreted as “and / or” if the context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, and may include multiple A, multiple B, or multiple C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, where any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of the various aspects described throughout the present disclosure that are known or will later be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. Words such as "module", "mechanism", "element", "device" cannot replace the word "component". Therefore, no claim element will be understood as a component plus function unless the element is explicitly stated using the phrase "component for..."

[0094] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored or sent as one or more instructions or codes on a computer-readable medium.

[0095] According to the present disclosure, the term "or" may be understood as "and / or" in the absence of context dictating otherwise. Additionally, while phrases such as "one or more" or "at least one" may have been used for some features disclosed herein but not for other features, features not using such language may be understood to have such implicit meanings in the absence of context dictating otherwise.

[0096] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on a computer-readable medium or sent on a computer-readable medium as one or more instructions or codes. Computer-readable media may include computer data storage media and communication media, including any media that facilitates the transfer of computer programs from one place to another. In this way, computer-readable media may generally correspond to (1) a non-transient tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this disclosure. As an example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices, magnetic disk storage devices, or other magnetic storage devices. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0097] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Thus, the term "processor" as used herein may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. Additionally, these techniques may be fully implemented in one or more circuits or logic elements.

[0098] The technology of the present disclosure can be implemented in a variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs) or IC groups (e.g., chipsets). Various components, modules, or units are described in the present disclosure to emphasize the functional aspects of devices configured to perform the disclosed technology, but they do not necessarily need to be implemented by different hardware units. On the contrary, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware. Therefore, the term "processor" as used herein can refer to any of the above structures or any other structure suitable for implementing the technology described herein. Similarly, these technologies can be fully implemented in one or more circuits or logic elements.

[0099] The following aspects are merely illustrative and may be combined with other aspects or teachings described herein without limitation.

[0100] Aspect 1 is a device for display processing, the device comprising a memory and at least one processor, the at least one processor being coupled to the memory and, at least in part based on information stored in the memory, the at least one processor being configured to: monitor at least one display task associated with a display software thread set, wherein the display software thread set corresponds to a display feature set; detect that a loading time of the at least one display task is less than a loading time threshold or a panel frame rate is less than a frame rate threshold; obtain a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold; and adjust the execution of the at least one display task from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread.

[0101] Aspect 2 is a device according to Aspect 1, wherein the at least one processor is further configured to: adjust the panel frame rate based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold.

[0102] Aspect 3 is a device according to any one of Aspects 1 and 2, wherein when the loading time of the at least one display task is less than the loading time threshold, the panel frame rate is reduced from a current frames per second (FPS) to a lower FPS, and wherein when the panel frame rate is less than the frame rate threshold, the panel frame rate is increased from the current FPS to a higher FPS.

[0103] Aspect 4 is a device according to any one of aspects 1 to 3, wherein the lower FPS is 1 Hz, 5 Hz, 10 Hz, 15 Hz or 30 Hz, and wherein the higher FPS is 30 Hz, 60 Hz, 90 Hz or 120 Hz.

[0104] Aspect 5 is an apparatus according to any one of Aspects 1 to 4, wherein, in order to adjust the execution of the at least one display task, the at least one processor is configured to: divide the execution of the at least one display task between the first configuration associated with the at least one thread and the second configuration associated with the at least one thread.

[0105] Aspect 6 is a device according to any one of Aspects 1 to 5, wherein the display software thread set includes a first group of display software threads and a second group of display software threads, and wherein in order to monitor the at least one display task, the at least one processor is configured to: monitor the first group of display software threads and the second group of display software threads.

[0106] Aspect 7 is an apparatus according to any one of Aspects 1 to 6, wherein the at least one processor is further configured to: during a display processing unit (DPU) control task handover, adjust the frame buffer cache from a double data rate (DDR) memory to an on-chip cache, wherein the frame buffer cache is adjusted based on detecting that the load time of the at least one display task is less than the load time threshold or the panel frame rate is less than the frame rate threshold.

[0107] Aspect 8 is an apparatus according to any one of Aspects 1 to 7, wherein the at least one processor is further configured to: detect a lack of update to a frame buffer cache based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold; and update a previous frame content and write it back to a current frame based on detecting the lack of update to the frame buffer cache.

[0108] Aspect 9 is a device according to any one of Aspects 1 to 8, wherein the loading time threshold or the frame rate threshold is associated with at least one of the following: (1) single layer frames or limited layer frames, (2) static display, or (3) frames per second (FPS) lower than an FPS threshold.

[0109] Aspect 10 is an apparatus according to any one of Aspects 1 to 9, wherein the first configuration of the at least one thread is associated with a low-power processor or a digital signal processor (DSP), and wherein in order to obtain the first configuration of the at least one thread, the at least one processor is configured to: receive an indication to adjust the first configuration from a central processing unit (CPU) to the low-power processor or the DSP.

[0110] Aspect 11 is a device according to any one of Aspects 1 to 10, wherein the execution of the at least one display task is adjusted based on at least one of the following: a touch event, a system performance lock, one or more system application specifications, a change in display software task loading time, or a change in the panel frame rate.

[0111] Aspect 12 is an apparatus according to any one of aspects 1 to 11, wherein the at least one display task is associated with at least one of: a frame layer, a frame geometry, or a hardware display link.

[0112] Aspect 13 is an apparatus according to any one of Aspects 1 to 12, wherein the first configuration of the at least one thread is associated with a low-power processor or a digital signal processor (DSP), and wherein the second configuration of the at least one thread is associated with a central processing unit (CPU).

[0113] Aspect 14 is a device according to any one of aspects 1 to 13, wherein the at least one display task corresponds to at least one first task for one or more of the following: display hardware, a display processing unit (DPU), or a display serial interface (DSI).

[0114] Aspect 15 is an apparatus according to any one of aspects 1 to 14, wherein the execution of the at least one display task is dynamically scheduled for at least one of the following: a low power processor, a digital signal processor (DSP), or a central processing unit (CPU).

[0115] Aspect 16 is an apparatus according to any one of aspects 1 to 15, wherein the apparatus is a wireless communication device, the apparatus further comprising at least one of an antenna or a transceiver coupled to the at least one processor.

[0116] Aspect 17 is a method for implementing the display processing of any one of aspects 1 to 16.

[0117] Aspect 18 is an apparatus for display processing, the apparatus comprising means for implementing any one of aspects 1 to 16.

[0118] Aspect 19 is a computer-readable medium (eg, non-transitory computer-readable medium) storing computer-executable code, which, when executed by at least one processor, causes the at least one processor to implement any one of aspects 1 to 16.

Claims

1. A device for display processing, the device comprising: Memory; and at least one processor coupled to the memory and based at least in part on the information stored in the memory, the at least one processor configured to: monitoring at least one display task associated with a set of display software threads, wherein the set of display software threads corresponds to a set of display features; detecting that the loading time of the at least one display task is less than a loading time threshold or the panel frame rate is less than a frame rate threshold; acquiring a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold; as well as Execution of the at least one display task is adjusted from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread.

2. The apparatus of claim 1 , wherein the at least one processor is further configured to: The panel frame rate is adjusted based on that the loading time of the at least one display task is less than the loading time threshold or the panel frame rate is less than the frame rate threshold.

3. An apparatus according to claim 2, wherein when the loading time of the at least one display task is less than the loading time threshold, the panel frame rate is reduced from a current frames per second (FPS) to a lower FPS, and wherein when the panel frame rate is less than the frame rate threshold, the panel frame rate is increased from the current FPS to a higher FPS.

4. The apparatus of claim 3, wherein the lower FPS is 1 Hz, 5 Hz, 10 Hz, 15 Hz, or 30 Hz, and wherein the higher FPS is 30 Hz, 60 Hz, 90 Hz, or 120 Hz.

5. The apparatus of claim 1 , wherein, in order to adjust the execution of the at least one display task, the at least one processor is configured to: divide the execution of the at least one display task between being associated with the first configuration of the at least one thread and being associated with the second configuration of the at least one thread.

6. The apparatus of claim 1 , wherein the set of display software threads comprises a first group of display software threads and a second group of display software threads, and wherein in order to monitor the at least one display task, the at least one processor is configured to: monitor the first group of display software threads and the second group of display software threads.

7. The apparatus of claim 1, wherein the at least one processor is further configured to: During a display processing unit (DPU) controlled task handover, a frame buffer cache is adjusted from a double data rate (DDR) memory to an on-chip cache, wherein the frame buffer cache is adjusted based on detecting that the load time of the at least one display task is less than the load time threshold or the panel frame rate is less than the frame rate threshold.

8. The apparatus of claim 1, wherein the at least one processor is further configured to: detecting a lack of updating a frame buffer cache based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold; and A previous frame content update is written back to a current frame based on detecting the lack of the update to the frame buffer cache.

9. The device of claim 1, wherein the loading time threshold or the frame rate threshold is associated with at least one of: (1) single layer frames or limited layer frames, (2) static display, or (3) frames per second (FPS) lower than an FPS threshold.

10. The apparatus of claim 1 , wherein the first configuration of the at least one thread is associated with a low-power processor or a digital signal processor (DSP), and wherein to obtain the first configuration of the at least one thread, the at least one processor is configured to: receive an indication to adjust the first configuration from a central processing unit (CPU) to the low-power processor or the DSP.

11. The apparatus of claim 1 , wherein the execution of the at least one display task is adjusted based on at least one of: a touch event, a system performance lock, one or more system application specifications, a change in display software task load time, or a change in the panel frame rate.

12. The device according to claim 1, wherein: The at least one display task is associated with at least one of: a frame layer, a frame geometry, or a hardware display link.

13. The apparatus of claim 1, wherein the first configuration of the at least one thread is associated with a low power processor or a digital signal processor (DSP), and wherein the second configuration of the at least one thread is associated with a central processing unit (CPU).

14. The device of claim 1, wherein the at least one display task corresponds to at least one first task for one or more of: display hardware, a display processing unit (DPU), or a display serial interface (DSI).

15. The apparatus of claim 1, further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein the apparatus is a wireless communication device, and wherein the execution of the at least one display task is dynamically scheduled for at least one of: a low power processor, a digital signal processor (DSP), or a central processing unit (CPU).

16. A method of display processing, the method comprising: monitoring at least one display task associated with a set of display software threads, wherein the set of display software threads corresponds to a set of display features; detecting that the loading time of the at least one display task is less than a loading time threshold or the panel frame rate is less than a frame rate threshold; acquiring a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold; as well as Execution of the at least one display task is adjusted from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread.

17. The method according to claim 16, further comprising: The panel frame rate is adjusted based on that the loading time of the at least one display task is less than the loading time threshold or the panel frame rate is less than the frame rate threshold.

18. A method according to claim 17, wherein when the loading time of the at least one display task is less than the loading time threshold, the panel frame rate is reduced from a current frames per second (FPS) to a lower FPS, and wherein when the panel frame rate is less than the frame rate threshold, the panel frame rate is increased from the current FPS to a higher FPS.

19. The method of claim 18, wherein the lower FPS is 1 Hz, 5 Hz, 10 Hz, 15 Hz, or 30 Hz, and wherein the higher FPS is 30 Hz, 60 Hz, 90 Hz, or 120 Hz.

20. The method of claim 16, wherein adjusting the execution of the at least one display task comprises: The execution of the at least one display task is divided between being associated with the first configuration of the at least one thread and being associated with the second configuration of the at least one thread.

21. The method of claim 16, wherein the set of display software threads comprises a first group of display software threads and a second group of display software threads, and wherein monitoring the at least one display task comprises: The first set of display software threads and the second set of display software threads are monitored.

22. The method according to claim 16, further comprising: During a display processing unit (DPU) controlled task handover, a frame buffer cache is adjusted from a double data rate (DDR) memory to an on-chip cache, wherein the frame buffer cache is adjusted based on detecting that the load time of the at least one display task is less than the load time threshold or the panel frame rate is less than the frame rate threshold.

23. The method according to claim 16, further comprising: detecting a lack of updating a frame buffer cache based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold; as well as A previous frame content update is written back to a current frame based on detecting the lack of the update to the frame buffer cache.

24. The method of claim 16, wherein the loading time threshold or the frame rate threshold is associated with at least one of: (1) single layer frames or limited layer frames, (2) static display, or (3) frames per second (FPS) lower than an FPS threshold.

25. The method of claim 16, wherein the first configuration of the at least one thread is associated with a low power processor or a digital signal processor (DSP), and wherein obtaining the first configuration of the at least one thread comprises: An indication is received to adjust the first configuration from a central processing unit (CPU) to the low power processor or the DSP.

26. The method of claim 16, wherein the execution of the at least one display task is adjusted based on at least one of: a touch event, a system performance lock, one or more system application specifications, a change in display software task load time, or a change in the panel frame rate.

27. The method of claim 16, wherein: The at least one display task is associated with at least one of: a frame layer, a frame geometry, or a hardware display link, and wherein the first configuration of the at least one thread is associated with a low-power processor or a digital signal processor (DSP), and wherein the second configuration of the at least one thread is associated with a central processing unit (CPU).

28. The method of claim 16, wherein the at least one display task corresponds to at least one first task for one or more of: display hardware, a display processing unit (DPU), or a display serial interface (DSI), and wherein the execution of the at least one display task is dynamically scheduled for at least one of: a low-power processor, a digital signal processor (DSP), or a central processing unit (CPU).

29. An apparatus for display processing, the apparatus comprising: means for monitoring at least one display task associated with a set of display software threads, wherein the set of display software threads corresponds to a set of display features; A component for detecting that a loading time of the at least one display task is less than a loading time threshold or a panel frame rate is less than a frame rate threshold; means for acquiring a first configuration for at least one thread in the set of display software threads and a second configuration for the at least one thread based on the load time of the at least one display task being less than the load time threshold or the panel frame rate being less than the frame rate threshold; and Means for adjusting execution of the at least one display task from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread.

30. A computer readable medium storing computer executable code for display processing, the code when executed by a processor causing the processor to: monitoring at least one display task associated with a set of display software threads, wherein the set of display software threads corresponds to a set of display features; detecting that the loading time of the at least one display task is less than a loading time threshold or the panel frame rate is less than a frame rate threshold; acquiring a first configuration for at least one thread in the display software thread set and a second configuration for the at least one thread based on the loading time of the at least one display task being less than the loading time threshold or the panel frame rate being less than the frame rate threshold; as well as Execution of the at least one display task is adjusted from being associated with the first configuration for the at least one thread to being associated with the second configuration for the at least one thread.

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