Erasing method for non-volatile memory with multiple levels

Abstract

A non-volatile memory system includes a plurality of non-volatile memory cells, the plurality of non-volatile memory cells being divided into three or more levels. The memory cell may be programmed, erased, and read. To achieve a uniform erase speed for the three or more levels, the erase process includes applying a voltage bias greater than the voltage bias applied to the control gates of the non-volatile memory cells in the one or more inner levels to the control gates of the non-volatile memory cells in the outer level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of, and is hereby incorporated by reference in its entirety, U.S. Non-Provisional Application No. 17 / 952,846, filed on September 26, 2022, entitled “ERASE METHOD FOR NON-VOLATILE MEMORY WITH MULTIPLETIERS,” for all purposes. Background Art

[0003] The present disclosure relates to non-volatile storage devices.

[0004] Semiconductor memories are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories may include non-volatile memories or volatile memories. Non-volatile memories allow information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Examples of non-volatile memories include flash memory (e.g., NAND-type and NOR-type flash memory).

[0005] Users of nonvolatile memory can program (i.e., write) data to nonvolatile memory and subsequently read the data back. For example, a digital camera can take a picture and store the picture in nonvolatile memory. Later, the user of the digital camera can view the picture by having the digital camera read the picture from the nonvolatile memory. Because users often rely on the data they store, it is important for users of nonvolatile memory to be able to reliably store data so that the data can be successfully read back. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Like numbered elements refer to common parts in different figures.

[0007] Figure 1 is a block diagram depicting one embodiment of a storage system.

[0008] Figure 2A is a block diagram of one embodiment of a memory die.

[0009] Figure 2B is a block diagram of one embodiment of an integrated memory component.

[0010] Figure 3A and Figure 3B Various embodiments of integrated memory components are depicted.

[0011] Figure 4is a perspective view of a portion of one embodiment of a monolithic three dimensional memory structure.

[0012] Figure 4A is a block diagram of one embodiment of a memory structure having two planes.

[0013] Figure 4B Depicted is a top view of a portion of one embodiment of a memory cell block.

[0014] Figure 4C A cross-sectional view of a portion of one embodiment of a memory cell block is depicted.

[0015] Figure 4D A cross-sectional view of a portion of one embodiment of a memory cell block is depicted.

[0016] Figure 4E A cross-sectional view of a portion of one embodiment of a memory cell block is depicted.

[0017] Figure 4F is a cross-sectional view of one embodiment of a vertical column of memory cells.

[0018] Figure 4G Depicted is a cross section of a memory cavity implementing a vertical NAND string.

[0019] Figure 4H Depicted is a cross section of a memory cavity implementing a vertical NAND string.

[0020] Fig. 4I Depicted is a cross section of a memory cavity implementing a vertical NAND string.

[0021] Figure 4J is a schematic diagram of multiple NAND strings.

[0022] Figure 4K A cross-sectional view of a portion of one embodiment of a memory cell block is depicted.

[0023] Figure 4L A cross-sectional view of a portion of one embodiment of a memory cell block is depicted.

[0024] Figure 5A The threshold voltage distribution is depicted.

[0025] Figure 5B The threshold voltage distribution is depicted.

[0026] Figure 5C The threshold voltage distribution is depicted.

[0027] Figure 5D The threshold voltage distribution is depicted.

[0028] Figure 5E The threshold voltage distribution is depicted.

[0029] Fig. 5F The threshold voltage distribution is depicted.

[0030] Figure 6 is a flow chart describing one embodiment of a process for programming non-volatile memory.

[0031] Figure 7 Depicted is the erasure of a NAND string.

[0032] Figure 8 is a flow chart describing one embodiment of a process for erasing.

[0033] Fig. 9A Three levels of memory holes are depicted.

[0034] Fig. 9B Five levels of memory holes are depicted.

[0035] Fig.10 is a flow chart describing one embodiment of a process for simultaneously erasing three or more levels, the process including compensating for inherent erasing speed differences between the levels to achieve uniform erasing speed for the three or more levels.

[0036] Fig.11 is a flow chart describing one embodiment of a process for simultaneously erasing three or more levels, the process including compensating for inherent erasing speed differences between the levels to achieve uniform erasing speed for the three or more levels.

[0037] Fig.12 is a flow chart describing one embodiment of a process for simultaneously erasing three or more levels, the process including compensating for inherent erasing speed differences between the levels to achieve uniform erasing speed for the three or more levels.

[0038] Fig.13A A graph of word line voltage versus word line position is depicted.

[0039] Fig. 13B Three levels of memory holes are depicted.

[0040] Fig. 13C A graph of word line voltage versus word line position is depicted.

[0041] Fig.14A A graph of word line voltage versus word line position is depicted.

[0042] Fig. 14B Three levels of memory holes are depicted.

[0043] Fig. 14C A graph of word line voltage versus word line position is depicted.

[0044] Fig.15A A graph of word line voltage versus word line position is depicted.

[0045] Fig. 15B Five levels of memory holes are depicted.

[0046] Fig. 15C A graph of word line voltage versus word line position is depicted.

[0047] Fig.16A A graph of word line voltage versus word line position is depicted.

[0048] Fig. 16B Five levels of memory holes are depicted.

[0049] Fig. 16C A graph of word line voltage versus word line position is depicted. DETAILED DESCRIPTION

[0050] Because there are limitations on the maximum height / depth that can be reliably etched, some non-volatile memories are manufactured in multiple levels. However, it has been determined that in systems with three or more levels, some levels erase at a slower rate than other levels, which can lead to issues with device reliability. Therefore, in order to achieve uniform erase speeds for three or more levels, the erase process includes applying a voltage bias to the control gates of non-volatile memory cells in the outer levels that is greater than the voltage bias applied to the control gates of non-volatile memory cells in one or more inner levels. More details are provided below.

[0051] Figure 1 1 is a block diagram of one embodiment of a non-volatile storage system 100 that implements the proposed technology described herein. In one embodiment, the non-volatile storage system 100 is a solid state drive ("SSD"). The non-volatile storage system 100 may also be a memory card, a USB drive, or other types of storage systems. The proposed technology is not limited to any one type of storage system. The storage system 100 is connected to a host 102, which may be a computer, a server, an electronic device (e.g., a smart phone, a tablet computer, or other mobile device), an appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from the storage system 100, but connected to the storage system. In other embodiments, the storage system 100 is embedded in the host 102.

[0052] Figure 1The components of the memory system 100 depicted in FIG. 1 are electrical circuits. The memory system 100 includes a memory controller 120 connected to a non-volatile memory 130 and a local high-speed volatile memory 140 (e.g., DRAM). The memory controller 120 uses the local high-speed volatile memory 140 to perform certain functions. For example, the local high-speed volatile memory 140 stores logic in a physical address translation table ("L2P table").

[0053] The memory controller 120 includes a host interface 152 connected to and communicating with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVMe) through PCI Express (PCIe). Other interfaces such as SCSI, SATA, etc. may also be used. The host interface 152 is also connected to a network on chip (NOC) 154. NOC is a communication subsystem on an integrated circuit. NOC can span synchronous clock domains and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication, and brings significant improvements compared to conventional bus and crossbar switch interconnections. Compared with other designs, NOC improves the scalability of the system on chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Since all links in the NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of the integrated subsystem continues to increase, compared with previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges), NOC provides enhanced performance (such as throughput) and scalability. In other embodiments, NOC 154 may be replaced by a bus. Processor 156, ECC engine 158, memory interface 160, and DRAM controller 164 are connected to and communicate with NOC 154. DRAM controller 164 is used to operate and communicate with local high-speed volatile memory 140 (e.g., DRAM). In other embodiments, local high-speed volatile memory 140 may be SRAM or another type of volatile memory.

[0054] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding according to the implemented ECC technology. In one embodiment, the ECC engine 158 is an electrical circuit programmed by software. For example, the ECC engine 158 can be a programmable processor. In other embodiments, the ECC engine 158 is a customized dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 158 are implemented by the processor 156.

[0055] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a customized dedicated hardware circuit without any software. Processor 156 also implements a conversion module, either as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the storage system using a physical address associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the storage system is idle to store data between the locations of one or more memory dies as desired. In order to implement such a system, memory controller 120 (e.g., conversion module) performs address conversion between the logical address used by the host and the physical address used by the memory die. An example implementation is to maintain a table (i.e., the above-mentioned L2P table) that identifies the current conversion between the logical address and the physical address. The entries in the L2P table may include identification of the logical address and the corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word "table", they need not be tables in the literal sense. Rather, logical address to physical address tables (or L2P tables) may be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables. In this case, the entire set of L2P tables is stored in the memory die 130, and a subset of the L2P tables is cached (L2P cache) in the local high-speed volatile memory 140.

[0056] The memory interface 160 communicates with the non-volatile memory 130. In one embodiment, the memory interface provides a switch mode interface. Other interfaces may also be used. In some example implementations, the memory interface 160 (or another portion of the controller 120) implements a scheduler and buffer for transmitting data to and receiving data from one or more memory dies.

[0057] In one embodiment, non-volatile memory 130 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of a memory die 200 including non-volatile memory 130. Each of the one or more memory dies of non-volatile memory 130 may be implemented as Figure 2A A memory die 200 is provided. Figure 2AThe components depicted in are electrical circuits. The memory die 200 includes a memory array 202, which may include non-volatile memory cells, as described in more detail below. The array terminal lines of the memory array 202 include individual word line layers organized into rows, and individual bit line layers organized into columns. However, other orientations may also be implemented. The memory die 200 includes a row control circuit 220, the output end 208 of which is connected to the corresponding word lines of the memory array 202. The row control circuit 220 receives a set of M row address signals and one or more various control signals from the system control logic circuit 206, and may generally include circuits such as a row decoder 222, an array terminal driver 224, and a block selection circuit 226 for both read operations and write (programming) operations. The row control circuit 220 may also include a read / write circuit. The memory die 200 also includes a column control circuit 210, which includes a sense amplifier 230, the input end / output end 206 of which is connected to the corresponding bit line of the memory array 202. Although only a single block is shown for array 202, the memory die may include multiple arrays that may be individually accessed. Column control circuitry 210 receives a set of N column address signals and one or more various control signals from system control logic 260, and may generally include circuits such as column decoders 212, array terminal receivers or driver circuits 214, and read / write circuits and I / O multiplexers.

[0058] The system control logic 260 receives data and commands from the memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (which includes one or more electrical circuits) includes a state machine 262 that provides die-level control of memory operations. In one embodiment, the state machine 262 can be programmed by software. In other embodiments, the state machine 262 does not use software and is completely implemented in hardware (e.g., electrical circuits). In another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor that is on or outside the memory chip. The system control logic 262 may also include a power control module 264 that controls the power and voltage supplied to the rows and columns of the memory structure 202 during memory operation, and may include a charge pump and regulator circuit for generating a regulated voltage. The system control logic 262 includes a storage device 366 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating the memory array 202.

[0059] Commands and data are transferred between the memory controller 120 and the memory die 200 via a memory controller interface 268 (also referred to as a "communication interface"). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120. Examples of the memory controller interface 268 include a switch mode interface and an open NAND flash interface (ONFI). Other I / O interfaces may also be used.

[0060] In some embodiments, all elements of memory die 200, including system control logic 260, may be formed as part of a single die. In other embodiments, some or all of system control logic 260 may be formed on different dies.

[0061] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed above a single substrate (such as a wafer). The memory structure may include any type of non-volatile memory formed integrally in one or more physical levels of memory cells having active regions disposed above a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0062] In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (eg, NOR-type flash memory) may also be used.

[0063] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required to implement the claimed new embodiments presented herein. Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin transfer torque MRAM, spin orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of suitable technologies for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0064] An example of a ReRAM crosspoint memory includes a reversible resistance switching element arranged in a crosspoint array accessed by an X line and a Y line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization unit. Based on the physical relocation of ions within a solid electrolyte, the conductive bridge memory element may be used as a state change element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of a solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold of the conductive bridge memory cell to decrease. Therefore, the conductive bridge memory element may have a wide range of programming thresholds over the entire temperature range.

[0065] Another example is a magnetoresistive random access memory (MRAM) that stores data via magnetic storage elements. These elements are formed by two ferromagnetic layers separated by a thin insulating layer, each of which can maintain magnetization. One of the two layers is a permanent magnet group set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of the storage memory by the external magnetic field. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cells, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated. MRAM-based memory implementations will be discussed in more detail below.

[0066] Phase change memory (PCM) takes advantage of the unique properties of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by changing the coordination state of germanium atoms using only laser pulses (or light pulses from another source). Therefore, the programming dose is a laser pulse. The memory cell can be disabled by preventing the memory cell from receiving light. In other PCM embodiments, the memory cell is programmed by a current pulse. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage light or other waves. These memory elements within each selectable memory cell or bit may include additional series elements as selectors, such as a bidirectional threshold switch or a metal insulator substrate.

[0067] Those of ordinary skill in the art will recognize that the technology described herein is not limited to a single particular memory structure, memory configuration, or material composition, but encompasses many related memory structures within the spirit and scope of the technology as described herein and as understood by those of ordinary skill in the art.

[0068] Figure 2A The components of the invention can be grouped into two parts: (1) memory structure 202 and (2) peripheral circuits, which include Figure 2A 202; however, this reduces the area of ​​the memory die available for peripheral circuitry. This can place quite severe constraints on these elements of the peripheral circuitry. For example, the need to fit sense amplifier circuitry within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic component 260, the reduction in available area can limit the available functionality that can be implemented on the chip. Therefore, in the design of the memory die of the memory system 100, a fundamental trade-off needs to be made between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuitry.

[0069] Another area where the memory structure 202 and the peripheral circuits often conflict is in the processing involved in forming these areas, as these areas often involve different processing technologies and the trade-offs when implementing different technologies on a single die. For example, when the memory structure 202 is a NAND flash memory, this is an NMOS structure, while the peripheral circuits are often CMOS based. For example, elements such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic component 260 often employ CMOS devices. The processing operations used to manufacture a CMOS die will differ in many ways from processing operations optimized for NMOS flash memory, NAND memory, or other memory cell technologies.

[0070] To improve these limitations, the embodiments described below can Figure 2AThe components of the memory structure 202 can be separated into separately formed dies, and then these dies are bonded together. More specifically, the memory structure 202 can be formed on one die (referred to as the memory die), and some or all of the peripheral circuit elements (including one or more control circuits) can be formed on a separate die (referred to as the control die). For example, the memory die can be formed only by memory elements, such as a memory cell array of a flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or other memory types. Some or all of the peripheral circuits (even including elements such as decoders and sense amplifiers) can then be moved to a separate control die. This allows each die in the memory die to be optimized individually according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS elements that have now been moved to a control die that can be optimized for CMOS processing. This provides more room for peripheral elements, and if the peripheral elements are confined to the edge of the same die that houses the memory cell array, additional capabilities that may not be easily combined can now be combined. The two dies can then be bonded together in a bonded multi-die memory circuit where the array on one die is connected to the peripheral components on the other die. For example, although the following will focus on a bonded memory circuit with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one control die.

[0071] Figure 2B Shows Figure 2A An alternative arrangement to the arrangement of may be achieved using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of an integrated memory component 207 is depicted. One or more integrated memory components 207 may be used to implement the non-volatile memory 130 of the memory system 100. The integrated memory component 207 includes two types of semiconductor dies (or more succinctly, "dies"). The memory die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to connect to the memory structure 202 in the memory die 201. In some embodiments, the memory die 201 and the control die 211 are bonded together.

[0072] Figure 2B An example of peripheral circuitry is shown, including control circuits formed in a peripheral circuit or control die 211 coupled to a memory structure 202 formed in a memory die 201. Common components are shown in a similar manner to Figure 2ASystem control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of column control circuitry 210 and all or a portion of row control circuitry 220 are located on memory die 201. In some embodiments, some of the circuits in system control logic 260 are located on memory die 201.

[0073] The system control logic 260, row control circuit 220, and column control circuit 210 may be formed by conventional processes (e.g., CMOS processes), so that adding elements and functions more commonly found on the memory controller 120, such as ECC, may require few or no additional process steps (i.e., the same process steps used to manufacture the controller 120 may also be used to manufacture the system control logic 260, row control circuit 220, and column control circuit 210). Therefore, while moving such circuits from a die (such as the memory 2 die 201) may reduce the number of steps required to manufacture such a die, adding such circuits to a die (such as the control die 211) may not require many additional process steps. Since some or all of the control circuits 260, 210, 220 are implemented using CMOS technology, the control die 211 may also be referred to as a CMOS die.

[0074] Figure 2B Column control circuitry 210 including sense amplifier 230 on control die 211 is shown coupled to memory structure 202 on memory die 201 via electrical path 206. For example, electrical path 206 may provide electrical connections between column decoder 212 and driver circuit 214 and bit lines of memory structure 202. Electrical paths may extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads of memory die 201 that are connected to bit lines of memory structure 202. Each bit line of memory structure 202 may have a corresponding electrical path in electrical path 306 connected to column control circuitry 210, including a pair of bond pads. Similarly, row control circuitry 220 (including row decoder 222, array driver 224, and block selector 226) is coupled to memory structure 202 via electrical path 208. Each of the electrical paths 208 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between the control die 211 and the memory die 201 .

[0075] For purposes of this document, the phrase "control circuitry" or "one or more control circuits" may include any one or any combination of memory controller 120, state machine 262, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, a microcontroller, a microprocessor, and / or other similarly functional circuitry. The control circuitry may include hardware alone or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuitry may include a processor, FGA, ASIC, integrated circuit, or other type of circuitry.

[0076] In some embodiments, there is more than one control die 211 and more than one memory die 201 in the integrated memory component 207. In some embodiments, the integrated memory component 207 includes a stack of multiple control dies 211 and multiple memory dies 201. Figure 3A A side view of an embodiment of an integrated memory component 207 (e.g., including a stack of control dies 211 and memory dies 201) stacked on a substrate 271 is depicted. The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are more than three memory dies 201 and more than three control dies 211.

[0077] Each control die 211 is attached (e.g., bonded) to at least one of the memory dies 201. Some of the bonding pads 282 / 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which can be formed of epoxy or other resins or polymers. The solid layer 280 protects the electrical connection between the dies 201, 211 and further secures the dies together. Various materials can be used as the solid layer 280, but in an embodiment, the material can be Hysol epoxy resin from Henkel Corporation (the company has offices in California, USA).

[0078] The integrated memory components 207 may be stacked, for example, in a stepped offset manner so that the bonding pads at each level are uncovered and accessible from above. Wire bonds 270 connected to the bonding pads connect the control die 211 to the substrate 271. Multiple such wire bonds may be formed across the width of each control die 211 (i.e., formed to Figure 3A ).

[0079] Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory die 201. Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211. TSVs 276, 278 may be formed before, during, or after the formation of integrated circuits in the semiconductor die 201, 211. The TSVs may be formed by etching holes through the wafer. These holes may then be lined with a barrier that prevents metal diffusion. The barrier layer may in turn be lined with a seed layer, and the seed layer may be plated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.

[0080] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory component 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory component 207 is to be used as an LGA package. Solder balls 272 may form part of the interface between integrated memory component 207 and memory controller 120.

[0081] Figure 3B A side view of another embodiment of an integrated memory component 207 stacked on a substrate 271 is depicted. Figure 3B The integrated memory component 207 has three control dies 211 and three memory dies 201. In some embodiments, there are far more than three memory dies 201 and far more than three control dies 211. In this example, each control die 211 is bonded to at least one memory die 201. Optionally, a control die 211 can be bonded to two or more memory dies 201.

[0082] Some of the bonding pads 282, 284 are depicted. There may be more bonding pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed of epoxy or other resins or polymers. Figure 3A Compared to the example in Figure 3B The integrated memory component 207 in FIG. 201 has no step offset. Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory die 201. Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211.

[0083] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted in the case where integrated memory assembly 207 is to be used as an LGA package.

[0084] As briefly discussed above, the control die 211 and the memory die 201 can be bonded together. The bonding pads on each die 201, 211 can be used to bond the two dies together. In some embodiments, in the so-called Cu-Cu bonding process, the bonding pads are directly bonded to each other without solder or other additional materials. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment, which is substantially free of environmental particles, otherwise the environmental particles may be deposited on the bonding pads and prevent close bonding. Under such properly controlled conditions, the bonding pads are aligned and pressed against each other to form mutual bonding based on surface tension. This bonding can be formed at room temperature, although heat can also be applied. In the embodiment using Cu-Cu bonding, the bonding pads can be about 5 μm square and spaced apart from each other at a spacing of 5 μm to 5 μm. Although the process is referred to as Cu-Cu bonding in this article, the term may also be applied to the case where the bonding pads are formed by materials other than copper.

[0085] When the area of ​​the bonding pad is small, it may be difficult to bond the semiconductor die together. By providing a film layer on the surface of the semiconductor die including the bonding pad, the size and spacing of the bonding pad can be further reduced. The film layer is disposed around the bonding pad. When the die are put together, the bonding pads can be bonded to each other, and the film layers on the individual dies can be bonded to each other. This bonding technique may be referred to as hybrid bonding. In an embodiment using hybrid bonding, the bonding pads may be approximately 5 μm square and spaced apart from each other at a spacing of 1 μm to 5 μm. Bonding techniques may be used to provide bonding pads with smaller sizes and spacings.

[0086] Some embodiments may include a film on the surface of the tube core 201, 211. If such a film is not initially provided, the space between the tube cores can be filled with epoxy or other resins or polymers at the bottom. The bottom filling material can be applied as a liquid and then hardened into a solid layer. This bottom filling step protects the electrical connection between the tube core 201, 211 and further fixes the tube core together. Various materials can be used as the bottom filling material, but in an embodiment, the bottom filling material can be Hysol epoxy resin from Henkel Corporation (the company has offices in California, USA).

[0087] Figure 4 is a perspective view of a portion of an example embodiment of a monolithic three-dimensional memory array / structure that may include a memory structure 202 that includes a plurality of non-volatile memory cells arranged as vertical NAND strings. For example, Figure 4A portion 400 of a memory block is shown. The depicted structure includes a set of bit lines BL located above a stack 401 of alternating dielectric and conductive layers. For example, one of the dielectric layers is labeled D, and one of the conductive layers (also referred to as a word line layer) is labeled W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements. As will be explained below, in one embodiment, the alternating dielectric and conductive layers are divided into six (or a different number of) regions by isolation regions IR. These regions are sometimes referred to as fingers or strings. Figure 4 An isolation region IR is shown separating the two regions. A source line layer SL is located below the alternating dielectric layer and word line layer. A memory cavity is formed in the stack of alternating dielectric layers and conductive layers. For example, a memory cavity is labeled MH. Note that Figure 4 202, the dielectric layers are depicted as perspective views so that the reader can see the memory holes located in the stack of alternating dielectric layers and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping material to form vertical columns of memory cells. Each memory cell can store one or more data bits. More details of a three-dimensional monolithic memory array including memory structure 202 are provided below.

[0088] Figure 4A 4 and 5. 4. The memory cells of FIG. 20 are grouped into blocks. FIG. 20 is a block diagram illustrating an example organization of a memory structure 202 that is divided into two planes 402 and 404. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, a different number of blocks and planes may also be used. In one embodiment, a block of memory cells is the unit of erase. That is, all memory cells of a block are erased together. Memory cells may also be grouped into blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells because the memory cells of a block share a common set of word lines. For example, the word lines of a block are all connected to all vertical NAND strings of the block. Although Figure 4A Two planes 402 / 404 are shown, but more or less than two planes may be implemented. In some embodiments, the memory structure 202 includes four planes, eight planes, or more than eight planes.

[0089] FIG. 4B to FIG. 4J An example three-dimensional ("3D") NAND structure is depicted, corresponding to Figure 4 structure and can be used to implement Figure 2A and Figure 2B Memory structure 202. Figure 4B is a block diagram depicting a top view of a portion 406 of block 2 of plane 402. Figure 4B As can be seen, Figure 4B The blocks depicted in FIG. extend in the direction of 432. In one embodiment, the memory array has many layers; however, Figure 4B Only the top layer is shown.

[0090] Figure 4B A plurality of circles representing vertical columns corresponding to memory holes are depicted. Each of the vertical columns includes a plurality of select transistors (also referred to as select gates / selection gates) and a plurality of memory cells. In one embodiment, each vertical column implements a NAND string. For example, Figure 4B A subset of vertical columns / NAND strings 426, 432, 436, 446, 456, 462, 466, 472, 474, and 476 are labeled.

[0091] Figure 4B Also depicted is a set of bit lines 415 , including bit lines 411 , 412 , 413 , 414 , . . . , 419 . Figure 4B Twenty-four bit lines are shown because only a portion of the block is shown. It is contemplated that more than twenty-four bit lines are connected to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line. For example, bit line 411 is connected to vertical columns 426, 436, 446, 456, 466, and 476.

[0092] Figure 4B The block depicted in FIG. 4 includes a set of isolation regions 480, 482, 484, 486, and 488 formed of SiO2; however, other dielectric materials may also be used. Isolation regions 480, 482, 484, 486, and 488 are used to divide the top layer of the block into six regions; for example, Figure 4B 4 is divided into regions 420, 430, 440, 450, 460, and 470. In one embodiment, the isolation regions divide only the layers used to implement the select gates (e.g., SGD) so that NAND strings in different regions can be independently selected. In one example implementation, the bit lines are connected to only one vertical column / NAND string in each of the regions 420, 430, 440, 450, 460, and 470. In this implementation, each block has twenty-four rows of active columns, and each bit line is connected to six rows in each block. In one embodiment, all six vertical columns / NAND strings connected to a common bit line are connected to the same word line (or word line group); therefore, the system uses a drain-side select line (SGD) to select one (or another subset) of the six to be subjected to a memory operation (program, verify, read, and / or erase).

[0093] although Figure 4BEach region 420, 430, 440, 450, 460, and 470 is shown as having four vertical columns in one block, and six regions have twenty-four vertical columns, but these exact numbers are example implementations. Other implementations may include more or fewer regions per block, more or fewer vertical columns per region, and more or fewer vertical columns per block. Figure 4B It is also shown that the vertical columns are staggered. In other embodiments, different staggered patterns can be used. In some embodiments, the vertical columns are not staggered.

[0094] Figure 4C Describes also Figure 4B A side view of portion 406 of block 2 is depicted in plane 402 . Figure 4C The side view of FIG. 1 shows the memory array implemented as a three-level architecture, where each level is separated by a bonding area. The first level (level 0) includes word lines WL0 to WL89. The second level (level 1) includes word lines WL90 to WL179. The third level (level 2) includes word lines WL180 to WL269. In other embodiments, the block has more than three levels.

[0095] Figure 4D A portion of one embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B The cross-sectional view cuts through the vertical columns (NAND strings) 472 and 474 of region 470 (see Figure 4B ). Figure 4D The structure includes: three drain side selection layers SGD0, SGD1 and SGD2 (which form selection lines); three source side selection layers SGS0, SGS1 and SGS2 (which form selection lines); dummy word line layers D0L, D0U, D1L, D1I, D2L and D2U for connecting to dummy memory cells (which do not store data from the host); two hundred and seventy data word line layers WL0 to WL269 for connecting to data memory cells (which store data) and dielectric layer DL. Other embodiments may implement more or less than the above embodiments for Figure 4D In one embodiment, SGD0, SGD1 and SGD2 are connected together; and SGDS0, SGS1 and SGS2 are connected together.

[0096] Vertical columns 472 and 474 are depicted as protruding through the drain side select layer, source side select layer, dummy word line layer, and word line layer. In one embodiment, each vertical column includes a vertical NAND string. Below the vertical columns and the layers listed below is a substrate 453, an insulating film 454 on the substrate, and a source line SL. The NAND string of vertical column 472 has a source terminal at the bottom of the stack and a drain terminal at the top of the stack. Figure 4BConsistent, Figure 4D Vertical columns 442 connected to bit lines 414 via connectors 417 are shown.

[0097] For ease of reference, the drain side selection layer, the source side selection layer, the dummy word line layer, and the data word line layer are collectively referred to as the conductive layer. In one embodiment, the conductive layer is made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layer, such as doped polysilicon, metals (such as tungsten or metal silicide). In some embodiments, different conductive layers may be formed of different materials. Between the conductive layers is a dielectric layer DL. In one embodiment, the dielectric layer is made of SiO2. In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0098] The non-volatile memory cells are formed along vertical columns that extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged in NAND strings to form a block having three levels (level 0, level 1, and level 2). Word line layers WL0 to W269 are connected to memory cells (also referred to as data memory cells). Each NAND string of the block includes memory cells in each of the three levels; for example, memory cells connected to word lines WL0 to WL89 are in level 0, memory cells connected to word lines WL90 to WL179 are in level 1, and memory cells connected to word lines WL180 to WL269 are in level 2. The dummy word line layer is connected to the dummy memory cells. The dummy memory cells do not store host data and are not eligible to store host data (data provided from an entity external to the host or storage system 100), while the data memory cells are eligible to store host data. The host data may be contrasted with system data generated by the memory system 100 (e.g., L2P table). In some embodiments, the data memory cells and the dummy memory cells may have the same structure. The drain side selection layers SGD0, SGD1, and SGD2 are used to electrically connect and disconnect the NAND string to the bit line. The source side selection layers SGS0, SGS1, and SGS2 are used to electrically connect and disconnect the NAND string to the source line SL.

[0099] Figure 4DTwo bonding regions are also shown. In one embodiment, etching so many word line layers intermixed with dielectric layers is expensive and / or challenging. To alleviate this burden, one embodiment includes laying a first stack of word line layers alternately with dielectric layers (e.g., for level 0), laying a lower bonding region, laying a second stack of word line layers alternately with dielectric layers (e.g., for level 1), laying an upper bonding region, and laying a third stack of word line layers alternately with dielectric layers (e.g., for level 2). The bonding region is located between the first stack and the second stack and between the second stack and the third stack. In one embodiment, the bonding region is made of polysilicon. The bonding region serves as a buffer layer to allow some misalignment between the upper level and the lower level.

[0100] Figure 4E A portion of one embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B The cross-sectional view cuts through the vertical columns (NAND strings) 432 and 434 of region 430 (see Figure 4B ). Figure 4E Shown with Figure 4D Same alternating conductive and dielectric layers. Figure 4E Isolation region 482 is also shown. Isolation regions 480, 482, 484, 486, and 488 occupy space that was already used for a portion of memory holes / vertical columns / NAND strings. For example, isolation region 482 occupies space that was already used for a portion of vertical column 434. More specifically, a portion of vertical column 434 (e.g., half of the diameter) has been removed in layers SDG0, SGD1, SGD2, and DD0 to accommodate isolation region 482. Thus, while most of vertical column 434 is cylindrical (having a circular cross-section), portions of vertical column 434 in layers SDG0, SGD1, and SGD2 have a semicircular cross-section. In one embodiment, after forming a stack of alternating conductive and dielectric layers, the stack is etched to create space for the isolation region, and the space is subsequently filled with SiO2.

[0101] Figure 4F A portion of a vertical column 472 is depicted. Figure 4C429 . In one embodiment, the vertical columns are circular; however, in other embodiments, other shapes may be used. In one embodiment, the vertical columns 472 include an inner core layer 490 made of a dielectric such as SiO2. Other materials may also be used. Surrounding the inner core 490 is a polysilicon channel 491. Materials other than polysilicon may also be used. Note that the channel 491 is connected to the bit line and the source line. Surrounding the channel 491 is a tunneling dielectric 492. In one embodiment, the tunneling dielectric 492 has an ONO structure. Surrounding the tunneling dielectric 492 is a charge trapping layer 493, such as (for example) silicon nitride. Other memory materials and structures may also be used. The technology described herein is not limited to any particular material or structure.

[0102] Figure 4F A dielectric layer DL is depicted, as well as word line layers WL264, WL265, WL266, WL267, and WL268. Each of the word line layers includes a word line region 496 surrounded by an aluminum oxide layer 497, which is surrounded by a blocking oxide layer 498. In other embodiments, the blocking oxide layer may be a vertical layer parallel to and adjacent to the charge trapping layer 493. The physical interaction of the word line layer with the vertical columns forms a memory cell. Thus, in one embodiment, a memory cell includes a channel 491, a tunneling dielectric 492, a charge trapping layer 493, a blocking oxide layer 498, an aluminum oxide layer 497, and a word line region 496. For example, word line layer WL268 and a portion of vertical column 472 constitute memory cell MC1. Word line layer WL267 and a portion of vertical column 472 constitute memory cell MC2. Word line layer WL266 and a portion of vertical column 472 constitute memory cell MC3. Word line layer WL265 and a portion of vertical column 472 constitute memory cell MC4. Word line layer WL264 and a portion of vertical column 472 constitute memory cell MC5. In other architectures, the memory cells may have different structures; however, the memory cells will still still be storage cells.

[0103] When programming a memory cell, electrons are stored in a portion of the charge trapping layer 493 that is associated with the memory cell (e.g., in the memory cell). In response to an appropriate voltage on the word line region 496, these electrons are attracted from the channel 491 into the charge trapping layer 493 through the tunneling dielectric 492. The threshold voltage (Vth) of the memory cell increases in proportion to the amount of charge stored. In one embodiment, programming is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer. During an erase operation, electrons return to the channel or holes are injected into the charge trapping layer to recombine with the electrons. In one embodiment, erasure is achieved using hole injection into the charge trapping layer via a physical mechanism such as GIDL.

[0104] Figure 4G Shows Figure 4F A cross section of a vertical column 472, wherein MC5 is cut through. Thus, Figure 4G Word line layer WL264, inner core 490, channel 491, tunnel dielectric 492, charge trapping layer 493, aluminum oxide layer 497, and blocking oxide layer 498 are depicted.

[0105] Figure 4H A cross section of a vertical column 472 is shown, with a cut through SGD1 (the select gate layer implementing the select gates). Figure 4H A drain side select line layer SGD1 , an inner core 490 , a channel 491 , a tunneling dielectric 492 , a charge trapping layer 493 , an aluminum oxide layer 497 , and a blocking oxide layer 498 are depicted.

[0106] Fig. 4I A cross section of a vertical column 434 is shown, with SGD1 cut through. Thus, Fig. 4I A drain side select line layer SGD1 , an inner core 490 , a channel 491 , a tunneling dielectric 492 , a charge trapping layer 493 , an aluminum oxide layer 497 , and a blocking oxide layer 498 are depicted. Fig. 4I A portion of the isolation region 482 is also shown. Fig. 4I As can be seen in FIG. 4 , because the vertical columns (NAND strings) 434 intersect the isolation region 482 , the select gates (select gate layers) of the vertical columns 434 are semicircular (or partially circular in shape).

[0107] Figure 4J yes Figures 4 to 4I Schematic diagram of a portion of memory array 202 is depicted in FIG. Figure 4J Physical data word lines WL0 to WL269 are shown extending across the block. Figure 4J The structure corresponds to Figure 4AThe portion 406 in block 2 includes bit lines 411. Within this block, in one embodiment, each bit line is connected to six NAND strings. Thus, Figure 4J Bit line 411 is shown connected to NAND string NS0 (which corresponds to vertical column 426), NAND string NS1 (which corresponds to vertical column 436), NAND string NS2 (which corresponds to vertical column 446), NAND string NS3 (which corresponds to vertical column 456), NAND string NS4 (which corresponds to vertical column 466), NAND string NS5 (which corresponds to vertical column 476). As described above, in one embodiment, SGD0, SGD1, and SGD2 are connected together to operate as a single logic select gate for each region separated by isolation regions (480, 482, 484, 486, and 487) to form SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4, and SGD-s5. SGS0, SG1, and SGS2 are also connected together to operate as a single logic select gate in Figure 4J Although the select gates SGD-s0, SGD-s1, SGD-s2, SGD-s3, SGD-s4, and SGD-s5 are isolated from each other due to the isolation region, the data word lines WL0 to WL269 are connected to the data memory cells in each region (e.g., 420, 430, 44, 450, 460, and 470) of the block. Figure 4J Only the NAND string connected to bit line 411 is shown. However, a complete schematic diagram of the block would show each bit line and the six vertical NAND strings connected to each bit line.

[0108] Figure 4K A side view of a memory cell block having five levels and a bonding area including a bonding area between each pair of adjacent levels is depicted. That is, the levels are separated by bonding areas. The first level (level 0) includes word lines WL0 to WL89. The second level (level 1) includes word lines WL90 to WL179. The third level (level 2) includes word lines WL180 to WL269. The fourth level (level 3) includes word lines W270 to WL359. The fifth level (level 4) includes word lines W360 to WL449. Other word line allocations may also be implemented. More or less than 450 word lines may also be implemented. In other embodiments, the memory has more than five levels. In another embodiment, the memory has four levels.

[0109] Figure 4L A portion of one embodiment of a three-dimensional memory structure is depicted, showing a cross-sectional view cutting through vertical columns (NAND strings) 492 and 494 . Figure 4L The structure includes Figure 4K The same five levels, bonding areas, and 450 word lines as depicted in FIG. Figure 4L The structure comprises: identical drain side select layers SGD0, SGD1 and SGD2 (which form select lines); and Figure 4D Three source side select layers SGS0, SGS1 and SGS2 are shown (they form the select lines). Figure 4L Dummy word line layers on either side of four bonding regions are shown, including dummy word line layers D0L, D0U, D1L, D1I, D2L, D2U, D3L, D3U, D4L, and D4U for connecting to dummy memory cells.

[0110] Although Figures 4 to 4L An example memory of is a three-dimensional memory structure including vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures may also be used with the techniques described herein.

[0111] The memory system discussed above can be erased, programmed, and read. At the end of a successful programming process, the threshold voltage of the memory cell should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. Figure 5A is a graph of threshold voltage versus number of memory cells and illustrates an example threshold voltage distribution for a memory array when each memory cell stores one bit of data per memory cell. A memory cell storing one bit of data per memory cell is referred to as a single-level cell ("SLC"). Data stored in an SLC memory cell is referred to as SLC data; therefore, SLC data includes one bit per memory cell. Data stored as one bit per memory cell is SLC data. Figure 5A Two threshold voltage distributions are shown: E and P. Threshold voltage distribution E corresponds to an erased data state. Threshold voltage distribution P corresponds to a programmed data state. Therefore, memory cells having threshold voltages in threshold voltage distribution E are in an erased data state (e.g., they are erased). Therefore, memory cells having threshold voltages in threshold voltage distribution P are in a programmed data state (e.g., they are programmed). In one embodiment, erased memory cells store data "1" and programmed memory cells store data "0". Figure 5A Depicted is a read compare voltage Vr. By testing (eg, performing one or more sense operations) whether the threshold voltage of a given memory cell is above or below Vr, the system can determine whether the memory cell is erased (state E) or programmed (state P). Figure 5A Also depicted is a verify reference voltage Vv. In some implementations, when programming memory cells to data state P, the system will test whether the memory cells have a threshold voltage greater than or equal to Vv.

[0112] FIG. 5B to FIG. 5F Example threshold voltage distributions for a memory array when each memory cell stores multiple bits of data per memory cell are illustrated. Memory cells that store multiple bits of data per memory cell are referred to as multi-level cells ("MLC"). Data stored in an MLC memory cell is referred to as MLC data; therefore, MLC data includes multiple bits per memory cell. Data stored as multiple bits of data per memory cell is MLC data. Figure 5B In an example embodiment, each memory cell stores two bits of data. Other embodiments may use other data capacities per memory cell (e.g., such as three bits of data, four bits of data, five bits of data, or six bits of data per memory cell).

[0113] Figure 5B A first threshold voltage distribution E is shown for erased memory cells. Also depicted are three threshold voltage distributions A, B, and C for programmed memory cells. In one embodiment, the threshold voltages in distribution E are negative, and the threshold voltages in distributions A, B, and C are positive. Figure 5B Each different threshold voltage distribution corresponds to a predetermined value for a set of data bits. In one embodiment, each bit of data stored in the memory cell is in a different logical page, referred to as a lower page (LP) and an upper page (UP). In other embodiments, all data bits stored in the memory cell are in a common logical page. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted by the cell. Table 1 provides an example encoding scheme.

[0114] Table 1

[0115] E A B C LP 1 0 0 1 UP 1 1 0 0

[0116] In one implementation, referred to as full sequence programming, the Figure 6 The process of programming memory cells from erased data state E directly to any of programmed data states A, B, or C (discussed below) is used. For example, a group of memory cells to be programmed may first be erased so that all memory cells in the group are in erased data state E. Then, a programming process is used to program the memory cells directly to data states A, B, and / or C. For example, while some memory cells are being programmed from data state E to data state A, other memory cells are being programmed from data state E to data state B and / or from data state E to data state C. Figure 5B The arrows represent full sequence programming. In some embodiments, data states AC may overlap, where the memory controller 120 (or control die 211) relies on error correction to identify the correct data being stored.

[0117] Figure 5C Example threshold voltage distributions for memory cells are depicted, where each memory cell stores three bits of data per memory cell (which is another example of MLC data). Figure 5C Eight threshold voltage distributions corresponding to eight data states are shown. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) AG represent programmed memory cells, and are therefore also referred to as programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined value of a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted by the cell. In one embodiment, the data value is assigned to the threshold voltage range using Gray code distribution, so that if the threshold voltage of the memory is incorrectly shifted to its adjacent physical state, only one bit will be affected. Table 2 provides an example of a coding scheme for an embodiment in which each bit of the three bits of data stored in the memory cell is in different logical pages, and the logical page is referred to as a lower page (LP), a middle page (MP), and an upper page (UP).

[0118] Table 2

[0119] Er A B C D E F G UP 1 1 1 0 0 0 0 1 MP 1 1 0 0 1 1 0 0 LP 1 0 0 0 0 1 1 1

[0120] Figure 5C Seven read compare voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG are shown for reading data from a memory cell. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is above or below the seven read compare voltages, the system can determine the data state (i.e., A, B, C, D, ...) that the memory cell is in.

[0121] Figure 5CAlso shown are seven verification comparison voltages VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when the memory cells are programmed to data state A, the system will test whether the memory cells have a threshold voltage greater than or equal to VvA. When the memory cells are programmed to data state B, the system will test whether the memory cells have a threshold voltage greater than or equal to VvB. When the memory cells are programmed to data state C, the system will determine whether the memory cells have a threshold voltage greater than or equal to VvC. When the memory cells are programmed to data state D, the system will test whether the memory cells have a threshold voltage greater than or equal to VvD. When the memory cells are programmed to data state E, the system will test whether the memory cells have a threshold voltage greater than or equal to VvE. When the memory cells are programmed to data state F, the system will test whether the memory cells have a threshold voltage greater than or equal to VvF. When the memory cells are programmed to data state G, the system will test whether the memory cells have a threshold voltage greater than or equal to VvG. Figure 5C Also shown is Vev, which is the voltage level used to test whether the memory cell has been properly erased.

[0122] In an implementation utilizing full sequence programming, the Figure 6 The process of programming memory cells from erased data state Er directly to any of programmed data states AG (discussed below) can be used. For example, a group of memory cells to be programmed can be first erased so that all memory cells in the group are in erased data state Er. Then, the programming process is used to program the memory cells directly to data states A, B, C, D, E, F, and / or G. For example, while some memory cells are being programmed from data state ER to data state A, other memory cells are being programmed from data state ER to data state B and / or from data state ER to data state C, and so on. Figure 5C The arrows represent full sequence programming. In some embodiments, data states AG may overlap, where the control die 211 and / or memory controller 120 rely on error correction to identify the correct data being stored. Note that in some embodiments, the system may use a multi-pass programming process known in the art instead of using full sequence programming.

[0123] Generally speaking, during a verify operation and a read operation, a selected word line is connected to a voltage (an example of a reference signal) whose level is determined for each read operation (eg, see Figure 5C of read comparison voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG) or a verification operation (see, for example, Figure 5CThe verification target voltages (VvA, VvB, VvC, VvD, VvE, VvF, and VvG) of the memory cell are specified in order to determine whether the threshold voltage of the associated memory cell has reached this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducting current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verification process, unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether these memory cells are programmed or erased).

[0124] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured at the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string that includes the memory cell to discharge the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has discharged. It should be noted that the techniques described herein can be used with different methods known in the art for verification / reading. Other read and verify techniques known in the art can also be used.

[0125] Figure 5D Depicted is a threshold voltage distribution when each memory cell stores four bits of data, which is another example of MLC data. Figure 5D It is shown that there can be some overlap between the threshold voltage distributions (data states) S0 to S15. This overlap can occur due to factors such as memory cells losing charge (and therefore the threshold voltage dropping). Program disturbances can unintentionally increase the threshold voltage of a memory cell. Similarly, read disturbances can unintentionally increase the threshold voltage of a memory cell. Over time, the position of the threshold voltage distributions can change. Such changes can increase the bit error rate, thereby increasing decoding time or even making decoding impossible. Changing the read compare voltage can help mitigate such effects. Using ECC during the read process can repair errors and ambiguities. Note that in some embodiments, the threshold voltage distributions of a group of memory cells storing four bits of data per memory cell do not overlap and are separated from each other; for example, Figure 5E Depicted. Figure 5D The threshold voltage distribution will include a read compare voltage and a verify compare voltage, as discussed above.

[0126] When four bits are used per memory cell, the memory can be programmed using the full sequence programming discussed above or a multi-pass programming process known in the art. Figure 5D Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the cell depends on the data encoding scheme adopted by the cell. Table 3 provides an example of an encoding scheme for an embodiment in which each bit of the four bits of data stored in the memory cell is in a different logical page, which is referred to as the lower page (LP), the middle page (MP), the upper page (UP), and the top page (TP).

[0127] Table 3

[0128]

[0129]

[0130] Fig. 5F Depicted is a threshold voltage distribution when each memory cell stores five bits of data (which is another example of MLC data). In one example implementation, when the memory cell stores five bits of data, the data is stored in any one of thirty-two data states (eg, S0 to S31).

[0131] Figure 6 2 is a flow chart describing one embodiment of a process for programming memory cells. For the purposes of this document, the term programming is synonymous with writing. In one example embodiment, memory array 202 is programmed using one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) discussed above. Figure 6 In one example embodiment, Figure 6 The process is performed by the integrated memory component 207 using one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) of the control die 211 to program the memory cells on the memory die 201. The process includes multiple cycles (referred to as programming cycles), each cycle including a programming phase and a verification phase. Figure 6 to achieve full sequence programming and other programming schemes including multi-pass programming, which includes a programming process that uses multiple passes to complete programming. When implementing multi-pass programming, Figure 6 The process is used to implement any / each pass of the multi-pass programming process.

[0132] Typically, the programming voltage applied to the control gate (via a selected data word line) during a programming operation is applied as a series of programming pulses (e.g., voltage pulses). Between the programming pulses are a set of verify pulses (e.g., voltage pulses) to perform verification. In many implementations, the magnitude of the programming pulses increases by a predetermined step size with each successive pulse. Figure 6 In step 602, the programming voltage signal (Vpgm) is initialized to a starting value (e.g., about 12V to 16V or another suitable level), and the programming counter PC maintained by the state machine 262 is initialized to 1. In one embodiment, a group of memory cells selected for programming (referred to herein as selected memory cells) are programmed simultaneously and are all connected to the same word line (the selected word line). There may be other memory cells (unselected memory cells) that are not selected for programming that are also connected to the selected word line. That is, the selected word line will also be connected to the memory cells that should be prohibited from programming. Additionally, when the memory cells reach their expected target data state, they will be prohibited from further programming. These NAND strings (e.g., unselected NAND strings) have their channels boosted to prohibit programming, and these strings include memory cells that are connected to the selected word line to be prohibited from programming. When the channel has an elevated voltage, the voltage difference between the channel and the word line is not enough to cause programming. To help boost, in step 604, the control die will precharge the channel of the NAND string including the memory cells connected to the selected word line that will be prohibited from programming. In some embodiments, the channel of the unselected NAND string is precharged to clear the electrons of the channel, and the channel is raised to a low positive voltage (e.g., about 1v to 1.3v). In step 606, the NAND string including the memory cell connected to the selected word line to be prohibited from programming has its channel boosted to prohibit programming. Such NAND strings are referred to as "unselected NAND strings" herein. In one embodiment, the unselected word line receives one or more boost voltages (e.g., about 7 volts to 11 volts) (also referred to as pass voltage) to perform the boost scheme. The program inhibit voltage is applied to the bit line of the coupled unselected NAND string. For example, in one embodiment, the channel is precharged to about 2 volts and then floated in step 604. In step 606, the channel is boosted from 2 volts to a boost voltage of about 8 volts to 10 volts.

[0133] In step 608, a programming voltage pulse of a programming voltage signal Vpgm is applied to the selected word line (the word line selected for programming). In some embodiments, the magnitude and / or pulse width of the programming voltage pulse may be modified by one or more offsets from the standard magnitude and / or pulse width, as described below. If the memory cell on the NAND string should be programmed, the corresponding bit line is biased at a programming enable voltage. In step 608, a programming pulse is applied simultaneously to all memory cells connected to the selected word line so that all memory cells connected to the selected word line are programmed simultaneously (unless they are prohibited from programming). That is, they are programmed at the same time or during overlapping time (both are considered to be simultaneous). In this way, all memory cells connected to the selected word line will have their threshold voltage changes at the same time unless they are prohibited from programming.

[0134] In step 610, program verification is performed and memory cells that have reached their target state are locked out from further programming by the control die. Step 610 includes performing verification of programming by sensing at one or more verify compare levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached the appropriate verify compare voltage. Figure 5C In one embodiment, executing Figure 6 6. The process for memory cells being programmed to data states A, B, C, D, E, F, and G. In one embodiment, step 610 may include testing each of the data states A, B, C, D, E, F, and G (e.g., testing to see if the threshold voltage of the memory cell is greater than VvA, VvB, VvC, VvD, VvE, VvF, and VvG). In another embodiment, the system tests only a subset of data states A, B, C, D, E, F, and G based on the current threshold voltage of the memory cell during each cycle of steps 604 to 626 in a process referred to as smart verification. In step 610, after the memory cell has been verified (by testing of Vt) that the memory cell has reached its target state, the memory cell may be locked out.

[0135] If, in step 612, it is determined that all memory cells have reached their target threshold voltage (PASS), then the programming process is complete and successful because all selected memory cells have been programmed and verified to their target states. In step 614, a "PASS" status is reported. Otherwise, if, in step 612, it is determined that not all memory cells have reached their target threshold voltage (FAIL), then the programming process will continue to step 616.

[0136] In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distribution is counted. That is, the number of memory cells that have so far been unable to reach their target state is counted. This counting may be done by the state machine 262, the memory controller 120, or another circuit. In one embodiment, there is a total count that reflects the total number of memory cells currently being programmed that have failed the last verification step. In another embodiment, a separate count is maintained for each data state.

[0137] In step 618, it is determined whether the count from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during the read process of a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and report a "pass" status in step 614. In this case, enough memory cells are correctly programmed so that the remaining few memory cells that have not been fully programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 618 is lower than the number of bits that can be corrected by an error correction code (ECC) during the read process to allow for future / additional errors. When programming less than all memory cells of a page, or comparing counts of only one data state (or less than all states), the predetermined limit can be a portion (proportional or non-proportional) of the number of bits that can be corrected by ECC during the read process of a page of memory cells. In some embodiments, the limit is not predetermined. Instead, it changes based on the number of errors that have been counted for the page, the number of program-erase cycles performed, or other criteria.

[0138] If the number of failed memory cells is not less than the predetermined limit, the programming process continues at step 620 and checks the programming counter PC against the programming limit value (PL). Examples of programming limit values ​​include 6, 12, 16, 19, 20, and 30; however, other values ​​may be used. If the programming counter PC is not less than the programming limit value PL, the programming process is deemed to have failed and a "failed" status is reported in step 624. If the programming counter PC is less than the programming limit value PL, the process continues at step 626, during which the programming counter PC is incremented by 1 and the programming voltage signal Vpgm is stepped to the next magnitude. For example, the next pulse will have a magnitude that is a step size ΔVpgm (e.g., a step size of 0.1 volts to 1.0 volts) greater than the previous pulse. After step 626, the process loops back to step 604 and another programming pulse is applied (to the control die) to the selected word line so that execution Figure 6 Another cycle of the programming process (steps 604 to 626). Figure 6The cycle of the programming process (steps 604 to 626) is called a programming cycle.

[0139] In some embodiments, the memory cells are programmed in order from the source side to the drain side. For example, first perform Figure 6 to program the memory cells connected to WL0, and then use Figure 6 The process of programming the memory cells connected to WL1 is then followed by Figure 6 The process of programming the memory cells connected to WL2 is then used Figure 6 to program the memory cells connected to WL3, ... and then use Figure 6 The process is used to program the memory cells connected to WL269.

[0140] In another embodiment, the memory cells are programmed in order from the drain side to the source side. For example, first perform Figure 6 process to program the memory cells connected to the WL269, followed by using Figure 6 The process of programming the memory cells connected to the WL268 is then used Figure 6 The process of programming the memory cells connected to WL267 is then used Figure 6 The process of programming the memory cells connected to WL266 is then used Figure 6 The process of programming the memory cells connected to WL1 is then followed by Figure 6 The memory cells connected to WL0 are programmed by the process of

[0141] In one embodiment, the memory cells are erased prior to programming. Erasing is the process of changing the threshold voltage of one or more memory cells from a programmed data state to an erased data state. For example, changing the threshold voltage of one or more memory cells from Figure 5A The state P changes to state E, from Figure 5B The state A / B / C changes to state E, from Figure 5C Change from state A to state G to state Er or from Figure 5D States S1 to S15 are changed to state S0.

[0142] One technique for erasing memory cells in some memory devices is to bias the p-well (or other type) substrate to a high voltage to charge the NAND channel. When the NAND channel is at a high voltage, an erase enable voltage (e.g., a low voltage) is applied to the control gate of the memory cell to erase the memory cell. This is referred to herein as p-well erase.

[0143] Another method of erasing a memory cell is to generate a gate induced drain leakage (GIDL) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the memory cell while maintaining the NAND string channel potential to erase the memory cell. This is referred to herein as GIDL erase. Both p-well erase and GIDL erase can be used to lower the threshold voltage (Vt) of a memory cell.

[0144] In one embodiment, the GIDL current is generated by causing a drain-to-gate voltage at a GIDL generating transistor (e.g., a transistor connected to SGDT0, SGDT1, SGDT2, SGSB0, SGSB1, and SGSB2). In some embodiments, a select gate (e.g., SGD or SGS) may be used as a GIDL generating transistor. The drain-to-gate voltage of the transistor that generates the GIDL current is referred to herein as the GIDL voltage. When the GIDL generating transistor drain voltage is significantly higher than the GIDL generating transistor control gate voltage, a GIDL current may be generated. The GIDL current is a result of carrier generation, i.e., electron-hole pair generation and / or trap-assisted generation due to band-band tunneling. In one embodiment, the GIDL current may cause one type of carrier (also referred to as charge carrier) (e.g., hole) to move primarily into the NAND channel, thereby increasing or changing the potential of the channel. Another type of carrier (e.g., electron) is extracted from the channel by an electric field in the direction of the bit line or in the direction of the source line. During erase, holes can tunnel from the channel to the charge storage region of the memory cell (eg, to the charge trapping layer 493) and recombine with electrons therein to lower the threshold voltage of the memory cell.

[0145] A GIDL current may be generated at either end (or both ends) of a NAND string. A first GIDL voltage may be generated between two terminals of a GIDL generating transistor (e.g., connected to SGDT0, SGDT1, SGDT2) connected to or near a bit line to generate a first GIDL current. A second GIDL voltage may be generated between two terminals of a GIDL generating transistor (e.g., SGSB0, SGSB1, and SGSB2) connected to or near a source line to generate a second GIDL current. Erasing based on GIDL current only at one end of a NAND string is referred to as single-sided GIDL erasing. Erasing based on GIDL current at both ends of a NAND string is referred to as double-sided GIDL erasing. The techniques described herein may be used with single-sided GIDL erasing and double-sided GIDL erasing.

[0146] Figure 7The movement of holes and electrons in a NAND string 800 during a double-sided GIDL erase is depicted. An example NAND string 800 is depicted including a channel 891 connected to a bit line (BL) and a source line (SL). The tunnel dielectric layer (TNL) 892, the charge trapping layer (CTL) 893, and the blocking oxide layer (BOX) 898 are layers that extend around the memory holes of the NAND string (see discussion above). Different regions of the channel layer represent channel regions associated with corresponding memory cells or select gate transistors.

[0147] For the purpose of simplifying the drawings and discussion only, Figure 7 Only one drain-side GIDL generating transistor 801 (eg, representing one of SGDT0, SGDT1, or SGDT2) is depicted in FIG. Figure 7 Only one source-side GIDL generating transistor 802 is depicted (e.g., representing one of SGSB0, SGSB1, or SGSB2). In addition, the select gates (i.e., SGS and SGD) of the NAND string 800 are not shown in FIG. Figure 7 However, Figure 7 Indeed, NAND string 800 is shown including memory cells 810, 815, 820, and 825, respectively; control gates 811, 816, 821, and 826; CTL regions 813, 818, 823, and 828; and channel regions 812, 817, 822, and 827. NAND string 800 also includes memory cells 860, 865, 870, and 875, respectively; control gates 861, 866, 871, and 876; CTL regions 863, 868, 873, and 878; and channel regions 862, 867, 872, and 877, respectively.

[0148] During the erase operation, the erase voltage Vera (e.g., about 20V) is applied to both the bit line (BL) and the source line (SL). The voltage V_GIDL (e.g., Vera-10V or Vera-10v) is applied to the gate 806 of the GIDL generation transistor 801 and the gate 856 of the GIDL generation transistor 802 to enable GIDL. Representative holes in the channel layer are depicted as circles with a "+" symbol, and representative electrons in the channel layer are depicted as circles with a "-" symbol. Electron-hole pairs are generated by the GIDL process. Initially, during the erase operation, electron-hole pairs are generated at the GIDL generation transistor. The holes move away from the drive end into the channel, thereby charging the channel to a positive potential. The electrons generated at the GIDL generation transistor 801 move toward the bit line (BL) due to the positive potential there. The electrons generated at the GIDL generation transistor 802 move toward the source line (SL) due to the positive potential there. Subsequently, during the erase cycle of each memory cell, additional holes are generated by the GIDL at the virtual junction formed in the channel at the edge of the control gate of the memory cell. Some holes are removed from the channel as they tunnel to the CTL region.

[0149] Electrons are also generated by the GIDL process. Initially, during the erase operation, electrons are generated at the GIDL generating S transistor and move toward the drive terminal. Subsequently, during the erase cycle of each storage element, additional electrons are generated by GIDL at the virtual junction formed in the channel at the edge of the control gate of the memory cell.

[0150] At one end (e.g., drain side) of the NAND string, example electrons 840 and 841 move toward the bit line. Electron 840 is generated at the GIDL generation transistor 801, and electron 841 is generated at the junction of the memory cell 815 in the channel region 817. In addition, in the drain side, example holes including hole 842 move away from the bit line as indicated by the arrow. Hole 842 is generated at the junction of the memory cell 815 in the channel region 817 and can tunnel into the CTL region 818 as indicated by arrow 843.

[0151] At the other end of the NAND string (e.g., source side), example electrons 845 and 849 move toward the source line. Electron 845 is generated at the GIDL generation transistor 802, and electron 849 is generated at the junction of the memory cell 865 in the channel region 867. In addition, at the source side, example holes including hole 847 move away from the source line, and hole 847 is generated at the junction of the memory cell 865 in the channel region 867, and can tunnel into the CTL region 868 as indicated by arrow 848.

[0152] Figure 8 is a flow chart describing one embodiment of a conventional process for erasing non-volatile memory. In one example implementation, Figure 8 The process utilizes the Figure 7 In another embodiment, Figure 8 The process utilizes single-sided GIDL erase (GIDL only at the source side or only at the drain side). Figure 8 The process may be performed by any of the one or more control circuits discussed above. For example, Figure 8 The process can be completely handled by the memory die 200 (see Figure 2A ) or by the integrated memory component 207 (see Figure 2B ) rather than being executed by memory controller 120. In one example, the state machine 262 is executed or directed by the state machine 262 using other components of the system control logic component 260, the column control circuit 210, and the row control circuit 220. Figure 8 In another embodiment, Figure 8 The process is performed by or under the direction of the memory controller 120. In one embodiment, the erase process is performed on a block of memory cells. That is, in one embodiment, a block is an erase unit.

[0153] exist Figure 8 In step 900, the magnitude of the initial erase voltage pulse (Vera) is set. An example of the initial magnitude is 20 volts (Vera=20v). However, other initial magnitudes may also be used. In step 902, various erase support voltages are applied. For example, step 902 may include applying appropriate voltages to data word lines, dummy word lines, drain side selection lines (SGD), and source side selection lines (SGS). In step 904, the erase voltage pulse is applied to the NAND string of the block. In one embodiment of double-sided GIDL erasure, the erase voltage pulse is applied to the bit line and the source line. In one embodiment of single-sided GIDL erasure, the erase voltage pulse is applied to the source line. In another embodiment of single-sided GIDL erasure, the erase voltage pulse is applied to the bit line.

[0154] In step 906, erase verification is performed separately for each area of ​​the block being erased. Figure 4BIn the embodiment of the six regions 420, 430, 440, 450, 460 and 470 of , step 906 is first performed for region 420, then for region 430, then for region 440, then for region 450, then for region 460, and finally for region 470. In one embodiment, when performing erase verification for a region, the erase verification of the memory cells connected to the even word lines is performed separately from the erase verification of the memory cells connected to the odd word lines. That is, the control circuit will perform erase verification on those memory cells connected to the even word lines, but not on the memory cells connected to the odd word lines. Subsequently, the control circuit will perform erase verification on those memory cells connected to the odd word lines, but not on the memory cells connected to the even word lines. When performing erase verification on the memory cells connected to the even word lines, the even word lines will receive VCG_Vfy, and the odd word lines will receive Vread. The control circuitry will sense the NAND string (eg, using a sense amplifier) ​​to determine if enough current is flowing in order to verify that all memory cells of the NAND string have a voltage below the erase verify voltage (eg, Figure 5C When performing erase verification on memory cells connected to odd word lines, the odd word lines will receive VCG_Vfy and the even word lines will receive Vread. The control circuit will sense the NAND string to determine if enough current is flowing in order to verify that all memory cells of the NAND string have a threshold voltage below the erase verify voltage.

[0155] In step 910, the control circuit determines the status of the erase verification (from step 906). If all NAND strings have passed the erase verification of the odd word lines and the erase verification of the even word lines, the process will continue at step 912 and return to a "passed" status if the erase process is not complete. In some embodiments, if the number of NAND strings that have failed the erase verification is less than a first threshold, the control circuit will consider the verification process to have passed, and the process will also continue at step 912. If the number of NAND strings that have failed the erase verification is greater than the first threshold, the process will continue with step 914. In one embodiment, the first threshold is less than the number of bits that can be corrected by the ECC during the read process.

[0156] In step 914, the control circuit determines whether the number of erase voltage pulses is less than or equal to the maximum number of pulses. In one example, the maximum number is six pulses. In another example, the maximum number is 20 pulses. Other examples of maximum numbers may also be used. If the number of pulses is less than or equal to the maximum number, the control circuit will perform another cycle of the erase process (e.g., steps 902 to 918), which includes applying another erase voltage pulse. Therefore, the process will continue to increase the magnitude of the next erase voltage pulse at step 918 (e.g., increase the step size between 0.1 volts and .25 volts), and then the process will loop back to step 902 (e.g., Vera=Vera+step size). If it is determined in step 914 that the number of erase voltage pulses that have been applied in the current erase process is greater than the maximum number, the erase process fails (step 916) and the current block being erased exits any further use of the memory system.

[0157] It has been determined that in systems with more than two tiers, the inner tiers erase at a slower rate than the outer tiers, which can lead to issues with device reliability. Figure 4C and Figure 4D Level 1 of is erased at a slower rate than levels 0 and 2. Similarly, Figure 4K and Figure 4L Level 2 of the POSIX 2000 is erased at a slower rate than levels 1 and 3, and levels 1 and 3 are erased at a slower rate than levels 0 and 4. Fig. 9A and Fig. 9B This phenomenon is described in .

[0158] Fig. 9A Three levels (level 0, level 1, and level 2) of memory holes (vertical columns) are depicted with a bonding region between the levels. Levels 0 and 2 erase faster, while level 1 erases slower. Arrow 950 depicts holes generated from GIDL at the SGS transistor moving through the channel, and arrow 960 depicts holes generated from GIDL at the SGD transistor moving through the channel. Arrow 952 shows holes transferring from level 0 to level 1 by moving through the bonding region, resulting in fewer holes in the channel of level 1 (see arrow 954). Arrow 958 shows holes transferring from level 2 to level 1 by moving through the bonding region, resulting in fewer holes in the channel of level 1 (see arrow 956). Therefore, the bonding region reduces the GIDL efficiency of the inner level (level 1). Since there are fewer holes in level 1, erasure of memory cells in level 1 occurs slower than level 0 or level 2 (outer levels).

[0159] Fig. 9BFive levels (level 0, level 1, level 2, level 3, and level 4) of memory holes (vertical columns) are depicted with a bonding region between adjacent (neighboring) levels. Level 0 and level 4 erase quickly. Level 1 and level 3 erase slower than levels 0 / 4. Level 2 erases the slowest of the five levels depicted. In this example, levels 0 and level 4 are outer levels, while levels 1, level 2, and level 3 are inner levels. Level 2 is an intermediate level. Arrow 962 depicts holes generated from GIDL at the SGS transistor moving through the channel, and arrow 978 depicts holes generated from GIDL at the SGD transistor moving through the channel. Arrow 964 shows that holes are transferred from level 0 to level 1 by moving through the bonding region, resulting in fewer holes in the channel of level 1 (see arrow 966). Arrow 968 shows that holes are transferred from level 1 to level 2 by moving through the bonding region, resulting in fewer holes in the channel of level 2 (see arrow 969). Arrow 976 shows that holes are transferred from level 4 to level 3 by moving through the bonding region, resulting in fewer holes in the channel of level 3 (see arrow 974). Arrow 972 shows that holes are transferred from level 3 to level 2 by moving through the bonding region, resulting in fewer holes in the channel of level 2 (see arrow 970). Therefore, the bonding region reduces the GIDL efficiency of the inner levels (level 1, level 2, and level 3). Due to the presence of fewer holes in level 1 and level 3, the erasure of memory cells in level 1 and level 3 (inner levels) occurs slower than level 0 or level 4 (outer levels). Due to the presence of fewer holes in level 2, the erasure of memory cells in level 2 occurs slower than level 1 or level 3.

[0160] Differences in erase speeds can cause problems with device reliability. For example, over-erasure or under-erasure can cause programming errors after erasure. Additionally, erasing a level that is too slow can cause blocks to be incorrectly marked as bad blocks. Therefore, in order to achieve uniform erase speeds for three or more levels, the erase process includes: by applying a voltage bias greater than the voltage bias applied to the control gates of non-volatile memory cells in one or more internal levels to the control gates of non-volatile memory cells in the external levels, erasing three or more levels simultaneously using a GIDL erase process that transfers holes from the external levels to the internal levels through a bonding region, the GIDL erase process includes compensating for inherent erase speed differences between the levels to achieve uniform erase speeds for the three or more levels.

[0161] Fig.10 is a flow chart describing one embodiment of a process for simultaneously erasing three or more levels, the process including compensating for inherent erasing speed differences between the levels to achieve uniform erasing speed for the three or more levels. Fig.10The process may be performed by any of the control circuits discussed above. For example, Fig.10 The process can be completely handled by the memory die 200 (see Figure 2A ) or by the integrated memory component 207 (see Figure 2B ) rather than being executed by memory controller 120. In one example, the state machine 262 is executed or directed by the state machine 262 using other components of the system control logic component 260, the column control circuit 210, and the row control circuit 220. Fig.10 In another embodiment, Fig.10 The process is performed by the memory controller 120 or under its instruction.

[0162] In one embodiment, Fig.10 The process is Figure 8 An example implementation of step 902 is such that Fig.10 The steps are part of the erasure of nonvolatile memory cells. Fig.10 In step 1002, the control circuit applies an enable voltage to the select gates. For example, the control circuit may apply Vera-10v to SGS and SGD. In step 1004, the control circuit applies a voltage bias to the control gates of the non-volatile memory cells in the outer levels that is greater than the voltage bias applied to the control gates of the non-volatile memory cells in one or more inner levels. For example, for a three-level architecture, the control circuit may apply a larger voltage to the control gates of Level 0 and Level 2 than the smaller voltage applied to the control gate of Level 1. Similarly, for a five-level architecture, the control circuit may apply a larger voltage to the control gates of Level 0 and Level 4 than the smaller voltage applied to the control gates of Level 1, Level 3, and Level 4. The technology may also be applied to a four-level architecture or an architecture for more than five levels. In one embodiment, the control circuit is configured to apply a larger voltage bias to the control gates of nonvolatile memory cells in the outer level to produce a weaker gradient between the word line and the channel of the outer level, and to apply a smaller voltage bias to the control gates of nonvolatile memory cells in the inner level to produce a stronger gradient between the word line and the channel of the outer level (to compensate for fewer holes in the channel) so that the inner level can be erased at the same speed as the outer level.

[0163] Fig.11 is a flow chart describing one embodiment of a process for simultaneously erasing three or more levels, the process including compensating for inherent erasing speed differences between the levels to achieve uniform erasing speed for the three or more levels. Fig.11 The process is Fig.10 An example specific implementation of the process. Fig.11The process may be performed by any of the control circuits discussed above. For example, Fig.11 The process can be completely handled by the memory die 200 (see Figure 2A ) or by the integrated memory component 207 (see Figure 2B ) rather than being executed by memory controller 120. In one example, the state machine 262 is executed or directed by the state machine 262 using other components of the system control logic component 260, the column control circuit 210, and the row control circuit 220. Fig.11 In another embodiment, Fig.10 The process is performed by the memory controller 120 or under its instruction.

[0164] In one embodiment, Fig.11 The process is Figure 8 An example implementation of step 902 is such that Fig.11 The steps are part of the erasure of nonvolatile memory cells. Fig.11 In step 1102, the control circuit applies an enable voltage to SGS and SGD. In step 1004, the control circuit simultaneously erases the nonvolatile memory cells of three or more levels using a GIDL erase process that transfers holes from the outer level to the one or more inner levels through the coalescence region by applying a voltage bias to the control gates of the nonvolatile memory cells in the outer level that is greater than the voltage bias applied to the control gates of the nonvolatile memory cells in the one or more inner levels, the GIDL erase process including compensating for the inherent erase speed differences between the levels to achieve a uniform erase speed for the three or more levels.

[0165] Fig.12 is a flow chart describing one embodiment of a process for simultaneously erasing three or more levels, the process including compensating for inherent erasing speed differences between the levels to achieve uniform erasing speed for the three or more levels. Fig.12 The process is Fig.10 An example specific implementation of the process. Fig.12 The process may be performed by any of the control circuits discussed above. For example, Fig.12 The process can be completely handled by the memory die 200 (see Figure 2A ) or by the integrated memory component 207 (see Figure 2B ) rather than being executed by memory controller 120. In one example, the state machine 262 is executed or directed by the state machine 262 using other components of the system control logic component 260, the column control circuit 210, and the row control circuit 220. Fig.12 In another embodiment, Fig.10The process is performed by the memory controller 120 or under its instruction.

[0166] In one embodiment, Fig.12 The process is Figure 8 The example implementation of steps 902 and 904 is such that Fig.12 The steps are part of the erasure of nonvolatile memory cells. Fig.12 In step 1202, the control circuit applies an erase voltage to both ends of a connected group of nonvolatile memory cells, which are divided into three or more levels with a bonding region between each pair of adjacent levels. For example, Vera is applied to the source line and the bit line of the NAND string. In step 1204, the control circuit applies an enable voltage to the select gates at both ends of the connected group of nonvolatile memory cells. For example, the control circuit may apply Vera-10v to SGS and SGD. In step 1206, the control circuit applies a first voltage to the control gates of the nonvolatile memory cells in the first group of levels that are physically closer to the select gates. For example, with respect to a three-level architecture, levels 0 and 2 are closer to the select gate (compared to level 1) because levels 0 and 2 are adjacent to the select gate. With respect to a five-level architecture, levels 0 and 4 are closer to the select gate because they are adjacent to the select gate. In step 1206, the control circuit applies a second voltage to the control gates of non-volatile memory cells in a second group of one or more levels that are physically farther from the select gates than the first group of levels. The first voltage is greater than the second voltage. For example, with respect to a three-level architecture, level 1 is farther from the select gate, and with respect to a five-level architecture, levels 1 / 2 / 3 are farther from the select gate. By applying a lower voltage to levels farther from the select gate, a stronger gradient is created between the word line and the channel for levels farther from the select gate than for levels closer to the select gate. The stronger gradient between the word line and the channel results in a speed-up of the erase process for an inherently slower erase level.

[0167] FIG. 13A to FIG. 13C Provides a three-tier architecture Fig.10 , Fig.11 and / or Fig.12 An example specific implementation of the process. Fig.13A A graph of word line voltage versus word line position is depicted. Fig. 13B Three levels are depicted for a NAND string. Fig.13A and Fig. 13BDepicted as part of step 1004, step 1104, and / or steps 1206 / 1208, 0.5 volts are applied to the control gates of memory cells in level 0 (e.g., by applying 0.5v to WL0 through WL89), 0 volts are applied to the control gates of memory cells in level 1 (e.g., by applying 0v to WL90 through WL179), and 0.5 volts are applied to the control gates of memory cells in level 2 (e.g., by applying 0.5v to WL180 through WL269). Fig.12 In step 1206 / 1208, the first voltage is 0.5v and the second voltage is 0v. Fig.13A and Fig. 13B As a result of the different voltages depicted in , the three levels erase at the same speed. Note that Fig. 13B Only three control gates for data memory cells (shaded squares) and two control gates for dummy memory cells (unshaded squares) are shown to simplify the drawing, but in actual implementations each level has many more data memory cells.

[0168] Fig. 13B The diagram depicts a GIDL erase process using a transfer of holes from an outer layer to one or more inner layers through a bonding region, including compensating for inherent erase speed differences between the layers to achieve a uniform erase speed. Fig. 13B , arrow 950 depicts holes generated from GIDL at the SGS transistor moving through the channel, and arrow 1212 depicts holes generated from GIDL at the SGD transistor moving through the channel. Arrow 1304 shows holes transferring from level 0 to level 1 by moving through the coalescence region, resulting in fewer holes in the channel of level 1 (see arrow 1306). Arrow 1310 shows holes transferring from level 2 to level 1 by moving through the coalescence region, resulting in fewer holes in the channel of level 1 (see arrow 1308). However, due to the lower control gate voltage applied to level 1, the erase speed of level 1 is the same as the erase speeds of levels 0 and 2.

[0169] Fig. 13C A graph of word line voltage versus word line position for an alternative implementation is depicted. Rather than having all data memory cells of a level receive the same control gate voltage, the control gate voltage is varied to produce a continuous gradient. For example, the voltage applied to the control gate may be implemented using the following function:

[0170] Control gate voltage = f(min(distance to SG, distance to SGD)) [Equation A]

[0171] FIG. 14A to FIG. 14C Similar to FIG. 13A to FIG. 13C ; However, the voltage applied to the control gate is lower and in some cases negative. Using a lower voltage at the control gate allows the use of a lower Vera (the erase voltage applied to the bit line and source line). Using a lower Vera allows a less complex, smaller, and less expensive charge pump. Fig.14A and Fig. 14B Depicted as part of step 1004, step 1104, and / or steps 1206 / 1208, 0 volts are applied to the control gates of the memory cells in level 0 (e.g., by applying 0v to WL0 through WL89), -0.5 volts are applied to the control gates of the memory cells in level 1 (e.g., by applying -0.5v to WL90 through WL179), and 0 volts are applied to the control gates of the memory cells in level 2 (e.g., by applying 0v to WL180 through WL269). Fig.14A and Fig. 14B As a result of the different voltages depicted in , the three levels are erased at the same speed. Fig. 14C An alternative approach is depicted that includes applying a control gate voltage as a function of word line position (eg, Equation A) to produce a continuous gradient.

[0172] FIG. 15A to FIG. 15C Provides a five-level architecture Fig.10 , Fig.11 and / or Fig.12 An example specific implementation of the process. Fig.15A A graph of word line voltage versus word line position is depicted. Fig. 15B Five levels for a NAND string are depicted. Fig.15A and Fig. 15B Depicted as part of step 1004, step 1104, and / or steps 1206 / 1208 is the application of 1 volt to the control gates of memory cells in level 0 (e.g., by applying 1 v to WL0 through WL89), 0.5 volts to the control gates of memory cells in level 1 (e.g., by applying 0.5 v to WL90 through WL179), 0 volts to the control gates of memory cells in level 2 (e.g., by applying 0 v to WL180 through WL269), 0.5 volts to the control gates of memory cells in level 3 (e.g., by applying 0.5 v to WL270 through WL359), and 1 volt to the control gates of memory cells in level 4 (e.g., by applying 1 v to WL360 through WL449). Fig.12 In step 1206 / 1208, the first voltage is 1v and the second voltage is 0.5v or 0v. Fig.15A and Fig. 15B As a result of the different voltages depicted in , the three levels are erased at the same speed. Fig. 15C An alternative approach is depicted that includes applying a control gate voltage as a function of word line position (eg, Equation A) to produce a continuous gradient.

[0173] FIG. 16A to FIG. 16C Similar to FIG. 15A to FIG. 15C ; However, the voltage applied to the control gate is lower and in some cases negative. Fig.16A and Fig. 16B Depicted as part of step 1004, step 1104, and / or steps 1206 / 1208, 0 volts are applied to the control gates of the memory cells in tier 0 (e.g., by applying 0v to WL0 through WL89), -0.5 volts are applied to the control gates of the memory cells in tier 1 (e.g., by applying -0.5v to WL90 through WL179), -1 volt is applied to the control gates of the memory cells in tier 2 (e.g., by applying -1v to WL180 through WL269), -0.5 volts are applied to the control gates of the memory cells in tier 3 (e.g., by applying -0.5v to WL270 through WL359), and 0 volts are applied to the control gates of the memory cells in tier 4 (e.g., by applying 1v to WL360 through WL449). Fig.16A and Fig. 16B As a result of the different voltages depicted in , the three levels are erased at the same speed. Fig. 16C An alternative approach is depicted that includes applying a control gate voltage as a function of word line position (eg, Equation A) to produce a continuous gradient.

[0174] A nonvolatile memory system has been disclosed that simultaneously erases three or more levels using a GIDL erase process that transfers holes from an outer level to an inner level through a bonding region, the GIDL erase process including compensating for inherent erase speed differences between levels to achieve uniform erase speed for the three or more levels.

[0175] One embodiment includes a nonvolatile memory device, the nonvolatile memory device including: a plurality of nonvolatile memory cells, the plurality of nonvolatile memory cells being divided into three or more levels; and a control circuit connected to the nonvolatile memory cells, the three or more levels including an outer level and one or more inner levels. The control circuit is configured to: erase the nonvolatile memory cells by applying a voltage bias greater than a voltage bias applied to the control gates of the nonvolatile memory cells in the one or more inner levels to the control gates of the nonvolatile memory cells in the outer level.

[0176] In an example implementation, the plurality of nonvolatile memory cells are divided into five levels with a bonding region between each pair of adjacent levels; the five levels include two outer levels and three inner levels; the three inner levels include two middle levels and one center level; the control circuit is configured to: erase the nonvolatile memory cells by applying a first voltage bias to the control gates of the nonvolatile memory cells in the outer levels, applying a second voltage bias to the control gates of the nonvolatile memory cells in the middle levels, and applying a third voltage bias to the control gates of the center levels; the first voltage bias is greater than the second voltage bias; and the second voltage bias is greater than the first voltage bias.

[0177] One embodiment includes a method of erasing a nonvolatile memory device, the method comprising: applying an erase voltage to both ends of a connected group of nonvolatile memory cells, the connected group of nonvolatile memory cells being divided into three or more levels with a coupling region between each pair of adjacent levels; applying an enable voltage to select gates at both ends of the connected group of nonvolatile memory cells; applying a first voltage to control gates of nonvolatile memory cells in a first group of levels that are physically closer to the select gates; and applying a second voltage to control gates of nonvolatile memory cells in a second group of one or more levels that are physically farther from the select gates than the first group of levels, the first voltage being greater than the second voltage.

[0178] One embodiment includes a nonvolatile memory device comprising: a nonvolatile memory cell block arranged as a NAND string and divided into three or more levels with a coupling region between each pair of adjacent levels; and means for simultaneously erasing the three or more levels using a gate-induced drain leakage erase process that transfers holes from an outer level to an inner level through the coupling region, the gate-induced drain leakage erase process including compensating for inherent erase speed differences between the levels to achieve a uniform erase speed for the three or more levels.

[0179] Examples of means for simultaneous erasing include executing FIG. 9, Fig.10 and / or Fig.11 process (including Figure 7 and Figure 8 any or any combination of the memory controller 120 (including GIDL erase of the memory controller 120), the state machine 262, all or a portion of the system control logic unit 260, all or a portion of the row control circuit 220, all or a portion of the column control circuit 210, a microcontroller, a microprocessor and / or other similar functional circuits (including hardware only or a combination of hardware and software / firmware).

[0180] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0181] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via one or more intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected such that they are able to communicate electronic signals between them.

[0182] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0183] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0184] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0185] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A non-volatile storage device, comprising: a plurality of non-volatile memory cells, the plurality of non-volatile memory cells being divided into three or more tiers, the three or more tiers comprising an outer tier and one or more inner tiers; and A control circuit is connected to the nonvolatile memory cells, the control circuit being configured to erase the nonvolatile memory cells in the outer levels by applying a voltage bias to the control gates of the nonvolatile memory cells in the one or more inner levels that is greater than a voltage bias applied to the control gates of the nonvolatile memory cells in the one or more inner levels.

2. The nonvolatile storage device according to claim 1, further comprising: A bonding area includes a bonding area between each pair of adjacent levels.

3. The nonvolatile memory device according to claim 1, wherein: The control circuit is configured to simultaneously erase the nonvolatile memory cells of the three or more levels by applying a voltage bias to the control gates of the nonvolatile memory cells in the outer levels that is greater than a voltage bias applied to the control gates of the nonvolatile memory cells in the one or more inner levels.

4. The nonvolatile memory device according to claim 1, wherein: The control circuit is configured to simultaneously erase the nonvolatile memory cells in the three or more levels using a gate induced drain leakage erase process by applying a voltage bias to the control gates of the nonvolatile memory cells in the outer levels that is greater than a voltage bias applied to the control gates of the nonvolatile memory cells in one or more intermediate levels.

5. The nonvolatile storage device according to claim 1, further comprising: The bonding areas between the levels.

6. The nonvolatile memory device according to claim 5, wherein: The control circuit is configured to simultaneously erase the nonvolatile memory cells in the three or more levels using a gate induced drain leakage erase process that transfers holes from the outer levels to the one or more inner levels through the binding region by applying a voltage bias to the control gates of the nonvolatile memory cells in the outer levels that is greater than a voltage bias applied to the control gates of the nonvolatile memory cells in the one or more inner levels.

7. The nonvolatile memory device according to claim 5, wherein: The control circuit is configured to simultaneously erase the nonvolatile memory cells of the three or more levels using a gate induced drain leakage erase process that transfers holes from the outer level to the one or more inner levels through the binding region by applying a voltage bias to the control gates of the nonvolatile memory cells in the outer level that is greater than a voltage bias applied to the control gates of the nonvolatile memory cells in the one or more inner levels, the gate induced drain leakage erase process including compensating for inherent erase speed differences between the levels to achieve a uniform erase speed for the three or more levels.

8. The nonvolatile storage device according to claim 1, further comprising: A word line connected to the control circuit and the nonvolatile memory cells, the nonvolatile memory cells being arranged as a NAND string each having a channel, the control circuit being configured to apply the larger voltage bias to control gates of the nonvolatile memory cells in the outer tiers to produce a weaker gradient between the word line and the channel for the outer tiers as compared to one or more inner tiers.

9. The nonvolatile memory device according to claim 1, wherein: The plurality of non-volatile memory cells are arranged as a connected memory cell group having two ends; The control circuit is configured to apply a voltage bias to the control gates of the nonvolatile memory cells in the outer levels that is greater than a voltage bias applied to the control gates of the nonvolatile memory cells in the one or more intermediate levels by applying different voltages to the control gates of the nonvolatile memory cells based on the distance to the closest ends of the two ends.

10. The nonvolatile memory device according to claim 1, wherein: The voltage applied to the control gates of the nonvolatile memory cells in the one or more intermediate levels is biased to a negative voltage.

11. The nonvolatile memory device according to claim 1, wherein: The control circuit is configured to apply the larger voltage bias to all control gates of the nonvolatile memory cells in the outer level.

12. The nonvolatile memory device according to claim 1, wherein: The plurality of nonvolatile memory cells are divided into five levels with a bonding region between each pair of adjacent levels; The five levels include two outer levels and three inner levels; The three internal levels include two intermediate levels and one central level; The control circuit is configured to: erase the nonvolatile memory cells by applying a first voltage bias to control gates of the nonvolatile memory cells in the outer level, applying a second voltage bias to control gates of the nonvolatile memory cells in the middle level, and applying a third voltage bias to control gates in the center level; The first voltage bias is greater than the second voltage bias; and The second voltage bias is greater than the first voltage bias.

13. The nonvolatile memory device according to claim 1, wherein: The plurality of nonvolatile memory cells include nonvolatile memory cell blocks arranged as NAND strings and divided into three or more levels with a coupling region between each pair of adjacent levels.

14. A method for erasing a non-volatile storage device, the method comprising: applying an erase voltage across a group of connected nonvolatile memory cells, the group of connected nonvolatile memory cells being divided into three or more levels with a bonding region between each pair of adjacent levels; applying an enable voltage to select gates at both ends of the connected group of nonvolatile memory cells; applying a first voltage to control gates of nonvolatile memory cells in a first set of levels that are physically closer to the select gates; as well as A second voltage is applied to control gates of nonvolatile memory cells in a second set of one or more levels that are physically farther from the select gates than the first set of levels, the first voltage being greater than the second voltage.

15. The method according to claim 14, wherein: The connected group of nonvolatile memory cells includes a block of nonvolatile memory cells arranged as NAND strings and divided into three or more levels with a bonding region between each pair of adjacent levels; and Applying the first voltage and applying the second voltage are performed simultaneously during a gate induced drain leakage erase process of transferring holes from an outer level to an inner level through the coupling region, the gate induced drain leakage erase process including compensating for inherent erase speed differences between the levels to achieve a uniform erase speed for the three or more levels.

16. The method according to claim 14, further comprising: A third voltage is applied to control gates of nonvolatile memory cells in a third set of one or more levels that are physically farther from the select gates than the second set of one or more levels, the second voltage being greater than the third voltage.

17. The method of claim 14, wherein: The second voltage is a negative voltage.

18. A non-volatile storage device, comprising: a block of nonvolatile memory cells arranged as NAND strings and divided into three or more levels with a bonding region between each pair of adjacent levels; and Means for simultaneously erasing the three or more levels using a gate induced drain leakage erase process that transfers holes from the outer level to the inner level through the coalescence region, the gate induced drain leakage erase process including compensating for inherent erase speed differences between the levels to achieve a uniform erase speed for the three or more levels.

19. The non-volatile memory device according to claim 18, wherein: The nonvolatile memory cell block is divided into five levels with a bonding area between each pair of adjacent levels.

20. The nonvolatile memory device according to claim 18, wherein: The means for simultaneously erasing includes applying a negative control gate voltage to one or more inner levels of the three or more levels during the gate induced drain leakage erase process.

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