Electronic device and control method

Abstract

The present application discloses an electronic device and a control method, which relate to the field of control. The electronic device comprises: a microcontroller and a processing core; the microcontroller counts operating parameters of the processing core executing instructions, and controls and adjusts the frequency of the processing core based on whether the operating parameters of the processing core executing instructions meet a trigger condition; wherein, at least when a frequency reduction strategy is adopted to control and adjust the frequency of the processing core, the performance loss of the processing core is monitored during the frequency reduction process, and the frequency reduction strategy is adjusted based on the performance loss.

Description

Technical Field

[0001] The present application relates to the field of control, and in particular to an electronic device and a control method. Background Art

[0002] The dynamic power consumption of a processor is linearly related to its clock frequency. As the processor's implementation frequency gets higher and higher, the dynamic power consumption also increases accordingly.

[0003] To address the issue of increased processor power consumption, the DVFS (Dynamic voltage and frequency scaling) solution is currently generally adopted. The software uses the proportion of past program tasks in the processor's working events and the corresponding tasks to determine the processor's load ratio within a time window, and further uses the load ratio as an indicator to adjust the processor's operating frequency and operating voltage for a period of time thereafter to achieve the purpose of reducing power consumption.

[0004] However, the existing software DVFS cannot know the internal state of the processor, the adjustment scheme has low accuracy, and the voltage and frequency adjustment takes a long time. Summary of the invention

[0005] A first aspect of the present application provides an electronic device, including:

[0006] Microcontrollers and processing cores;

[0007] The microcontroller counts the operating parameters of the processing core executing the instruction, and controls and adjusts the frequency of the processing core based on whether the operating parameters of the processing core executing the instruction meet the trigger condition;

[0008] At least when the frequency reduction strategy is adopted to control and adjust the frequency of the processing core, the performance loss of the processing core is monitored during the frequency reduction process, and the frequency reduction strategy is adjusted based on the performance loss.

[0009] In a possible implementation, the microcontroller includes a statistical module, a frequency modulation control module and a configuration module;

[0010] The statistical module includes at least two statistical units, and the frequency modulation control module includes at least two frequency modulation control elements, and the statistical units and the frequency modulation control elements are arranged corresponding to the processing core;

[0011] The statistical unit counts the operation parameters of the instructions executed by the corresponding processing core;

[0012] The configuration module configures a target frequency modulation parameter based on that the operating parameter of the instruction executed by the first processing core meets the trigger condition, and sends the target frequency modulation parameter to a target frequency modulation control element, the target frequency modulation control element is a frequency modulation control element corresponding to the first processing core, and the first processing core is any one of the at least one processing core of the electronic device;

[0013] The target frequency modulation control element generates a control signal based on the target frequency modulation parameter, and the control signal is used to adjust the frequency of the first processing core.

[0014] In a possible implementation, the operating parameter includes the number of pause signals inside the processing core.

[0015] In a possible implementation, the method further includes:

[0016] The first trigger module is used to determine whether a trigger condition is met based on the number of pause signals inside the processing core obtained within a first preset time window; and trigger the configuration module based on the first trigger condition being met.

[0017] In a possible implementation, the method further includes:

[0018] The second trigger module is used to determine the proportion of the first duration in the first preset time window, where the first duration is the waiting time when the processing core executes instructions; based on the fact that the duration proportion is greater than a preset proportion threshold, it is determined that the first duration meets the triggering second condition, thereby triggering the configuration module.

[0019] In a possible implementation, the first duration is determined based on the number of pause signals inside the processing core acquired within a first preset time window.

[0020] In a possible implementation, it further includes: a function control module;

[0021] The processing core includes at least two execution units;

[0022] The function control module is used to determine a control strategy based on the operating status of the processing core and when the number of target execution units currently in operation in the processing core does not match the operating status, the control strategy is used to control the number of target execution units in operation to match the operating status of the processing core.

[0023] In a possible implementation, each execution unit in the processing core performs a data processing task based on an instruction;

[0024] Correspondingly, the function control module is used to determine the proportion of the target type instructions in the instructions received in the second preset time window based on the number of target type instructions received in the second preset time window, and the proportion represents the operating status of the processing core. The target execution unit is used to execute the target type instructions.

[0025] A second aspect of the present application provides a control method, which is applied to a microcontroller in an electronic device, wherein the electronic device is provided with a processing core, and the method comprises:

[0026] Statistical processing core execution instruction operating parameters;

[0027] adjusting the frequency of the processing core based on an operating parameter of the processing core satisfying a trigger condition;

[0028] At least when the frequency reduction strategy is adopted to control and adjust the frequency of the processing core, the performance loss of the processing core is monitored during the frequency reduction process, and the frequency reduction strategy is adjusted based on the performance loss.

[0029] In a possible implementation, adjusting the frequency of the processing core based on an operating parameter of the processing core satisfying a trigger condition includes:

[0030] Based on the running parameters of the processing core executing the instruction satisfying the triggering conditions, the target frequency modulation parameters are configured;

[0031] Determine a frequency modulation mode based on a first operating parameter of the processing core in a current first preset time window and a second operating parameter of the processing core in a previous first preset time window, wherein the frequency modulation mode includes up-frequency adjustment and down-frequency adjustment;

[0032] If the difference between the first operating parameter and the second operating parameter meets the frequency reduction condition, determine the frequency reduction strategy according to the target frequency modulation parameter; control the frequency reduction of the processing core based on the frequency reduction strategy, and the frequency reduction strategy at least includes the frequency reduction step size and the number of frequency reduction executions;

[0033] If the difference between the first operating parameter and the second operating parameter meets the frequency increase condition, determine the frequency increase strategy according to the target frequency adjustment parameter; control the frequency increase of the processing core based on the frequency increase strategy, and the frequency increase strategy at least includes the frequency increase step size and the number of frequency increase executions.

[0034] In a possible implementation, monitoring the performance loss of the processing core during the frequency reduction process and adjusting the frequency reduction strategy based on the performance loss includes:

[0035] Based on the frequency reduction step size in the frequency reduction strategy, the frequency reduction of the processing core is controlled according to the number of frequency reduction executions;

[0036] Wherein, after the frequency reduction step is adopted each time to control the processing core frequency to be reduced, a third operating parameter before the frequency reduction and a fourth operating parameter after the frequency reduction are obtained based on a third preset time window, and the third preset time window is smaller than the first preset time window;

[0037] Determining a performance loss of frequency reduction based on a third operating parameter and a fourth operating parameter;

[0038] Based on the performance loss corresponding to the Nth frequency reduction being greater than a specific loss threshold, the frequency reduction strategy is stopped, and the frequency before the Nth frequency reduction is used to control the operation of the processing core, where N is a positive integer.

[0039] In a possible implementation, after adjusting the frequency of the processing core based on the operating parameter of the processing core satisfying the trigger condition, the method further includes:

[0040] The number of target type instructions received by the counting processing core in the second preset time window;

[0041] Based on the number, determining a proportion of the target type instructions in the instructions received in the second preset time window;

[0042] Based on the ratio and the number of target execution units currently in operation, a control strategy is determined, wherein the control strategy is used to control the number of target execution units in operation in the processing core to match the target type instructions, and the target execution units are used to execute the target type instructions.

[0043] In a possible implementation, determining a control strategy based on the ratio and the number of target execution units currently in operation includes:

[0044] Based on the ratio being less than a specific ratio threshold, controlling the number of target execution units currently in operation in the processing core to decrease;

[0045] Based on the ratio being greater than a specific ratio threshold, the number of target execution units currently in operation in the processing core is controlled to increase.

[0046] A third aspect of the present application provides a computer program product, including computer-readable instructions. When the computer-readable instructions are executed on an electronic device, the electronic device implements the control method of the second aspect or any implementation manner of the second aspect.

[0047] A fourth aspect of the present application provides a computer storage medium, which carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement the control method of the second aspect or any implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0049] Figure 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0050] Figure 2 is a schematic diagram of the structure of a microcontroller provided in an embodiment of the present application;

[0051] Figure 3 is another structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0052] Figure 4 is another structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0053] Figure 5 It is a structural schematic diagram of an electronic device in an application scenario provided by an embodiment of the present application;

[0054] Figure 6 It is a structural diagram of a frequency output module in an application scenario provided by an embodiment of the present application;

[0055] Figure 7 is another structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0056] Figure 8 is another structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0057] Fig. 9 is another structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0058] Fig.10 is a schematic diagram of a structure for controlling a processing core provided by an embodiment of the present application;

[0059] Fig.11 It is a flow chart of a control method provided in an embodiment of the present application;

[0060] Fig.12 It is a flowchart of adjusting the frequency of a processing core based on an operating parameter of the processing core satisfying a trigger condition provided by an embodiment of the present application;

[0061] Fig.13 It is a schematic diagram of a frequency modulation process for a processing core of an electronic device in an application scenario provided by an embodiment of the present application;

[0062] Fig.14is a schematic diagram of a process flow of controlling the frequency reduction of a processing core based on the frequency reduction strategy provided in an embodiment of the present application;

[0063] Fig.15 is another schematic diagram of a frequency modulation process for a processing core of an electronic device in an application scenario provided by an embodiment of the present application;

[0064] Fig.16 It is a schematic diagram of a process for reducing power consumption by controlling the processing core provided by an embodiment of the present application;

[0065] Fig.17 This is another structural schematic diagram of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0066] The following describes the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.

[0067] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0068] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0069] Figure 1 1 is a schematic diagram of a structure of an electronic device provided by an embodiment of the present application, the electronic device comprising: a microcontroller 101 and a processing core 102;

[0070] Among them, the electronic device has multiple processing cores, each of which can perform processing tasks independently or cooperate with each other to perform processing tasks. The specific functions of the processing cores are not limited in this application. At present, the processors of most electronic devices have multiple processing cores. The embodiments of this application take multiple processing cores as an example, and do not exclude the situation where the electronic device has only a single processing core.

[0071] As an example, the electronic device may use a CPU (central processing unit), and the number of processing cores in the CPU may be two or even more. This application does not limit the specific number and specific type of processing cores contained in the electronic device.

[0072] The microcontroller 101 counts the operating parameters of the processing core 102 executing instructions, and controls and adjusts the frequency of the processing core 102 based on whether the operating parameters of the processing core 102 executing instructions meet the triggering condition.

[0073] At least when the frequency reduction strategy is adopted to control and adjust the frequency of the processing core, the performance loss of the processing core is monitored during the frequency reduction process, and the frequency reduction strategy is adjusted based on the performance loss.

[0074] The microcontroller 101 can collect statistics on the operating parameters of the processing core executing instructions, and the operating parameters of the processing core 102 executing instructions represent the internal state of the electronic device during operation.

[0075] Accordingly, after counting the operating parameters of the processing core 102 executing instructions, the microcontroller 101 determines whether the operating parameters of the processing core 102 meet the trigger condition, and controls and adjusts the frequency of the processing core 102 based on whether the operating parameters of any processing core 102 meet the trigger condition.

[0076] Among them, the microcontroller 101, as a hardware structure in an electronic device, can be connected to each processing core through a line, relative to the software DVFS, and obtain the operating parameters when executing instructions in each processing core, thereby ensuring that the internal state of the processor is known during the process of controlling the frequency of the processing core, and the adjustment plan determined according to the state of each processing core inside the processor has a higher accuracy.

[0077] In a possible implementation, the microcontroller sets an independent statistics unit and a frequency modulation control unit for each processing core. Figure 2 The structure of the microcontroller is described in detail.

[0078] Furthermore, when the microcontroller controls and adjusts the frequency of the processing core, it may adopt a frequency reduction strategy to control and adjust the frequency of the processing core, or it may adopt a frequency increase strategy to control the frequency of the processing core.

[0079] Among them, the operating parameters of the execution instruction may include the current frequency, the number of instructions, the memory stall cycle, etc. The specific content of the operating parameters is not limited in this application.

[0080] Different processing cores may use different or the same frequencies, the number of instructions may be the number of instructions obtained in a set detection time window, and the memory stall cycle is the duration of stalling when requesting data from the memory.

[0081] In a specific implementation, the microcontroller may adopt a rsicv (reduced instruction set computer-V) core.

[0082] In a possible implementation, the processing core includes multiple execution units, each of which can execute instructions independently. After adjusting the frequency of the processing core, the number of execution units in the running state can also be controlled. The control process of the execution units in the processing core is implemented by a functional control module. Figure 6 The structure of an electronic device including a functional control module is described in the specification.

[0083] In this embodiment, a microcontroller is provided in the electronic device. The microcontroller is capable of counting operating parameters of a processing core in the electronic device for executing instructions, and controlling and adjusting the frequency of the processing core based on whether the operating parameters of the processing core for executing instructions satisfy a trigger condition, thereby realizing control of the processing core in the electronic device. A separate hardware structure such as a microcontroller is used to count the state of the processing core inside the processor and control the frequency of the processing core. The response speed of the hardware circuit is faster than the response speed of the software process. The frequency is directly controlled based on the state of the internal processing core of the processor, and the accuracy of adjusting the frequency is high. Moreover, at least when a frequency reduction strategy is adopted to control and adjust the frequency of the processing core, the performance loss of the processing core is monitored during the frequency reduction process, and the frequency reduction strategy is adjusted based on the performance loss, thereby realizing timely adjustment of the frequency reduction strategy during the frequency reduction process, and being able to meet the performance requirements of load or instruction processing in a timely manner.

[0084] Figure 2 20 is a schematic diagram of the structure of a microcontroller provided in an embodiment of the present application, wherein the microcontroller includes a statistical module 201, a frequency modulation control module 202 and a configuration module 203;

[0085] The statistical module 201 includes a statistical unit 2011, and the frequency modulation control module 202 includes a frequency modulation control element 2021. The statistical unit 2011 and the frequency modulation control element 2021 are set corresponding to the processing core to be frequency modulated; taking an electronic device having multiple processing cores as an example, the corresponding statistical module 201 includes at least two statistical units 2011, and the frequency modulation control module 202 includes at least two frequency modulation control elements 2021, and each statistical unit 2011 and each frequency modulation control element 2021 are respectively set corresponding to the corresponding processing core.

[0086] The statistical unit 2011 is used to count the operation parameters of the corresponding processing core executing the instruction;

[0087] The statistical module 201 includes a plurality of statistical units 2011, and the statistical units 2011 are arranged in one-to-one correspondence with the processing cores. The statistical units collect statistics on the operating parameters of the instructions executed by the corresponding processing cores.

[0088] The frequency modulation control module 202 includes a plurality of frequency modulation control elements 2021 , and the frequency modulation control elements 2021 are arranged in a one-to-one correspondence with the processing cores, and the frequency modulation control elements 2021 adjust the frequency of the corresponding processing cores.

[0089] The frequency adjustment for the processing core may be a dynamic frequency adjustment (DFS, dynamic frequency scale) to achieve dynamic adjustment for the running processing core and reduce its power consumption.

[0090] In a possible implementation, the statistical unit 2011 counts the operating parameters of the execution instructions according to a set time window.

[0091] The operating parameter is a parameter that can reflect the processing state of the electronic device, and the parameter is related to power consumption.

[0092] For example, when the load of the processing core is too large, it is unable to process the received instructions in time.

[0093] In a possible implementation, the operating parameter may include a parameter of a pause signal within the processing core, specifically, the number of pause signals. In a subsequent embodiment, a first trigger module is provided in the electronic device to process the operating parameter and trigger the configuration module. The pause signal is triggered when the instruction cannot be processed in time.

[0094] In a possible implementation, the operating parameter may also be the waiting time when the processing core executes the instruction. In a subsequent embodiment, a second trigger module is set in the electronic device to process the operating parameter and trigger the configuration module. The waiting time includes the waiting time of the instruction corresponding to the pause signal.

[0095] The pause signal may be a signal sent by the processing core during operation, which may cause at least some instructions to be in a paused processing state to wait for completion of related instructions.

[0096] In a possible implementation, the pause signal may include a stall signal, or other signals that indirectly reflect the stall. Of course, any parameter that can characterize the power consumption of the processing core may be used as an operating parameter.

[0097] Among them, in a pipeline computer, instructions flow through the central processing unit (CPU) in stages. For example, there may be a stage for each step of the von Neumann cycle: get instructions, get operands, execute instructions, write results. Pipeline computers usually have "pipeline registers" after each stage. These store information from instructions and calculations so that the logic gates at the next level can perform the next step. Instruction data is usually passed from one stage to the next in pipeline registers, and each stage has some separate control logic. The control unit also ensures that the instructions at each stage do not harm the operation of instructions at other stages. For example, if two stages must use the same block of data, the control logic ensures that the use is completed in the correct order. When running efficiently, the pipeline computer will have an instruction at each stage. Then it processes all of these instructions at the same time. It can complete about one instruction in each cycle of its clock. But when the program switches to a different instruction sequence, the pipeline sometimes has to discard the data being processed and restart. This is called "stall."

[0098] Correspondingly, the stall is caused by resource competition or dependency between instructions, which results in the inability to continue executing the next instruction. The longer the stall of a processing core and the more times it stalls, the greater the invalid dynamic power consumption of the processing core caused by the stall.

[0099] Therefore, when the processing core of an electronic device is stalled due to access, the subsequent programs in the processing core that need to rely on the access results for calculations cannot be executed in the processing core. At this time, running the CPU at a higher frequency will not bring any benefits. On the contrary, a higher frequency will cause corresponding dynamic power consumption. Therefore, it is necessary to reduce the frequency of the processing core to save the corresponding dynamic power consumption.

[0100] In the scheme of the present application, the microcontroller counts the operating parameters of the processing core executing instructions, especially the operating parameters of the pause signal, in order to determine the load of the processing core, especially the situation where the instruction is paused. Usually, when the load is large, it is required to increase the system operating frequency, and when the load is small, the frequency should be reduced; and for the scheme of the present application, when the operating parameters of the pause signal represent that the system pause duration accounts for a large proportion, or when the number of provisional signals is large, the frequency should be reduced to reduce invalid power consumption losses. When the load is large, due to the large number of instructions, resource competition and dependency increase, and more pause signals may be generated. Based on this scheme, the frequency reduction processing will be performed in the time period when the pause signal is generated more. At the same time, through the monitoring of the frequency reduction stage, the frequency reduction strategy is adjusted in time to meet the performance requirements of load or instruction processing while reducing invalid power consumption losses.

[0101] As an example, the operating parameter uses information about CPU processing core stalling due to memory access. CPU stalling during operation means that when the CPU is executing instructions, the required data is not in the register or cache (memory), and the CPU needs to load data from the memory. During this period, the CPU will enter a waiting state, that is, a stall state. Of course, memory access is one reason for the processing core stalling. This is just an example. The reason for the processing core stalling can also be other reasons, and it is not used to limit the specific content of the operating parameters.

[0102] For example, the signal that indirectly reflects stall can be IPC (Instructions Per Cycle), which is a core metric used to measure CPU performance. If the IPC value is less than 1.0, it is likely that memory access (Memory stall) is dominant, RCU (Read-Copy-Update) related stall warnings, etc.

[0103] In a possible implementation, a trigger module is set in the microcontroller, and the trigger module determines whether the trigger condition is met according to the operating parameters obtained by the statistics of each statistical unit, and triggers the configuration module when the trigger condition is met. Figure 3 The functions of the electronic device including the trigger module are described in detail.

[0104] The configuration module 203 configures target frequency modulation parameters based on the operation parameters of the first processing core executing the instruction satisfying the trigger condition, and sends the target frequency modulation parameters to the target frequency modulation control element, which is the frequency modulation control element 2021 corresponding to the first processing core;

[0105] The first processing core is any one of at least one processing core of the electronic device.

[0106] When the operating parameters of the instruction executed by the first processing core in the electronic device meet the triggering conditions, the target frequency modulation parameters are configured for the first processing core.

[0107] The frequency modulation control element 2021 is pre-set with a frequency modulation scheme, and the frequency modulation scheme is set with relevant configuration strategies, such as the frequency of the processing core in different time periods, the frequency used by the processing core in different operating states of the electronic device, etc.

[0108] The trigger condition may indicate that the power consumption of the first processing core is too high. For example, the statistical number of stagnation information of the processing core in the operating parameters is greater than a set number threshold, or the duration of the stagnation information in the operating parameters is greater than a set duration threshold.

[0109] Among them, when the operating parameters of the first processing core executing the instruction meet the trigger conditions, the configuration module 203 reconfigures and adjusts the parameters in the frequency modulation scheme of the first processing core so that the operating parameters of the first processing core executing the command no longer meet the trigger conditions, thereby achieving the purpose of reducing the power consumption of the processing core.

[0110] The configuration module 203 specifically adjusts and configures the parameters in the frequency modulation scheme, and sends the adjusted parameters to the corresponding frequency modulation control element 2021 .

[0111] If the parameters of the command executed by the first processing core meet the triggering condition, the configuration module 203 configures the target frequency modulation parameters for the first processing core and sends the target frequency modulation parameters to the frequency modulation control element corresponding to the first processing core.

[0112] The target frequency modulation control element generates a control signal based on the target frequency modulation parameter, and the control signal is used to adjust the frequency of the first processing core.

[0113] The electronic device is provided with a frequency output module, and the frequency output module is used to output a frequency to the processing core to instruct the processing core to operate at the output frequency.

[0114] Correspondingly, the control signal generated by the target frequency modulation control element is sent to the frequency output module, and the frequency output module changes the output frequency to achieve the purpose of frequency modulation.

[0115] Each processing core corresponds to a frequency modulation control element, and the target frequency modulation control element is the frequency modulation control element corresponding to the first processing core.

[0116] Among them, each frequency modulation control element is provided with a frequency modulation scheme, and can generate a control signal for the corresponding processing core based on the frequency modulation scheme, so as to realize frequency modulation for the processing core using the control signal.

[0117] The target frequency modulation parameters may include a preset time window, a frequency modulation strategy level, execution times, etc. The frequency modulation strategy level corresponds to the frequency modulation step length. The higher the frequency modulation strategy level, the larger the frequency modulation step length. Conversely, the lower the frequency modulation strategy level, the smaller the frequency modulation step length.

[0118] In a possible implementation, the target frequency modulation parameter may be sent to the frequency output module in the form of a control signal, so that the frequency output module performs frequency modulation for the execution times using the frequency modulation step.

[0119] The frequency modulation strategy includes: a frequency modulation process and a stop process. In the frequency modulation process, the frequency increase strategy or frequency reduction strategy is determined based on the difference in operating parameters in adjacent time windows, and the step size and execution times in the frequency increase / decrease strategy are set based on the target frequency modulation parameters configured by the aforementioned configuration module, and the frequency increase / decrease is performed on the corresponding processing core based on the step size and execution times.

[0120] The gap may be the difference between similar parameters in the operating parameters of adjacent time windows, the gap may be the ratio between similar parameters in the operating parameters of adjacent time windows, or the ratio between the difference between similar parameters and other types of parameters.

[0121] As an example, the gap may take the form of a ratio of the reduced frequency of the processing core to a change in the number of instructions received.

[0122] In a possible implementation, a first preset time window may be pre-set as a determination period of the frequency modulation strategy, and whether the processing core needs to adjust the frequency is determined based on the period.

[0123] In a specific implementation, the frequency modulation control element 2021 determines the frequency modulation mode based on the first operating parameter of the first processing core in the current first preset time window and the second operating parameter in the previous first preset time window; if the difference between the first operating parameter and the second operating parameter meets the frequency reduction condition, the frequency reduction strategy is determined according to the target frequency modulation parameter; the frequency of the first processing core is controlled to be reduced based on the frequency reduction strategy, and the frequency reduction strategy at least includes the frequency reduction step size and the number of frequency reduction executions; if the difference between the first operating parameter and the second operating parameter meets the frequency increase condition, the frequency increase strategy is determined according to the target frequency modulation parameter; the frequency of the first processing core is controlled to be increased based on the frequency increase strategy, and the frequency increase strategy at least includes the frequency increase step size and the number of frequency increase executions.

[0124] The first preset time window is used as a determination period of the frequency modulation strategy, and the frequency modulation mode is determined based on the operating parameters of the first preset time window.

[0125] Among them, the statistical unit corresponding to the processing core performs parameter statistics for the processing core according to the first preset time window, and the frequency modulation control element 2021 compares the first operating parameter of the current first preset time window with the second operating parameter of the previous first preset time window to determine whether the difference between the two meets the frequency increase condition or the frequency reduction condition. If neither condition is met, no frequency modulation processing is performed. If the frequency increase condition is met, the frequency increase strategy is determined according to the target frequency modulation parameters of the configuration module. If the frequency reduction condition is met, the frequency reduction strategy is determined according to the target frequency modulation parameters of the configuration module.

[0126] The previous first preset time window is a time window before the current first preset time window. In this time window, a frequency increase process may be executed, a frequency decrease process may be executed, or the frequency may not be changed.

[0127] In the current first preset time window, a frequency increase process may be executed, a frequency decrease process may be executed, or the frequency may not be changed.

[0128] In a possible implementation, a frequency range of frequency modulation is preset, and during the frequency up-conversion process, the frequency reached by the frequency up-conversion cannot be greater than the upper limit of the frequency range, and during the frequency down-conversion process, the frequency reached by the frequency down-conversion cannot be less than the lower limit of the frequency range.

[0129] In a possible implementation, during the frequency upscaling process, if the frequency upscaling is performed according to the frequency upscaling step size, and the frequency of the processing core has reached the upper limit before the actual number of frequency upscaling executions reaches the upper limit, the frequency upscaling is stopped and the processing core is controlled to run at the upper limit of the frequency range.

[0130] Since the frequency reduction process will reduce the frequency of the processing core, and the reduction in the frequency of the processing core means a reduction in the processing speed of the processing core, which may affect the performance of the processing core, the gradual frequency reduction method is adopted to control the gradual reduction of the performance of the processing core. Therefore, in the process of executing the frequency reduction, it is necessary to determine the performance loss of this frequency reduction each time the frequency reduction is executed, and make timely adjustments to ensure that the performance of the processing core will not drop significantly.

[0131] In a possible implementation, a third preset time window is pre-set as a monitoring period of the frequency reduction strategy, and the performance loss of the processing core is monitored based on the third preset time window.

[0132] Among them, the target frequency modulation control element is specifically used to: based on the frequency reduction step in the frequency reduction strategy, control the frequency reduction of the corresponding processing core according to the number of frequency reduction executions; wherein, after each frequency reduction step is adopted to control the frequency reduction of the first processing core, based on the third preset time window, obtain the third operating parameter before the frequency reduction and the fourth operating parameter after the frequency reduction, and the third preset time window is smaller than the first preset time window; determine the performance loss of the frequency reduction based on the third operating parameter and the fourth operating parameter; based on the performance loss corresponding to the Nth frequency reduction being greater than a specific loss threshold, stop executing the frequency reduction strategy, and use the frequency before the Nth frequency reduction to control the operation of the first processing core, where N is a positive integer.

[0133] The process of determining the frequency reduction performance loss based on the third preset time window is implemented following the frequency reduction process, and the process of determining the frequency reduction performance loss is started when the frequency reduction process is started.

[0134] In a possible implementation, the number of detections may be set. After each frequency reduction step, the number of times for detecting performance loss may be set, so that the performance loss of the processing core may be detected using the third preset time window according to the set number of times.

[0135] In a possible implementation, the target frequency modulation parameters may include a first preset time window, a third preset time window, a frequency modulation level, a frequency increase / decrease execution number, a specific loss threshold, etc.

[0136] Each time window in this embodiment may be at the level of hundreds of nanoseconds (ns).

[0137] In a possible implementation, a system register is used in the electronic device to configure various parameters.

[0138] As an example, the system registers include a full processing core frequency modulation enable register, a single processing core frequency modulation enable register, a processing core frequency modulation level control register, a frequency modulation time window configuration register, a frequency modulation threshold control register, a correction time window configuration register, and a correction frequency modulation threshold control register.

[0139] Among them, when the frequency modulation enable register of all processing cores is assigned an enable signal, the frequency modulation of all processing cores is triggered; when the frequency modulation enable register of a single processing core is assigned an enable signal, the frequency modulation of the corresponding processing core is triggered; the processing core frequency modulation level controller is used to store the frequency modulation level for the corresponding processing core, and different frequency modulation levels correspond to different frequency modulation steps; the frequency modulation time window configuration register corresponds to the aforementioned first preset time window; the frequency modulation threshold controller is used to configure the upper and lower limits of the processing core frequency during the frequency modulation process; the correction time window configuration register is used to store the time window used in the correction process; the correction frequency modulation threshold control register is used to configure the upper and lower limits of the processing core frequency during the correction process.

[0140] Among them, the correction time window is the third preset time window corresponding to the aforementioned determination of frequency reduction performance loss, and the correction frequency modulation threshold corresponds to the upper and lower limits of frequency reduction within the third preset time window when the third preset time window is used to determine the performance loss during the aforementioned frequency reduction process.

[0141] When each frequency modulation control element performs frequency reduction on its corresponding processing core, the target frequency modulation control element may be used to execute the function.

[0142] In this embodiment, each statistical unit in the statistical module of the microcontroller respectively counts the operating parameters of the execution instructions of its corresponding processing core. The configuration module of the microcontroller configures the target frequency modulation parameters based on the operating parameters of the execution instructions of the first processing core satisfying the trigger conditions, and sends the target frequency modulation parameters to the target frequency modulation control element. The target frequency modulation control element is a frequency modulation control element corresponding to the first processing core among multiple frequency modulation control units in the frequency modulation control module of the microcontroller; the target frequency modulation control element adjusts the frequency of the first processing core based on the target frequency modulation parameters. The microcontroller sets an independent statistical unit and a frequency modulation control unit for each processing core in the electronic device. Each structure in the microcontroller adjusts the frequency according to the operating status of the processing core, thereby realizing independent control of each processing core in the electronic device and improving the control effect.

[0143] Figure 3 is another structural schematic diagram of an electronic device provided by an embodiment of the present application, the electronic device comprising: a microcontroller 301, a first trigger module 302 and a processing core 303;

[0144] The microcontroller includes a statistics module 3011, a frequency modulation control module 3012 and a configuration module 3013;

[0145] Among them, the various structural functions of the microcontroller are consistent with the corresponding structures in the aforementioned embodiments, and will not be described in detail here.

[0146] The first trigger module 302 is used to determine whether a first trigger condition is met based on the number of pause signals inside the processing core obtained within a first preset time window; and trigger the configuration module 3013 based on the first trigger condition being met.

[0147] The operating parameter includes the number of pause signals in the processing core.

[0148] In a possible implementation, the trigger module 302 determines the number of pause signals inside the processing core in the first preset time window according to the first preset time window, and the number of pause signals is used as a basis for determining whether the first trigger condition is met.

[0149] For example, a larger number of the pause signals indicates that the processing efficiency of the processing core is lower in the first preset time window; a smaller number of the pause signals indicates that the processing efficiency of the processing core is higher in the first preset time window.

[0150] The first trigger condition may be that the number of pause signals is greater than a set signal number threshold, or that the ratio of the number of pause signals to the total number of signals is greater than a specific ratio threshold.

[0151] Among them, for a certain processing core, if the number of the pause signals in the first preset time window is greater than the set signal number threshold, it is determined that the frequency currently used by the processing core does not match its processing instructions, and its frequency needs to be adjusted.

[0152] Among them, for a certain processing core, if the ratio of the number of pause signals in the first preset time window to the total number of signals inside the processing core obtained in the first preset time window is greater than a specific ratio threshold, it is determined that the frequency currently used by the processing core does not match its processing instructions and its frequency needs to be adjusted.

[0153] In a possible implementation, the target frequency modulation parameter may also include a frequency modulation enable signal.

[0154] The configuration module 3013 also sends a frequency modulation enable signal to the target frequency modulation control module 3012 to trigger the target frequency modulation control module to perform policy configuration based on the received target frequency modulation parameters.

[0155] In this embodiment, the electronic device also includes a first trigger module, which can determine whether a first trigger condition is met based on the number of pause signals inside the processing core obtained within a first preset time window; based on meeting the first trigger condition, the configuration module is triggered to quantify the processing efficiency of the processing core and achieve precise adjustment of the frequency of the processing core.

[0156] Figure 4 4 is another structural diagram of an electronic device provided in an embodiment of the present application, the electronic device comprising: a microcontroller 401, a second trigger module 402 and a processing core 403;

[0157] The microcontroller includes a statistics module 4011, a frequency modulation control module 4012 and a configuration module 4013;

[0158] Among them, the various structural functions of the microcontroller are consistent with the corresponding structures in the aforementioned embodiments, and will not be described in detail here.

[0159] Among them, the second trigger module 402 is used to determine the proportion of the first duration in the first preset time window, and the first duration is the waiting time when the processing core executes the instruction; based on the fact that the duration proportion is greater than the preset proportion threshold, it is determined that the first duration meets the second trigger condition, and the configuration module 4013 is triggered.

[0160] The trigger module 402 determines whether the statistical results of each statistical unit meet the triggering conditions for dynamically adjusting the frequency provided in this application.

[0161] In a possible implementation, the first duration is determined based on the number of pause signals inside the processing core acquired within a first preset time window.

[0162] Among them, a pause signal can last for one or more cycles, and the continuous period is used as a memory stall cycle. After obtaining the number of pause signals within a first preset time window, the corresponding memory stall cycle can be determined based on each pause signal, and then the first duration can be determined based on its memory stall cycle.

[0163] Correspondingly, the second trigger condition may be whether the proportion is greater than a preset proportion threshold.

[0164] In a possible implementation, the trigger module 402 determines the proportion of the waiting time for the processing core to execute instructions in the first preset time window according to the first preset time window, and the proportion of the waiting time is used as a basis for determining whether the second trigger condition is met.

[0165] For example, the larger the proportion of this time length, the longer the waiting time in the first preset time window, and the lower the processing efficiency of the processing core; the smaller the proportion of this time length, the shorter the waiting time in the first preset time window, and the higher the processing efficiency of the processing core.

[0166] Among them, for a certain processing core, the proportion of the first duration in the first preset time window is greater than the preset proportion threshold, and it is determined that the frequency currently used by the processing core does not match its processing instructions, and its frequency needs to be adjusted.

[0167] In a possible implementation, the target frequency modulation parameter may also include a frequency modulation enable signal.

[0168] The configuration module 4013 also sends a frequency modulation enable signal to the target frequency modulation control module 4012 to trigger the target frequency modulation control module to perform policy configuration based on the received target frequency modulation parameters.

[0169] In this embodiment, the electronic device also includes a trigger module, which can determine the proportion of the waiting time when the processing core executes an instruction in the first preset time window. If the proportion of the time is greater than the preset proportion threshold, it is determined that the first time meets the second trigger condition. The trigger module triggers the configuration module to quantify the processing efficiency of the processing core and achieve precise adjustment of the frequency of the processing core.

[0170] Figure 5It is a schematic diagram of the structure of an electronic device in an application scenario provided by an embodiment of the present application, including: multiple processing cores 501, a microcontroller 502 and a frequency output module 503. Among them, the microcontroller includes a statistical module 5021, a trigger module 5022, a frequency modulation control module 5023, a storage module 5024, a configuration module 5025 and a bus 5026. In this application scenario, there are i processing cores, and correspondingly, the statistical module 5021 includes i statistical units, and the frequency modulation control module 5023 includes i frequency modulation control units, where i is an integer greater than 1.

[0171] The trigger module may adopt the first trigger module or the second trigger module. In this scenario, the trigger module adopts the second trigger module.

[0172] Among them, each statistical unit counts the operating parameters of the corresponding processing core execution instruction, and sends the statistical results to the trigger module 5022. The trigger module 5022 determines whether to trigger the dynamic frequency adjustment process, and determines the ratio of the waiting time to the set time window when the processing core executes the instruction. If the ratio is greater than the preset proportion threshold, it is determined to be triggered, and then the configuration module 5025 is triggered; the configuration module 5025 configures the parameters in the frequency modulation scheme, and sends the target frequency modulation parameters to the storage module 5024 through the bus. The storage module 5024 controls the frequency modulation control unit to enable through the system instruction sys_ctrl, and sends the target frequency modulation parameters to the corresponding frequency modulation control unit. After enabling, the frequency modulation control unit uses the configured target frequency modulation parameters to detect the events corresponding to the operating parameters, and uses the frequency modulation strategy to perform frequency modulation. Among them, the frequency modulation control unit specifically controls the corresponding processing core to perform frequency modulation through the frequency output module 503.

[0173] Figure 6 6 is a schematic diagram of the structure of a frequency output module in an application scenario provided in an embodiment of the present application. The frequency output module includes a control element 601 and a switch element 602.

[0174] The input signals of the frequency output module include the input clock signal clkin, the configuration signals Clk_div_cfg_dn (frequency reduction) and Clk_div_cfg_up (frequency increase), the selection signal Sel_up_or_dn, and the frequency modulation enable signal Clk_ctl_en.

[0175] Among them, the input clock signal clkin is the clock source of the entire module; the configuration signal Clk_div_cfg_dn is used to select the clock division mode. When the signal is high, the division mode is selected; the configuration signal Clk_div_cfg_up is used to select the clock division mode. When the signal is high, the non-division mode is selected; the enable signal Clk_ctl_en is used to control the enable of the entire clock control module.

[0176] The control signal sent by the frequency modulation control unit includes a configuration signal and selection information, and the control signal is used to adjust the frequency of the processing core.

[0177] The control element 601 includes a logic gate control unit lg_en_ctl_dn 6011 , a logic gate control unit lg_en_ctl_up 6012 , a selector 6013 and a clock gating logic unit 6014 .

[0178] The switch element 602 adopts ICG (Integrated Clock Gating, clock gating module).

[0179] Among them, the logic gating unit lg_en_ctl_dn is used to control the clock signal in the frequency division mode, and receives clkin, Clk_div_cfg_dn and Clk_ctl_en as inputs; the logic gating unit lg_en_ctl_up is used to control the clock signal in the non-frequency division mode, and also receives clkin, Clk_div_cfg_up and Clk_ctl_en as inputs.

[0180] The selector 6013 determines whether to use the output of the logic gating unit lg_en_ctl_dn or the output of the logic gating unit lg_en_ctl_up according to the values ​​of Clk_div_cfg_dn and Clk_div_cfg_up. If Clk_div_cfg_dn is high, the output of lg_en_ctl_dn is selected; if Clk_div_cfg_up is high, the output of lg_en_ctl_up is selected.

[0181] The clock gating logic unit 6014 is an AND gate, which transmits the output of the selector 6013 to the switch element 602 based on the received frequency modulation enable signal Clk_ctl_en.

[0182] The switch element 602 receives the output of the frequency output module and the input clock signal clkin to generate the final clock output signal CLKOUT. The ICG is responsible for implementing the clock gating function, turning off the clock when the clock signal is not needed to reduce power consumption.

[0183] The control signal and the selection signal are provided by the frequency modulation control unit, which is set by the frequency modulation control unit according to the frequency modulation strategy. The control signal is not divided by frequency by default.

[0184] Among them, the frequency modulation enable signal is specifically a register bit configured by the configuration module. The value of the register bit indicates whether the frequency modulation operation is turned on. The value of the register bit is configured after the configuration module is triggered and receives the frequency modulation information.

[0185] The frequency output module outputs CLKOUT to generate a frequency modulation result, and the frequency modulation result controls the corresponding processing core to perform frequency modulation.

[0186] Figure 7 70 is another structural diagram of an electronic device provided in an embodiment of the present application, the electronic device includes: a processing core 701 and a function control module 702;

[0187] Each processing core includes at least two execution units 7011, and the at least two execution units execute data processing tasks based on instructions;

[0188] In a possible implementation, the execution unit 7011 in the processing core may adopt an EU (Execution Unit).

[0189] The processing core may include multiple types of execution units 7011 , and different types of execution units 7011 are used to respond to different types of instructions and execute data processing tasks of the instructions.

[0190] Each execution unit 7011 in the processing core can be controlled individually to control the execution unit 7011 to be in a running state or a prohibited running state.

[0191] Among them, the function control module 702 is used to determine, based on the operating status of the processing core, a control strategy when the number of target execution units currently in the operating state in the processing core does not match the operating status. The control strategy is used to control the number of target execution units in the running state to match the operating status of the processing core.

[0192] The function control module 702 controls the execution unit 7011 in each processing core in the electronic device.

[0193] The function control module 702 specifically adjusts the number of execution units in the processing core that are in operation so as to match the operation status of the processing core.

[0194] Among them, the function control module 702 first determines the operating status of the processing core, which represents the load of the processing core 701. When the load of the processing core is large, more execution units 7011 are required to run, and when the load of the processing core is small, fewer execution units 7011 are required to run.

[0195] The target execution unit may be an execution unit currently in operation, and the target execution unit is used to process tasks such as instructions received by the processing core.

[0196] In one possible implementation, each execution unit 7011 in the processing core 701 performs data processing tasks based on instructions; accordingly, the function control module 702 is used to determine the proportion of the target type instructions in the instructions received in the second preset time window based on counting the number of target type instructions received in the second preset time window, and the proportion represents the operating status of the processing core, and the target execution unit is used to execute the target type instructions.

[0197] The target execution unit is an execution unit for executing a specific type of instruction, and different target execution units are determined for different types of instructions.

[0198] In a possible implementation, the second preset time window may be preset as a determination period for adjusting the resource policy, and the period is used as a reference to determine whether the running state of the execution unit in the processing core needs to be adjusted.

[0199] Among them, the second preset time window is a time window for counting the number of instructions. The duration of the second preset time window can be set according to actual conditions and can be a time window of hundreds of nanoseconds. The specific duration of the second preset time window is not limited in this application.

[0200] Among them, the function control module 702 can count the number of target type instructions received by each processing core according to the second preset time window, or other structures with statistical functions can count the number of target type instructions received by each processing core and pass the number to the function control module 702.

[0201] Among them, different types of instructions correspond to different operating scenarios. Therefore, in this embodiment, by counting the number of specific types of instructions received in the time window, the state of the processing core in the corresponding operating scenario can be determined to determine whether to perform frequency modulation on the processing core.

[0202] As an example, when one wants to check the stall of an electronic device, the type of instructions that cause the stall are counted.

[0203] In a possible implementation, relevant information representing the target scene in the corresponding operation scene may also be counted.

[0204] As an example, when one wants to check the stall of an electronic device, the type of instructions that cause the stall are counted, and the information that characterizes the stall is also counted.

[0205] Among them, statistics are also taken for all instructions received in the second preset time window, and the function control module 702 determines the proportion of the number of target type instructions in all instructions, and determines the control strategy in combination with the number of target execution units 7011 currently in operation in the processing core to ensure that the number of target execution units 7011 in operation in the processing core matches the target type instructions.

[0206] In one possible implementation, there are multiple execution units 7011 in the processing core to execute a certain type of instruction, but the multiple execution units 7011 do not need to be all in operation. Only the number of execution units 7011 that matches the instruction needs to be retained, and the remaining execution units 7011 may not be enabled to reduce the power consumption of the processing core.

[0207] Accordingly, in the present application, the number of target execution units 7011 required to execute the target type instructions can be determined based on the proportion of the number of target type instructions in all instructions, and combined with the number of target execution units 7011 currently in operation in the processing core 701, a control strategy can be determined, which is to adjust the number of target execution units 7011 in operation in the processing core so that the number of target execution units in operation in the processing core matches the load of the processing core.

[0208] As an example, the processing core includes three types of execution units ABC, among which execution unit A is used to execute type a instructions, execution unit B is used to execute type b instructions, and execution unit C is used to execute type c instructions. According to statistics, the proportion of type a instructions in all instructions is N%, the number of execution units A matching the proportion is 2, and the number of execution units currently in operation is 4. The control strategy is to reduce the number of execution units A in operation to 2, and disable two of the four execution units A currently in operation.

[0209] Of course, when there are multiple execution units in the processing core, the control of various execution units can be executed in parallel, and the present application does not limit the execution order of the control strategies of various execution units.

[0210] In a possible implementation, the electronic device may include a microcontroller, a processing core, and a function control module.

[0211] Figure 8 80 is another structural diagram of an electronic device provided in an embodiment of the present application, the electronic device includes: a microcontroller 801, a processing core 802 and a function control module 803;

[0212] Among them, please refer to the above Figure 1-Figure 6 For the corresponding explanation, please refer to the above Figure 7 For the structure and function explanation of this function control module, please refer to Figure 7-Figure 9 , which will not be described in detail here.

[0213] In a possible implementation, the instruction received by the processing core may be decoded by a decoding unit to determine the type of the instruction.

[0214] Fig. 9 90 is another structural diagram of an electronic device provided in an embodiment of the present application, the electronic device comprising: a microcontroller 901, a processing core 902 and a function control module 903;

[0215] Each processing core includes at least two execution units 9021 and a decoding unit 9022 .

[0216] Among them, the structure and function of the microcontroller are as mentioned above Figure 1-6 Corresponding explanation, the structure and function of the function control module are as mentioned above Figure 7 The corresponding explanation is given in , which will not be repeated here.

[0217] Among them, the structures of each processing core are similar. Fig. 9 Only the structure of one processing core is shown in detail, and the structures of other processing cores can refer to the structure of this processing core.

[0218] The decoding unit 9022 is used to analyze the received instruction to obtain the type of the instruction.

[0219] The instruction is encoded in a specific form, and the decoding unit 9022 decodes the instruction received by the processing core to determine the type of the instruction.

[0220] The decoding unit 9022 may count the number of target type instructions according to the second time window, and send the statistical result to the function control module 903. Accordingly, the function control module 903 determines the control strategy based on the statistical result.

[0221] In specific implementation, the function control module can adopt rsicv core or other external hardware structures, which is not limited in this application.

[0222] In this embodiment, the processing core includes multiple execution units, and the execution units execute data processing tasks based on instructions. The electronic device also includes a function control module, which is used to determine the proportion of target type instructions in the instructions received in the second preset time window based on the number of target type instructions received in the second preset time window; based on the proportion and the number of target execution units currently in operation, determine a control strategy, and the control strategy is used to control the number of target execution units in operation to match the target type instructions. The target execution units are used to execute target type instructions. Through the function control module, the number of execution units corresponding to the target type instructions in the processing core that are in operation is controlled to match the target type instruction quantity, thereby preventing the execution units from being idle, reducing the power consumption of the processing core, and thereby reducing the overall power consumption of the electronic device.

[0223] Fig.10 It is a structural diagram of controlling a processing core provided by an embodiment of the present application, including a processing core 1001 and a function control module 1002, wherein the processing core 1001 includes an acquisition unit 10011, a decoding unit 10012, a processing unit 10013 and a plurality of execution units EU, which are represented by EU0, EU1, ... EUn in the figure, and n is an integer greater than 1. The acquisition unit 10011 obtains the program currently required to be executed from the cache / memory (such as Icache, Dcache, etc.), and the decoding unit 10012 obtains the instruction code from the acquisition unit for decoding, and sends the decoding result to the function control module 1002, and the instruction is also sent to each execution unit for execution through the processing unit 10103.

[0224] Among them, the function control module 1002 determines the proportion of a specific type of instructions in the time window in the total number of instructions, determines the corresponding number of execution units and the number of execution units in running state according to the instruction category, and determines whether it is necessary to reduce the execution units in running state based on the proportion and number, and sends a disable signal based on the result to control the shutdown of some execution units and reduce the power consumption of the processing core.

[0225] Fig.11 It is a flow chart of a control method provided in an embodiment of the present application. The method is applied to a microcontroller in an electronic device, and a processing core is provided in the electronic device. The method may include steps 1101 to 1102. These steps are described in detail below.

[0226] 1101. Count the operating parameters of the instructions executed by the processing core;

[0227] Among them, the electronic device has multiple processing cores, each of which can perform processing tasks independently or cooperate with each other to perform processing tasks. The specific functions of the processing cores are not limited in this application. At present, the processors of most electronic devices have multiple processing cores. The embodiments of this application take multiple processing cores as an example, and do not exclude the situation where the electronic device has only a single processing core.

[0228] The operating parameters of the instructions executed by the processing core represent the operating conditions of the processing core. By statistically analyzing the operating parameters of the instructions executed by the processing core, the internal state of the processor during operation can be understood.

[0229] Among them, the operating parameters of the execution instruction may include the current frequency, the number of instructions, the memory stall cycle, etc. The specific content of the operating parameters is not limited in this application.

[0230] Different processing cores may use different or the same frequencies, the number of instructions may be the number of instructions obtained in a set detection time window, and the memory stall cycle is the duration of stalling when requesting data from the memory.

[0231] 1102. Adjust the frequency of the processing core based on the operating parameters of the processing core satisfying the trigger condition;

[0232] At least when the frequency reduction strategy is adopted to control and adjust the frequency of the processing core, the performance loss of the processing core is monitored during the frequency reduction process, and the frequency reduction strategy is adjusted based on the performance loss.

[0233] If the operating parameters of a processing core in the electronic device meet the triggering condition, the frequency of the processing core is adjusted.

[0234] The adjustment may include frequency increase adjustment and frequency decrease adjustment.

[0235] The trigger condition is preset, and corresponding trigger conditions can be set for different operating parameters.

[0236] The trigger module determines whether the statistical results meet the triggering conditions for dynamically adjusting the frequency provided in this application.

[0237] In a possible implementation, the trigger condition may include multiple types. In a specific implementation, when the operating parameters of the processing core meet any one of the multiple trigger conditions, the frequency of the processing core is adjusted.

[0238] In one possible implementation, the operating parameters may include parameters of a pause signal within the processing core, specifically, the number of pause signals. Accordingly, the first trigger condition may be that the number of pause signals is greater than a set signal number threshold, or that the proportion of the number of pause signals to the total number of signals is greater than a specific proportion threshold, etc.

[0239] In a possible implementation, a first preset time window may be pre-set as a determination period of the frequency modulation strategy, and whether the processing core needs to adjust the frequency is determined based on the period.

[0240] Among them, for a certain processing core, if the number of pause signals obtained in the first preset time window is greater than the set signal number threshold, it is determined that the frequency currently used by the processing core does not match its processing instructions, and its frequency needs to be adjusted.

[0241] Among them, for a certain processing core, if the ratio of the number of pause signals obtained in the first preset time window to the total number of signals inside the processing core obtained in the first preset time window is greater than a specific ratio threshold, it is determined that the frequency currently used by the processing core does not match its processing instructions, and its frequency needs to be adjusted.

[0242] In a possible implementation, the operating parameter may also be a waiting time when the processing core executes an instruction, and the waiting time includes a waiting time for an instruction corresponding to a pause signal.

[0243] Among them, the waiting time of the instruction corresponding to the pause signal is represented by a first time duration; correspondingly, the second trigger condition may be that the proportion of the first time duration in the first preset time window duration is greater than a preset proportion threshold.

[0244] For example, the larger the proportion of this time length, the longer the waiting time in the first preset time window, and the lower the processing efficiency of the processing core; the smaller the proportion of this time length, the shorter the waiting time in the first preset time window, and the higher the processing efficiency of the processing core.

[0245] Among them, for a certain processing core, the proportion of the first duration in the first preset time window is greater than the preset proportion threshold, and it is determined that the frequency currently used by the processing core does not match its processing instructions, and its frequency needs to be adjusted to meet the trigger condition.

[0246] In a possible implementation, when the operating parameters of the processing core executing the instruction meet the trigger condition, the target frequency modulation parameters can be configured and the frequency modulation mode can be determined. For different frequency modulation modes, the frequency modulation can be performed in combination with the target frequency modulation parameters. Fig.12 The process of adjusting the core frequency is described in detail in .

[0247] In a possible implementation, during the frequency reduction process, the third preset time window can be used as a monitoring period to monitor the performance loss of the processing core, so as to adjust the frequency reduction strategy based on the performance loss. Fig.14 The process of adjusting the frequency reduction strategy for monitoring core performance loss is described in detail.

[0248] Among them, the control method of the present application is applied to a microcontroller. The specific structure and function of the microcontroller are explained in detail in the aforementioned electronic device embodiment, and the similarities are not repeated here.

[0249] In this embodiment, the control method is executed by a microcontroller in an electronic device, and the operating parameters of the processing core in the electronic device executing the instructions are counted, and based on the operating parameters of the processing core executing the instructions satisfying the trigger condition, the frequency of the processing core is controlled and adjusted. Moreover, at least when the frequency reduction strategy is adopted to control and adjust the frequency of the processing core, the performance loss of the processing core is monitored during the frequency reduction process, and the frequency reduction strategy is adjusted based on the performance loss, so as to achieve control of the processing core in the electronic device, and adopt a separate hardware structure such as a microcontroller to count the state of the internal processing core of the processor and control the frequency of the processing core. The response speed is faster than the response speed of the software process, and the frequency is controlled based on the state of the internal processing core of the processor, and the accuracy of adjusting the frequency is higher; moreover, at least when the frequency reduction strategy is adopted to control and adjust the frequency of the processing core, the performance loss of the processing core is monitored during the frequency reduction process, and the frequency reduction strategy is adjusted based on the performance loss, so as to achieve timely adjustment of the frequency reduction strategy during the frequency reduction process, and the performance requirements of load or instruction processing can be met in time.

[0250] Fig.12 This is a flow chart of adjusting the frequency of a processing core based on the operating parameters of the processing core satisfying a trigger condition provided by an embodiment of the present application, which may include steps 1201 to 1204, and these steps are described in detail below.

[0251] 1201. Based on the running parameters of the processing core executing the instruction satisfying the triggering condition, configure the target frequency modulation parameters;

[0252] If the operating parameters of the processing core executing the instruction meet the triggering condition, the frequency of the processing core is adjusted.

[0253] The target frequency modulation parameters are configured for the processing core, and the target frequency modulation parameters are used to adjust and configure the parameters in the frequency modulation strategy. If the electronic device includes multiple processing cores, each processing core can adjust the frequency using the method in this embodiment.

[0254] In a possible implementation, the target frequency modulation parameter may include a preset time window, a level of the frequency modulation strategy, an execution number, etc. The level of the frequency modulation strategy corresponds to the frequency modulation step length. The higher the level of the frequency modulation strategy, the larger the frequency modulation step length. Conversely, the lower the level of the frequency modulation strategy, the smaller the frequency modulation step length.

[0255] 1202. Determine a frequency modulation mode based on a first operating parameter of the processing core in a current first preset time window and a second operating parameter of the processing core in a previous first preset time window, where the frequency modulation mode includes up-frequency adjustment and down-frequency adjustment;

[0256] The frequency adjustment for the processing core may be a dynamic frequency adjustment, so as to achieve dynamic adjustment for the processing core in operation and reduce its power consumption.

[0257] In a possible implementation, the operating parameters of the executed instructions are counted according to a set time window. The operating parameters may include frequency, number of instructions, memory stall cycles and other parameters. The specific content of the operating parameters is not limited in this application.

[0258] The first preset time window is used as a determination period of the frequency modulation strategy, and the frequency modulation mode is determined based on the operating parameters of the first preset time window.

[0259] In one possible implementation, the operating parameter may include the number of pause signals within the processing core, and the pause signal may include a stall signal, or other signals that indirectly reflect the stall. Of course, any parameter that can characterize the power consumption of the processing core can be used as an operating parameter.

[0260] The stall is caused by resource competition or dependency between instructions, which results in the inability to continue executing the next instruction. The longer the stall of a processing core and the more stall times a processing core has, the greater the invalid dynamic power consumption of the processing core caused by the stall.

[0261] In a possible implementation, the operating parameter may be a waiting time when the processing core executes an instruction.

[0262] The waiting time may be determined based on the number of pause signals inside the processing core acquired within the first preset time window.

[0263] Among them, a pause signal can last for one or more cycles, and the continuous period is used as a memory stall cycle. After obtaining the number of pause signals within a first preset time window, the corresponding memory stall cycle can be determined based on each pause signal, and then the first duration can be determined based on its memory stall cycle.

[0264] The pause signal may be a signal sent by the processing core during operation, which may cause at least some instructions to be in a paused processing state to wait for completion of related instructions.

[0265] The pause signal may be in the form of stall information. Stalling during CPU operation means that when the CPU is executing instructions, the required data is not in the register or cache (memory), and the data needs to be loaded from the memory. During this period, the CPU will enter a waiting state, that is, a stall state.

[0266] The longer the stall state of a certain processing core is and the more times the stall state occurs, the greater the invalid dynamic power consumption of the processing core caused by the stall.

[0267] Among them, according to the first preset time window, parameter statistics are performed for each processing core, and a comparison is performed based on the first operating parameter of the current first preset time window and the second operating parameter of the previous first preset time window to determine whether the difference between the two meets the frequency increase condition or the frequency decrease condition. If neither condition is met, it is determined that the corresponding processing core will not be frequency-adjusted; if the frequency increase condition is met, it is determined that the corresponding processing core will be adjusted to increase the frequency; if the frequency decrease condition is met, it is determined that the corresponding processing core will be adjusted to decrease the frequency.

[0268] The previous first preset time window is a time window before the current first preset time window. In this time window, a frequency increase process may be executed, a frequency decrease process may be executed, or the frequency may not be changed.

[0269] In the current first preset time window, a frequency increase process may be executed, a frequency decrease process may be executed, or the frequency may not be changed.

[0270] In a possible implementation, during the frequency modulation process, the frequency increase strategy or the frequency decrease strategy is determined based on the difference in operating parameters in adjacent time windows, and based on the target frequency modulation parameters configured by the aforementioned configuration module, the step size and the number of executions in the frequency increase / decrease strategy are set, and the frequency is increased / decreased for the corresponding processing core based on the step size and the number of executions.

[0271] In a possible implementation, a frequency range of frequency modulation is preset, and during the frequency up-conversion process, the frequency reached by the frequency up-conversion cannot be greater than the upper limit of the frequency range, and during the frequency down-conversion process, the frequency reached by the frequency down-conversion cannot be less than the lower limit of the frequency range.

[0272] 1203. If the difference between the first operating parameter and the second operating parameter meets the frequency reduction condition, determine a frequency reduction strategy according to the target frequency modulation parameter; and control the frequency reduction of the processing core based on the frequency reduction strategy, wherein the frequency reduction strategy at least includes a frequency reduction step length and a frequency reduction execution number.

[0273] Among them, if the difference between the first operating parameter and the second operating parameter meets the frequency reduction condition, the frequency reduction strategy is configured based on the aforementioned target frequency adjustment parameters, so that the frequency reduction strategy adopts the frequency reduction step size and the number of frequency reduction executions in the target adjustment parameters, and then controls the frequency reduction in the processing core according to the frequency reduction strategy.

[0274] In a possible implementation, in order to ensure that the performance of the processing core does not drop significantly after the frequency reduction, the performance loss of the frequency reduction is determined during each frequency reduction process to determine whether to retain the frequency reduction operation. Fig.11 The process of controlling the frequency reduction of the processing core according to the frequency reduction strategy is described in detail.

[0275] 1204. If the difference between the first operating parameter and the second operating parameter meets the frequency increase condition, determine a frequency increase strategy according to the target frequency adjustment parameter; and control the frequency increase of the processing core based on the frequency increase strategy, wherein the frequency increase strategy at least includes a frequency increase step size and a frequency increase execution number.

[0276] Among them, if the difference between the first operating parameter and the second operating parameter meets the frequency increase condition, the frequency increase strategy is configured based on the aforementioned target frequency adjustment parameters, so that the frequency increase strategy adopts the frequency increase step size and the number of frequency increase executions in the target adjustment parameters, and then controls the frequency increase in the processing core according to the frequency increase strategy.

[0277] In a possible implementation, during the frequency upscaling process, if the frequency upscaling is performed according to the frequency upscaling step size, and the frequency of the processing core has reached the upper limit before the actual number of frequency upscaling executions reaches the upper limit, the frequency upscaling is stopped and the processing core is controlled to run at the upper limit of the frequency range.

[0278] In a specific implementation, different processing cores have different operating parameters. Accordingly, each processing core in the electronic device may be frequency-up, frequency-down, or not adjusted, and each processing core is controlled separately.

[0279] In this embodiment, based on whether the operating parameters of the processing core executing the instruction meet the trigger condition, the target frequency modulation parameters are configured; based on the first operating parameter of the processing core in the current first preset time window and the second operating parameter in the previous first preset time window, the frequency modulation method is determined, and the frequency modulation method includes frequency increase adjustment and frequency decrease adjustment; if the difference between the first operating parameter and the second operating parameter meets the frequency decrease condition, the frequency decrease strategy is determined according to the target frequency modulation parameter; the frequency of the processing core is controlled to be reduced based on the frequency decrease strategy, and the frequency decrease strategy at least includes the frequency decrease step size and the number of frequency decrease executions; if the difference between the first operating parameter and the second operating parameter meets the frequency increase condition, the frequency increase strategy is determined according to the target frequency modulation parameter; the frequency of the processing core is controlled to be increased based on the frequency increase strategy, and the frequency increase strategy at least includes the frequency increase step size and the number of frequency increase executions, thereby achieving the purpose of controlling the frequency of the processing core, and because the hardware execution control such as a microcontroller is adopted, the response speed is fast, and the control effect is improved.

[0280] Fig.13 This is a schematic diagram of a frequency modulation process for a processing core in an electronic device in an application scenario provided by an embodiment of the present application, including:

[0281] 1301. Counting operation parameters of the instructions executed by the processing core based on the first preset time window;

[0282] In this application scenario, the operating parameter is information that causes CPU stall, such as the current frequency of the processing core, the number of instructions received by the processing core, etc.

[0283] In a specific implementation, the number of operation cycles of the processing core may be counted, and when the number of operation cycles of the processing core reaches a set number, a first preset time window is obtained.

[0284] 1302. Determine a difference between an operating parameter of a current first preset time window and an operating parameter of a previous first preset time window;

[0285] The difference may be a ratio of a reduced frequency of the processing core to a change in the number of received instructions.

[0286] 1303. Determine whether the difference is greater than a first threshold;

[0287] The first threshold may be a ratio threshold.

[0288] If it is not greater than the first threshold, execute 1304; if it is greater than the first threshold, execute 1306.

[0289] The first threshold is a threshold used to determine whether the frequency needs to be further reduced. If the difference is greater than the first threshold, it indicates that the frequency can be further reduced. Otherwise, it cannot be reduced. It is further determined whether the processing core needs to be increased.

[0290] 1304. Determine whether the difference is less than a first threshold and the frequency is currently reduced;

[0291] If the current state is a frequency reduction state, it is determined that the current state is a frequency reduction process; otherwise, the current state is not a frequency reduction process.

[0292] If the difference is smaller than the first threshold and the frequency is currently reduced, execute 1305 ; otherwise, return to execute 1301 .

[0293] Wherein, the execution returns to step 1301 based on the current frequency.

[0294] 1305. Control the processing core frequency increase;

[0295] The frequency increase amount may be calculated based on the current frequency and a set ratio, and the frequency increase may not exceed the set frequency upper limit.

[0296] The frequency increase setting information is also generated to start the frequency increase process. The frequency increase setting information is used to indicate that the current frequency increase state is in progress.

[0297] 1306. Control the processing core to reduce frequency.

[0298] The frequency reduction amount may be calculated based on the current frequency and a set ratio, and the frequency reduction may not exceed the set frequency lower limit.

[0299] The frequency reduction setting information is also generated to start the frequency reduction process. The frequency reduction setting information is used to indicate that the current frequency reduction state is in progress.

[0300] Fig.14 It is a flowchart of controlling the frequency reduction of the processing core based on the frequency reduction strategy provided in an embodiment of the present application, which may include steps 1401 to 1404, and these steps are described in detail below.

[0301] 1401. Based on the frequency reduction step in the frequency reduction strategy, control the frequency reduction of the processing core according to the number of frequency reduction executions;

[0302] The frequency modulation strategy includes: a frequency modulation process and a detection process.

[0303] Since the frequency reduction process will reduce the frequency of the processing core, and the reduction in the frequency of the processing core means a reduction in the processing speed of the processing core, which may affect the performance of the processing core, the gradual frequency reduction method is adopted to control the gradual reduction of the performance of the processing core. Therefore, during the frequency reduction process, it is necessary to perform a frequency reduction to check the performance loss of this frequency reduction to ensure that the performance of the processing core will not drop significantly.

[0304] The frequency modulation process refers to the above Fig.12 Explanation in .

[0305] 1402. After the frequency reduction step is adopted each time to control the processing core frequency to be reduced, a third operating parameter before the frequency reduction and a fourth operating parameter after the frequency reduction are obtained based on a third preset time window, where the third preset time window is smaller than the first preset time window.

[0306] Each time the frequency of the control processing core is reduced, the performance loss of this frequency reduction is detected.

[0307] Among them, a smaller third preset time window is used to obtain the third operating parameters of the processing core before the frequency reduction step is used for a frequency reduction and the fourth operating parameters after the frequency reduction. The difference between the fourth operating parameters and the third operating parameters can characterize the performance loss caused by this frequency reduction.

[0308] The third preset time window is used as a monitoring period of the frequency reduction strategy, and the core performance loss is monitored based on the third preset time window.

[0309] In a possible implementation, the third preset time window is smaller than the first preset time window, so that during the frequency reduction process based on the first preset time window, performance loss can be detected for the frequency reduction process.

[0310] As an example, the first preset time window is 100 nanoseconds, and the third preset time window is 80 nanoseconds. During the frequency reduction process, the performance loss of the frequency reduction process is detected through the third preset time window. Once a sharp drop in the frequency reduction process is detected, the frequency reduction process is stopped in time before the frequency reduction is completed.

[0311] In a possible implementation, the first preset time window may be several times the third preset time window, so that during the frequency reduction process based on the first preset time window, multiple performance detections are performed based on the third preset time window to improve response efficiency.

[0312] As an example, the first preset time window is 100 nanoseconds, and the third preset time window is 20 nanoseconds. During the frequency reduction process through the first preset time window, the performance loss of the frequency reduction process is detected 5 times through the third preset time window. Once a sharp drop in the frequency reduction process is detected, the frequency reduction process is stopped in time.

[0313] 1403. Determine a performance loss of frequency reduction based on the third operating parameter and the fourth operating parameter;

[0314] Correspondingly, the third operating parameter before the frequency reduction and the fourth operating parameter after the frequency reduction are used to determine the difference between the two, and the difference represents the performance loss caused by the frequency reduction.

[0315] In a possible implementation, the number of detections can be set. After each frequency reduction step, the number of performance loss detections can be set. The performance loss of the processing core is detected using the third preset time window according to the set number of detections.

[0316] 1404. Based on the fact that the performance loss corresponding to the Nth frequency reduction is greater than a specific loss threshold, stop executing the frequency reduction strategy, and use the frequency before the Nth frequency reduction to control the operation of the processing core, where N is a positive integer.

[0317] The specific loss threshold is used to indicate a situation where the performance of the processing core drops significantly.

[0318] When the performance loss corresponding to a frequency reduction is greater than a specific loss threshold, the frequency reduction process is stopped, and the frequency used before the frequency reduction is used to control the operation of the processing core, and the frequency obtained by the last frequency reduction is used as the basis.

[0319] In a possible implementation, only the frequency reduction process may be stopped, and the frequency increase process may be started to increase the frequency of the processing core to alleviate the problem of significant performance degradation caused by the frequency reduction.

[0320] The third preset time window in this embodiment may be at the level of hundreds of nanoseconds (ns).

[0321] In this embodiment, based on the frequency reduction step in the frequency reduction strategy, the frequency reduction of the processing core is controlled according to the number of times the frequency reduction is executed; wherein, each time the frequency reduction step is adopted to control the frequency reduction of the processing core, based on the third preset time window, a third operating parameter before the frequency reduction and a fourth operating parameter after the frequency reduction are obtained, and the third preset time window is smaller than the first preset time window; based on the third operating parameter and the fourth operating parameter, the performance loss of the frequency reduction is determined; based on the performance loss corresponding to the Nth frequency reduction being greater than a specific loss threshold, the execution of the frequency reduction strategy is stopped, and the frequency before the Nth frequency reduction is used to control the operation of the processing core, where N is a positive integer, to implement performance detection of the processing core after the frequency reduction, and determine whether to continue or stop the frequency reduction based on the detection result, thereby ensuring that the performance of the processing core will not drop significantly.

[0322] Fig.15 1 is another schematic diagram of a frequency modulation process for a processing core of an electronic device in an application scenario provided by an embodiment of the present application, including:

[0323] 1501. Counting operation parameters of instructions executed by each processing core based on a first preset time window;

[0324] 1502. Determine a difference between an operating parameter of a current first preset time window and an operating parameter of a previous first preset time window;

[0325] 1503. Determine whether the gap is greater than a first distance threshold;

[0326] If it is not greater than the first threshold, execute 1504; if it is greater than the first threshold, execute 1506 and 1507.

[0327] 1504. Determine whether the difference is less than a first threshold and the frequency is currently reduced;

[0328] If the difference is smaller than the first threshold and the frequency is currently reduced, execute 1505; otherwise, return to execute 1501.

[0329] Wherein, the execution returns to step 1501 based on the current frequency.

[0330] 1505. Control the processing core frequency increase;

[0331] 1506. Control the processing core to reduce the frequency;

[0332] Among them, steps 1501-1506 are the same as the above Fig.13 The corresponding steps are the same as in , and will not be repeated here.

[0333] 1507. Counting the operating parameters of the down-clocked processing core executing the instruction based on the third preset time window;

[0334] Among them, the third preset time window is smaller than the first preset time window, and the corresponding duration of the time window can be set in advance according to actual conditions.

[0335] Among them, steps 1507-1510 are a process of checking the performance loss of each frequency reduction of the processing core.

[0336] 1508. Determine, based on the operating parameter, that the frequency reduction of the processing core causes performance loss of the electronic device;

[0337] The performance loss may be represented by a ratio of the performance of the electronic device in the current third preset time window to the performance of the electronic device in the previous third preset time window.

[0338] The performance of the electronic device in the current third preset time window can be calculated by using the IPC (Instructions Per Clock) corresponding to the current window and the corresponding frequency in the previous window and the preset coefficient.

[0339] After the performance of the electronic device in the current third preset time window is calculated each time, the performance value is recorded to provide a basis for calculating the performance loss in the next time window.

[0340] 1509. Determine whether the performance loss exceeds a second threshold;

[0341] The second threshold may be a preset threshold.

[0342] If the performance loss exceeds the second threshold, execute 1510; otherwise, return to execute step 1501 according to the frequency after the frequency reduction.

[0343] 1510. Increase the frequency to the frequency before the current frequency reduction, and clear the frequency reduction setting information.

[0344] Fig.16 This is a flow chart of reducing power consumption for processing core control provided by an embodiment of the present application, which may include steps 1601 to 1603, and these steps are described in detail below.

[0345] This process is executed after the frequency of the processing core is adjusted based on the operating parameters of the processing core satisfying the trigger condition.

[0346] 1601. Count the number of target type instructions received by the processing core in the second preset time window;

[0347] This embodiment is a process for adjusting resources in a processing core, and the power consumption in the processing core is further reduced through resource adjustment.

[0348] Among them, a second preset time window required for statistics is set, and the duration of the second preset time window can be set according to actual conditions. The second preset time window can be a time window of hundreds of nanoseconds level. The specific duration of the second preset time window is not limited in this application.

[0349] Among them, a processing core can respond to different types of instructions and execute data processing tasks of the instructions.

[0350] The number of target type instructions received by the processing core in the second preset time window is counted, and the target type corresponds to the scene controlled by the target.

[0351] Among them, different types of instructions correspond to different operating scenarios. Therefore, in this embodiment, by counting the number of specific types of instructions received in the time window, the state of the processing core in the corresponding operating scenario can be determined to determine whether to perform frequency modulation on the processing core.

[0352] As an example, when one wants to check the stall of an electronic device, the type of instructions that cause the stall are counted.

[0353] In a possible implementation, relevant information representing the target scene in the corresponding operation scene may also be counted.

[0354] As an example, when one wants to check the stall of an electronic device, the type of instructions that cause the stall are counted, and the information that characterizes the stall is also counted.

[0355] 1602. Based on the number, determine the proportion of the target type instruction in the instructions received in the second preset time window;

[0356] When counting the number of target type instructions, the number of all instructions received by the processing core in the second preset time window is also counted.

[0357] Wherein, based on the number of target type instructions received and the number of all instructions received in the second preset time window, it is determined whether the number of target execution units in the processing core that are in a running state and execute the target type instructions matches.

[0358] 1603. Based on the ratio and the number of target execution units currently in operation, determine a control strategy for controlling the number of target execution units in operation in the processing core to match the target type instruction, and the target execution unit is used to execute the target type instruction.

[0359] There are multiple execution units in the processing core, and different execution units execute different types of instructions.

[0360] Among them, the proportion of the number of target type instructions in all instructions is determined, and the control strategy is determined in combination with the number of target execution units currently in operation in the processing core to ensure that the number of target execution units in operation in the processing core matches the target type instructions.

[0361] If the number of target execution units in the running state does not match the target type instruction, the number of target execution units in the running state needs to be adjusted.

[0362] In a possible implementation, the control strategy is determined based on the ratio and the number of target execution units currently in operation, including:

[0363] Based on the ratio being less than a specific ratio threshold, controlling the number of target execution units currently in operation in the processing core to decrease;

[0364] Based on the ratio being greater than a specific ratio threshold, the number of target execution units currently in operation in the processing core is controlled to increase.

[0365] Of course, when there are multiple execution units in the processing core, the control of various execution units can be executed in parallel, and the present application does not limit the execution order of the control strategies of various execution units.

[0366] The specific ratio threshold and the second preset time window can be used as parts of the target frequency modulation parameters to adjust the running state of the execution unit.

[0367] In this embodiment, it also includes: counting the number of target type instructions received by the processing core in the second preset time window; based on the number, determining the proportion of the target type instructions in the instructions received in the second preset time window; based on the proportion and the number of target execution units currently in operation, determining a control strategy, the control strategy is used to control the number of target execution units in operation in the processing core to match the target type instructions, the target execution units are used to execute the target type instructions, and the number of execution units in operation corresponding to the target type instructions in the processing core is controlled to match the target type instruction quantity, thereby preventing the execution units from being idle, reducing the power consumption of the processing core, and thereby reducing the overall power consumption of the electronic device.

[0368] The present application also provides an electronic device in an embodiment. Fig.17 As shown, it shows another structural schematic diagram of an electronic device suitable for implementing the embodiment of the present application. The electronic device in the embodiment of the present application may include but is not limited to fixed terminals such as mobile phones, laptops, PDAs (personal digital assistants), PADs (tablet computers), desktop computers, etc. Fig.17The electronic device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0369] like Fig.17 As shown, the electronic device may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1702 or a program loaded from a storage device 1708 to a random access memory (RAM) 1703. When the electronic device is powered on, various programs and data required for the operation of the electronic device are also stored in the RAM 1703. The processing device 1701, the ROM 1702, and the RAM 1703 are connected to each other via a bus 1704. An input / output (I / O) interface 1705 is also connected to the bus 1704.

[0370] Typically, the following devices may be connected to the I / O interface 1705: an input device 1706 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 1707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1708 including, for example, a memory card, a hard disk, etc.; and a communication device 1709. The communication device 1709 may allow the electronic device to communicate with other devices wirelessly or by wire to exchange data. Although Fig.17 An electronic device having various devices is shown, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0371] An embodiment of the present application also provides a computer program product including computer-readable instructions. When the computer-readable instructions are executed on an electronic device, the electronic device implements any control method provided in the embodiment of the present application.

[0372] A computer-readable storage medium is also provided in an embodiment of the present application. The storage medium carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement any control method provided in the embodiment of the present application.

[0373] It should also be noted that the device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. In addition, in the drawings of the device embodiments provided by the present application, the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines.

[0374] Through the description of the above implementation mode, the technicians in the field can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course, it can also be implemented by special hardware including special integrated circuits, special CPUs, special memories, special components, etc. In general, all functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be various, such as analog circuits, digital circuits or special circuits. However, for the present application, software program implementation is a better implementation mode in more cases. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer floppy disk, a U disk, a mobile hard disk, a ROM, a RAM, a disk or an optical disk, etc., including a number of instructions to enable a computer device (which can be a personal computer, a training device, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0375] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0376] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a training device, or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, training device, or data center. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device, a data center, etc. that includes one or more available media integrations. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

Claims

1. An electronic device, comprising: Microcontrollers and processing cores; The microcontroller counts the operating parameters of the processing core executing the instruction with the first preset time window as a period, and controls and adjusts the frequency of the processing core based on whether the operating parameters of the processing core executing the instruction meet the trigger condition; Wherein, at least when the frequency reduction strategy is adopted to control and adjust the frequency of the processing core, the performance loss of the processing core caused by the frequency reduction is monitored in a third preset time window as a period during the frequency reduction process, and the frequency reduction strategy within the frequency period of the current adjustment of the processing core is adjusted based on the performance loss, the third preset time window is pre-set as the monitoring period of the frequency reduction strategy, the third preset time window is smaller than the first preset time window, and the frequency reduction strategy at least includes a frequency reduction step size and a number of frequency reduction execution times; The method of monitoring the performance loss of the processing core due to the frequency reduction with a third preset time window as a period during the frequency reduction process and adjusting the frequency reduction strategy within the frequency period of the processing core currently adjusting the frequency based on the performance loss includes: based on the frequency reduction step in the frequency reduction strategy, controlling the frequency reduction of the processing core according to the number of frequency reduction executions; wherein, after each time the frequency reduction step is adopted to control the frequency reduction of the processing core, based on the third preset time window, obtaining a third operating parameter before the frequency reduction and a fourth operating parameter after the frequency reduction; determining the performance loss of the frequency reduction based on the third operating parameter and the fourth operating parameter; and stopping executing the frequency reduction strategy based on the performance loss corresponding to the Nth frequency reduction being greater than a specific loss threshold, and using the frequency before the Nth frequency reduction to control the operation of the processing core, where N is a positive integer.

2. The electronic device according to claim 1, wherein the microcontroller comprises a statistical module, a frequency modulation control module and a configuration module; The statistical module includes at least two statistical units, and the frequency modulation control module includes at least two frequency modulation control elements, and the statistical units and the frequency modulation control elements are arranged corresponding to the processing core; in, The statistical unit counts the operation parameters of the instructions executed by the corresponding processing core; The configuration module configures a target frequency modulation parameter based on that the operating parameter of the instruction executed by the first processing core meets the trigger condition, and sends the target frequency modulation parameter to a target frequency modulation control element, the target frequency modulation control element is a frequency modulation control element corresponding to the first processing core, and the first processing core is any one of the at least one processing core of the electronic device; The target frequency modulation control element generates a control signal based on the target frequency modulation parameter, and the control signal is used to adjust the frequency of the first processing core. The electronic device according to claim 2 , wherein the operating parameter comprises the number of pause signals within the processing core.

4. The electronic device according to claim 3, further comprising: A first trigger module, configured to determine whether a first trigger condition is met based on the number of pause signals inside the processing core acquired within a first preset time window; Based on satisfying a first trigger condition, the configuration module is triggered.

5. The electronic device according to claim 2, further comprising: A second trigger module is used to determine a proportion of a first duration in a first preset time window, wherein the first duration is a waiting duration when the processing core executes an instruction; Based on the fact that the duration ratio is greater than a preset ratio threshold, it is determined that the first duration satisfies a second trigger condition, thereby triggering the configuration module. 6 . The electronic device according to claim 5 , wherein the first duration is determined based on the number of pause signals inside the processing core acquired within a first preset time window.

7. The electronic device according to claim 1, further comprising: Function control module; The processing core includes at least two execution units; The functional control module is used to determine, based on the operating status of the processing core, a control strategy when the number of target execution units currently in operation in the processing core does not match the operating status. The control strategy is used to control the number of target execution units in operation to match the operating status of the processing core.

8. The electronic device according to claim 7, wherein each execution unit in the processing core performs a data processing task based on an instruction; Correspondingly, the function control module is used to determine the proportion of the target type instructions in the instructions received in the second preset time window based on the number of target type instructions received in the second preset time window, and the proportion represents the operating status of the processing core. The target execution unit is used to execute the target type instructions.

9. A control method, the method being applied to a microcontroller in an electronic device, wherein a processing core is provided in the electronic device, the method comprising: Taking the first preset time window as a period, counting the operation parameters of the processing core executing the instruction; adjusting the frequency of the processing core based on an operating parameter of the processing core satisfying a trigger condition; Wherein, at least when the frequency reduction strategy is adopted to control and adjust the frequency of the processing core, the performance loss of the processing core caused by the frequency reduction is monitored in a third preset time window as a period during the frequency reduction process, and the frequency reduction strategy within the frequency period of the current adjustment of the processing core is adjusted based on the performance loss, the third preset time window is pre-set as the monitoring period of the frequency reduction strategy, the third preset time window is smaller than the first preset time window, and the frequency reduction strategy at least includes a frequency reduction step size and a number of frequency reduction execution times; The method of monitoring the performance loss of the processing core due to the frequency reduction with a third preset time window as a period during the frequency reduction process and adjusting the frequency reduction strategy within the frequency period of the processing core currently adjusting the frequency based on the performance loss includes: based on the frequency reduction step in the frequency reduction strategy, controlling the frequency reduction of the processing core according to the number of frequency reduction executions; wherein, after each time the frequency reduction step is adopted to control the frequency reduction of the processing core, based on the third preset time window, obtaining a third operating parameter before the frequency reduction and a fourth operating parameter after the frequency reduction; determining the performance loss of the frequency reduction based on the third operating parameter and the fourth operating parameter; and stopping executing the frequency reduction strategy based on the performance loss corresponding to the Nth frequency reduction being greater than a specific loss threshold, and using the frequency before the Nth frequency reduction to control the operation of the processing core, where N is a positive integer.

10. The control method according to claim 9, wherein adjusting the frequency of the processing core based on the operating parameters of the processing core satisfying the trigger condition comprises: Based on the running parameters of the processing core executing the instruction satisfying the triggering conditions, the target frequency modulation parameters are configured; Determine a frequency modulation mode based on a first operating parameter of the processing core in a current first preset time window and a second operating parameter of the processing core in a previous first preset time window, wherein the frequency modulation mode includes up-frequency adjustment and down-frequency adjustment; If the difference between the first operating parameter and the second operating parameter meets the frequency reduction condition, determining the frequency reduction strategy according to the target frequency modulation parameter; Controlling the frequency reduction of the processing core based on the frequency reduction strategy; If the difference between the first operating parameter and the second operating parameter meets the frequency increase condition, determining the frequency increase strategy according to the target frequency modulation parameter; The frequency of the processing core is increased based on the frequency increase strategy, and the frequency increase strategy at least includes a frequency increase step length and a frequency increase execution number.

11. The control method according to claim 9, after adjusting the frequency of the processing core based on the operating parameters of the processing core satisfying the trigger condition, further comprising: Counting the number of target type instructions received by the processing core in the second preset time window; Based on the number, determining a proportion of the target type instructions in the instructions received in the second preset time window; Based on the ratio and the number of target execution units currently in operation, a control strategy is determined, wherein the control strategy is used to control the number of target execution units in operation in the processing core to match the target type instructions, and the target execution units are used to execute the target type instructions.

12. The control method according to claim 11, wherein the determining of the control strategy based on the ratio and the number of target execution units currently in operation comprises: Based on the ratio being less than a specific ratio threshold, controlling the number of target execution units currently in operation in the processing core to decrease; Based on the ratio being greater than a specific ratio threshold, the number of target execution units currently in operation in the processing core is controlled to increase.

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