An adaptive weighted greedy instruction scheduling system and method for DSP

Abstract

The present invention relates to the field of instruction scheduling of DSP, and discloses an adaptive weighted greedy instruction scheduling system and method for DSP, wherein the system comprises a ready instruction queue input module, a greedy scoring decision module, an adaptive weight adjustment module, a scheduling queue generation module, a scheduling termination check module, a ready queue update module, and a post-scheduling instruction queue output module. The system and method disclosed by the present invention comprehensively consider factors such as instruction delay, register pressure, and critical path, introduce an adaptive weight dynamic adjustment mechanism, weigh multi-objective optimization on the basis of a greedy strategy, can flexibly adapt to different program characteristics, efficiently utilize hardware resources, improve scheduling quality in complex scenarios, and improve overall program performance. At the same time, the algorithm is improved on the basis of the original algorithm, reuses a large part of the content, has moderate complexity, is easy to implement and integrate in a compiler, and has strong practicality and engineering value.

Description

Technical Field

[0001] The present invention relates to the field of DSP instruction scheduling, and in particular to an adaptive weighted greedy instruction scheduling system and method for DSP. Background Art

[0002] Digital Signal Processor (DSP) is a type of microprocessor optimized for digital signal processing applications, and is widely used in multimedia, communications, image processing, speech recognition, and other fields. Compared with general-purpose CPUs, DSP emphasizes real-time performance and low power consumption. By adopting specialized hardware acceleration circuits, multi-address instructions, and dedicated peripherals, DSP demonstrates efficient performance and excellent energy efficiency when processing a large number of complex digital signal processing operations.

[0003] With the booming development of emerging fields such as the Internet of Things and artificial intelligence, the market demand for energy-efficient and high-performance embedded processors has surged. More and more edge computing scenarios require complex signal processing and machine learning tasks to be completed on the device side, which places higher demands on the performance and power consumption of digital signal processors. At the same time, the open source instruction set architecture RISC-V has become a popular choice for academia and industry to develop embedded processors due to its openness, customizability and modular design. The RISC-V architecture based on the reduced instruction set (RISC) is simple and efficient, and is very suitable for application scenarios such as digital signal processors that are sensitive to code density and execution efficiency.

[0004] Compiler optimization is crucial for developing high-performance digital signal processors for the RISC-V architecture. Since there are a large number of loop iterations and complex data dependencies in digital signal processing algorithms, the compiler needs to fully exploit the parallelism of the program and improve the operating efficiency of the processor through means such as instruction-level parallelism, data flow analysis, and loop optimization. Among them, instruction scheduling is a key link in compilation optimization. By reasonably arranging the execution order of instructions, while ensuring data dependencies, it can maximize instruction-level parallelism and reduce pipeline pauses, thereby shortening program execution time.

[0005] Traditional instruction scheduling algorithms are mainly list scheduling heuristic algorithms based on data dependencies, which sort and schedule instructions according to the dependencies between instructions and preset priority rules, such as delay, critical path, etc. However, faced with the complex data dependencies and demanding real-time requirements in digital signal processing applications, traditional algorithms often find it difficult to weigh various factors and are prone to falling into local optimality, resulting in suboptimal scheduling results and failing to fully tap the performance potential of RISC-V architecture digital signal processors.

[0006] In addition, modern digital signal processing applications usually involve complex digital signal processing algorithms, such as fast Fourier transform (FFT), finite impulse response (FIR) filtering, convolution, matrix operations, etc. These algorithms exhibit high computational density and complex data access patterns, which place extremely high demands on the computing power and storage performance of the processor. Simple static scheduling strategies are difficult to adapt to dynamically changing resource constraints and data dependencies, while complex dynamic scheduling algorithms face the problems of high hardware overhead and high implementation difficulty. Therefore, there is an urgent need for an instruction scheduling optimization technology that takes into account flexibility, efficiency, and feasibility. Summary of the invention

[0007] In order to solve the above technical problems, the present invention provides an adaptive weighted greedy instruction scheduling system and method for DSP, so as to flexibly adapt to the characteristics of complex digital signal processing applications and RISC-V architecture characteristics, while improving the operation efficiency and taking into account the complexity of implementation.

[0008] To achieve the above object, the technical solution of the present invention is as follows:

[0009] An adaptive weighted greedy instruction scheduling system for DSP, comprising a ready instruction queue input module, a greedy scoring decision module, an adaptive weight adjustment module, a scheduling queue generation module, a scheduling termination check module, a ready queue update module and a post-scheduling instruction queue output module;

[0010] The ready instruction queue input module is used to store the ready instruction queue;

[0011] The greedy scoring decision module: calculates the basic score according to the attributes of the instructions in the ready instruction queue input module, and prioritizes the instructions; this module combines the greedy algorithm and interacts with the adaptive weight adjustment module to quickly select the best candidate instructions through comprehensive scoring;

[0012] The adaptive weight adjustment module: dynamically adjusts the scoring factor weight according to the current hardware status, and the dynamically adjusted scoring factor weight directly participates in the final comprehensive score calculation of the greedy scoring decision module;

[0013] The scheduling queue generation module: selects the current best scheduling instruction according to the final comprehensive score calculation result, removes it from the ready instruction queue and adds it to the post-scheduling instruction queue;

[0014] The scheduling termination check module: after each scheduling is completed, check whether the ready instruction queue is empty. If it is empty, it indicates that the scheduling is completed, and output the final post-scheduling instruction queue; if it is not empty, execute the ready queue update module;

[0015] The ready queue update module is responsible for traversing the remaining instructions that have not been added to the ready instruction queue, identifying the instructions that have met the dependency conditions and have the scheduling conditions by checking the current dependency status of these instructions, and adding them to the ready instruction queue to prepare for the next round of scheduling;

[0016] The post-scheduled instruction queue output module is used to store the post-scheduled instruction queue and output the final post-scheduled instruction queue.

[0017] In the above scheme, the formula for calculating the basic score of the greedy scoring decision module is as follows:

[0018] ;

[0019] in, Represents the base score of Directive I, is the basic scoring weight, which is used to control the impact of greedy scoring on the overall scheduling priority. is a scaling factor used to adjust the impact of greedy cost on the score, Represents the greedy cost of instruction I.

[0020] In the above scheme, the greedy cost calculation formula of the instruction I is as follows:

[0021] ;

[0022] in, , and are the latency, operand usage, and number of subsequent instructions of instruction I, respectively. , and Corresponding to , and The weight of .

[0023] In the above scheme, the final comprehensive score is calculated as follows:

[0024] ;

[0025] in, For the final comprehensive score, Represents the base score of Directive I, , , They are the adjusted register pressure weight, resource conflict weight, and critical path weight; , , They are register pressure score, resource conflict score, and critical path score.

[0026] An adaptive weighted greedy instruction scheduling method for DSP, using the adaptive weighted greedy instruction scheduling system for DSP as described above, is characterized by comprising the following steps:

[0027] (1) System initialization: After the system is started, initialization operations are performed, including preparation of data structures and scheduling environment;

[0028] (2) Preprocessing stage: The ready instruction queue input module receives the input instruction sequence, forms an initial set of instructions to be processed, analyzes the dependencies between the input instructions, determines the dependencies between each instruction, and adds the instructions that meet the dependencies and meet the scheduling conditions to the ready instruction queue, waiting for subsequent scheduling operations;

[0029] (3) Core scheduling loop: The greedy scoring decision module obtains candidate instructions from the ready instruction queue, calculates the basic score based on the attributes of the instructions and the obtained system status, and prioritizes the instructions; at the same time, the adaptive weight adjustment module collects the current hardware status information, dynamically adjusts the scoring factor weight according to the current hardware status, and calculates the final comprehensive score based on the dynamically adjusted scoring factor weight combined with the basic score;

[0030] (4) Update system status: The scheduling queue generation module selects the current best scheduling instruction based on the final comprehensive score calculation result, removes it from the ready instruction queue and adds it to the post-scheduling instruction queue; at the same time, it checks the instructions that have not been added to the ready instruction queue, identifies the instructions whose dependency conditions have been met, and adds them to the ready instruction queue to prepare for the next round of scheduling;

[0031] (5) The scheduling termination check module checks the ready instruction queue: if it is empty, it indicates that the system has completed the scheduling of the instructions and outputs the final scheduled instruction queue; if it is not empty, it returns to step (3) for the next round of scoring and screening until all instructions are scheduled;

[0032] (6) Output optimized sequence: After completing the scheduling operations of all instructions, the post-scheduling instruction queue output module will generate the final instruction queue output as the optimized instruction execution sequence.

[0033] Through the above technical solution, the adaptive weighted greedy instruction scheduling system and method for DSP provided by the present invention has the following beneficial effects:

[0034] 1. Improve system performance and resource utilization: By dynamically adjusting the weight of scoring factors and evaluating instruction scores in real time, the present invention effectively reduces register pressure, alleviates resource conflicts, and optimizes pipeline utilization. In a large number of fixed-point and floating-point digital signal processing benchmarks, the performance is improved by more than 5% on average compared to the scheduling algorithm used in LLVM-O3 optimization. It is particularly outstanding in complex digital signal processing algorithms (such as convolution and fast Fourier transform).

[0035] 2. Better adaptability and flexibility: Through the adaptive weight adjustment mechanism, the scheduling strategy can be dynamically adjusted according to different program characteristics and hardware status. At the same time, it has good scalability, is easy to integrate new scoring factors and optimization strategies, and can better adapt to different target architectures.

[0036] 3. Modular design, easy to integrate and expand: The scheduling system of the present invention adopts a modular design, supports multiple modules such as candidate instruction generation, adaptive weight management and greedy scoring decision, and realizes decoupling through standardized interfaces. This design improves the flexibility and scalability of the system, making it easy to integrate into mainstream compilers (such as LLVM, GCC, etc.), greatly expanding the application scope and applicability of the technology.

[0037] 4. Moderate implementation complexity: The present invention is mainly based on the improvement of the existing compiler framework, reusing a large number of existing components, and bringing about a considerable performance improvement without increasing the time complexity of the algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0039] Figure 1 A schematic diagram of an adaptive weighted greedy instruction scheduling system for DSP disclosed in an embodiment of the present invention;

[0040] Figure 2 A flow chart of an adaptive weighted greedy instruction scheduling method for DSP disclosed in an embodiment of the present invention;

[0041] Figure 3 This is the workflow diagram of the greedy scoring decision module;

[0042] Figure 4 This is the workflow diagram of the adaptive weight adjustment module;

[0043] Figure 5 Fixed-point benchmark results running on the RISC-V SummerCore digital signal processor;

[0044] Figure 6 Floating-point benchmark results running on the RISC-V architecture SummerCore digital signal processor. DETAILED DESCRIPTION

[0045] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0046] The present invention provides an adaptive weighted greedy instruction scheduling system for DSP, such as Figure 1 As shown, it includes a ready instruction queue input module, a greedy scoring decision module, an adaptive weight adjustment module, a scheduling queue generation module, a scheduling termination check module, a ready queue update module and a post-scheduling instruction queue output module.

[0047] 1. Ready instruction queue input module:

[0048] The ready instruction queue input module is used to store the ready instruction queue.

[0049] 2. Greedy scoring decision module

[0050] The greedy scoring decision module calculates the basic score according to the attributes of the instructions in the ready instruction queue input module and prioritizes the instructions; this module combines the greedy algorithm and interacts with the adaptive weight adjustment module to quickly select the optimal candidate instructions through comprehensive scoring.

[0051] The core idea of ​​the greedy algorithm is to select the local optimal solution in the current state at each step, and to get as close to the global optimal solution as possible by accumulating the local optimal solutions. In this module, the greedy algorithm calculates the score of the instruction attributes (such as Figure 3 As shown in Figure 1), local scheduling factors such as instruction latency, operand usage, and the number of subsequent instructions are mainly considered to calculate the corresponding greedy cost. Instructions with lower greedy costs are more suitable for priority scheduling and are thus given higher basic scores.

[0052] The greedy cost calculation formula for instruction I is as follows:

[0053] ;

[0054] in, , and are the latency, operand usage, and number of subsequent instructions of instruction I, respectively. , and Corresponding to , and The weight of .

[0055] Then the greedy cost is used to calculate the basic score. The formula for calculating the basic score in the greedy scoring decision module is as follows:

[0056] ;

[0057] in, Represents the base score of Directive I, It is the basic scoring weight, which is used to control the impact of greedy scoring on the total scheduling priority. The larger its value, the more significant the effect of the greedy strategy. It is a scaling factor used to adjust the impact of greedy cost on the score. By using this factor, the speed at which the score of high-cost instructions decreases can be controlled, thereby smoothing the gap between high and low costs. Represents the greedy cost of instruction I.

[0058] At the same time, in order to avoid local optimality leading to global suboptimality, the system also comprehensively considers global scheduling factors (such as resource conflicts, register pressure, whether it is on the critical path, etc.), and sets initial weights for these factors to participate in the comprehensive scoring. These weights will be dynamically adjusted according to the system status, thus affecting the final score. The entire scoring system also adopts the idea of ​​a greedy algorithm, and the instructions with a higher comprehensive score are considered to be the optimal execution instructions under the current conditions. Combined with the adaptive weight adjustment mechanism, the module can quickly and effectively make decisions among multiple candidate instructions, taking into account both local optimality and balancing global scheduling requirements.

[0059] 3. Adaptive weight adjustment module

[0060] During the scoring process, the scoring factor weights of the greedy scoring decision module are not fixed, but are dynamically adjusted by the adaptive weight adjustment module according to the current hardware status (such as register pressure, whether it is on the critical path, resource conflicts, etc.). The dynamically adjusted scoring factor weights directly participate in the final comprehensive score calculation of the greedy scoring decision module. This dynamic adjustment mechanism can optimize the weight allocation according to the real-time status of the hardware and changes in task requirements. For example, when the register pressure is greater than a certain set threshold, the adaptive weight adjustment module will increase the size of the corresponding weight and reduce the size of other weights:

[0061] ;

[0062] ;

[0063] ;

[0064] in, , , They are the adjusted register pressure weight, resource conflict weight, and critical path weight; , , They are the initial register pressure weight, resource conflict weight, and critical path weight; , , It is a weight offset artificially set in the module, so that more attention is paid to instructions that alleviate register conflicts in the scoring; in the critical path tasks, priority is given to factors that contribute to the optimization of the critical path. If some instructions are on the critical path, the weight will be increased accordingly, making these instructions more likely to be selected first.

[0065] The final comprehensive score is calculated as follows:

[0066] ;

[0067] in, For the final comprehensive score, Represents the base score of Directive I, , , They are the adjusted register pressure weight, resource conflict weight, and critical path weight; , , They are register pressure score, resource conflict score, and critical path score.

[0068] Different weights are adjusted according to different situations, so that the scoring process can adapt to different task scenarios and hardware conditions in real time. This collaborative mechanism not only ensures the efficiency of greedy scoring, but also balances the needs of local optimality and global optimization, thereby further improving the overall scheduling performance.

[0069] 4. Scheduling queue generation module

[0070] The scheduling queue generation module selects the current best scheduling instruction according to the final comprehensive score calculation result, removes it from the ready instruction queue and adds it to the post-scheduling instruction queue.

[0071] 5. Scheduling termination check module

[0072] After each scheduling is completed, the scheduling termination check module checks whether the ready instruction queue is empty. If it is empty, it indicates that the scheduling is completed and the final post-scheduling instruction queue is output; if it is not empty, the ready queue update module is executed.

[0073] 6. Ready queue update module

[0074] The ready queue update module is responsible for traversing the remaining instructions that have not been added to the ready instruction queue. By checking the current dependency status of these instructions, it identifies the instructions that have met the dependency conditions and are eligible for scheduling and adds them to the ready instruction queue to prepare for the next round of scheduling. This ensures the continuity and effectiveness of the scheduling process and improves the overall scheduling efficiency of the system.

[0075] 7. Post-scheduling instruction queue output module

[0076] The post-scheduled instruction queue output module is used to store the post-scheduled instruction queue and output the final post-scheduled instruction queue.

[0077] An adaptive weighted greedy instruction scheduling method for DSP, using the above adaptive weighted greedy instruction scheduling system for DSP, such as Figure 2 As shown, the following steps are included:

[0078] (1) System initialization: After the system is started, initialization operations are performed, including preparation of data structures and scheduling environment to prepare for subsequent scheduling.

[0079] (2) Preprocessing stage: The preprocessing stage of instructions mainly consists of three parts: input instruction sequence, instruction dependency analysis, and generation of ready queue. In this stage, the ready instruction queue input module receives the input instruction sequence and forms the initial set of instructions to be processed. Next, it analyzes the dependency relationship between the input instructions, determines the dependencies between each instruction, and adds the instructions that meet the dependencies and meet the scheduling conditions to the ready instruction queue, waiting for subsequent scheduling operations.

[0080] (3) Core scheduling loop:

[0081] Obtain candidate instructions: After entering the core scheduling loop, the greedy scoring decision module obtains candidate instructions from the ready instruction queue.

[0082] System status acquisition: The system collects current status information from the data flow graph, including register pressure, resource occupancy, and pipeline utilization. This step provides contextual information for subsequent scoring calculations.

[0083] Greedy basic score: In this process, the greedy basic score is calculated based on the partial system status obtained in the previous step, such as Figure 3As shown in the figure, this part of the calculation mainly considers the delay of the instruction, the operands used by the instruction, and the number of subsequent instructions of the current instruction to calculate the corresponding greedy cost. The lower the cost, the higher the basic score will be. When other factors such as register pressure or resource usage do not conflict much, the system will tend to schedule instructions with lower greedy costs, which plays a role in rapid selection. After completing the basic score calculation, it will also combine other global scheduling factors for comprehensive score calculation.

[0084] Dynamic weight adjustment: In order to better prevent the system from falling into local optimality, the present invention also introduces factors that take more global information into consideration, such as register pressure, resource usage, and critical path. Each factor is part of the scoring system. In the initial stage, these items will be given the initial scoring factor basic weight. Figure 4 As shown in the figure, the adaptive weight adjustment module collects the current hardware status information, dynamically adjusts the scoring factor weight according to the current hardware status, and forms the final weight. When the register pressure exceeds a certain threshold, the weight of this item will be increased and the weights of the other two items will be reduced. Instructions that occupy fewer registers will be given priority to improve resource utilization, ensuring that the scoring process can flexibly adapt to the current environment, effectively improving the system's robustness and global optimality.

[0085] Comprehensive score calculation: After the weights are adjusted, they will be combined with the previous greedy basic score to obtain a comprehensive score.

[0086] (4) Selecting the optimal instruction: The scheduling queue generation module selects the current best scheduling instruction based on the final comprehensive score calculation result. The instruction with the highest comprehensive score is selected as the current optimal execution instruction.

[0087] (5) Update system status: After selecting the current optimal execution instruction, it needs to be removed from the ready instruction queue and added to the scheduling queue. At the same time, check the instructions that have not been added to the ready instruction queue, identify the instructions whose dependency conditions have been met, add them to the ready queue, and prepare for the next round of scheduling. This part corresponds to Figure 1 The dispatch queue generation module in .

[0088] (6) Next, the ready queue is checked: the scheduling termination check module checks the ready instruction queue: if it is empty, it indicates that the system has completed the scheduling of instructions, and outputs the final scheduled instruction queue; if it is not empty, it returns to step (3) for the next round of scoring and screening until all instructions are scheduled;

[0089] (7) Output optimized sequence: After completing the scheduling operations of all instructions, the post-scheduling instruction queue output module will generate the final instruction queue output as the optimized instruction execution sequence.

[0090] Figure 5 and Figure 6 The results of fixed-point and floating-point benchmarks running on the SummerCore digital signal processor of the RISC-V architecture are shown. These results are obtained by integrating the adaptive weighted greedy instruction scheduling system proposed in the present invention into the LLVM compiler, compiling specific test cases, and running them on the SummerCore digital signal processor. During the experiment, the performance of the scheduling algorithm using the default -O3 optimization mode of LLVM and the scheduling algorithm of the present invention in the same environment were statistically analyzed, and then the performance improvement ratio brought by the present invention was calculated. The test cases used were all written in C language, as follows:

[0091] CFFT (Complex Fast Fourier Transform): Complex Fast Fourier Transform is an algorithm for efficiently calculating Discrete Fourier Transform (DFT), specifically for processing complex inputs. Complex FFT is used to analyze the frequency domain characteristics of signals and is a basic tool in the field of digital signal processing. It is widely used in scenarios such as audio signal processing, image processing, and communication signal analysis. By converting time domain signals into frequency domain signals, CFFT can quickly identify the frequency components, phase information, and amplitude characteristics of the signal.

[0092] ICFFT (Inverse Complex Fast Fourier Transform): ICFFT is a complex inverse fast Fourier transform, which is used to convert frequency domain signals back to time domain signals. The calculation process of ICFFT is opposite to that of CFFT, and it is an important tool for frequency domain to time domain conversion in digital signal processing. ICFFT is widely used in image restoration, signal filtering, communication demodulation and other fields.

[0093] RFFT (Real Fast Fourier Transform): Real Fast Fourier Transform, which is a special form of Fast Fourier Transform (FFT) optimized for real input. Since the input data is real, RFFT can reduce storage and computing requirements during the calculation process, thereby improving processing efficiency. RFFT is widely used in signal processing, audio compression, and communication systems. It differs from CFFT in that RFFT is specifically designed to process real data and can avoid the additional overhead of processing complex operations.

[0094] FIR (Finite Impulse Response Filter): FIR stands for finite impulse response filter, which is an important digital filter. FIR filter can filter signals with precise linear phase and is widely used in signal processing, communication systems, audio processing and other scenarios.

[0095] IIR (Infinite Impulse Response Filter): IIR is an infinite impulse response filter. Compared with FIR filters, IIR has higher computational efficiency, but the complexity of instruction scheduling is higher during implementation. IIR is widely used in real-time signal processing and audio filtering.

[0096] Conv2D (2D Convolution): Conv2D refers to the two-dimensional convolution operation, which is a widely used operation in image processing and deep learning. It plays an important role in feature extraction, edge detection and convolutional neural networks.

[0097] Through the fixed-point and floating-point versions of the above test cases, the adaptive weighted greedy instruction scheduling algorithm proposed in the present invention has excellent performance on the SummerCore digital signal processor. Figure 5 and Figure 6 The experimental results show that the average performance is improved by more than 5% compared with the scheduling algorithm in the traditional LLVM-O3 optimization. In particular, the present invention shows obvious advantages in complex digital signal processing algorithms (such as convolution and fast Fourier transform). These performance improvements are due to the dynamically adjusted scheduling weight mechanism and the scoring strategy that combines global and local information, making the scheduling process more flexible and efficient, providing strong technical support for complex signal processing applications, and having a wide range of application value and potential.

[0098] In summary, the present invention proposes an adaptive scoring mechanism combined with a greedy algorithm. The present invention introduces an innovative scoring mechanism in the instruction scheduling process, which combines the advantages of fast decision-making and adaptive weight adjustment of the greedy algorithm. In each scheduling cycle, the mechanism dynamically calculates the weighted score of the candidate instruction by comprehensively considering multiple key attributes (such as register pressure, critical path, data dependency and execution delay, etc.) of the candidate instruction. Unlike the traditional fixed weight scoring method, this mechanism combines the greedy algorithm to give priority to assigning higher scores to instructions with lower latency and less resource consumption, thereby achieving high efficiency in scheduling decisions. At the same time, the scoring process works in conjunction with the adaptive weight adjustment mechanism to dynamically adjust the weights of each factor according to the real-time hardware status and data dependency, so that the scoring results can take into account both local and global scheduling goals. This adaptive scoring mechanism overcomes the local optimal problem that may be caused by the greedy strategy, and always maintains flexible and efficient scheduling decisions under complex resource constraints and dependencies, effectively improving the overall performance of the system.

[0099] The present invention also proposes an adaptive weight adjustment mechanism that comprehensively considers the instruction scheduling environment. The mechanism can dynamically adjust the weight of the scoring factor according to the key characteristics of the candidate instructions and the current scheduling environment. The mechanism comprehensively considers multiple attributes such as instruction delay, critical path length, data dependency and resource occupancy during the instruction scheduling process, and dynamically calculates and adjusts the weight of each scoring factor by analyzing the instruction characteristics and the scheduling environment status in real time. When the system detects that there are a large number of instructions on the critical path, the mechanism will increase the weight of the critical path related factors and give priority to scheduling these instructions to shorten the total execution time. Similarly, when the register pressure is high, the system will increase the register related weights and give priority to instructions with less register occupancy to alleviate resource pressure. Compared with the traditional fixed weight strategy, the mechanism has stronger adaptability and flexibility, and can be adaptively optimized according to different instruction characteristics and real-time scheduling environment. In addition, the mechanism provides a configurable interface to facilitate the introduction of new scoring factors and weight calculation strategies, and has good extensibility. By comprehensively weighing multiple instruction characteristics and environmental factors, the adaptive weight adjustment mechanism achieves more balanced optimization in terms of performance, power consumption, resource utilization, etc. Through real-time analysis and dynamic adjustment, the system maximizes resource utilization while meeting application requirements, reduces interference between instructions and resource conflicts, and significantly improves overall performance.

[0100] In order to give full play to the advantages of the scoring mechanism and the weight adjustment mechanism, the present invention designs and implements an efficient and scalable instruction scheduling framework specifically for RISC-V digital signal processors. The framework adopts a modular design, mainly including components such as a ready instruction queue input module, a greedy scoring decision module, an adaptive weight adjustment module, a scheduling queue generation module, a scheduling termination check module, a ready queue update module, and a post-scheduling instruction queue output module. Through clearly defined interfaces, each component is decoupled, providing great flexibility, so that the system can flexibly select and configure each module according to actual needs to meet the optimization requirements of different application scenarios. The framework fully considers compilation efficiency and resource overhead in design and implementation. Through optimized data structures and efficient caching mechanisms, the time and space complexity of instruction scheduling are significantly reduced, and the compilation cost is effectively controlled while improving performance. In addition, the framework adopts a standardized interface design, so that it can be easily integrated into the optimization process of mainstream compilers (such as LLVM, GCC, etc.), and can reuse many existing heuristic rules in the original scheduling system, greatly simplifying the development complexity. Through more precise weight adjustment and module configuration, more target architectures can be adapted on the basis of the RISC-V architecture, effectively expanding the scope of application of the technology.

[0101] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An adaptive weighted greedy instruction scheduling system for DSP, characterized in that: It includes a ready instruction queue input module, a greedy scoring decision module, an adaptive weight adjustment module, a scheduling queue generation module, a scheduling termination check module, a ready queue update module and a post-scheduling instruction queue output module; The ready instruction queue input module is used to store the ready instruction queue; The greedy scoring decision module: calculates the basic score according to the attributes of the instructions in the ready instruction queue input module, and prioritizes the instructions; this module combines the greedy algorithm and interacts with the adaptive weight adjustment module to quickly select the best candidate instructions through comprehensive scoring; The adaptive weight adjustment module: dynamically adjusts the scoring factor weight according to the current hardware status, and the dynamically adjusted scoring factor weight directly participates in the final comprehensive score calculation of the greedy scoring decision module; The scheduling queue generation module: selects the current best scheduling instruction according to the final comprehensive score calculation result, removes it from the ready instruction queue and adds it to the post-scheduling instruction queue; The scheduling termination check module: after each scheduling is completed, check whether the ready instruction queue is empty. If it is empty, it indicates that the scheduling is completed, and output the final post-scheduling instruction queue; if it is not empty, execute the ready queue update module; The ready queue update module is responsible for traversing the remaining instructions that have not been added to the ready instruction queue, identifying the instructions that have met the dependency conditions and have the scheduling conditions by checking the current dependency status of these instructions, and adding them to the ready instruction queue to prepare for the next round of scheduling; The post-scheduled instruction queue output module is used to store the post-scheduled instruction queue and output the final post-scheduled instruction queue.

2. The adaptive weighted greedy instruction scheduling system for DSP according to claim 1, characterized in that: The formula for calculating the basic score of the greedy scoring decision module is as follows: ； in, Represents the base score of Directive I, is the basic scoring weight, which is used to control the impact of greedy scoring on the overall scheduling priority. is a scaling factor used to adjust the impact of greedy cost on the score, Represents the greedy cost of instruction I.

3. The adaptive weighted greedy instruction scheduling system for DSP according to claim 2, characterized in that: The greedy cost calculation formula of the instruction I is as follows: ； in, , and are the latency, operand usage, and number of subsequent instructions of instruction I, respectively. , and Corresponding to , and The weight of .

4. The adaptive weighted greedy instruction scheduling system for DSP according to claim 1, characterized in that: The final composite score is calculated as follows: ； in, For the final comprehensive score, Represents the base score of Directive I, , , They are the adjusted register pressure weight, resource conflict weight, and critical path weight; , , They are register pressure score, resource conflict score, and critical path score.

5. An adaptive weighted greedy instruction scheduling method for DSP, using an adaptive weighted greedy instruction scheduling system for DSP as claimed in any one of claims 1 to 4, characterized in that: The steps include: (1) System initialization: After the system is started, initialization operations are performed, including preparation of data structures and scheduling environment; (2) Preprocessing stage: The ready instruction queue input module receives the input instruction sequence, forms an initial set of instructions to be processed, analyzes the dependencies between the input instructions, determines the dependencies between each instruction, and adds the instructions that meet the dependencies and meet the scheduling conditions to the ready instruction queue, waiting for subsequent scheduling operations; (3) Core scheduling loop: The greedy scoring decision module obtains candidate instructions from the ready instruction queue, calculates the basic score based on the attributes of the instructions and the obtained system status, and prioritizes the instructions; at the same time, the adaptive weight adjustment module collects the current hardware status information, dynamically adjusts the scoring factor weight according to the current hardware status, and calculates the final comprehensive score based on the dynamically adjusted scoring factor weight combined with the basic score; (4) Update system status: The scheduling queue generation module selects the current best scheduling instruction based on the final comprehensive score calculation result, removes it from the ready instruction queue and adds it to the post-scheduling instruction queue; at the same time, it checks the instructions that have not been added to the ready instruction queue, identifies the instructions whose dependency conditions have been met, and adds them to the ready instruction queue to prepare for the next round of scheduling; (5) The scheduling termination check module checks the ready instruction queue: if it is empty, it indicates that the system has completed the scheduling of the instructions, and outputs the final scheduled instruction queue; if it is not empty, it returns to step (3) for the next round of scoring and screening until all instructions are scheduled; (6) Output optimized sequence: After completing the scheduling operations of all instructions, the post-scheduling instruction queue output module will generate the final instruction queue output as the optimized instruction execution sequence.

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