Processor verification system and method

Abstract

The invention discloses a processor verification system and method. The processor verification system comprises a monitoring component and a storage component, the storage component is used for storing verification cases; the verification case comprises a plurality of nodes; the verification case is used for triggering the target processor to write node data corresponding to a node into the target memory when the target processor executes any node of the verification case, and the node data represents the state of the target processor when the node of the verification case is executed; and the monitoring component is used for monitoring node data of the target processor.

Description

Technical Field

[0001] The present application relates to the field of verification technology, and in particular to a processor verification system and method. Background Art

[0002] In order to verify whether the processor of an electronic device can work properly, the processor needs to be verified. One method of verifying the processor is that the processor executes a pre-written verification case, and the verification platform collects the relevant data of the processor during the execution of the verification case, and determines whether the processor can successfully execute the verification case by analyzing the data, thereby verifying whether the processor can work properly.

[0003] In the related art, the verification platform obtains the data to be analyzed by monitoring the input / output pins (such as GPIO pins) and registers of the processor. The amount of data collected in this way is small and it is difficult to meet the analysis requirements. Summary of the invention

[0004] To this end, this application discloses the following technical solutions: A first aspect of the present application provides a processor verification system, including a monitoring component and a storage component; The storage component is used to store verification use cases; The verification case includes a plurality of nodes; The verification case is used to trigger the target processor to write node data corresponding to any node of the verification case to the target memory when the target processor executes the verification case, wherein the node data represents the state of the target processor when the node of the verification case is executed; The monitoring component is used to monitor the node data of the target processor.

[0005] Optionally, the monitoring the node data of the target processor includes: When it is detected that the node data is updated, the updated node data is obtained; The updated node data is output.

[0006] Optionally, the monitoring the node data of the target processor includes: Determining target node data among a plurality of node data of the target processor; The target node data of the target processor is monitored.

[0007] Optionally, determining the target node data from a plurality of node data of the target processor includes: The target node data is determined from the plurality of node data of the target processor according to the user operation instruction.

[0008] Optionally, the monitoring of the target node data of the target processor includes: Determining a target storage address of the target node data; The data stored at the target storage address of the target memory is monitored.

[0009] Optionally, the target processor includes a first target processor and a second target processor; The monitoring of the node data of the target processor includes: When it is detected that the first node data written by the first target processor is updated, second node data associated with the updated first node data is obtained from the target memory, where the second node data is the node data written by the second target processor; The associated second node data is output.

[0010] Optionally, the node data also includes interaction data, and the interaction data is data transmitted between the first processor and the second processor when executing to the corresponding node of the verification use case.

[0011] Optionally, the monitoring component is also used for: Update the nodes contained in the verification case.

[0012] A second aspect of the present application provides a processor verification method, comprising: Execute a verification case based on a target processor, wherein the verification case includes a plurality of nodes; When the target processor executes any of the nodes of the verification case, the target memory writes node data corresponding to the node, wherein the node data represents the state of the target processor when the node of the verification case is executed; The node data of the target processor is monitored.

[0013] Optionally, the target processor includes a first target processor and a second target processor; The monitoring of the node data of the target processor includes: When it is detected that the first node data written by the first target processor is updated, second node data associated with the updated first node data is obtained from the target memory, where the second node data is the node data written by the second target processor; The associated second node data is output. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0015] Figure 1 is a structural diagram of a processor verification system provided by an embodiment of the present application; Figure 2 This is a schematic diagram of writing node data provided by an embodiment of the present application; Figure 3 It is a flowchart of a processor verification method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0017] This embodiment provides a processor verification system. Figure 1 The system may include a monitoring component 102 and a storage component 101 .

[0018] The storage component 101 is used to store verification use cases; The verification use case includes multiple nodes; The verification case is used to trigger the target processor to write node data corresponding to the node to the target memory when the target processor executes to any node of the verification case, and the node data represents the state of the target processor when the node of the verification case is executed; The monitoring component 102 is used to monitor the node data of the target processor.

[0019] The monitoring component 102 can be connected to the target storage, thereby monitoring the data in the target storage based on the connection.

[0020] The target processor may include a central processing unit (CPU) of an electronic device, and the verification case may include a first verification case for CPU execution. The first verification case may include a CPU-executable computer program (which may be referred to as a C program) developed entirely based on the C language, and may also include data required for the execution of the computer program.

[0021] The program of the verification case may include multiple pre-set nodes. For example, for the first verification case, the program of the first verification case may include but is not limited to the following nodes: The node that enters the C main function, the node that enters the Handler, the node that completes the IP register configuration, and the node where the C program execution ends.

[0022] The target processor may also include an intellectual property (IP) core of the electronic device. The verification case may include a second verification case for executing the IP core. The second verification case may include a UVM / SV program executable by the IP core and data required to execute the program. UVM stands for Universal Verification Methodology, and SV (SystemVerilog) stands for a hardware description and verification language.

[0023] For the second verification case, the procedure of the second verification case may include but is not limited to the following nodes: Nodes that monitor whether the processor has configured the IP registers, nodes that determine whether the IP core can start working, nodes that wait for interrupts to be cleared, nodes that jump out of the while loop, nodes that wait for operations, and nodes that notify the processor.

[0024] Each of the above nodes may include a number of computer instructions edited by a corresponding programming language. When these computer instructions are executed by a target processor, the target processor will access a target memory of the electronic device to which it belongs, and then write the collected node data corresponding to the node into the target memory.

[0025] The node data corresponding to each node may be the same or different, and which node data a node corresponds to may be specified in the computer instructions contained in the node.

[0026] Taking the target processor as a CPU as an example, during the verification process, the CPU can load a first verification case from the storage component and execute the C program contained in the first verification case. Assuming that the verification case includes a node that completes the IP register configuration, each time the CPU configures the IP register, it can execute the computer instructions contained in the node to collect the node data corresponding to the node, and write the collected node data into the target memory for storage.

[0027] The monitoring component can monitor the node data stored in the target memory regularly or irregularly based on the verification requirements, so that the relevant verification engineers can analyze the node data to determine whether the various functions of the target processor are normal during the verification process.

[0028] The beneficial effect of this embodiment is that, in this embodiment, the processor can write node data reflecting the processor state into the target memory when executing the verification use case, and analyze the function of the processor by monitoring the node data of the target memory. Compared with the related technology of collecting data through input / output pins and registers, this embodiment can use the larger storage space of the target memory to collect larger and more comprehensive node data, thereby providing better data support for the subsequent analysis of the processor function.

[0029] In this embodiment, the target memory and the storage component can be two different modules. The storage component can be a disk, hard disk or other module capable of storing data included in the verification system of this embodiment for storing verification use cases. The target memory can be any storage medium for storing data in the system to which the target processor belongs (that is, the system being verified), including but not limited to the disk, hard disk, memory stick, etc. of the system.

[0030] As an example, when the verification system of this embodiment verifies a target processor installed in a server, the target memory may be a memory bar of the server.

[0031] The verification system of this embodiment has the following advantages in that: Any computer system must contain several memories. Different memories can generally be read and written in a common way, and the reading and writing of data in these memories generally does not affect the functions of the various processors in the system. Therefore, when using it, you only need to connect the monitoring component to the memory of the system to be verified, and you can use the monitoring component to verify the target processor of the system to be verified; In contrast, registers and GPIO pins of different computer systems are quite different, and the reading and writing of registers and GPIO pins may affect the normal operation of the target processor in the system. Therefore, when verifying the target processor through registers or GPIO pins in the related art, it is obviously necessary to configure accordingly according to the characteristics of the GPIO pins and registers in the verified system; It can be seen that the verification system of this embodiment can be conveniently used to verify the target processors of various different computer systems, while the solution of verification through registers or GPIO pins needs to rely on a specific computer system. Therefore, the verification system of this embodiment has higher portability and can be applied to the verification of multiple computer systems.

[0032] The target processor can collect and write the node data to the target memory in a variety of ways. As an example, the target processor can encapsulate the collected node data into a node data packet in a certain format and write the node data packet to the target memory.

[0033] As an example, a node data packet may include 32 bits of data as shown in Table 1, wherein the meaning and default value of each part of the data are as shown in Table 1.

[0034] Taking the node data packet shown in Table 1 as an example, when the target processor executes to a node, it can determine whether the processor has just entered the main function of the C program. If so, it determines that the 0th bit of the node data packet is 1, if not, it determines that the 0th bit of the node data packet is 0. By analogy, the target processor can respectively determine whether the register of the current IP core is configured, whether the program jumps out of the wait state, whether the program jumps out of the while loop, whether the IP core in the system starts working, and whether the processor has completed the execution of the main function. Based on the determined results, the 1st to 3rd bits, the 24th bit and the 31st bit of the node data packet are configured, and the interrupt number and exception number of the processor (if there are interruptions and exceptions) are obtained as the data of the 4th to 23rd bits of the node data packet, and the data of the 24th to 30th bits are set to 0, thereby obtaining a node data packet, and then the target processor can write the node data packet into the target memory.

[0035] Optionally, for any node, the node data corresponding to the node may include other data except the data defined in Table 1.

[0036] As some examples, the node data of a node may include data sent by the target processor to other processors and / or received from other processors. For example, when the target processor is a CPU, the node data of a node may include data sent by the CPU to other IP cores in the system when executing at the node, as well as data sent by other IP cores to the CPU.

[0037] As other examples, the node data of a node may include various data obtained by the target processor when executing the program contained in the verification case, such as the processing result data output by the program when the program is finished executing, the intermediate data generated during the execution of the program, etc.

[0038] During the execution of the verification case by the target processor, the same node may be executed multiple times. Each time a node is executed, the target processor may write a node data corresponding to the node. In the target memory, the same node may correspond to multiple node data.

[0039] Exemplarily, during the execution of the verification use case, the CPU may execute to the node entering the Handler multiple times in succession. Each time the CPU executes to the node, it writes a copy of the node's node data to the target memory (for example, writes a node data packet corresponding to the node). Correspondingly, the target memory may contain multiple copies of node data corresponding to the nodes entering the Handler.

[0040] In a computer system, a Handler can be understood as a program responsible for handling specific tasks or specific events. The handler can perform corresponding operations based on input parameters or events. For example, an operating system can have an interrupt handler and an event handler. When a hardware interrupt event occurs, the target processor can enter the interrupt handler to handle the hardware interrupt event. When a user interaction event occurs, the target processor can enter the event handler to handle the user interaction operation.

[0041] The monitoring component 102 may monitor the node data of the target processor in the following manner: When it is detected that the node data is updated, the updated node data is obtained; Output the updated node data.

[0042] Monitoring that the node data is updated may include monitoring that new node data is added in the target storage. In this case, the updated node data may include the new node data.

[0043] As an example, when the monitoring component detects that a node data packet corresponding to a node newly added to the target memory and entering the Handler is added, the monitoring component can read the node data packet from the target memory and output the node data packet as updated node data.

[0044] Monitoring that node data is updated may also include monitoring that new node data different from original node data in the target memory is written into the target memory. In this case, the updated node data may include the new node data different from original node data in the target memory.

[0045] As an example, when the monitoring component detects a new node data packet corresponding to a node entering the Handler in the target memory, the monitoring component can compare the new node data packet with the node data packet corresponding to the node entering the Handler previously written by the target processor. If the two are inconsistent, it is determined that the node data corresponding to the node entering the Handler is updated, and the new node data packet is obtained as the updated node data.

[0046] Monitoring that the node data is updated may also include monitoring that new node data different from original node data in the target memory is written into the target memory, and the target data contained in the new node data is different from the target data contained in the original node data.

[0047] The target data may be a specific part of the data contained in the node data. In combination with the example in Table 1, a piece of node data written by the target processor to the memory may be a node data packet shown in Table 1, and the target data may be the data of bits 12 to 19 in the node data packet, that is, the data in the node data packet indicating the interrupt number (hexadecimal) entering the interrupt handler.

[0048] In combination with the above example, if a node data packet corresponding to a new node entering the Handler is monitored in the target memory, and it is determined that the target data in the newly added node data packet is different from the target data in the node data packet of the node entering the Handler written last time, that is, the data from bits 12 to 19 of the two node data packets are different, then it is determined that the node data corresponding to the node entering the Handler is updated. At this time, the monitoring component can obtain the newly added node data packet as the updated node data.

[0049] The monitoring component can output the updated node data in a variety of ways. For example, the monitoring component can print the updated node data as an electronic document or a paper document, and the monitoring component can display and output the updated node data on a display screen.

[0050] In some embodiments, when the monitoring component outputs the updated node data, only a portion of the updated node data may be output. Taking the node data packet shown in Table 1 as an example, when the monitoring component outputs the updated node data packet, only the data of bits 12 to 19 in the node data packet may be output. The monitoring component may determine which data in the node data packet to output based on the user's operation.

[0051] In some optional embodiments, in order to reduce the power consumption of the monitoring component, the monitoring component may monitor only a part of the node data when monitoring the node data. That is, the monitoring component may: determining target node data among a plurality of node data of a target processor; Monitor target node data of the target processor.

[0052] In the above embodiment, the monitoring component can determine at least one target node from the multiple nodes included in the verification use case, and use the node data written when the target processor executes the target node as the target node data. Then, the monitoring component can only monitor whether the target node data is updated, and output the updated target node data when it is detected that the target node data is updated.

[0053] As an example, assuming that the monitoring component determines that the node that has completed the IP register configuration is the target node, the monitoring component can only monitor whether the node data of the node that has completed the IP register configuration in the target memory is updated, and output the updated node data of the node that has completed the IP register configuration when the update is detected, and the node data of other nodes will not be monitored and output.

[0054] The monitoring component can determine the target node data in the following ways: The target node data is determined from a plurality of node data of the target processor according to the user operation instruction.

[0055] In this embodiment, when determining the target node, the monitoring component can prompt the user to input one or more node identifiers, or prompt the user to select one or more node identifiers from multiple node identifiers, and then determine the node corresponding to the node identifier input or selected by the user as the target node, and then determine the node data corresponding to the target node as the target node data.

[0056] Exemplarily, when determining the target node, the user can select the node identifier 3 representing the node that has completed the IP register configuration, whereby the monitoring component can determine that the target node is the node that has completed the IP register configuration, and use the node data corresponding to the target node as the target node data.

[0057] In some optional embodiments, several storage addresses for storing node data can be pre-specified in the target memory, each storage address corresponds to a node of the verification use case, and each time the target processor executes a node, the obtained node data of the node can be written into the storage address corresponding to the node for storage.

[0058] For example, see Figure 2 , storage address 1 to storage address N can be specified in the target memory, corresponding to nodes 1 to node N of the verification use case in turn. When the target processor executes the verification use case, when it executes to node 1, it obtains node data 1 corresponding to node 1, and writes node data 1 to storage address 1. When it executes to node 2, it obtains node data 2 corresponding to node 2, and writes node data 2 to storage address 2, and so on.

[0059] Based on the above storage method, when monitoring the target node data, the monitoring component can: Determine the target storage address of the target node data; Data stored at a target storage address of a target memory is monitored.

[0060] For example, after determining that the target node is node 4, the monitoring component can detect in real time whether the node data at storage address 4 in the target memory is updated. If it is detected that the node data at storage address 4 is updated, the updated node data stored in storage address 4 is obtained and output.

[0061] Optionally, the monitoring component can also be used to: Update the nodes included in the verification case.

[0062] In this embodiment, the monitoring component can display the program included in the verification use case based on the user operation, so that the user can add or delete a node at any position of the program.

[0063] For any existing node in the verification case, the monitoring component can display the computer instructions contained in the node on the display screen, so that the user can add, delete or modify the computer instructions in the node as needed.

[0064] In some optional embodiments, the target processor may include a first target processor and a second target processor; When the monitoring component monitors the node data of the target processor, it can be used to: When it is detected that the first node data written by the first target processor is updated, second node data associated with the updated first node data is obtained from the target memory, where the second node data is the node data written by the second target processor; Output the associated second node data.

[0065] As some examples, the first target processor may be a CPU and the second target processor may be an IP core.

[0066] If there are two nodes with a dependency relationship between a first verification case executed by a first target processor and a second verification case executed by a second target processor, that is, there is a dependency relationship between the first node of the first verification case and the second node of the second verification case, then it can be considered that the first node data corresponding to the first node is associated with the second node data corresponding to the second node.

[0067] In this embodiment, if the first node and the second node are both related to specific partial data, it can be considered that there is a dependency relationship between the first node and the second node. Exemplarily, in the following cases, it can be considered that there is a dependency relationship between the first node and the second node: When the first target processor executes to the first node of the first verification case, it sends specific data to the second target processor. When the second target processor executes to the second node of the second verification case, it processes the specific data sent by the first target processor.

[0068] In this embodiment, the monitoring component can analyze the node data written by the first target processor and the node data written by the second target processor to determine which node data are related to each other. For example, the node data A written by the first target processor and the node data B written by the second target processor both contain certain data C, and the data C is data sent from the first target processor to the second target processor, or from the second target processor to the first target processor. In this case, it can be determined that there is a dependency relationship between the node corresponding to the node data A and the node corresponding to the node data B, and the node data A and the node data B are related to each other.

[0069] Alternatively, the monitoring component may determine which node data are related to each other based on dependencies between nodes pre-set by the user.

[0070] Optionally, the target memory can store multiple second node data written by the second target processor multiple times. When it is detected that the first node data written by the first target processor is updated, the monitoring component can obtain the data associated with the updated first node from the target memory, and output the second node data most recently written by the second target processor.

[0071] In the above embodiment, the monitoring component may output the second node data and the updated first node data together.

[0072] This embodiment also provides a processor verification method, see Figure 3 , is a flow chart of the method, and the method may include the following steps.

[0073] S301, executing a verification case based on a target processor, where the verification case includes multiple nodes.

[0074] S302, when the target processor executes to any node of the verification case, the target memory writes the node data corresponding to the node, and the node data represents the state of the target processor when executing to the node of the verification case.

[0075] S303, monitoring the node data of the target processor.

[0076] Optionally, the target processor includes a first target processor and a second target processor; Monitor the node data of the target processor, including: When it is detected that the first node data written by the first target processor is updated, the second node data associated with the updated first node data is obtained from the target memory, and the second node data is the node data written by the second target processor.

[0077] The implementation of the processor verification method of this embodiment can refer to the working principle of the aforementioned processor verification system, which will not be described in detail.

[0078] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0079] For the convenience of description, the above system or device is described by dividing it into various modules or units according to its functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0080] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.

[0081] Finally, it should be noted that, in this article, relational terms such as first, second, third and fourth are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0082] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A processor verification system, comprising a monitoring component and a storage component; The storage component is used to store verification use cases; The verification case includes a plurality of nodes; The verification case is used to trigger the target processor to write node data corresponding to any node of the verification case to the target memory when the target processor executes the verification case, wherein the node data represents the state of the target processor when the node of the verification case is executed; The monitoring component is used to monitor the node data of the target processor.

2. The system according to claim 1, wherein monitoring the node data of the target processor comprises: When it is detected that the node data is updated, the updated node data is obtained; The updated node data is output.

3. The system according to claim 1, wherein monitoring the node data of the target processor comprises: Determining target node data among a plurality of node data of the target processor; The target node data of the target processor is monitored.

4. The system according to claim 3, wherein determining the target node data from the plurality of node data of the target processor comprises: The target node data is determined from the plurality of node data of the target processor according to the user operation instruction.

5. The system according to claim 3, wherein monitoring the target node data of the target processor comprises: Determining a target storage address of the target node data; The data stored at the target storage address of the target memory is monitored.

6. The system according to claim 1, wherein the target processor comprises a first target processor and a second target processor; The monitoring of the node data of the target processor includes: When it is detected that the first node data written by the first target processor is updated, second node data associated with the updated first node data is obtained from the target memory, where the second node data is the node data written by the second target processor; The associated second node data is output.

7. According to the system of claim 6, the node data also includes interaction data, and the interaction data is data transmitted between the first processor and the second processor when executing to the corresponding node of the verification use case.

8. The system according to claim 1, wherein the monitoring component is further configured to: Update the nodes contained in the verification case.

9. A processor verification method, comprising: Execute a verification case based on a target processor, wherein the verification case includes a plurality of nodes; When the target processor executes any of the nodes of the verification case, the target memory writes node data corresponding to the node, wherein the node data represents the state of the target processor when the node of the verification case is executed; The node data of the target processor is monitored.

10. The method according to claim 9, wherein the target processor comprises a first target processor and a second target processor; The monitoring of the node data of the target processor includes: When it is detected that the first node data written by the first target processor is updated, second node data associated with the updated first node data is obtained from the target memory, where the second node data is the node data written by the second target processor; The associated second node data is output.

Images