Parameter transmission method, electronic device and medium based on chip verification

Abstract

The present invention relates to the field of chip technology, and in particular to a parameter transmission method based on chip verification, an electronic device and a medium, the method comprising: step S1, constructing a hierarchical verification component and determining hierarchical structure information corresponding to each verification component; step S2, constructing each A n The corresponding parameter definition file, and F n Mounted on the corresponding A n Step S3, define the parameter setting list in the simulation tool command line; Step S4, in target A n Get the target P i n , the target P i n With target A n The corresponding target H n Splice to generate target B m , determine target B based on the parameter setting list m The corresponding parameter value target V m The present invention avoids parameter conflicts in the parameter transmission process, improves the accuracy of parameter transmission, and improves chip verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a parameter transmission method, electronic equipment and medium based on chip verification. Background Art

[0002] In chip verification (Intellectual Property), parameters need to be defined and values ​​need to be transmitted for the parameters. In the prior art, Plus-args is often used for parameter transmission. The Plus-args parameter transmission method can be quickly recognized by simulation tools (such as VCS), and the Plus-args-based parameter transmission method can quickly and accurately transmit parameters during the verification process of a single IP (Intellectual Property). However, if the system-on-chip (System on Chip, referred to as SOC) is verified, it is necessary to involve the interaction between multiple IPs. If different IPs define parameters with the same name, parameter conflicts will occur and they cannot interact normally, and a lot of cost will be spent to modify the parameters. In addition, for parameters with the same name that do not conflict, it will be difficult to locate and debug them later, which greatly increases the cost of chip debugging and reduces the efficiency of chip verification. It can be seen from this that how to avoid parameter conflicts in the parameter transmission process, improve the accuracy of parameter transmission, and improve chip verification efficiency have become technical problems that need to be solved urgently. Summary of the invention

[0003] The purpose of the present invention is to provide a parameter transmission method, electronic device and medium based on chip verification, which avoids parameter conflicts in the parameter transmission process, improves the accuracy of parameter transmission, and improves chip verification efficiency.

[0004] According to a first aspect of the present invention, a parameter transmission method based on chip verification is provided, comprising:

[0005] Step S1: Construct a verification component {A1, A2, ..., A n ,...,A N} and determine the hierarchical structure information corresponding to each verification component {H1,H2,...,H n ,...,H N}, where A n is the nth verification component, H n A n The corresponding hierarchical structure, n ranges from 1 to N, where N is the total number of verification components;

[0006] Step S2: construct each A n Corresponding parameter definition file F n ={P1 n ,P2 n ,...,Pi n ,...,P f(n) n}, and F n Mounted on the corresponding A n Upper, P i n A n The corresponding i-th parameter definition, i ranges from 1 to f(n), f(n) is A n The total number of corresponding parameters;

[0007] Step S3: define the parameter setting list {(B1, V1), (B2, V2), ..., (B m ,V m ),...,(B M ,V M )},B m is the mth parameter name set in the simulation tool command line. The parameter name is generated by combining the parameter definition and the hierarchical structure corresponding to the verification component where the parameter definition is located. m B is set in the simulation tool command line m The corresponding parameter value;

[0008] Step S4: At target A n Get the target P i n , the target P i n With target A n The corresponding target H n Splice to generate target B m , determine target B based on the parameter setting list m The corresponding parameter value target V m .

[0009] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the parameter transmission method, electronic device and medium based on chip verification provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects:

[0012] The present invention sets parameters based on the hierarchical structure of verification components, defines corresponding parameters for each verification component according to the hierarchical structure, and sets corresponding parameter values ​​based on the unique name of each parameter in the simulation tool command line, thereby avoiding parameter conflicts in the parameter transmission process, improving the accuracy of parameter transmission, and improving chip verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flow chart of a parameter transmission method based on chip verification provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a parameter transmission method based on chip verification, such as Figure 1 As shown, including:

[0017] Step S1: Construct a verification component {A1, A2, ..., A n ,...,A N} and determine the hierarchical structure information corresponding to each verification component {H1,H2,...,H n ,...,H N}, where A n is the nth verification component, H n A n Corresponding to the hierarchical structure, the value of n ranges from 1 to N, where N is the total number of verification components.

[0018] It should be noted that the verification component is a module for implementing chip verification, and verification of the chip design to be verified is achieved through interaction between verification components and interaction between verification components and the chip design to be verified.

[0019] Step S2: construct each A n Corresponding parameter definition file F n ={P1 n ,P2 n ,...,P i n ,...,P f(n) n}, and F n Mounted on the corresponding A n Upper, P i n A n The corresponding i-th parameter definition, i ranges from 1 to f(n), f(n) is A n The total number of corresponding parameters.

[0020] It should be noted that each A n The corresponding parameter definition files can be developed independently. n Different P i n There will be no duplication of names, no conflicts. n The corresponding P i n There may be duplicate names, but when parameters are transmitted across components later, the corresponding parameter name is P i n With A n The combination of corresponding hierarchical structures ensures that parameter names are unique and conflict-free when parameters are transmitted across components.

[0021] Step S3: define the parameter setting list {(B1, V1), (B2, V2), ..., (B m ,V m ),...,(B M ,V M )},B m is the mth parameter name set in the simulation tool command line. The parameter name is generated by combining the parameter definition and the hierarchical structure corresponding to the verification component where the parameter definition is located. m B is set in the simulation tool command line m The corresponding parameter value.

[0022] The simulation tool may specifically be VCS or the like.

[0023] Step S4: At target A n Get the target Pi n , the target P i n With target A n The corresponding target H n Splice to generate target B m , determine target B based on the parameter setting list m The corresponding parameter value target V m .

[0024] It should be noted that, based on the method described in the embodiment of the present invention, conflict-free parameter transfer can be achieved no matter within a verification component or across components.

[0025] As an example, if the parameter transmission is located at target A n In the example of FIG. 1 , that is, within a verification component, step S4 comprises:

[0026] Step S41: At target A n Get the target P i n , based on the target P i n In Target A n Build the target execution statement in .

[0027] The target execution statement may be a selection judgment statement, which may be set to be based on the current target P i n The specific value of , selects the corresponding operation statement to execute, so it is necessary to accurately obtain the current target P i n The value of .

[0028] Step S42: Set the target P i n With target A n The corresponding target H n Splice to generate target B m .

[0029] It should be noted that the target P is determined in step S42. i n The corresponding unique parameter name target B m .

[0030] Step S43: Determine target B based on the parameter setting list m The corresponding parameter value target V m , the target V m Transfer to target A n The target P i n .

[0031] Through Target B m Ability to obtain target V from parameter settings list defined in simulation tool command line m .

[0032] Step S44, target A n Based on the target P i n The corresponding target V m Execute the target execution statement.

[0033] In which, the target V is set to m Substitute into the target execution statement, determine the target operation statement and execute it.

[0034] As an embodiment, if the parameter transmission is located in the first A n and the second A n Between, that is, to transmit parameters across components, the first A n and the second A n All belong to {A1,A2,...,A n ,...,A N}. First A n and the second A n For two A with interaction requirements n , first A n A is currently to be executed n , Second A n For the first A n A of the transmission parameters n , the step S4 comprises:

[0035] Step C41: The second A n Determined as Target A n , at target A n Get the target P i n .

[0036] It is understandable that the target P i n For the first A n Need to start from the second A n Parameters obtained from .

[0037] Step C42: Set the target P i n With target A n The corresponding target H n Splice to generate target B m , based on target B m In the first A n Build the target execution statement in .

[0038] It should be noted that the target P is determined in step C42.i n The corresponding unique parameter name target B m .

[0039] Step C43: Determine target B based on the parameter setting list m The corresponding parameter value target V m , the target V m Transmit to First A n Target B m .

[0040] Through Target B m Ability to obtain target V from parameter settings list defined in simulation tool command line m .

[0041] Step C44, first A n Based on Target B m The corresponding target V m Execute the target execution statement.

[0042] In step C44, the target V m Substitute into the target execution statement, determine the target operation statement and execute it.

[0043] The hierarchical verification components can specifically adopt the hierarchical structure of the unified verification methodology (Universal Verification Methodology, UVM for short), and no matter the embodiments of the present invention are used for the verification of chip IP or the verification of a SOC chip composed of multiple chip IPs, there will be no parameter conflict and accurate transmission of parameters can be achieved.

[0044] As an embodiment, in the step S1, the design to be verified is a chip IP, and the verification components of the hierarchical setting include {IPT, IPE, IPD, IPM, IPS}; wherein, IPT, IPE, IPD, IPM, IPS are all generated based on a hardware description language, and the hardware description language can specifically adopt Verilog, SystemVerilog, etc. IPT is a test case component of the chip IP, IPE is a verification environment component of the chip IP, IPD is a driver component of the chip IP, IPM is a monitoring component of the chip IP, and IPS is a sequencer of the chip IP. The specific hierarchical structure is set as follows: IPT is the root node, IPT is the parent node of IPE, IPE is the parent node of IPD, IPM and IPS, and IPD, IPM and IPS are leaf nodes. Normally, IPS is used to generate incentives and send them to IPD, IPD drives the design to be verified through the engine, and when the design to be verified is executed, data comparison is performed through IPM to realize the verification of the design to be verified. In this process, the verification components corresponding to the chip IP need to continuously transmit parameters for interaction, and the parameter transmission process can be implemented based on steps S1-step S4.

[0045] As an embodiment, in step S1, the chip to be verified is designed as a SOC chip, and the SOC chip includes K chip IPs {IP1, IP2, ..., IP k ,...,IP K}, IP k For the Kth chip IP of the SOC chip, the verification components set at the level include {SOCT, SOCE, SOCD, SOCM, SOCS}. Among them, SOCT, SOCE, SOCD, SOCM, SOCS are generated based on the hardware description language, and the hardware description language can be specifically Verilog, SystemVerilog, etc. SOCT is the test case component of the SOC chip, SOCE is the verification environment component of the SOC chip, SOCD is the driver component of the SOC chip, SOCM is the monitoring component of the chip SOCIP, SOCS is the sequencer of the SOC chip, and the specific hierarchical structure is set as follows: SOCT is the root node, SOCT is the parent node of IPE, SOCE is the parent node of SOCD, SOCM and SOCS, and SOCD, SOCM and SOCS are leaf nodes. Normally, SOCS is used to generate stimulus and send it to SOCD. SOCD drives the design to be verified through the engine. When the design to be verified is executed, data comparison is performed through SOCM to realize the verification of the design to be verified. In this process, the verification components corresponding to the chip IP need to continuously transmit parameters for interaction. The parameter transmission process can be implemented based on steps S1 to S4.

[0046] In order to further reduce the cost of chip verification and improve the efficiency of chip verification, when the chip to be verified is designed as a SOC chip, the verification components corresponding to the chip IP contained in the SOC chip can be directly reused, and the verification components of different chip IPs and the verification components of the chip IP and the verification components of the SOC can be based on steps S1 to S4. Parameter transmission will not occur. As an embodiment, in step S1, the chip to be verified is designed as a SOC chip, and the SOC chip includes K chip IPs {IP1, IP2, ..., IP k ,...,IP K}, IP k is the Kth chip IP of the SOC chip, the value range of k is 1 to K, and K is the total number of chip IPs contained in the SOC chip. The verification components of the hierarchical setting include: {SOCT, SOCE, IPE1, IPD1, IPM1, IPS1, IPE2, IPD2, IPM2, IPS2, ..., IPE k ,IPD k ,IPM k ,IPS k ,...,IPE K ,IPD K ,IPM K ,IPS K}; Among them, SOCT, SOCE, IPE1, IPD1, IPM1, IPS1, IPE2, IPD2, IPM2, IPS2, ..., IPE k ,IPD k ,IPM k ,IPS k ,...,IPE K ,IPD K ,IPM K ,IPS K Generated based on hardware description language, which can be Verilog, SystemVerilog, etc. SOCT is the test case component of SOC chip, SOCE is the verification environment component of SOC chip, IPD1, IPM1, IPS1, IPE2, IPD2, IPM2, IPS2, ..., IPE k ,IPD k ,IPM k ,IPS k ,...,IPE K ,IPD K ,IPM K ,IPS K They are all verification components corresponding to the reused chip IP. k IP kVerification environment components, IPD k IP k Drive components, IPM k IP k Monitoring component, IPS k IP k The specific hierarchical structure is set as follows: SOCT is the root node, SOCT is the parent node of SOCE, SOCE is IPE1, IPE2, ... IPE k ...、IPE k The parent node of IPE k IPD k 、IPM k ,IPS k The parent node of all IPD k ,IPM k ,IPS k They are all leaf nodes. Usually, when verification involves IP k When IPS k Used to generate incentives and send to IPD k , IPD k The engine drives the design to be verified. When the design to be verified is executed, data comparison is performed through IPM. When it comes to the interaction between different chip IPs, the verification components of different chip IPs and the verification components of different chip IPs and SOC chips will also interact. In these processes, it is necessary to continuously transmit parameters between the verification components corresponding to the chip IPs and between the verification components of different chip IPs and SOC chip verification components for interaction. The parameter transmission process can be implemented based on steps S1-S4.

[0047] It should be noted that during the verification process, some software configuration operations may also be designed, and software parameters need to be transmitted, such as configuring GPU (Graphics Processing Unit), managing GPU memory, modifying command lines, etc. When implementing software parameter transmission, it can also be implemented based on steps S1-S4. As an embodiment, in step S1, the hierarchical verification components {SWT, SWA, SWD, SWC} are generated based on software languages, SWT is a software test case component, SWA is a software application program interface, SWD is a software driver component, SWC is a software test code component, SWT is the root node, SWT is the parent node of SWA, SWD is the parent node of SWC, and SWC is a leaf node. Usually, SWT calls SWA, drives SWC based on SWD, and implements operations such as software-based parameter configuration. Implementing based on steps S1-S4 can also avoid parameter conflicts and improve the accuracy of parameter transmission.

[0048] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0049] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0050] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0051] The embodiment of the present invention sets parameters based on the hierarchical structure of the verification components, defines corresponding parameters for each verification component according to the hierarchical structure, and sets corresponding parameter values ​​based on the unique name of each parameter in the simulation tool command line, thereby avoiding parameter conflicts in the parameter transmission process, improving the accuracy of parameter transmission, and improving chip verification efficiency.

[0052] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A parameter transmission method based on chip verification, characterized in that: include: Step S1: Construct a verification component {A1, A2, ..., A n ,...,A N } and determine the hierarchical structure information corresponding to each verification component {H1,H2,...,H n ,...,H N }, where A n is the nth verification component, H n A n The corresponding hierarchical structure, n ranges from 1 to N, where N is the total number of verification components; Step S2: construct each A n Corresponding parameter definition file F n ={P1 n ,P2 n ,...,P i n ,...,P f(n) n }, and F n Mounted on the corresponding A n Upper, P i n A n The corresponding i-th parameter definition, i ranges from 1 to f(n), f(n) is A n The total number of corresponding parameters; Step S3: define the parameter setting list {(B1, V1), (B2, V2), ..., (B m ,V m ),...,(B M ,V M )},B m is the mth parameter name set in the simulation tool command line. The parameter name is generated by combining the parameter definition and the hierarchical structure corresponding to the verification component where the parameter definition is located. m B is set in the simulation tool command line m The corresponding parameter value; Step S4: At target A n Get the target P i n , the target P i n With target A n The corresponding target H n Splice to generate target B m , determine target B based on the parameter setting list m The corresponding parameter value target V m .

2. The method according to claim 1, characterized in that If the parameter transfer is located at target A n In the step S4, the step S4 comprises: Step S41: At target A n Get the target P i n , based on the target P i n In Target A n Build the target execution statement in Step S42: Set the target P i n With target A n The corresponding target H n Splice to generate target B m ; Step S43: Determine target B based on the parameter setting list m The corresponding parameter value target V m , the target V m Transfer to target A n The target P i n ; Step S44, target A n Based on the target P i n The corresponding target V m Execute the target execution statement.

3. The method according to claim 1, characterized in that If the parameter transmission is located in the first A n and the second A n Between, the first A n and the second A n For two A with interaction requirements n , first A n A is currently to be executed n , Second A n For the first A n A of the transmission parameters n , the step S4 comprises: Step C41: The second A n Determined as Target A n , at target A n Get the target P i n ; Step C42: Set the target P i n With target A n The corresponding target H n Splice to generate target B m , based on target B m In the first A n Build the target execution statement in Step C43: Determine target B based on the parameter setting list m The corresponding parameter value target V m , the target V m Transmit to First A n Target B m ; Step C44, first A n Based on Target B m The corresponding target V m Execute the target execution statement.

4. The method according to any one of claims 1 to 3, characterized in that: In step S1, the design to be verified is a chip IP, and the hierarchical verification components include {IPT, IPE, IPD, IPM, IPS}; Among them, IPT, IPE, IPD, IPM, and IPS are all generated based on the hardware description language, IPT is the test case component of the chip IP, IPE is the verification environment component of the chip IP, IPD is the driver component of the chip IP, IPM is the monitoring component of the chip IP, IPS is the sequencer of the chip IP, IPT is the root node, IPT is the parent node of IPE, IPE is the parent node of IPD, IPM and IPS, and IPD, IPM and IPS are leaf nodes.

5. The method according to any one of claims 1 to 3, characterized in that: In step S1, the chip to be verified is designed as a SOC chip, and the SOC chip includes K chip IPs {IP1, IP2, ..., IP k ,...,IP K }, IP k For the Kth chip IP of the SOC chip, the verification components set at the level include {SOCT, SOCE, SOCD, SOCM, SOCS}; Among them, SOCT, SOCE, SOCD, SOCM, and SOCS are generated based on the hardware description language, SOCT is the test case component of the SOC chip, SOCE is the verification environment component of the SOC chip, SOCD is the driver component of the SOC chip, SOCM is the monitoring component of the chip SOCIP, SOCS is the sequencer of the SOC chip, SOCT is the root node, SOCT is the parent node of IPE, SOCE is the parent node of SOCD, SOCM, and SOCS, and SOCD, SOCM, and SOCS are leaf nodes.

6. The method according to any one of claims 1 to 3, characterized in that: In step S1, the chip to be verified is designed as a SOC chip, and the SOC chip includes K chip IPs {IP1, IP2, ..., IP k ,...,IP K }, IP k The Kth chip IP of the SOC chip, the value range of k is 1 to K, and the verification components of the hierarchical setting include: {SOCT, SOCE, IPE1, IPD1, IPM1, IPS1, IPE2, IPD2, IPM2, IPS2, ..., IPE k ,IPD k ,IPM k ,IPS k ,...,IPE K ,IPD K ,IPM K ,IPS K }; Among them, SOCT, SOCE, IPE1, IPD1, IPM1, IPS1, IPE2, IPD2, IPM2, IPS2, ..., IPE k ,IPD k ,IPM k ,IPS k ,...,IPE K ,IPD K ,IPM K ,IPS K Based on hardware description language generation, SOCT is the test case component of SOC chip, SOCE is the verification environment component of SOC chip, and IPE is the verification environment component of SOC chip. k IP k Verification environment components, IPD k IP k Drive components, IPM k IP k Monitoring component, IPS k IP k The sequence generator, SOCT is the root node, SOCT is the parent node of SOCE, SOCE is IPE1, IPE2, ... IPE k ...、IPE k The parent node of IPE k IPD k 、IPM k ,IPS k The parent node of all IPD k ,IPM k ,IPS k All are leaf nodes.

7. The method according to any one of claims 1 to 3, characterized in that: In the step S1, the verification components {SWT, SWA, SWD, SWC} are set up in a hierarchical manner, wherein SWT, SWA, SWD, and SWC are generated based on the software language, SWT is a software test case component, SWA is a software application program interface, SWD is a software driver component, SWC is a software test code component, SWT is a root node, SWT is a parent node of SWA, SWD is a parent node of SWC, and SWC is a leaf node.

8. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions to be executed by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method of any one of the preceding claims 1-7.

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