LOD effect mismatch model extraction method and storage medium thereof

Abstract

The invention discloses an LOD effect mismatch model extraction method. The method comprises the following steps: S1, designing devices with different active region length sizes; s2, performing full map test of wafers on the electrical parameters under the device structures with the multiple groups of paired source regions with the same length size; s3, calculating a threshold voltage difference value and a saturation current difference value of two devices with the same source region length size under the same Die; s4, Median values and standard deviation Sigma are calculated for electrical parameters of two devices under all dies, whether data of all dies are reasonable or not is judged, unreasonable data of dies are removed, and reasonable data of dies are reserved; s5, calculating a standard deviation of the threshold voltage difference value and the saturation current difference value of the reasonable die to obtain a mismatch data value of the threshold voltage and the saturation current, and performing fitting simulation on the mismatch data value to obtain a mismatch rate simulation curve of each parameter; s6, establishing a mismatch model in the LOD effect; and S7, adjusting parameters of the mismatch model to obtain the mismatch model related to the length of the active area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a LOD effect mismatch model extraction method and a storage medium thereof. Background Art

[0002] Effective isolation between adjacent MOS transistors is one of the key technologies in CMOS integrated chip manufacturing. Nowadays, shallow trench dielectric isolation (STI) has replaced the local silicon oxide isolation (LOCOS) process and become the mainstream isolation technology in integrated circuit manufacturing. However, as the size of MOSFET devices continues to shrink, the impact of the mechanical stress generated by STI on device performance has become increasingly serious and has reached a level that cannot be ignored. The mechanical stress generated by STI technology will cause a series of changes in the physical parameters of the device, such as carrier mobility, impurity diffusion coefficient, and effective carrier mass, resulting in device electrical parameters such as threshold voltage and drain saturation current changing with the length of the active area (Length of Diffusion, referred to as LOD), that is, the distance from the device gate to STI.

[0003] In order to improve the carrier mobility of devices, a large number of stress enhancement technologies are introduced in advanced processes. These have led to an increasing influence of the environment around the device on the electrical characteristics of the device itself. However, the mismatch model of LOD is lacking in the current LOD model. In advanced integrated circuits, the mismatch characteristics of devices and their modeling are receiving more and more attention. As the size of devices becomes smaller and smaller, the different active length region environments have an increasing impact on the electrical characteristics of the device itself, which in turn affects the local mismatch characteristics of the device. In the current LOD model, the impact of different active length environments on its mismatch characteristics is not considered. In actual situations, the mismatch characteristics of different active region lengths have different effects on the performance of devices. This is where the current LOD model is relatively lacking.

[0004] A trend break or trend mutation generally refers to a sudden and significant change or turning point observed in a field or data set. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which are all simplifications of the prior art in the field, and will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention of the present invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] The technical problem to be solved by the present invention is to provide a method for extracting LOD effect mismatch models which takes into account the influence of the change in active area length on the device LOD effect mismatch model, and can accurately characterize the mismatch characteristics of the device under different active length environments, thereby providing a more accurate and more practical LOD effect mismatch model extraction method.

[0007] In order to solve the above technical problems, the present invention provides a method for extracting a LOD effect mismatch model, comprising:

[0008] S1, design devices with different active area length dimensions;

[0009] S2, perform full map test of wafer for vtlin, vtsat, idlin, and idsat under two device structures with the same source region length size;

[0010] Vtlin is the threshold voltage in the linear region, Vtsat is the threshold voltage in the saturation region, Idlins is the linear current, and Idsats is the saturation current

[0011] S3, calculating the difference in threshold voltage and saturation current between two devices under the same Die;

[0012] S4, calculate the Median value and the standard deviation Sigma of the vtlin, vtsat, idlin, and idsat of the two devices under all dies, determine whether the data of each die is reasonable, remove the unreasonable die data, and retain the reasonable die data;

[0013] S5, calculating the standard deviation of the threshold voltage difference value and the saturation current difference value of the reasonable die, obtaining the mismatch data value of the threshold voltage and the saturation current, and performing fitting simulation on the mismatch data value to obtain the mismatch rate simulation curve of each parameter;

[0014] S6, establish mismatch model in LOD effect;

[0015]

[0016] γ1, γ2, A1, A2, B1, B2, C1, C2, D1, D2, α1, α2, c1, c2, d1 and d2 are specified coefficients, SA, SB are the distances from the edges of the gate to the trench, pwr(a, b) is a function that calculates a to the power of b, W is the active area width, L is the active area length, WL;

[0017] S7, adjusting parameters of the mismatch model to obtain a mismatch model related to the active region length.

[0018] Preferably, the LOD effect mismatch model extraction method is further improved, and the implementation step S7 includes:

[0019] Fixed size active area W and L, adjust SA, SB;

[0020] γ1 and γ2 are set to non-zero values, and the mismatch data values ​​of vtlin, vtsat, idlin, and idsat under different SA and SB are obtained;

[0021] Specify initial values ​​of γ1, γ2, A1, A2, B1, B2, C1, C2, D1, D2, α1, α2, c1, c2, d1, and d2;

[0022] According to the mismatch model, the model values ​​of the calculated standard deviation Sigma of vtlin, vtsat, idlin, and idsat under different SA and SB are obtained;

[0023] If the difference between the model value and the mismatch value of vtlin, vtsat, idlin, idsat is less than the specified threshold, the current specified parameter value is determined to be the mismatch model parameter of the active area environment, otherwise the above specified parameters are modified and the solution is re-solved.

[0024] Preferably, the LOD effect mismatch model extraction method is further improved, and the implementation step S7 further includes:

[0025] Add the absolute values ​​of the differences between the model values ​​and the mismatch values ​​under all different SAs to obtain the total difference between the model values ​​and the mismatch values ​​under different source area length SAs. Monitor the changes in the total difference when adjusting the parameters to ensure that the total difference is minimized.

[0026] Preferably, the LOD effect mismatch model extraction method is further improved, further comprising:

[0027] S8, curve fitting of the mismatch model related to the active region length

[0028] The model value and the mismatch value are plotted with SA as the horizontal axis to represent the trend. If the model value and the mismatch value in the graph are consistent, there is no trend mutation, and the model value and the mismatch value under different SA conditions coincide, then it is judged that the mismatch model curve is fitted successfully, otherwise it is refitted.

[0029] Preferably, the LOD effect mismatch model extraction method is further improved, further comprising:

[0030] S9, specify the device that does not participate in the SA change modeling as the test key for verification;

[0031] S10, execute steps S1 to S5 on Testkey, and substitute Testkey into the mismatch model obtained in step S7;

[0032] If the difference between the obtained vtlin, vtsat, idlin, idsat model values ​​and the full map test value is less than the specified threshold, it is determined that the mismatch model obtained in step S7 passes the verification.

[0033] Preferably, the LOD effect mismatch model extraction method is further improved, further comprising:

[0034] S11, use simulation software to substitute multiple groups of SA and SB values ​​to simulate the mismatch values ​​of vtlin, vtsat, idlin, and idsat. If the calculated model values ​​are all on the trend line derived from the mismatch values, it is considered that the mismatch model obtained in S7 has passed the verification.

[0035] Preferably, the LOD effect mismatch model extraction method is further improved, and the threshold is specified as:

[0036] The difference between the model value and the mismatch value of vtlin and vtsat is less than 3mV;

[0037] The percentage differences between the model values ​​and the mismatch values ​​of idlin and idsat are less than 0.1%.

[0038] The present invention also provides a computer-readable storage medium, characterized in that: a computer program is stored therein, and when the computer program is executed, it is used to implement the steps in any one of the above-mentioned LOD effect mismatch model extraction methods.

[0039] This invention takes into account the impact of changes in the active region length on the device LOD effect mismatch model, introduces a function related to the active length change, and can construct a more accurate LOD effect mismatch model to better reflect the actual circuit characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings of the present invention are intended to illustrate the general characteristics of the methods, structures and / or materials used in specific exemplary embodiments of the present invention, and to supplement the description in the specification. However, the drawings of the present invention are schematic diagrams not drawn to scale, and thus may not accurately reflect the precise structure or performance characteristics of any given embodiment, and the drawings of the present invention should not be interpreted as limiting or restricting the range of values ​​or properties covered by the exemplary embodiments of the present invention. The present invention is further described in detail below in conjunction with the drawings and specific embodiments:

[0041] Figure 1 This is a schematic diagram of the active area length.

[0042] Figure 2 It is a schematic diagram of LOD local mismatch model fitting of the present invention.

[0043] Figure 3It is a schematic diagram of the process flow of the fourth embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following is an explanation of the embodiments of the present invention by specific specific embodiments, and those skilled in the art can fully understand other advantages and technical effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and the details in this specification can also be applied based on different viewpoints, and various modifications or changes can be made without deviating from the general design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in a variety of different forms and should not be interpreted as being limited to the specific embodiments described here. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary specific embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "coupled" to another element, the element can be directly connected or coupled to another element, or there can be an intermediate element. The difference is that when an element is referred to as "directly connected" or "directly coupled" to another element, there is no intermediate element. In all the drawings, the same reference numerals always represent the same elements.

[0045] First embodiment;

[0046] The present invention provides a method for extracting a LOD effect mismatch model, comprising:

[0047] In order to characterize the impact of different active area lengths on the mismatch performance of its device, we will first increase the design layout related to it. In the added design layout, we should pay attention to the following points: draw active area lengths different from the device body structure, and then measure the wafer run out of the design layout, analyze, screen and calculate the measured data, and then calculate the mismatch rate of each parameter, and start to adjust the function coefficients related to different active area lengths. From the figure below, we can find that the mismatch model and the mismatch rate calculated by the wat data fit better. In this way, we can get a mismatch model with different active area lengths. Designers can understand the characteristics of the device under different active area lengths by simulating the model, and can take this factor into consideration when starting the design, so that the new model can better reflect the actual device characteristics.

[0048] S1, design devices with different active area length dimensions;

[0049] S2, perform full map test of wafer for vtlin, vtsat, idlin, idsat under two device structures with the same source region length size, for example, 66 dies;

[0050] Vtlin is the threshold voltage in the linear region, Vtsat is the threshold voltage in the saturation region, Idlins is the linear current, and Idsats is the saturation current;

[0051] S3, calculating the difference in threshold voltage and saturation current between two devices under the same Die;

[0052] Delta Vtlin =Vtlin1-Vtlin2

[0053] Delta Vtsat =Vtsat1-Vtsat2

[0054]

[0055] S4, calculate the Median value and the standard deviation Sigma of the vtlin, vtsat, idlin, and idsat of the two devices under all dies, determine whether the data of each die is reasonable, remove the unreasonable die data, and retain the reasonable die data;

[0056] For the Full Map (66 Dies), take the Median value and calculate the standard deviation Sigma for Vtlin1, Vtsat1, Idlin1, Idsat1 and Vtlin2, Vtsat2, Idlin2, Idsat2 respectively, and then calculate the difference between the value of each die and the median value. If the difference is greater than 3 times sigma, the die data is considered unreasonable and the test data of the die is removed.

[0057] Taking vtlin1 as an example, medianvtlin1=Median(vtlin1,vtlin2…vtlin66), sigmavtlin1=stdev(vtlin1,vt lin2…vtlin66), the screening condition is that if Die1vtlin1-medianvtlin1>3sigmavtlin1, the vtlin1 of the Die is considered unreasonable, and the difference value of the vtlin of the Die is no longer calculated; on the contrary, if both vtlin1 and vtlin2 meet the condition Die1vtlin1-medianvtlin1≤3sigmavtlin1, the Die data is retained and Delta is calculated.

[0058] S5, calculating the standard deviation of the threshold voltage difference value and the saturation current difference value of the reasonable die, namely Stdev (Delta1, Delta2...Delta66), obtaining the mismatch data value of the threshold voltage and the saturation current, and performing fitting simulation on the mismatch data value to obtain the simulation curve of the mismatch rate of each parameter;

[0059] S6, establish mismatch model in LOD effect;

[0060]

[0061] γ1, γ2, A1, A2, B1, B2, C1, C2, D1, D2, α1, α2, c1, c2, d1 and d2 are specified coefficients, SA, SB are the distances from the edges of the gate to the trench, pwr(a, b) is a function that calculates a to the power of b, W is the active area width, L is the active area length, WL;

[0062] S7, adjusting parameters of the mismatch model to obtain a mismatch model related to the active region length.

[0063] Exemplarily, the implementation step S7 includes:

[0064] In the mismatch model of the above LOD effect, the first is the fixed size W, L, such as W / L = 0.1 / 0.03, only SA, SB (the distance from the gate edge to the trench) are changed. γ can be understood as a mismatch switch. If γ1 and γ2 are both 0, then the mismatch value is 0, and the mismatch model in the LOD effect is not considered. If the initial value of γ is set to a non-zero value, the mismatch model is considered. The following Table 1 shows the mismatch values ​​of VT and ID under different SA and SB. Taking vtlin as an example, first set the coefficients of γ1, γ2, A1, A2, B1, B2, C1, C2, D1, D2, α1, α2, c1, c2, d1 and d2 to 0.1 according to empirical values, and then substitute them into the formula to obtain the model value of vtlin_sigma under each SA and SB, and then use the model value to subtract the mismatch value to obtain the error between the model value and the mismatch value, and adjust the values ​​of γ1, γ2, A1, A2, B1, B2, C1, C2, D1, D2, α1, α2, c1, c2, d1 and d2 (adjusting the parameters means modifying the local mismatch model related to different active area environments, and "related to different active area environments" refers to different source area lengths SA). The error of vtlin and vtsat does not exceed 3mV, and the error of idlin and idsat does not exceed 0.1%. Otherwise, modify the parameters and perform planning and solving again. Finally, the "active area length-dependent model" is obtained, that is, the "local mismatch model" whose coefficients are determined to meet the requirements of vt and id error accuracy.

[0065] Table 1, Silicon mismatch_Sigma of devices with different SA sizes with W=0.1 / L=0.03;

[0066]

[0067] Second embodiment

[0068] The second implementation of the present invention is a further improvement on the above first implementation, and the same parts are not repeated here. The implementation step S7 further includes:

[0069] Add the absolute values ​​of the differences between the model values ​​and the mismatch values ​​under all different SAs to obtain the total difference between the model values ​​and the mismatch values ​​under different source area length SAs. Monitor the changes in the total difference when adjusting the parameters to ensure that the total difference is minimized.

[0070] Third embodiment

[0071] The second embodiment of the present invention is a further improvement on the above first embodiment or second embodiment, and the same parts are not repeated here, and further includes:

[0072] S8, curve fitting of the mismatch model related to the active region length

[0073] The model value and mismatch value are plotted with SA as the horizontal axis to represent the trend. If the model value and mismatch value trends in the figure are consistent, there is no trend mutation, and the model value and mismatch value under different SA conditions coincide, then it is judged that the mismatch model curve is fitted successfully. Otherwise, refit, refer to Figure 2 shown.

[0074] Table 2, comparison of mismatch values ​​between Silicon and Model for various SA size devices;

[0075]

[0076] Third embodiment

[0077] refer to Figure 3 As shown, the second embodiment of the present invention is a further improvement based on the first embodiment, the second embodiment or the third embodiment, and the same parts are not repeated here, and further include:

[0078] S9, designate the device that does not participate in the SA change of the model as the test key for verification; Testkey refers to the specific input or condition used to test the function or performance of the product;

[0079] S10, execute steps S1 to S5 on Testkey, and substitute Testkey into the mismatch model obtained in step S7;

[0080] If the difference between the obtained vtlin, vtsat, idlin, idsat model values ​​and the full map test value is less than the specified threshold, it is determined that the mismatch model obtained in step S7 passes the verification.

[0081] Further improving the fourth embodiment, further comprising:

[0082] S11, use simulation software to substitute multiple groups of SA and SB values ​​to simulate the mismatch values ​​of vtlin, vtsat, idlin, and idsat. If the calculated model values ​​are all on the trend line derived from the mismatch values, it is considered that the mismatch model obtained in S7 has passed the verification.

[0083] The specified thresholds in the first to fourth embodiments are:

[0084] The difference between the model value and the mismatch value of vtlin and vtsat is less than 3mV;

[0085] The percentage differences between the model values ​​and the mismatch values ​​of idlin and idsat are less than 0.1%.

[0086] Fifth embodiment

[0087] The present invention provides a computer-readable storage medium, which stores a computer program therein. When the computer program is executed, it is used to implement the steps in the LOD effect mismatch model extraction method described in any one of the first embodiment to the fourth embodiment.

[0088] The computer-readable medium includes permanent and non-permanent, removable and non-removable media and can be implemented by any method or technology to store information. Information can be computer-readable instructions, data structures, modules of programs or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include non-transitory media such as modulated data signals and carrier waves.

[0089] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will also be understood that, unless expressly defined herein, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not interpreted in an ideal or overly formal sense.

[0090] The present invention has been described in detail above through specific implementation modes and embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may also make many variations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A LOD effect mismatch model extraction method, characterized in that: include: S1, design devices with different active area lengths; S2, perform full map test of wafer for vtlin, vtsat, idlin, idsat under multiple groups of device structures with the same source region length size; Vtlin is the threshold voltage in the linear region, Vtsat is the threshold voltage in the saturation region, Idlins is the linear current, and Idsats is the saturation current S3, calculating the difference in threshold voltage and saturation current of two devices with the same source region length under the same die; S4, calculate the Median value and the standard deviation Sigma of the vtlin, vtsat, idlin, and idsat of the two devices under all dies, determine whether the data of each die is reasonable, remove the unreasonable die data, and retain the reasonable die data; S5, calculating the standard deviation of the threshold voltage difference value and the saturation current difference value of the reasonable die, obtaining the mismatch data value of the threshold voltage and the saturation current, and performing fitting simulation on the mismatch data value to obtain the mismatch rate simulation curve of each parameter; S6, establish mismatch model in LOD effect; γ1, γ2, A1, A2, B1, B2, C1, C2, D1, D2, α1, α2, c1, c2, d1 and d2 are specified coefficients, SA, SB are the distances from the edges of the gate to the trench, pwr(a, b) is a function that calculates a to the power of b, W is the width of the active area, and L is the length of the active area; S7, adjusting parameters of the mismatch model to obtain a mismatch model related to the active region length.

2. The LOD effect mismatch model extraction method according to claim 1, characterized in that: The implementation step S7 includes: Fixed size active area W and L, adjust SA, SB; γ1 and γ2 are set to non-zero values, and the mismatch data values ​​of vtlin, vtsat, idlin, and idsat under different SA and SB are obtained; Specify initial values ​​of γ1γ2, A1, A2, B1, B2, C1, C2, D1, D2, α1, α2, c1, c2, d1, and d2; According to the mismatch model, the model values ​​of the calculated standard deviation Sigma of vtlin, vtsat, idlin, and idsat under different SA and SB are obtained; If the difference between the model value and the mismatch value of vtlin, vtsat, idlin, idsat is less than the specified threshold, the current specified parameter value is determined to be the mismatch model parameter of the active area environment, otherwise the above specified parameters are modified and the solution is re-solved.

3. The LOD effect mismatch model extraction method according to claim 2, characterized in that: The implementation step S7 also includes: Add the absolute values ​​of the differences between the model values ​​and the mismatch values ​​under all different SAs to obtain the total difference between the model values ​​and the mismatch values ​​under different source area length SAs. Monitor the changes in the total difference when adjusting the parameters to ensure that the total difference is minimized.

4. The LOD effect mismatch model extraction method according to claim 1, characterized in that: Also includes: S8, curve fitting of the mismatch model related to the active region length The model value and the mismatch value are plotted with SA as the horizontal axis to represent the trend. If the model value and the mismatch value in the graph are consistent, there is no trend mutation, and the model value and the mismatch value under different SA conditions coincide, then it is judged that the mismatch model curve is fitted successfully, otherwise it is refitted.

5. The LOD effect mismatch model extraction method according to claim 4, characterized in that: Also includes: S9, specify the device that does not participate in the SA change of the modeling as the test key for verification; S10, executing steps S1 to S5 on Testkey, and substituting Testkey into the mismatch model obtained in step S7; If the difference between the obtained vtlin, vtsat, idlin, idsat model values ​​and the fullmap test value is less than the specified threshold, it is determined that the mismatch model obtained in step S7 passes the verification.

6. The LOD effect mismatch model extraction method according to claim 5, characterized in that: Also includes: S11, use simulation software to substitute multiple groups of SA and SB values ​​to simulate the mismatch values ​​of vtlin, vtsat, idlin, and idsat. If the calculated model values ​​are all on the trend line derived from the mismatch values, it is considered that the mismatch model obtained in S7 has passed the verification.

7. The LOD effect mismatch model extraction method according to claim 2, characterized in that: Specify the threshold as: The difference between the model value and the mismatch value of vtlin and vtsat is less than 3mV; The percentage differences between the model values ​​and the mismatch values ​​of idlin and idsat are less than 0.1%.

8. A computer-readable storage medium, characterized in that: A computer program is stored therein, and when the computer program is executed, it is used to implement the steps in the LOD effect mismatch model extraction method according to any one of claims 1 to 7.

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