Display driving chip, display driving method, display device and electronic equipment

Abstract

The embodiment of the invention relates to a display driving chip, a display driving method, a display device and electronic equipment, and relates to the technical field of image processing. The chip comprises a power supply end and a plurality of output ends, the power end is used for receiving power voltage; the plurality of output ends comprise a first output end and a second output end; the first output end is used for outputting a first display driving voltage in a first time period and outputting a second display driving voltage in a second time period, and the first display driving voltage is equal to the power supply voltage; the second output end is used for keeping outputting the third display driving voltage in the first time period, the first switching time period and the second time period, and the first switching time period is located between the first time period and the second time period; wherein the second display driving voltage is located in a preset voltage interval, and the maximum value of the preset voltage interval is smaller than the third display driving voltage. Therefore, the power consumption of the display driving chip can be reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of image processing technology, and in particular to a display driver chip, a display driver method, a display device, and an electronic device. Background Art

[0002] The display screen includes a pixel circuit, which is usually driven by a display driver IC (DDIC). About a quarter of the power consumption of the whole machine is on the display driver chip side. As the time users use the whole machine gradually increases, it is increasingly important to reduce the power consumption of the display driver chip. In the organic light-emitting diode (OLED) display screen, there is a red-green-blue-green (RGBG) pixel circuit. When the display driver chip drives the RGBG pixel circuit to display, the power consumption of the display driver chip is relatively large. Summary of the invention

[0003] The embodiments of the present application provide a display driver chip, a display driver method, a display device and an electronic device, which solve the problem in the prior art that the display driver chip has high power consumption when the display driver chip drives the RGBG pixel circuit to display.

[0004] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0005] In a first aspect, a display driver chip is provided, the display driver chip comprising a power supply terminal and a plurality of output terminals. The power supply terminal is used to receive a power supply voltage. The plurality of output terminals include a first output terminal and a second output terminal. The first output terminal is used to output a first display driver voltage in a first time period and a second display driver voltage in a second time period, wherein the first display driver voltage is equal to the power supply voltage. The second output terminal is used to maintain output of a third display driver voltage in a first time period, a first switching time period, and a second time period, wherein the first switching time period is between the first time period and the second time period. The second display driver voltage is within a preset voltage interval, and the maximum value of the preset voltage interval is less than the third display driver voltage.

[0006] In the above technical solution, the display driver chip can obtain multiple voltages according to the power supply voltage of the power supply terminal. The multiple voltages include voltages in a preset voltage interval. The second display drive voltage is usually one of the multiple voltages in the preset voltage interval. If the first display drive voltage and the second display drive voltage are both voltages obtained according to the power supply voltage, in the process of switching from the first display drive voltage to the second display drive voltage, the values ​​of the multiple voltages obtained according to the power supply voltage will cause interference. The technical solution uses a voltage equal to the power supply voltage as the first display drive voltage. That is, the first display drive voltage may not be a voltage obtained according to the power supply voltage, but may be the power supply voltage itself. When the first output terminal outputs a dynamic voltage, the interference to the values ​​of the multiple voltages obtained according to the power supply voltage is alleviated. The third display drive voltage output by the second output terminal may be a voltage obtained according to the power supply voltage, or may be a power supply voltage, and the third display drive voltage output by the second output terminal will not be interfered with. Compared with the situation where an additional current is required to stabilize the voltage of the second output terminal due to interference, the technical solution does not require additional stabilization of the second output terminal voltage, which can reduce power consumption. Moreover, compared with the situation where it is necessary to wait for the voltage of the second output terminal to recover (re-establish) due to interference, the technical solution does not need to wait for the voltage of the second output terminal to recover, which can improve the driving capability of the display driver chip and speed up the voltage output process. In addition, the technical solution does not need to reduce power consumption through additional power consumption or circuit area, but reduces power consumption by outputting the power supply voltage, which can save circuit area and minimize power consumption.

[0007] In a possible implementation of the first aspect, the plurality of output terminals further include a third output terminal, the third output terminal being used to output a fourth display driving voltage in a first time period, and output a first display driving voltage in a second time period, and the fourth display driving voltage is within a preset voltage interval. The fourth display driving voltage output by the third output terminal in the first time period is different in magnitude from the second display driving voltage output by the first output terminal in the second time period. In the above possible implementation, if the first display driving voltage and the fourth display driving voltage are both voltages obtained according to the power supply voltage, in the process of switching from the first display driving voltage to the fourth display driving voltage, the values ​​of the plurality of voltages obtained according to the power supply voltage will generate interference. The first display driving voltage of the technical solution may not be a voltage obtained according to the power supply voltage, but may be the power supply voltage itself. When the first output terminal outputs a dynamic voltage, the interference to the values ​​of the plurality of voltages obtained according to the power supply voltage is alleviated. The third display driving voltage output by the second output terminal will not be interfered with. For the plurality of output terminals, power consumption can be reduced and the voltage output process can be accelerated.

[0008] In a possible implementation of the first aspect, the first output terminal is specifically used to output the first display driving voltage in the first time period, the second display driving voltage in the second time period, the first display driving voltage in the third time period, and the second display driving voltage in the fourth time period. The second output terminal is specifically used to keep outputting the third display driving voltage in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period and the fourth time period, the second switching time period is between the second time period and the third time period, and the third switching time period is between the third time period and the fourth time period. In the above possible implementation, when driving the color display of multiple sub-pixels in the third time period and the fourth time period, the first display driving voltage may not be a voltage obtained according to the power supply voltage, but may be the power supply voltage itself. When the first output terminal outputs a dynamic voltage, the interference of the values ​​of the multiple voltages obtained according to the power supply voltage is alleviated. For the case of driving multiple sub-pixels, power consumption can be reduced and the voltage output process can be accelerated.

[0009] In a possible implementation of the first aspect, the first output terminal is specifically used to output the first display driving voltage in the first time period, the second display driving voltage in the second time period, the first display driving voltage in the third time period, the second display driving voltage in the fourth time period, the first display driving voltage in the nth time period, and the second display driving voltage in the n+1th time period, where n is an odd number greater than or equal to 5. The second output terminal is specifically used to keep outputting the third display driving voltage in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, the fourth time period, the fourth switching time period, the nth time period, the nth switching time period, and the n+1th time period, the fourth switching time period is between the fourth time period and the nth time period, and the nth switching time period is between the nth time period and the n+1th time period. In the above possible implementation, when driving the color display of multiple sub-pixels in multiple time periods, the first display driving voltage may not be a voltage obtained according to the power supply voltage, but may be the power supply voltage itself. When the first output terminal outputs a dynamic voltage, the interference of the values ​​of the multiple voltages obtained according to the power supply voltage is alleviated. For the case of driving multiple sub-pixels, power consumption can be reduced and the voltage output process can be accelerated.

[0010] In a possible implementation of the first aspect, the chip further includes a first display channel circuit, a first display switch, and a first power switch. The output end of the first display channel circuit is coupled to the first end of the first display switch, and the second end of the first display switch is coupled to the first output end. The power supply end is coupled to the first end of the first power switch, and the second end of the first power switch is coupled to the first output end. In the above possible implementation, the first display channel circuit is coupled to the first output end through the first display switch, and the power supply end is coupled to the first output end through the first power switch. The first output end can output a voltage provided by the first display channel circuit, or can output a power supply voltage received by the power supply end. When the first output end needs to output a voltage for driving a sub-pixel to emit light, the first display switch can be turned on and the first power switch can be turned off, so that the first display channel circuit outputs a voltage to the first output end. When the first output end needs to output a voltage for driving a sub-pixel not to emit light, the first display switch can be turned off and the first power switch can be turned on, so that the power supply end outputs a power supply voltage to the first output end. It can be seen that when the first output end outputs a dynamic voltage, the voltage is switched by turning on and off the first display switch and the first power switch, rather than switching the voltage inside the first display channel circuit. In this way, the interference to the voltage output by the display channel circuit adjacent to the first display channel circuit is alleviated.

[0011] In a possible implementation of the first aspect, the chip further includes a plurality of display channel circuits, a plurality of display switches, and a plurality of power switches. The output end of the mth display channel circuit is coupled to the first end of the mth display switch, and the second end of the mth display switch is coupled to the mth output end. The power end is coupled to the first end of the mth power switch, and the second end of the mth power switch is coupled to the mth output end. The mth display channel circuit is any one of the multiple display channel circuits, the mth display switch is any one of the multiple display switches, the mth power switch is any one of the multiple power switches, and the mth output end is any one of the multiple output ends. In the above possible implementation, the mth display channel circuit is coupled to the mth output end through the mth display switch, and the power end is coupled to the mth output end through the mth power switch. The mth output end can output a voltage provided by the mth display channel circuit, or output a power supply voltage received by the power end. When the mth output end needs to output a voltage for driving a sub-pixel to emit light, the mth display switch can be turned on and the mth power switch can be turned off, so that the mth display channel circuit outputs a voltage to the mth output end. When the mth output terminal needs to output a voltage for driving the sub-pixel not to emit light, the mth display switch can be turned off and the mth power switch can be turned on, so that the power supply terminal outputs the power supply voltage to the output terminal. It can be seen that when the mth output terminal outputs a dynamic voltage, the voltage is switched by turning on and off the mth display switch and the mth power switch, rather than by switching the voltage inside the mth display channel circuit. In this way, the interference to the voltage output by the display channel circuit adjacent to the mth display channel circuit is alleviated.

[0012] In a possible implementation of the first aspect, the chip further includes a plurality of drive enhancement circuits, and the kth drive enhancement circuit is coupled to the control end of the kth display switch. The kth drive enhancement circuit is any one of the plurality of drive enhancement circuits, and the kth display switch is any one of the plurality of display switches. In the above possible implementations, the ideal waveform of the control waveform for controlling the display switch to be turned on or off is a square wave, but in practice the control waveform may be unstable. The drive enhancement circuit can stabilize the control waveform of the display switch to which it is coupled. Providing a drive enhancement circuit for each display switch can achieve high-speed on and off of multiple display switches.

[0013] In a possible implementation of the first aspect, the third display driving voltage is equal to the power supply voltage. In the above possible implementation, the third display driving voltage can be provided by the power supply terminal, which can further reduce the power consumption of the display channel circuit.

[0014] In a possible implementation of the first aspect, the power supply terminal is used to connect to a power supply. In the above possible implementation, the power supply terminal is connected to a power supply, and a power supply voltage can be used as a voltage to drive the sub-pixel not to emit light through the power supply terminal. The power supply voltage has a strong power supply network and a small path impedance, which can reduce the additional power consumption caused by the dynamic voltage output by the display channel circuit.

[0015] In a second aspect, a display driver chip is provided, the display driver chip comprising a power supply terminal, a first output terminal, a first display channel circuit, a first display switch and a first power switch. The power supply terminal is used to receive a power supply voltage. The output terminal of the first display channel circuit is coupled to the first terminal of the first display switch, and the second terminal of the first display switch is coupled to the first output terminal. The power supply terminal is coupled to the first terminal of the first power switch, and the second terminal of the first power switch is coupled to the first output terminal. In the above possible implementation, the first display channel circuit is coupled to the first output terminal through the first display switch, and the power supply terminal is coupled to the first output terminal through the first power switch. The first output terminal can output the voltage provided by the first display channel circuit, or can output the power supply voltage received by the power supply terminal. When the first output terminal needs to output a voltage for driving a sub-pixel to emit light, the first display switch can be turned on and the first power switch can be turned off, so that the first display channel circuit outputs a voltage to the first output terminal. When the first output terminal needs to output a voltage for driving a sub-pixel not to emit light, the first display switch can be turned off and the first power switch can be turned on, so that the power supply terminal outputs a power supply voltage to the first output terminal. It can be seen that when the first output terminal outputs a dynamic voltage, the voltage is switched by turning on and off the first display switch and the first power switch, rather than by switching the voltage inside the first display channel circuit. Compared with the situation where additional current is required to stabilize the voltage due to interference, this technical solution does not require additional stable voltage and can reduce power consumption. Moreover, compared with the situation where it is necessary to wait for voltage recovery (re-establishment) due to interference, this technical solution does not need to wait for voltage recovery, which can enhance the driving capability of the display driver chip and speed up the voltage output process. In addition, this technical solution does not need to reduce power consumption through additional power consumption or circuit area, but can reduce power consumption by outputting power supply voltage, which can save circuit area and minimize power consumption.

[0016] In a possible implementation of the second aspect, the chip further includes multiple output terminals, multiple display channel circuits, multiple display switches, and multiple power switches. The output terminal of the mth display channel circuit is coupled to the first terminal of the mth display switch, and the second terminal of the mth display switch is coupled to the mth output terminal. The power terminal is coupled to the first terminal of the mth power switch, and the second terminal of the mth power switch is coupled to the mth output terminal. The mth display channel circuit is any one of the multiple display channel circuits, the mth display switch is any one of the multiple display switches, the mth power switch is any one of the multiple power switches, and the mth output terminal is any one of the multiple output terminals. In the above possible implementation, the mth display channel circuit is coupled to the mth output terminal through the mth display switch, and the power terminal is coupled to the output terminal through the mth power switch. The mth output terminal can output the voltage provided by the mth display channel circuit, or output the power voltage received by the power terminal. When the mth output terminal needs to output a voltage for driving a sub-pixel to emit light, the mth display switch can be turned on and the mth power switch can be turned off, so that the mth display channel circuit outputs a voltage to the mth output terminal. When the mth output terminal needs to output a voltage for driving a sub-pixel not to emit light, the mth display switch can be turned off and the mth power switch can be turned on, so that the power supply terminal outputs a power supply voltage to the first output terminal. The power supply voltage of the power supply terminal can replace the voltage provided by the mth display channel circuit. It can be seen that when the mth output terminal outputs a dynamic voltage, the voltage is switched by turning on and off the mth display switch and the mth power switch, rather than by switching the voltage inside the mth display channel circuit. In this way, the interference to the voltage output by the display channel circuit adjacent to the mth display channel circuit is alleviated.

[0017] In a possible implementation of the second aspect, the chip further includes a plurality of drive enhancement circuits, the kth drive enhancement circuit is coupled to the control end of the kth display switch, the kth drive enhancement circuit is any one of the plurality of drive enhancement circuits, and the kth display switch is any one of the plurality of display switches. In the above possible implementation, the ideal waveform of the control waveform for controlling the on or off of the display switch is a square wave, but in practice the control waveform may be unstable. The drive enhancement circuit can stabilize the control waveform of the display switch to which it is coupled. Providing a drive enhancement circuit for each display switch can realize high-speed on and off of multiple display switches.

[0018] In a possible implementation of the second aspect, the power supply terminal is used to connect to a power supply. In the above possible implementation, the power supply terminal is connected to a power supply, and a power supply voltage can be used as a voltage to drive the sub-pixel not to emit light through the power supply terminal. The power supply voltage has a strong power supply network and a small path impedance, which can reduce the additional power consumption caused by the dynamic voltage output by the display channel circuit.

[0019] In a third aspect, a display driving method is provided, and the display driving method is applied to a display driving chip, and the display driving chip includes a power supply terminal and a plurality of output terminals. The power supply terminal is used to receive a power supply voltage. The plurality of output terminals include a first output terminal and a second output terminal. The method includes: outputting a first display driving voltage in a first time period through the first output terminal, and outputting a second display driving voltage in a second time period, wherein the first display driving voltage is equal to the power supply voltage. Outputting a third display driving voltage in a first time period, a first switching time period, and a second time period through the second output terminal, wherein the first switching time period is between the first time period and the second time period. Wherein, the second display driving voltage is within a preset voltage interval, and the maximum value of the preset voltage interval is less than the third display driving voltage.

[0020] In a possible implementation of the third aspect, the method further includes: outputting a fourth display driving voltage in a first time period through a third output terminal, outputting the first display driving voltage in a second time period, and the fourth display driving voltage is within a preset voltage range. The fourth display driving voltage output by the third output terminal in the first time period is different in magnitude from the second display driving voltage output by the first output terminal in the second time period.

[0021] In a possible implementation of the third aspect, outputting a first display driving voltage in a first time period and outputting a second display driving voltage in a second time period through a first output terminal includes: outputting the first display driving voltage in a first time period, outputting the second display driving voltage in a second time period, outputting the first display driving voltage in a third time period, and outputting the second display driving voltage in a fourth time period through the first output terminal. Maintaining outputting a third display driving voltage in a first time period, a first switching period, and a second time period through a second output terminal includes: maintaining outputting a third display driving voltage in a first time period, a first switching period, a second time period, a second switching period, a third time period, a third switching period, and a fourth time period through a second output terminal, the second switching period being between the second time period and the third time period, and the third switching period being between the third time period and the fourth time period.

[0022] In a possible implementation of the third aspect, outputting a first display driving voltage in a first time period and outputting a second display driving voltage in a second time period through a first output terminal includes: outputting the first display driving voltage in a first time period, outputting the second display driving voltage in a second time period, outputting the first display driving voltage in a third time period, outputting the second display driving voltage in a fourth time period, outputting the first display driving voltage in an nth time period, and outputting the second display driving voltage in an n+1th time period, where n is an odd number greater than or equal to 5. Outputting a third display driving voltage in a first time period, a first switching time period, and a second time period through a second output terminal includes: outputting a third display driving voltage in a first time period, a first switching time period, a second time period, a second switching time period, a third time period, a third switching time period, a fourth time period, a fourth switching time period, an nth time period, an nth switching time period, and an n+1th time period through a second output terminal, wherein the fourth switching time period is between the fourth time period and the nth time period, and the nth switching time period is between the nth time period and the n+1th time period.

[0023] In a possible implementation manner of the third aspect, the third display driving voltage is equal to the power supply voltage.

[0024] In a fourth aspect, a display device is provided, comprising a display screen and a display driver chip provided by the first aspect, or any possible implementation of the first aspect, or the second aspect, or any possible implementation of the second aspect. The display screen comprises a plurality of pixel channels. The jth pixel channel is coupled to the jth output terminal, the jth pixel channel is any one of the plurality of pixel channels, and the jth output terminal is any one of the plurality of output terminals of the display driver chip.

[0025] In a fifth aspect, an electronic device is provided. The electronic device includes a circuit board and the display device provided in the fourth aspect, wherein a display driver chip in the display device is arranged on the circuit board.

[0026] In another aspect of the present application, a computer-readable storage medium is provided, in which a program code is stored. The program code can be called by a processor to execute the method provided by the third aspect or any possible implementation of the third aspect.

[0027] According to another aspect of the present application, a computer program product is provided. When the computer program product is run on a computer, the computer is enabled to execute the method provided by the third aspect or any possible implementation manner of the third aspect.

[0028] It can be understood that any of the display driving methods, devices, equipment, computer storage media or computer program products provided above all apply the corresponding display driving chip provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding chip provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a first display device provided in an embodiment of the present application;

[0030] Figure 2 A schematic diagram of the principle of driving a sub-pixel to emit light provided in an embodiment of the present application;

[0031] Figure 3 A voltage waveform for driving a sub-pixel to emit light provided in an embodiment of the present application Figure 1 ;

[0032] Figure 4 A voltage waveform for driving a sub-pixel to emit light provided in an embodiment of the present application Figure 2 ;

[0033] Figure 5 A voltage waveform for driving a sub-pixel to emit light provided in an embodiment of the present application Figure 3 ;

[0034] Figure 6 A schematic diagram of an electronic device provided in an embodiment of the present application;

[0035] Figure 7 A schematic diagram of a second display device provided in an embodiment of the present application;

[0036] Figure 8 A schematic diagram of a second display driver chip provided in an embodiment of the present application Figure 1 ;

[0037] Fig. 9 A schematic diagram of a second display driver chip provided in an embodiment of the present application Figure 2 ;

[0038] Fig.10 A voltage waveform for driving a sub-pixel to emit light provided in an embodiment of the present application Figure 4 ;

[0039] Fig.11 A voltage waveform for driving a sub-pixel to emit light provided in an embodiment of the present application Figure 5 ;

[0040] Fig.12 A voltage waveform for driving a sub-pixel to emit light provided in an embodiment of the present application Figure 6 ;

[0041] Fig.13 A schematic diagram of a display driving method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0043] The terms "exemplary" or "for example" and the like in the embodiments of the present application are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the related concepts in a specific way.

[0044] The terms "coupling" and "connection" involved in the embodiments of the present application should be understood in a broad sense. For example, they may refer to a direct physical connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0045] First, some basic concepts involved in the embodiments of the present application are explained:

[0046] The organic light-emitting diode (OLED) display is a display technology that uses organic light-emitting materials as pixel light sources. Each pixel of the OLED display includes three sub-pixels: red (red, R), green (green, G) and blue (blue, B). Each sub-pixel includes an OLED element. When current passes through, the OLED element emits light of the corresponding color. The brightness and color of each OLED element can be controlled individually. Each sub-pixel can also include a capacitor-resistor (RC) load. There is a certain delay in the OLED element's response to voltage changes. The RC load can slow down the rise and fall rates of the signal, making the voltage change curve of the OLED element more ideal. The RC load can also control the current of the OLED element to maintain the brightness and color consistency of the OLED element. Therefore, the RC load can improve the stability of the display.

[0047] The red-green-blue-green (RGBG) pixel circuit is a pixel circuit that uses the RGBG pixel arrangement. Each pixel includes a red sub-pixel, a blue sub-pixel, and two green sub-pixels. This can provide more color depth and more delicate color transitions. By adjusting the brightness combination of these four colors, countless colors can be generated to form a colorful visual effect.

[0048] Display driver IC (DDIC) is an integrated circuit chip specially used to control and drive display screens. It is mainly used to convert the data to be displayed into electrical signals to ensure that the image indicated by the data to be displayed can be presented clearly and accurately on the display screen.

[0049] In a possible implementation, Figure 1 As shown, the first display device 1100A includes a first display screen 100A and a first display driver IC 200A (display driver IC, DDIC). For example, the first display screen 100A may be an OLED display screen.

[0050] The first display screen 100A may include a first pixel circuit 110A. The first pixel circuit 110A may include a plurality of channels, such as a first channel 11A, a second channel 12A, a third channel 13A, a fourth channel 14A, and more channels not shown. Each of the plurality of channels may include a plurality of sub-pixels. Taking the first pixel circuit 110A as an RGBG pixel circuit as an example, the first channel 11A may include at least four sub-pixels: B, R, B, R, the second channel 12A may include at least four sub-pixels: G, G, G, G, the third channel 13A may include at least four sub-pixels: R, B, R, B, and the fourth channel 14A may include at least four sub-pixels: G, G, G, G. One sub-pixel B, one sub-pixel R, and two sub-pixels G may be used as a pixel. For example, the first row of sub-pixels B in the first channel 11A, the first row of sub-pixels G in the second channel 12A, the first row of sub-pixels R in the third channel 13A, and the first row of sub-pixels G in the fourth channel 14A may be used as a pixel. The first display driver chip 200A may include a first power supply terminal, a plurality of output terminals, a first gamma circuit 210A, and a plurality of drive channel circuits. The plurality of output terminals may include a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, and more output terminals not shown. The plurality of drive channel circuits may include a first drive channel circuit 221A, a second drive channel circuit 222A, a third drive channel circuit 223A, a fourth drive channel circuit 224A, and more drive channel circuits not shown.

[0051] The first power supply terminal and the plurality of driving channel circuits of the first display driver chip 200A are coupled to the first gamma circuit 210A. The plurality of driving channel circuits of the first display driver chip 200A are coupled to the plurality of output terminals in a one-to-one correspondence. For specific corresponding coupling methods, please refer to Figure 1 The multiple sub-pixels in each channel of the first pixel circuit 110A can be coupled to the same output terminal of the first display driver chip 200A, and the multiple channels of the first pixel circuit 110A correspond to the multiple output terminals of the first display driver chip 200A one by one. For specific correspondence, please refer to Figure 1 . For example, the first row of sub-pixels B in the first channel 11A, the second row of sub-pixels R in the first channel 11A, the third row of sub-pixels B in the first channel 11A, and the fourth row of sub-pixels R in the first channel 11A are all coupled to the first output terminal of the first display driver chip 200A. The first row of sub-pixels G in the second channel 12A, the second row of sub-pixels G in the second channel 12A, the third row of sub-pixels G in the second channel 12A, and the fourth row of sub-pixels G in the second channel 12A are all coupled to the second output terminal of the first display driver chip 200A. The sub-pixels in the same row in multiple channels of the first pixel circuit 110A can be coupled to the same clock signal line ( Figure 1 For example, the sub-pixels B of the first row in the first channel 11A, the sub-pixels G of the first row in the second channel 12A, the sub-pixels R of the first row in the third channel 13A, and the sub-pixels G of the first row in the fourth channel 14A may be coupled to the first clock signal line. The sub-pixels R of the second row in the first channel 11A, the sub-pixels G of the second row in the second channel 12A, the sub-pixels B of the second row in the third channel 13A, and the sub-pixels G of the second row in the fourth channel 14A may be coupled to the second clock signal line.

[0052] In one example, the first power supply terminal of the first display driver chip 200A is used to connect the power supply, thereby receiving the power supply voltage from the power supply. The first gamma circuit 210A receives the power supply voltage through the first power supply terminal, and converts the power supply voltage into multiple voltages of different sizes. For example, the multiple voltages can be: Vgmp', Vdata1', Vdata2', ..., Vdataq', Vgsp' from large to small. Among them, the maximum voltage (such as Vgmp') provided by the first gamma circuit 210A is less than the power supply voltage. The first gamma circuit 210A can output multiple voltages to each drive channel circuit. The drive channel circuit is used to input multiple voltages and output a voltage obtained according to the multiple voltages. Each drive channel circuit can provide a voltage of multiple voltages to the corresponding channel of the output terminal through the corresponding output terminal. For example, the first gamma circuit 210A can output Vgmp', Vdata1', Vdata2', ..., Vdataq', Vgsp' to the first drive channel circuit 221A. The first driving channel circuit 221A can obtain Vgmp according to Vgmp', obtain Vdata1 according to Vdata1', obtain Vdata2 according to Vdata2', obtain Vdataq according to Vdataq', and obtain Vgsp according to Vgsp'. The first driving channel circuit 221A can provide one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp to the sub-pixel in the first channel 11A through the first output terminal. The maximum voltage (such as Vgmp) output by the driving channel circuit is less than the power supply voltage. When Vgmp is applied to the sub-pixel, the sub-pixel does not emit light; when Vdata1, Vdata2, ..., Vdataq, and Vgsp are applied to the sub-pixel in sequence, the brightness of the sub-pixel changes from small to large.

[0053] like Figure 2As shown, the first driving channel circuit 221A can output Vgmp in the first driving period, output Vdata in the second driving period, output Vgmp in the third driving period, and output Vdata in the fourth driving period through the first output terminal. Wherein, Vdata is any voltage among Vdata1, Vdata2, ..., Vdataq. The first channel 11A receives Vgmp in the first driving period, and with the cooperation of the clock signal line, the first row of sub-pixels B is applied with Vgmp, and the first row of sub-pixels B does not emit light. The first channel 11A receives Vdata in the second driving period, and with the cooperation of the clock signal line, the second row of sub-pixels R is applied with Vdata, and the second row of sub-pixels R emits light. The first channel 11A receives Vgmp in the third driving period, and with the cooperation of the clock signal line, the third row of sub-pixels B is applied with Vgmp, and the third row of sub-pixels B does not emit light. The first channel 11A receives Vdata in the fourth driving period, and with the cooperation of the clock signal line, the fourth row of sub-pixels R is applied with Vdata, and the fourth row of sub-pixels R emits light.

[0054] like Figure 3 As shown, Figure 2 The same principle is shown, when the voltage waveforms of multiple output terminals are Figure 3 When the voltage waveform in , the second row of sub-pixels R of the first channel 11A emit light, the fourth row of sub-pixels R of the first channel 11A emit light, the first row of sub-pixels R of the third channel 13A emit light, the third row of sub-pixels R of the third channel 13A emit light, and the remaining sub-pixels do not emit light. At this time, the screen of the first display screen 100A is red.

[0055] like Figure 4 As shown, Figure 2 The same principle is shown, when the voltage waveforms of multiple output terminals are Figure 4 When the voltage waveform in , the first row of sub-pixels B of the first channel 11A emit light, the third row of sub-pixels B of the first channel 11A emit light, the second row of sub-pixels B of the third channel 13A emit light, the fourth row of sub-pixels B of the third channel 13A emit light, and the remaining sub-pixels do not emit light. At this time, the screen of the first display screen 100A is blue.

[0056] like Figure 5 As shown, Figure 2 The same principle is shown, when the voltage waveforms of multiple output terminals are Figure 5 When the voltage waveform in , the first row of sub-pixels G of the second channel 12A emit light, the third row of sub-pixels G of the second channel 12A emit light, the first row of sub-pixels G of the fourth channel 14A emit light, the third row of sub-pixels G of the fourth channel 14A emit light, and the remaining sub-pixels do not emit light. At this time, the screen of the first display screen 100A is green.

[0057] from Figure 3 to Figure 5It can be seen that the output terminal can output dynamic voltage. Dynamic voltage refers to voltages of different magnitudes. The output terminal outputs dynamic voltage, which means that the output terminal does not always output the same voltage, but outputs voltages of different magnitudes in different driving periods. The dynamic voltage is a voltage of different magnitudes converted according to the data to be displayed, rather than a voltage of different magnitudes caused by interference. For example, Figure 3 The voltage output by the first output terminal in the circuit is switched from Vgmp to Vdata, or from Vdata to Vgmp. When the output terminal outputs a dynamic voltage, the adjacent output terminals should keep outputting the same voltage, but the voltage of the adjacent output terminals will be disturbed. For example, Figure 3 During the period when the voltage outputted by the first output terminal switches from Vgmp to Vdata, or switches from Vdata to Vgmp, the Vgmp outputted by the adjacent second output terminal will be pulled down. The second output terminal should keep outputting Vgmp, but the actual voltage waveform has a depression.

[0058] The above interference is the gamma disturbance caused by the first gamma circuit 210A. The first gamma circuit 210A outputs multiple voltages to the first drive channel circuit 221A, so that the multiple voltages are used as the input voltages of the first drive channel circuit 221A, and outputs the multiple voltages to the second drive channel circuit 222A, so that the multiple voltages are used as the input voltages of the second drive channel circuit 222A. When the first drive channel circuit 221A outputs a dynamic voltage, it switches the voltage according to the multiple voltages provided by the first gamma circuit 210A, which causes the voltage provided by the first gamma circuit 210A to the first drive channel circuit 221A to be disturbed. When the voltage output by the first gamma circuit 210A is disturbed, the input voltage of the second drive channel circuit 222A is also disturbed, and therefore, the voltage output by the second drive channel circuit 222A is disturbed.

[0059] When the voltage is disturbed, it is necessary to draw a large current through the power supply voltage to stabilize the voltage, which will result in greater power consumption. In addition, the first gamma circuit 210A has many wirings, and the impedance and parasitic capacitance brought by the wiring will limit the driving ability of the first gamma circuit 210A, thereby limiting the driving ability and output voltage process of the driving channel circuit. This will slow down the process of voltage re-establishment (voltage recovery). In addition, if the gamma disturbance is to be reduced, the performance of the first gamma circuit 210A needs to be enhanced through additional power consumption or circuit area, which will result in greater power consumption and circuit area waste. Therefore, this implementation has conversion efficiency problems and thermal power consumption problems when outputting dynamic voltages. These dynamic voltage screens have high power consumption and cannot provide an optimal low-power solution.

[0060] In another possible implementation, the Vgmp may be provided by a low dropout regulator (LDO). However, the driving force of the LDO is insufficient, and when interference occurs in the LDO, the process of voltage re-establishment is particularly slow.

[0061] The present application embodiment provides an electronic device. Figure 6 As shown, the electronic device 1000B may include a circuit board ( Figure 6 The second display device 1100B may include a coupled second display screen 100B and a second display driver chip 200B. The second display driver chip 200B may be disposed on a circuit board.

[0062] like Figure 7 As shown, the second display screen 100B may include a second pixel circuit 110B. The second pixel circuit 110B may include a plurality of pixel channels, such as a first pixel channel 11B, a second pixel channel 12B, a third pixel channel 13B, a fourth pixel channel 14B, and more pixel channels not shown. Each of the plurality of pixel channels may include a plurality of sub-pixels. Taking the second pixel circuit 110B as an RGBG pixel circuit as an example, the first pixel channel 11B may include at least four sub-pixels: B, R, B, R, the second pixel channel 12B may include at least four sub-pixels: G, G, G, G, the third pixel channel 13B may include at least four sub-pixels: R, B, R, B, and the fourth pixel channel 14B may include at least four sub-pixels: G, G, G, G. One sub-pixel B, one sub-pixel R, and two sub-pixels G may be used as one pixel. For example, the first row of sub-pixels B in the first pixel channel 11B, the first row of sub-pixels G in the second pixel channel 12B, the first row of sub-pixels R in the third pixel channel 13B, and the first row of sub-pixels G in the fourth pixel channel 14B may serve as one pixel.

[0063] The second display driver chip 200B may include a second power supply terminal, a plurality of output terminals, a plurality of display switches, a plurality of power switches, a second gamma circuit 210B and a plurality of display channel circuits. The plurality of output terminals may include a first output terminal, a second output terminal, a third output terminal, a fourth output terminal and more output terminals not shown. The plurality of display switches may include a first display switch S1B, a second display switch S2B, a third display switch S3B, a fourth display switch S4B, and more display switches not shown. The plurality of power switches may include a first power switch K1B, a second power switch K2B, a third power switch K3B, a fourth power switch K4B, and more power switches not shown. The plurality of display channel circuits may include a first display channel circuit 221B, a second display channel circuit 222B, a third display channel circuit 223B, a fourth display channel circuit 224B and more display channel circuits not shown.

[0064] The second power supply terminal and multiple display channel circuits of the second display driver chip 200B are coupled to the second gamma circuit 210B. The multiple display channel circuits of the second display driver chip 200B are coupled to the first ends of the multiple display switches in a one-to-one correspondence, and the second ends of the multiple display switches are coupled to the multiple output ends in a one-to-one correspondence. The second power supply terminal is coupled to the first ends of the multiple power switches, and the second ends of the multiple power switches are coupled to the multiple output ends in a one-to-one correspondence. For example, the output end of the first display channel circuit 221B is coupled to the first end of the first display switch S1B, and the second end of the first display switch S1B is coupled to the first output end. The second power supply terminal is coupled to the first end of the first power switch K1B, and the second end of the first power switch K1B is coupled to the first output end. For another example, the output end of the mth display channel circuit is coupled to the first end of the mth display switch, and the second end of the mth display switch is coupled to the mth output end. The power supply terminal is coupled to the first end of the mth power switch, and the second end of the mth power switch is coupled to the mth output end. The mth display channel circuit is any one of the multiple display channel circuits, the mth display switch is any one of the multiple display switches, the mth power switch is any one of the multiple power switches, and the mth output end is any one of the multiple output ends.

[0065] The multiple pixel channels of the second pixel circuit 110B are coupled to the multiple output terminals of the second display driver chip 200B in a one-to-one correspondence. For example, the jth pixel channel is coupled to the jth output terminal, the jth pixel channel is any one of the multiple pixel channels, and the jth output terminal is any one of the multiple output terminals of the display driver chip. Optionally, the multiple sub-pixels in each pixel channel of the second pixel circuit 110B can be coupled to the same output terminal of the second display driver chip 200B, and the multiple pixel channels of the second pixel circuit 110B are in a one-to-one correspondence with the multiple output terminals of the second display driver chip 200B. For example, the first row of sub-pixels B in the first pixel channel 11B, the second row of sub-pixels R in the first pixel channel 11B, the third row of sub-pixels B in the first pixel channel 11B, and the fourth row of sub-pixels R in the first pixel channel 11B are all coupled to the first output terminal of the second display driver chip 200B. The first row of sub-pixels G in the second pixel channel 12B, the second row of sub-pixels G in the second pixel channel 12B, the third row of sub-pixels G in the second pixel channel 12B, and the fourth row of sub-pixels G in the second pixel channel 12B are all coupled to the second output terminal of the second display driver chip 200B.

[0066] The sub-pixels in the same row in the multiple pixel channels of the second pixel circuit 110B can be coupled to the same clock signal line ( Figure 7 For example, the subpixel B in the first row of the first pixel channel 11B, the subpixel G in the first row of the second pixel channel 12B, the subpixel R in the first row of the third pixel channel 13B, and the subpixel G in the first row of the fourth pixel channel 14B may be coupled to the third clock signal line. The subpixel R in the second row of the first pixel channel 11B, the subpixel G in the second row of the second pixel channel 12B, the subpixel B in the second row of the third pixel channel 13B, and the subpixel G in the second row of the fourth pixel channel 14B may be coupled to the fourth clock signal line.

[0067] In one example, next, Figure 8 , possible implementations of multiple display channel circuits and the second pixel circuit 110B in the second display driver chip 200B are introduced. Figure 8 Multiple power switches are not shown.

[0068] The second power supply terminal of the second display driver chip 200B is used to connect the power supply to receive the power supply voltage from the power supply. The second gamma circuit 210B receives the power supply voltage through the second power supply terminal and converts the power supply voltage into multiple voltages of different sizes. For example, the second gamma circuit 210B may include multiple resistors, and multiple voltages are obtained by resistor voltage division. The multiple voltages may be: Vgmp', Vdata1', Vdata2', ..., Vdataq', Vgsp' in descending order. Among them, the maximum voltage (such as Vgmp') provided by the second gamma circuit 210B is less than the power supply voltage. The second gamma circuit 210B can output multiple voltages to each display channel circuit.

[0069] The display channel circuit is used to input multiple voltages and output a voltage obtained according to the multiple voltages. Each display channel circuit can provide one of the multiple voltages to the corresponding pixel channel of the output end through the corresponding output end when the corresponding display switch is turned on. For example, each display channel circuit may include a multiplexer (MUX) and a driving operational amplifier (channel operational amplifier, CH-OP). The i-th input end of the multiplexer is coupled to the i-th voltage output end of the second gamma circuit 210B. The i-th input end of the multiplexer is any one of the multiple input ends of the multiplexer. The i-th voltage output end of the second gamma circuit 210B is any one of the multiple voltage output ends of the second gamma circuit 210B. The output end of the multiplexer is coupled to the first input end of the driving operational amplifier, and the second input end and the output end of the driving operational amplifier are both coupled to the first end of the first display switch S1B.

[0070] The first voltage output terminal of the second gamma circuit 210B can be used to output Vgmp' to the first input terminal of the multiplexer of the first display channel circuit 221B, the second voltage output terminal of the second gamma circuit 210B can be used to output Vdata1' to the second input terminal of the multiplexer of the first display channel circuit 221B, the third voltage output terminal of the second gamma circuit 210B can be used to output Vdata2' to the third input terminal of the multiplexer of the first display channel circuit 221B, ..., the q+1th voltage output terminal of the second gamma circuit 210B can be used to output Vdataq' to the q+1th input terminal of the multiplexer of the first display channel circuit 221B, and the q+2th voltage output terminal of the second gamma circuit 210B can be used to output Vgsp' to the q+2th input terminal of the multiplexer of the first display channel circuit 221B. The first display channel circuit 221B can obtain Vgmp according to Vgmp′, obtain Vdata1 according to Vdata1′, obtain Vdata2 according to Vdata2′, obtain Vdataq according to Vdataq′, and obtain Vgsp according to Vgsp′.

[0071] The first display channel can provide one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp to the sub-pixel in the first pixel channel 11B through the first output terminal when the first display switch S1B is turned on and the first power switch K1B is turned off. The maximum voltage (such as Vgmp) output by the display channel circuit is less than the power supply voltage. The second power supply terminal can provide the power supply voltage to the first pixel channel 11B through the first output terminal when the first power switch K1B is turned on and the first display switch S1B is turned off. Each sub-pixel may include an RC load, the RC load includes a resistor R and a capacitor C, the first end of the resistor R is coupled to the first output terminal, the second end of the resistor R is coupled to the first end of the capacitor C, and the second end of the capacitor C is grounded.

[0072] In this embodiment, the display channel circuit is coupled to the output terminal through the display switch, and the second power supply terminal is coupled to the output terminal through the power switch. The output terminal can output the voltage of the display channel circuit, or output the power supply voltage received by the second power supply terminal. When the output terminal needs to output a voltage (such as Vdata) for driving the sub-pixel to emit light, the display switch and the power switch can be turned on and off to make the display channel circuit output the voltage to the output terminal. When the output terminal needs to output a voltage (such as Vgmp) for driving the sub-pixel not to emit light, the display switch and the power switch can be turned on and off to make the second power supply terminal output the power supply voltage to the output terminal. If the power supply voltage is greater than Vgmp, the power supply voltage can also drive the sub-pixel not to emit light, so the power supply voltage can replace the Vgmp output by the display channel circuit. It can be seen that when the output terminal outputs a dynamic voltage, it does not switch the voltage according to the multiple voltages provided by the second gamma circuit 210B, but switches the voltage by turning on and off the display switch and the power switch. In this way, the interference of the voltage provided by the second gamma circuit 210B to the display channel circuit is alleviated, and the interference of the voltage output by the display channel circuit adjacent to the display channel circuit is alleviated. In this way, the interference to the voltage finally outputted from the output terminal is alleviated.

[0073] In a possible implementation, Fig. 9 As shown, the multiple display switches can be metal-oxide-semiconductor field-effect transistors (MOSFET). The second display driver chip 200B also includes multiple drive enhancement (buffer) circuits, for example, a first drive enhancement circuit 231B, a second drive enhancement circuit 232B, a third drive enhancement circuit 233B, and a fourth drive enhancement circuit 234B. In some examples, the kth drive enhancement circuit is coupled to the control end of the kth display switch. The kth drive enhancement circuit is any one of the multiple drive enhancement circuits, and the kth display switch is any one of the multiple display switches. For example, the first drive enhancement circuit 231B is coupled to the control end of the first display switch S1B, the second drive enhancement circuit 232B is coupled to the control end of the second display switch S2B, the third drive enhancement circuit 233B is coupled to the control end of the third display switch S3B, and the fourth drive enhancement circuit 234B is coupled to the control end of the fourth display switch S4B. Exemplarily, the drive enhancement circuit is used to stabilize the control waveform of the display switch to which it is coupled.

[0074] In this embodiment, the ideal waveform of the control waveform for controlling the display switch to be turned on or off is a square wave, but in practice the control waveform may be unstable. The drive enhancement circuit can stabilize the control waveform of the display switch coupled thereto. By providing a drive enhancement circuit for each display switch, high-speed on and off of multiple display switches can be achieved.

[0075] In a possible implementation, the power supply voltage at the second power supply terminal may be used to replace the maximum voltage (eg, Vgmp) provided by the display channel circuit.

[0076] In some examples, such as Fig.10 As shown, the second display driver chip 200B is used to drive the second display screen 100B to display a red picture.

[0077] Exemplarily, in the first time period T1, the first power switch K1B is turned on, and the first display switch S1B is turned off (optionally, S1B is turned off first, and K1B is turned on later). In the second time period T2, the first display switch S1B is turned on, and the first power switch K1B is turned off. The first output terminal is used to output a first display drive voltage in the first time period T1, and output a second display drive voltage in the second time period T2. Wherein, the first display drive voltage is used to drive the sub-pixel not to emit light. For example, the first display drive voltage is equal to the power supply voltage received by the second power supply terminal. Optionally, the second power supply terminal is used to connect the power supply. The second power supply terminal is used to receive an analog power supply voltage (AVDD). Since AVDD is greater than the maximum voltage (such as Vgmp) provided by the display channel circuit, AVDD can be used to drive the sub-pixel not to emit light, and AVDD can be used to replace the maximum voltage Vgmp provided by the display channel circuit. In this embodiment, the second power supply terminal is connected to the power supply, and the power supply voltage can be used as the voltage for driving the sub-pixel not to emit light through the second power supply terminal. The power supply voltage has a strong power supply network and a small path impedance, which can reduce the additional power consumption caused by the dynamic voltage output by the display channel circuit. Furthermore, the second display driving voltage is used to drive the sub-pixel to emit light. For example, the second display driving voltage is within a preset voltage interval. The maximum value of the preset voltage interval is less than the first display driving voltage. For example, the preset voltage interval is between Vgsp and Vgmp (the preset voltage interval does not include Vgsp and Vgmp). For example, Vgsp is 0.2V, AVDD is 8V, Vgmp = AVDD-Vgsp = 7.8V, and the preset voltage interval can be between 0.2V and 7.8V.

[0078] In the first time period T1, the first switching period Tz1 and the second time period T2, the second power switch K2B is turned on and the second display switch S2B is turned off. The first switching period Tz1 is between the first time period T1 and the second time period T2. The second output terminal is used to keep outputting the third display drive voltage in the first time period T1, the first switching period Tz1 and the second time period T2. The third display drive voltage is used to drive the sub-pixel not to emit light. For example, the third display drive voltage is equal to the power supply voltage received by the second power supply terminal. The maximum value of the preset voltage interval is also less than the third display drive voltage.

[0079] Alternatively, in the first time period T1, the first switching period Tz1 and the second time period T2, the second display switch S2B is turned on and the second power switch K2B is turned off. The third display drive voltage output by the second output terminal in the first time period T1, the first switching period Tz1 and the second time period T2 is equal to the maximum voltage (such as Vgmp) provided by the second display channel circuit 222B, that is, the third display drive voltage is less than the power supply voltage received by the second power supply terminal. The maximum value of the preset voltage interval is also less than the third display drive voltage.

[0080] Also exemplarily, in the first time period T1, the first power switch K1B is turned on, and the first display switch S1B is turned off (optionally, S1B is turned off first, and K1B is turned on later). In the second time period T2, the first display switch S1B is turned on, and the first power switch K1B is turned off. In the third time period T3, the first power switch K1B is turned on, and the first display switch S1B is turned off (optionally, S1B is turned off first, and K1B is turned on later). In the fourth time period T4, the first display switch S1B is turned on, and the first power switch K1B is turned off. The first output terminal is specifically used to output the first display drive voltage in the first time period T1, output the second display drive voltage in the second time period T2, output the first display drive voltage in the third time period T3, and output the second display drive voltage in the fourth time period T4. Among them, the second display drive voltage output by the first output terminal in the first time period T1 can be Vdata12, and the second display drive voltage output by the first output terminal in the fourth time period T4 can be Vdata14. Vdata12 and Vdata14 are preset voltage values ​​in a preset voltage interval. For example, Vdata12 and Vdata14 are respectively one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp. Vdata12 and Vdata14 can be the same voltage value or different voltage values.

[0081] In the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3 and the fourth time period T4, the second power switch K2B is turned on and the second display switch S2B is turned off. The second switching period Tz2 is between the second time period T2 and the third time period T3, and the third switching period Tz3 is between the third time period T3 and the fourth time period T4. The second output terminal is specifically used to maintain the output of the third display drive voltage in the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3 and the fourth time period T4. Wherein, the third display drive voltage is equal to the power supply voltage (such as AVDD) received by the second power supply terminal. Alternatively, in the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3 and the fourth time period T4, the second display switch S2B is turned on and the second power switch K2B is turned off. The third display driving voltage is equal to the maximum voltage (eg, Vgmp) provided by the second display channel circuit 222B.

[0082] Again exemplarily, in the first time period T1, the first power switch K1B is turned on, and the first display switch S1B is turned off (optionally, S1B is turned off first, and K1B is turned on later). In the second time period T2, the first display switch S1B is turned on, and the first power switch K1B is turned off. In the third time period T3, the first power switch K1B is turned on, and the first display switch S1B is turned off (optionally, S1B is turned off first, and K1B is turned on later). In the fourth time period T4, the first display switch S1B is turned on, and the first power switch K1B is turned off. In the nth time period Tn, the first power switch K1B is turned on, and the first display switch S1B is turned off (optionally, S1B is turned off first, and K1B is turned on later). In the n+1th time period Tn+1, the first display switch S1B is turned on, and the first power switch K1B is turned off. n is an odd number greater than or equal to 5. The first output terminal is specifically used to output a first display driving voltage in a first time period T1, output a second display driving voltage in a second time period T2, output a first display driving voltage in a third time period T3, output a second display driving voltage in a fourth time period T4, output a first display driving voltage in an nth time period Tn, and output a second display driving voltage in an n+1th time period Tn+1. The second display driving voltage output by the first output terminal in the first time period T1 may be Vdata12, the second display driving voltage output by the first output terminal in the fourth time period T4 may be Vdata14, and the second display driving voltage output by the first output terminal in the n+1th time period Tn+1 may be Vdata1(n+1). Vdata12, Vdata14, and Vdata1(n+1) are preset voltage values ​​in a preset voltage interval, for example, Vdata12, Vdata14, and Vdata1(n+1) are respectively one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp. Vdata12, Vdata14, and Vdata1(n+1) may be the same voltage value, or at least two voltages may be different voltage values.

[0083] In the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, and the third switching period Tn+1, the second power switch K2B is turned on and the second display switch S2B is turned off. The fourth switching period Tz4 is between the fourth time period T4 and the nth time period Tn, and the nth switching period Tzn is between the nth time period Tn and the n+1th time period Tn+1. The second output terminal is specifically used to maintain the output of the third display drive voltage in the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3, the fourth time period T4, the fourth switching period Tz4, the nth time period Tn, the nth switching period Tzn and the n+1th time period Tn+1. Wherein, the third display drive voltage is equal to the power supply voltage (such as AVDD) received by the second power supply terminal. Alternatively, in the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, the fourth time period T4, the fourth switching time period Tz4, the nth time period Tn, the nth switching time period Tzn and the n+1th time period Tn+1, the second display switch S2B is turned on and the second power switch K2B is turned off. The third display driving voltage is equal to the maximum voltage (such as Vgmp) provided by the second display channel circuit 222B.

[0084] As another example, the first display channel circuit 221B outputs the second display driving voltage only when the first display switch S1B is turned on. In this embodiment, the first display channel circuit 221B outputs the voltage only when the first display switch S1B is turned on, further reducing the power consumption of the first display channel circuit 221B. Alternatively, the first display channel outputs the maximum voltage (such as Vgmp) that the first display channel circuit 221B can provide when the first display switch S1B is turned on and the first power switch K1B is turned on. In this embodiment, the first display channel circuit 221B continuously outputs the second display driving voltage, and the first display channel circuit 221B is in a static output mode. In this way, the interference of the output voltage of the first display channel circuit 221B with the power supply voltage of the power supply end can be avoided, and the design complexity of the first display channel circuit 221B can also be reduced.

[0085] Again exemplarily, in the first time period T1, the third display switch S3B is turned on, and the third power switch K3B is turned off. In the second time period T2, the third power switch K3B is turned on, and the third display switch S3B is turned off. In the third time period T3, the third display switch S3B is turned on, and the third power switch K3B is turned off. In the fourth time period T4, the third power switch K3B is turned on, and the third display switch S3B is turned off. In the nth time period Tn, the third display switch S3B is turned on, and the third power switch K3B is turned off. In the n+1th time period Tn+1, the third power switch K3B is turned on, and the third display switch S3B is turned off. n is an odd number greater than or equal to 5. The third output terminal is specifically used to output the fourth display drive voltage in the first time period T1, output the first display drive voltage in the second time period T2, output the fourth display drive voltage in the third time period T3, output the first display drive voltage in the fourth time period T4, output the fourth display drive voltage in the nth time period Tn, and output the first display drive voltage in the n+1th time period Tn+1. Wherein, the fourth display driving voltage is within the above-mentioned preset voltage interval. The fourth display driving voltage output by the third output terminal in the first time period T1 may be Vdata31, the fourth display driving voltage output by the third output terminal in the third time period T3 may be Vdata33, and the fourth display driving voltage output by the third output terminal in the nth time period Tn may be Vdata3n. Vdata31, Vdata33 and Vdata3n are preset voltage values ​​in the preset voltage interval, for example, Vdata31, Vdata33 and Vdata3n are respectively one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp. Vdata12, Vdata14, Vdata1(n+1), Vdata31, Vdata33 and Vdata3n may be the same voltage value, or there may be at least two voltages with different voltage values.

[0086] In the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3, the fourth time period T4, the fourth switching period Tz4, the nth time period Tn, the nth switching period Tzn and the n+1th time period Tn+1, the fourth power switch K4B is turned on and the fourth display switch S4B is turned off. The fourth output terminal is specifically used to keep outputting the third display drive voltage in the first time period T1, the first switching period Tz1, the second time period T2, the second switching period Tz2, the third time period T3, the third switching period Tz3, the fourth time period T4, the fourth switching period Tz4, the nth time period Tn, the nth switching period Tzn and the n+1th time period Tn+1. Wherein, the third display drive voltage is equal to the power supply voltage (such as AVDD) received by the second power supply terminal. Alternatively, in the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, the fourth time period T4, the fourth switching time period Tz4, the nth time period Tn, the nth switching time period Tzn and the n+1th time period Tn+1, the fourth display switch S4B is turned on and the fourth power switch K4B is turned off. The third display driving voltage is equal to the maximum voltage (such as Vgmp) provided by the fourth display channel circuit 224B.

[0087] In other examples, the second display driver chip 200B can be used to drive the second display screen 100B to display a blue image. The voltage waveforms of the multiple output terminals are as follows: Fig.11 shown. Fig.11 The principle of the voltage waveform shown can be referred to Fig.10 The description of the principle of the voltage waveform diagram shown in the embodiment of the present application is not repeated here. Exemplarily, Vdata11, Vdata13, Vdata1n, Vdata32, Vdata34, Vdata3(n+1) are preset voltage values ​​in the preset voltage interval. For example, Vdata11, Vdata13, Vdata1n, Vdata32, Vdata34, Vdata3(n+1) are respectively one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp. Vdata11, Vdata13, Vdata1n, Vdata32, Vdata34, Vdata3(n+1) can be the same voltage value, or there can be at least two voltages with different voltage values.

[0088] In some other examples, the second display driver chip 200B can be used to drive the second display screen 100B to display a green image. The voltage waveforms of the multiple output terminals are as follows: Fig.12 shown. Fig.12 The principle of the voltage waveform shown can be referred to Fig.10The description of the principle of the voltage waveform diagram shown in the embodiment of the present application is not repeated here. Exemplarily, Vdata21, Vdata23, Vdata2n, Vdata41, Vdata43, Vdata4n are preset voltage values ​​in the preset voltage interval. For example, Vdata21, Vdata23, Vdata2n, Vdata41, Vdata43, Vdata4n are respectively one of Vgmp, Vdata1, Vdata2, ..., Vdataq, and Vgsp. Vdata21, Vdata23, Vdata2n, Vdata41, Vdata43, Vdata4n can be the same voltage value, or there can be at least two voltages with different voltage values.

[0089] In this embodiment, when the voltage outputted by the first output terminal is not a fixed voltage, a voltage equal to the power voltage received by the second power terminal is used as the first display driving voltage. That is, the first display driving voltage and the second display driving voltage have different sources. Figure 3 to Figure 5 Compared with the embodiment shown in the figure, the power supply voltage at the second power supply terminal can be used to replace the maximum voltage provided by the display channel circuit. When the first output terminal outputs a dynamic voltage, the voltage is no longer switched according to the multiple voltages provided by the second gamma circuit 210B. The interference to the voltage provided by the second gamma circuit 210B to the first display channel circuit 221B is alleviated, and the interference to the voltage output by the second display channel circuit 222B is alleviated. In this way, the interference to the voltage finally output by the second output terminal is alleviated. In this way, there is no need to extract a large current through the power supply voltage for voltage stabilization, which can reduce power consumption. In addition, the problem that the impedance and parasitic capacitance limit the driving capability of the second gamma circuit 210B can be alleviated, thereby improving the driving capability of the second display driver chip 200B and speeding up the voltage output process. In addition, there is no need to enhance the performance of the second gamma circuit 210B through additional power consumption or circuit area in order to eliminate voltage interference, thereby reducing power consumption and reducing circuit area waste.

[0090] based on Figure 6 to Figure 12 The second display driver chip 200B provided in the present application also provides a display driving method applied to the second display driver chip 200B. Fig.13 As shown, the method may at least include:

[0091] S100: Outputting a first display driving voltage in a first time period T1 and outputting a second display driving voltage in a second time period T2 via a first output terminal. Exemplarily, the first display driving voltage is equal to the power supply voltage received by the second power supply terminal.

[0092] S200: Maintain outputting the third display driving voltage through the second output terminal in the first time period T1, the first switching time period Tz1, and the second time period T2. Exemplarily, the first switching time period Tz1 is between the first time period T1 and the second time period T2. The second display driving voltage is within a preset voltage interval, and the maximum value of the preset voltage interval is less than the third display driving voltage.

[0093] In a possible implementation, S100 may specifically include: outputting a first display driving voltage in a first time period T1, outputting a second display driving voltage in a second time period T2, outputting the first display driving voltage in a third time period T3, and outputting the second display driving voltage in a fourth time period T4 through the first output terminal.

[0094] S200 may specifically include: maintaining output of a third display driving voltage through the second output terminal in a first time period T1, a first switching time period Tz1, a second time period T2, a second switching time period Tz2, a third time period T3, a third switching time period Tz3 and a fourth time period T4, the second switching time period Tz2 being between the second time period T2 and the third time period T3, and the third switching time period Tz3 being between the third time period T3 and the fourth time period T4.

[0095] In a possible implementation, S100 may specifically include: outputting a first display driving voltage in a first time period T1 through a first output terminal, outputting a second display driving voltage in a second time period T2, outputting the first display driving voltage in a third time period T3, outputting the second display driving voltage in a fourth time period T4, outputting the first display driving voltage in an nth time period Tn, and outputting the second display driving voltage in an n+1th time period Tn+1, where n is an odd number greater than or equal to 5.

[0096] S200 may specifically include: maintaining output of a third display driving voltage through the second output terminal in the first time period T1, the first switching time period Tz1, the second time period T2, the second switching time period Tz2, the third time period T3, the third switching time period Tz3, the fourth time period T4, the fourth switching time period Tz4, the nth time period Tn, the nth switching time period Tzn and the n+1th time period Tn+1, the fourth switching time period Tz4 is between the fourth time period T4 and the nth time period Tn, and the nth switching time period Tzn is between the nth time period Tn and the n+1th time period Tn+1.

[0097] In a possible implementation manner, the third display driving voltage is equal to the power supply voltage received by the power supply terminal.

[0098] It can be understood that the above display driving method can be applied to the aforementioned second display driving chip 200B. Since the effect of the chip has been described in detail in the aforementioned chip embodiment, it will not be repeated here.

[0099] An embodiment of the present application also provides a computer-readable storage medium, which stores program code. When the computer-readable storage medium is run on a device (for example, the device may be a single-chip microcomputer, a chip, a computer or a processor, etc.), the program code therein may be called to execute one or more steps in the above method embodiment.

[0100] Based on this understanding, the embodiments of the present application also provide a computer program product comprising instructions. The essence of the technical solution of the present application or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor therein to execute all or part of the steps of the methods of the various embodiments of the present application.

[0101] In the several embodiments provided in the present application, it should be understood that the disclosed chips, devices, equipment and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0102] In addition, each functional module in each embodiment of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0103] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display driver chip, characterized in that: The display driver chip includes a power supply terminal and a plurality of output terminals; the plurality of output terminals include a first output terminal and a second output terminal; The power supply terminal is used to receive a power supply voltage; The first output terminal is used to output a first display driving voltage in a first time period and a second display driving voltage in a second time period, wherein the first display driving voltage is equal to the power supply voltage; The second output terminal is used to keep outputting the third display driving voltage in the first time period, the first switching time period and the second time period, and the first switching time period is between the first time period and the second time period; The second display driving voltage is within a preset voltage interval, and a maximum value of the preset voltage interval is smaller than the third display driving voltage.

2. The display driver chip according to claim 1, characterized in that: The plurality of output terminals further includes a third output terminal; The third output terminal is used to output a fourth display driving voltage in the first time period and output the first display driving voltage in the second time period, and the fourth display driving voltage is within the preset voltage range; The fourth display driving voltage output by the third output terminal in the first time period is different in magnitude from the second display driving voltage output by the first output terminal in the second time period.

3. The display driver chip according to claim 1 or 2, characterized in that: The first output terminal is specifically configured to output the first display driving voltage in the first time period, output the second display driving voltage in the second time period, output the first display driving voltage in the third time period, and output the second display driving voltage in the fourth time period; The second output terminal is specifically used to maintain outputting the third display driving voltage in the first time period, the first switching period, the second time period, the second switching period, the third time period, the third switching period and the fourth time period, the second switching period is located between the second time period and the third time period, and the third switching period is located between the third time period and the fourth time period.

4. The display driver chip according to claim 1 or 2, characterized in that: The first output terminal is specifically configured to output the first display driving voltage in the first time period, output the second display driving voltage in the second time period, output the first display driving voltage in the third time period, output the second display driving voltage in the fourth time period, output the first display driving voltage in the nth time period, and output the second display driving voltage in the n+1th time period, where n is an odd number greater than or equal to 5; The second output terminal is specifically used to maintain outputting the third display driving voltage in the first time period, the first switching period, the second time period, the second switching period, the third time period, the third switching period, the fourth time period, the fourth switching period, the nth time period, the nth switching period and the n+1th time period, the fourth switching period is between the fourth time period and the nth time period, and the nth switching period is between the nth time period and the n+1th time period.

5. The display driver chip according to any one of claims 1 to 4, characterized in that: The chip also includes a first display channel circuit, a first display switch and a first power switch; The output end of the first display channel circuit is coupled to the first end of the first display switch, and the second end of the first display switch is coupled to the first output end; The power supply terminal is coupled to a first terminal of the first power switch, and a second terminal of the first power switch is coupled to the first output terminal.

6. The display driver chip according to claim 5, characterized in that: The chip also includes a plurality of display channel circuits, a plurality of display switches and a plurality of power switches; The output end of the mth display channel circuit is coupled to the first end of the mth display switch, and the second end of the mth display switch is coupled to the mth output end; the power supply end is coupled to the first end of the mth power switch, and the second end of the mth power switch is coupled to the mth output end; The mth display channel circuit is any one of the multiple display channel circuits, the mth display switch is any one of the multiple display switches, the mth power switch is any one of the multiple power switches, and the mth output end is any one of the multiple output ends.

7. The display driver chip according to claim 6, characterized in that: The chip also includes a plurality of driving enhancement circuits, The kth driving enhancement circuit is coupled to the control end of the kth display switch; the kth driving enhancement circuit is any one of the multiple driving enhancement circuits, and the kth display switch is any one of the multiple display switches.

8. The display driver chip according to any one of claims 1 to 7, characterized in that: The third display driving voltage is equal to the power supply voltage.

9. The display driver chip according to any one of claims 1 to 8, characterized in that: The power supply end is used to connect to a power supply.

10. A display driver chip, characterized in that: The display driver chip comprises a power supply terminal, a first output terminal, a first display channel circuit, a first display switch and a first power switch; the power supply terminal is used to receive a power supply voltage; The output end of the first display channel circuit is coupled to the first end of the first display switch, and the second end of the first display switch is coupled to the first output end; the power supply end is coupled to the first end of the first power switch, and the second end of the first power switch is coupled to the first output end.

11. The display driver chip according to claim 10, characterized in that: The chip also includes a plurality of output terminals, a plurality of display channel circuits, a plurality of display switches and a plurality of power switches; The output end of the mth display channel circuit is coupled to the first end of the mth display switch, and the second end of the mth display switch is coupled to the mth output end; the power supply end is coupled to the first end of the mth power switch, and the second end of the mth power switch is coupled to the mth output end; The mth display channel circuit is any one of the multiple display channel circuits, the mth display switch is any one of the multiple display switches, the mth power switch is any one of the multiple power switches, and the mth output end is any one of the multiple output ends.

12. The display driver chip according to claim 11, characterized in that: The chip also includes a plurality of driving enhancement circuits, The kth driving enhancement circuit is coupled to the control end of the kth display switch, the kth driving enhancement circuit is any one of the multiple driving enhancement circuits, and the kth display switch is any one of the multiple display switches.

13. The display driver chip according to any one of claims 10 to 12, characterized in that: The power supply end is used to connect to a power supply.

14. A display driving method, characterized in that: The display driving method is applied to a display driving chip, the display driving chip comprises a power supply terminal and a plurality of output terminals; the power supply terminal is used to receive a power supply voltage; the plurality of output terminals comprises a first output terminal and a second output terminal; the method comprises: Outputting a first display driving voltage in a first time period and a second display driving voltage in a second time period through the first output terminal, wherein the first display driving voltage is equal to the power supply voltage; Maintaining output of a third display driving voltage through the second output terminal in the first time period, a first switching time period and the second time period, wherein the first switching time period is between the first time period and the second time period; The second display driving voltage is within a preset voltage interval, and a maximum value of the preset voltage interval is smaller than the third display driving voltage.

15. The display driving method according to claim 14, characterized in that: The plurality of output terminals further include a third output terminal, and the method further includes: outputting a fourth display driving voltage in the first time period and outputting the first display driving voltage in the second time period through the third output terminal, wherein the fourth display driving voltage is within the preset voltage range; The fourth display driving voltage output by the third output terminal in the first time period is different in magnitude from the second display driving voltage output by the first output terminal in the second time period.

16. The display driving method according to claim 14 or 15, characterized in that: The step of outputting a first display driving voltage in a first time period and a second display driving voltage in a second time period through the first output terminal comprises: outputting the first display driving voltage in the first time period, outputting the second display driving voltage in the second time period, outputting the first display driving voltage in the third time period, and outputting the second display driving voltage in the fourth time period through the first output terminal; The step of outputting the third display driving voltage through the second output terminal during the first time period, the first switching period and the second time period comprises: The third display driving voltage is outputted through the second output terminal in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period and the fourth time period, the second switching time period is between the second time period and the third time period, and the third switching time period is between the third time period and the fourth time period.

17. The display driving method according to claim 14 or 15, characterized in that: The step of outputting a first display driving voltage in a first time period and a second display driving voltage in a second time period through the first output terminal comprises: outputting the first display driving voltage in the first time period, outputting the second display driving voltage in the second time period, outputting the first display driving voltage in the third time period, outputting the second display driving voltage in the fourth time period, outputting the first display driving voltage in the nth time period, and outputting the second display driving voltage in the n+1th time period, where n is an odd number greater than or equal to 5, through the first output terminal; The step of outputting the third display driving voltage through the second output terminal during the first time period, the first switching period and the second time period comprises: The third display driving voltage is outputted through the second output terminal in the first time period, the first switching time period, the second time period, the second switching time period, the third time period, the third switching time period, the fourth time period, the fourth switching time period, the nth time period, the nth switching time period and the n+1th time period, the fourth switching time period is between the fourth time period and the nth time period, and the nth switching time period is between the nth time period and the n+1th time period.

18. The display driving method according to any one of claims 14 to 17, characterized in that: The third display driving voltage is equal to the power supply voltage.

19. A display device, characterized in that: The display device comprises a display screen and a display driver chip as claimed in any one of claims 1 to 13; the display screen comprises a plurality of pixel channels; The jth pixel channel is coupled to the jth output end, the jth pixel channel is any one of the multiple pixel channels, and the jth output end is any one of the multiple output ends of the display driver chip.

20. An electronic device, characterized in that: The electronic device comprises a circuit board and the display device as claimed in claim 19, wherein a display driving chip in the display device is arranged on the circuit board.

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