Driving module and display device

Abstract

The present application belongs to the field of display, and specifically relates to a driving module and a display device. The driving module includes a source driving chip, a polarity partition control module, a picture detection module and a frequency division selection module. The source driving chips of odd columns are connected to a first signal line, and the first signal line is used to transmit a first polarity inversion signal. The source driving chips of even columns are connected to the polarity partition control module through a second signal line. The picture detection module is used to control the polarity partition control module to work according to the detected crosstalk degree of the display picture to form a conventional polarity mode and a polarity symmetry mode. The polarity partition control module makes the polarities of the display areas controlled by adjacent source driving chips symmetrical to offset coupling and eliminate lateral crosstalk. The frequency division selection module is used to halve the frequency of the first polarity inversion signal and the second polarity inversion signal in the polarity symmetry mode to avoid the formation of bright and dark lines at the boundary position, thereby improving the display effect of the display panel.

Description

Technical Field

[0001] The present application belongs to the field of display, and specifically relates to a driving module and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) includes an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. When the liquid crystal display is displayed, the pixel electrode on one side of the array substrate and the common electrode on one side of the color filter substrate form a liquid crystal capacitor (Clc) to drive the deflection of the liquid crystal molecules and control the brightness of each sub-pixel to realize the picture display. The pixel electrode and the common electrode on one side of the array substrate form a storage capacitor (Cst) to maintain the voltage of the liquid crystal capacitor.

[0003] If a single-direction electric field is applied to the liquid crystal molecules for a long time, the liquid crystal molecules may be polarized, resulting in a decrease in display quality or even damage to the liquid crystal material. By reversing the polarity and alternating the direction of the electric field, the polarization of the liquid crystal molecules can be effectively avoided. Polarity reversal methods include frame reversal, row reversal, column reversal, and dot reversal.

[0004] When the liquid crystal display is displaying, the data line provides pixel voltage to the pixel electrode. The polarity reversal makes the pixel voltage greater than or less than the voltage of the common electrode. The coupling capacitance (Cdc) formed between the data line and the pixel electrode will cause the pixel voltage to shift, resulting in lateral crosstalk (H-Crosstalk), which affects the display effect of the liquid crystal display. Summary of the invention

[0005] The purpose of the present application is to provide a driving module and a display device to improve or eliminate lateral crosstalk and improve the display effect of a liquid crystal display.

[0006] In order to achieve the above object, the present application provides a driving module, including a plurality of source driving chips, each of which is connected to a plurality of columns of data lines of a display panel, and the driving module further includes:

[0007] A polarity partition control module, wherein the source driver chips in the odd columns are connected to a first signal line, the first signal line is used to transmit a first polarity inversion signal, and the source driver chips in the even columns are connected to the polarity partition control module via a second signal line;

[0008] A picture detection module, connected to the display panel and the polarity partition control module, for controlling the polarity partition control module to work according to the detected crosstalk degree of the display picture, forming a conventional polarity mode and a polarity symmetric mode, wherein in the conventional polarity mode, the polarity partition control module outputs the first polarity inversion signal to the second signal line, and controls the display panel to be single-point inversion in both the row direction and the column direction, and in the polarity symmetric mode, the polarity partition control module outputs the second polarity inversion signal to the second signal line, so that the polarities of the display areas controlled by the adjacent source driver chips are symmetric, and the first polarity inversion signal and the second polarity inversion signal have opposite phases;

[0009] The frequency division selection module is used to halve the frequency of the first polarity inversion signal and the second polarity inversion signal in the polarity symmetry mode.

[0010] Optionally, the polarity partition control module includes a first transistor and a second transistor, wherein: one of the first transistor and the second transistor is an N-type field effect transistor and the other is a P-type field effect transistor, the control ends of the first transistor and the second transistor are both connected to the screen detection module, the first end of the first transistor is connected to the timing controller, the second end of the first transistor is connected to the second signal line, the first end of the second transistor is connected to the timing controller, and the second end of the second transistor is connected to the second signal line.

[0011] Optionally, the polarity partition control module further includes an inverter, and the inverter is connected to the timing controller and the first end of the second transistor.

[0012] Optionally, the frequency division selection module includes a frequency division selection unit and a comparison unit, the first ends of the inverter and the first transistor are connected to the timing controller through the frequency division selection unit, the frequency division selection unit includes a frequency divider, the first input end of the comparison unit is connected to the first signal line, the second input end of the comparison unit is connected to the second signal line, and the output end of the comparison unit is connected to the frequency division selection unit. When the first signal line signal and the second signal line signal are in phase, the first polarity inversion signal is output through the frequency divider.

[0013] Optionally, the comparison unit includes a comparator, an operational amplifier or an XOR gate circuit.

[0014] Optionally, the frequency division selection unit also includes a third transistor and a fourth transistor, the third transistor is an N-type field effect transistor, the fourth transistor is a P-type field effect transistor, the control ends of the third transistor and the fourth transistor are both connected to the comparison unit, the first end of the third transistor and the first end of the fourth transistor are both connected to the timing controller, the second end of the third transistor is connected to the polarity partition control module through the frequency divider, and the second end of the fourth transistor is connected to the polarity partition control module.

[0015] Optionally, the frequency division selection module also includes a fifth transistor, which is a triode, a control end of the fifth transistor is connected to the comparison unit, a first end of the fifth transistor is connected to a switching power supply, and a second end of the fifth transistor is connected to the frequency division selection unit.

[0016] Optionally, the frequency division selection module includes a frequency division selection unit and a comparison unit, the first signal line is connected to the source driver chip of the odd column through one frequency division selection unit, the second signal line is connected to the source driver chip of the even column through another frequency division selection unit, the frequency division selection unit includes a frequency divider, the first input end of the comparison unit is connected to the first signal line, the second input end of the comparison unit is connected to the second signal line, and the output end of the comparison unit is connected to the frequency division selection unit, when the first signal line signal and the second signal line signal are in different phases, the first signal line signal and the second signal line signal are output through their respective corresponding frequency dividers.

[0017] Optionally, the picture detection module includes a timing controller, the timing controller includes a waveform recognition unit, the waveform recognition unit is connected to the common electrode of the display panel and the polarity partition control module, and the waveform recognition unit is used to control the polarity partition control module to output the second polarity inversion signal to the second signal line when the common electrode voltage exceeds a preset interval.

[0018] The present application also provides a display device, comprising:

[0019] Display panel;

[0020] The driving module is connected to the display panel.

[0021] The driving module and display device disclosed in this application have the following beneficial effects:

[0022] In the present application, the driving module includes a source driver chip, a polarity partition control module, a picture detection module and a frequency division selection module. The source driver chips of the odd columns are connected to the first signal line, and the first signal line is used to transmit the first polarity inversion signal. The source driver chips of the even columns are connected to the polarity partition control module through the second signal line. The picture detection module is connected to the display panel and the polarity partition control module, and is used to control the polarity partition control module to work according to the detected crosstalk degree of the display picture, forming a conventional polarity mode and a polarity symmetry mode. The polarity partition control module makes the polarity of the display area controlled by the adjacent source driver chips symmetrical to offset the coupling, improve or eliminate the lateral crosstalk, and the frequency division selection module is used to halve the frequency of the first polarity inversion signal and the second polarity inversion signal in the polarity symmetry mode, so that the coupling directions of the two rows are opposite and offset each other, avoiding the formation of bright and dark lines at the boundary position, and improving the display effect of the display panel.

[0023] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0024] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 It is a structural schematic diagram of the driving module in Example 1 of the present application.

[0027] Figure 2 This is a schematic diagram of the conventional polarity mode in Example 1 of the present application.

[0028] Figure 3 It is a schematic diagram of the polarity symmetry of the display area in the first embodiment of the present application.

[0029] Figure 4 This is a schematic diagram of double-dot reversal in the following direction in the conventional polarity mode in Example 1 of the present application.

[0030] Figure 5 This is a schematic diagram of the polar symmetry mode in Example 1 of the present application.

[0031] Figure 6 It is a schematic diagram of the structure of the XOR gate circuit in the first embodiment of the present application.

[0032] Figure 7 It is the truth table of the XOR gate circuit in the first embodiment of the present application.

[0033] Figure 8 It is a structural diagram of the frequency division selection unit in the first embodiment of the present application.

[0034] Fig. 9 This is a schematic diagram of a polarity reversal signal in a conventional polarity mode in Example 1 of the present application.

[0035] Fig.10 This is a schematic diagram of a polarity reversal signal in a polarity symmetric mode in the first embodiment of the present application.

[0036] Fig.11 Schematic diagram of the common electrode voltage waveform in Example 1 of the present application.

[0037] Fig.12 It is a schematic diagram of the structure of the display device in the second embodiment of the present application.

[0038] Description of reference numerals:

[0039] 10. Drive module;

[0040] 100, source driver chip; 200, polarity partition control module; 210, first transistor; 220, second transistor; 230, inverter;

[0041] 300, picture detection module; 310, waveform recognition unit;

[0042] 400, frequency division selection module; 410, frequency division selection unit; 411, frequency divider; 412, third transistor; 413, fourth transistor; 420, comparison unit; 430, fifth transistor;

[0043] 501, first signal line; 502, second signal line; 503, switching power supply;

[0044] 20. Display panel; 21. First display area; 22. Second display area. DETAILED DESCRIPTION

[0045] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0046] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0047] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0048] Embodiment 1

[0049] See also Figure 1 As shown, in this embodiment, the driving module 10 is used to drive the display panel 20 to display a picture, and the driving module 10 includes a source driving chip 100, a polarity partition control module 200, a picture detection module 300 and a frequency division selection module 400. The display panel 20 includes multiple rows of scan lines and multiple columns of data lines, and the driving module 10 includes multiple source driving chips 100, each source driving chip 100 is connected to multiple columns of data lines of the display panel 20, that is, multiple source driving chips 100 form multiple columns.

[0050] The source driver chips 100 of the odd columns are connected to the first signal line 501, which is used to transmit the first polarity inversion signal. The source driver chips 100 of the even columns are connected to the polarity partition control module 200 through the second signal line 502. The first signal line 501 and the polarity partition control module 200 are both connected to the timing controller (TCON). The picture detection module 300 is connected to the display panel 20 and the polarity partition control module 200, and is used to control the polarity partition control module 200 to work according to the detected crosstalk degree of the display picture, forming a normal polarity mode and a polarity symmetric mode.

[0051] In the normal polarity mode, the polarity of the first display area 21 controlled by the source driver chip 100 of the odd columns is "+-+-" in both the row direction and the column direction, and the polarity partition control module 200 outputs the first polarity inversion signal to the second signal line 502, and the polarity of the second display area 22 controlled by the source driver chip 100 of the even columns is "+-+-" in both the row direction and the column direction, that is, the polarity partition control module 200 controls the display panel 20 to be single-point inversion in both the row direction and the column direction, such as Figure 2 shown.

[0052] In the polarity symmetry mode, the polarity of the first display area 21 controlled by the source driver chip 100 of the odd columns is "+-+-" in the row direction and the column direction, and the polarity partition control module 200 outputs a second polarity reversal signal to the second signal line 502, and the first polarity reversal signal and the second polarity reversal signal are opposite in phase, and the polarity of the second display area 22 controlled by the source driver chip 100 of the even columns is "-+-+" in the row direction and the column direction, that is, the polarity partition control module 200 makes the polarity of the display area controlled by the adjacent source driver chips 100 symmetrical, such as Figure 3 shown.

[0053] In the normal polarity mode, the first row of the first column is + polarity, the second row is - polarity, and the coupling from positive to negative is downward. The third row is + polarity, the fourth row is - polarity, and the coupling from positive to negative is downward. By analogy, the first column is all downward coupling. The first row of the second column is - polarity, the second row is + polarity, and the coupling from positive to negative is upward. The third row is - polarity, the fourth row is + polarity, and the coupling from positive to negative is upward. By analogy, the second column is all upward coupling. The same is true for the third and fourth columns. It can be seen that the coupling directions of adjacent columns are opposite, and the coupling directions of two rows of adjacent columns are opposite, which can offset the coupling. However, in the polarity symmetry mode, the boundary position will affect the display because the polarities of the two adjacent columns are consistent and coupled in the same direction, resulting in bright or dark lines that are different from the surroundings.

[0054] In order to improve or eliminate the display unevenness caused by bright and dark lines, the driving module 10 in this embodiment further includes a frequency division selection module 400, which is used to halve the frequency of the first polarity inversion signal and the second polarity inversion signal in the polarity symmetry mode.

[0055] After halving the frequency of the polarity inversion signal, Figure 4 As shown, the second line of the first column is + polarity, the third line is - polarity, and the coupling from positive to negative is downward. The fourth line is - polarity, the fifth line is + polarity, and the coupling from positive to negative is upward. By analogy, the coupling direction of every two rows in the first column is opposite to the coupling direction of the next two rows, and they weaken and cancel each other. The second line of the second column is - polarity, the third line is + polarity, and the coupling from positive to negative is upward. The fourth line is + polarity, the fifth line is - polarity, and the coupling from positive to negative is downward. By analogy, the coupling direction of every two rows in the second column is opposite to the coupling direction of the next two rows, and they weaken and cancel each other. The same is true for the third and fourth columns. It can be seen that the coupling directions of every two rows in adjacent columns are opposite, and the coupling direction of every two rows in the column itself is also weakened and canceled.

[0056] In polarity symmetry mode, the frequency of the polarity-reversed signal is halved, such as Figure 5As shown, the coupling directions of the pixel voltage and the common voltage of the adjacent first display area 21 and the second display area 22 are opposite, which can offset the coupling and improve or eliminate the lateral crosstalk. At the same time, since the polarity of the two adjacent columns at the boundary is consistent, although they are coupled in the same direction, the coupling directions of every two rows of the two columns themselves are opposite, which weakens the offset, so there is no obvious bright and dark dividing line.

[0057] In this embodiment, the driving module 10 includes a source driving chip 100, a polarity partition control module 200, a picture detection module 300 and a frequency division selection module 400, the source driving chip 100 of the odd column is connected to the first signal line 501, the first signal line 501 is used to transmit the first polarity inversion signal, the source driving chip 100 of the even column is connected to the polarity partition control module 200 through the second signal line 502, the picture detection module 300 is connected to the display panel 20 and the polarity partition control module 200, and is used to control the polarity partition control module 300 according to the crosstalk degree of the detected display picture. The control module 200 works to form a conventional polarity mode and a polarity symmetry mode. The polarity partition control module 200 makes the polarity of the display area controlled by the adjacent source driver chip 100 symmetric to offset the coupling and improve or eliminate the lateral crosstalk. The frequency division selection module 400 is used to halve the frequency of the first polarity inversion signal and the second polarity inversion signal in the polarity symmetry mode, so that the coupling directions of the two rows are opposite and offset each other, avoiding the formation of bright and dark lines at the boundary position. In other words, it not only improves or eliminates the lateral crosstalk, but also avoids the formation of bright and dark lines at the boundary position, thereby improving the display effect of the display panel 20.

[0058] See also Figure 1 As shown, the polarity partition control module 200 includes a first transistor 210 and a second transistor 220, wherein one of the first transistor 210 and the second transistor 220 is an N-type metal oxide field effect transistor (NMOS) and the other is a P-type metal oxide field effect transistor (PMOS), for example, the first transistor 210 is a P-type metal oxide field effect transistor, and the second transistor 220 is an N-type metal oxide field effect transistor. The control ends of the first transistor 210 and the second transistor 220 are both connected to the picture detection module 300, the first end of the first transistor 210 is connected to the timing controller, the second end of the first transistor 210 is connected to the second signal line 502, the first end of the second transistor 220 is connected to the timing controller, and the second end of the second transistor 220 is connected to the second signal line 502.

[0059] In the normal polarity mode, the picture detection module 300 outputs a low-level signal, the first transistor 210 is turned on and the second transistor 220 is turned off, and the first polarity inversion signal is output to the source driver chip 100 of the even column through the first transistor 210 and the second signal line 502; in the polarity symmetry mode, the picture detection module 300 outputs a high-level signal, the first transistor 210 is turned off and the second transistor 220 is turned on, and the second polarity inversion signal is output to the source driver chip 100 of the even column through the second transistor 220 and the second signal line 502, and the polarity of the display area controlled by adjacent source driver chips 100 is symmetrical.

[0060] See also Figure 1 As shown, the polarity partition control module 200 further includes an inverter 230 , and the inverter 230 is connected to the timing controller and the first end of the second transistor 220 .

[0061] The first polarity inversion signal is generated by the timing controller, and the inverter 230 inverts the first polarity inversion signal to generate a second polarity inversion signal. With this design, the timing controller only needs to generate one polarity inversion signal, which can reduce the manufacturing cost of the driving module 10.

[0062] It should be noted that the second polarity inversion signal can be generated by converting the first polarity inversion signal through the inverter 230, but is not limited thereto. The second polarity inversion signal can also be generated by a timing controller, depending on the specific situation.

[0063] See also Figure 1 As shown, the frequency division selection module 400 includes a frequency division selection unit 410 and a comparison unit 420. The first ends of the inverter 230 and the first transistor 210 are connected to the timing controller through the frequency division selection unit 410, that is, the frequency division selection unit 410 can be arranged between the timing controller and the polarity partition control module 200. The frequency division selection unit 410 includes a frequency divider 411. The first input end of the comparison unit 420 is connected to the first signal line 501, the second input end of the comparison unit 420 is connected to the second signal line 502, and the output end of the comparison unit 420 is connected to the frequency division selection unit 410. When the first signal line signal 501 and the second signal line signal 502 are in phase, the first polarity inversion signal is output through the frequency divider 411.

[0064] In the conventional polarity mode, the first signal line signal 501 and the second signal line signal 502 are both first polarity inversion signals, the first signal line signal 501 and the second signal line signal 502 have the same phase, the comparison unit 420 outputs a low-level signal to the frequency division selection unit 410, the first polarity inversion signal is not output through the frequency divider 411, and the display panel 20 is single-point inversion in the column direction; in the polarity symmetry mode, the first signal line signal 501 is a first polarity inversion signal, the second signal line signal 502 is a second polarity inversion signal, the first signal line signal 501 and the second signal line signal 502 have different phases, the comparison unit 420 outputs a high-level signal to the frequency division selection unit 410, the first polarity inversion signal is output through the frequency divider 411, and the display panel 20 is double-point inversion in the column direction.

[0065] It should be noted that the frequency division selection unit 410 can be set between the timing controller and the polarity partition control module 200, but is not limited thereto. The frequency division selection unit 410 can also be set between the polarity partition control module 200 and the source driver chip 100, depending on the specific situation.

[0066] For example, the frequency division selection module 400 includes a frequency division selection unit 410 and a comparison unit 420. The first signal line 501 is connected to the source driver chip 100 of the odd column through one frequency division selection unit 410, and the second signal line 502 is connected to the source driver chip 100 of the even column through another frequency division selection unit 410. The frequency division selection unit 410 includes a frequency divider 411. The first input end of the comparison unit 420 is connected to the first signal line 501, the second input end of the comparison unit 420 is connected to the second signal line 502, and the output end of the comparison unit 420 is connected to the frequency division selection unit 410. When the first signal line signal 501 and the second signal line 502 are in phase, the first signal line 501 signal and the second signal line 502 signal are output through the corresponding frequency dividers 411.

[0067] The frequency division selection unit 410 is disposed between the polarity partition control module 200 and the source driver chip 100 . When the polarity partition control module 200 performs polarity partitioning, the frequency division selection unit 410 further reduces the frequency of the polarity inversion signal by half.

[0068] See also Figure 1 and Figure 6 As shown, the comparison unit 420 includes an XOR gate circuit, a first input terminal A of the XOR gate circuit is connected to the first signal line 501 , a second input terminal B of the XOR gate circuit is connected to the second signal line 502 , and an output terminal Y of the XOR gate circuit is connected to the frequency division selection unit 410 .

[0069] In the normal polarity mode, the first signal line signal 501 and the second signal line signal 502 are both first polarity inversion signals, the two input terminals of the XOR gate circuit are both high level or low level at the same time, and the XOR gate circuit outputs a low level signal to the frequency division selection unit 410. Figure 7 As shown, the first polarity inversion signal is not output through the divider 411, and the display panel 20 is single-point inversion in the column direction; in the polarity symmetry mode, the first signal line signal 501 is a first polarity inversion signal, and the second signal line signal 502 is a second polarity inversion signal. The first signal line signal 501 and the second signal line signal 502 have different phases, one input end of the XOR gate circuit is high level and the other input end is low level, the XOR gate circuit outputs a high level signal to the frequency division selection unit 410, the first polarity inversion signal is output through the divider 411, and the display panel 20 is double-point inversion in the column direction.

[0070] It should be noted that the comparison unit 420 may be an XOR gate circuit, but is not limited thereto. The comparison unit 420 may also be a comparator or an operational amplifier, etc., depending on the specific situation.

[0071] See also Figure 1 As shown, the frequency division selection module 400 also includes a fifth transistor 430, which is a triode. The control end of the fifth transistor 430 is connected to the comparison unit 420, the first end of the fifth transistor 430 is connected to the switching power supply 503, and the second end of the fifth transistor 430 is connected to the frequency division selection unit 410.

[0072] The fifth transistor 430 is a triode capable of amplifying current. The comparison unit 420 controls the switch of the triode. The switching power supply 503 controls the operation of the frequency division selection unit 410. This design can avoid the control signal from attenuating and affecting the operation of the frequency division selection unit 410.

[0073] See also Figure 8 As shown, the frequency division selection unit 410 also includes a third transistor 412 and a fourth transistor 413, the third transistor 412 is an N-type metal oxide field effect transistor, and the fourth transistor 413 is a P-type metal oxide field effect transistor. The control ends of the third transistor 412 and the fourth transistor 413 are both connected to the comparison unit 420 through the fifth transistor 430, the first end of the third transistor 412 and the first end of the fourth transistor 413 are both connected to the timing controller, the second end of the third transistor 412 is connected to the polarity partition control module 200 through the frequency divider 411, and the second end of the fourth transistor 413 is connected to the polarity partition control module 200.

[0074] See also Fig. 9As shown, in the normal polarity mode, the comparison unit 420 outputs a low level signal, the fourth transistor 413 is turned on and the third transistor 412 is turned off, the first polarity inversion signal generated by the timing controller does not pass through the frequency divider 411, the timing controller signal, the first signal line 501 signal and the second signal line 502 signal have the same frequency, and the display panel 20 is single-point inverted in the column direction; see Fig.10 As shown, in the polarity symmetry mode, the comparison unit 420 outputs a high-level signal, the third transistor 412 is turned on and the fourth transistor 413 is turned off, the first polarity inversion signal generated by the timing controller is output through the divider 411, the signal frequencies of the first signal line 501 and the second signal line 502 are both half of the signal frequency of the timing controller, and the display panel 20 is double-point inverted in the column direction.

[0075] In some embodiments, the picture detection module 300 is a timing controller, which includes a waveform recognition unit 310, which is connected to the common electrode of the display panel 20 and the polarity partition control module 200, and the waveform recognition unit 310 is used to control the polarity partition control module 200 to output a second polarity reversal signal to the second signal line 502 when the common electrode voltage Vcom exceeds a preset interval. It should be noted that the picture detection module 300 can be a timing controller, but is not limited thereto, and the picture detection module 300 can also be an additional detection module, which can be determined according to the specific situation.

[0076] When the pixel voltage is offset during lateral crosstalk, it will cause coupling fluctuation of the common electrode voltage Vcom. In the waveform recognition unit 310, an interval value is set according to the common electrode voltage Vcom, that is, a positive and negative trigger value m1 and m2 are set, such as Fig.11 As shown, when it is recognized that the common electrode voltage Vcom exceeds the preset interval (greater than m1 and maintained for t1 time or less than m2 and maintained for t2 time, indicating that the lateral crosstalk is serious and the picture effect is poor), a high-level signal is output to the source driver chip 100 of the even-numbered columns, and the display panel 20 switches to the polarity symmetric mode. The pixel voltage and common voltage coupling directions of the adjacent first display area 21 and second display area 22 are opposite, so that the coupling can be offset and the lateral crosstalk can be improved or eliminated. On the contrary, when the common electrode voltage Vcom does not exceed the preset interval, the display panel 20 is in the normal polarity mode.

[0077] In some embodiments, the timing controller can detect the display screen and control the display panel 20 to a conventional polarity mode or a polarity symmetric mode according to the display screen. When using the timing controller to detect the display screen, some complex screens may not be detected, and the detection must be performed based on the pixel arrangement structure and number. The existing known lateral crosstalk screens may not be complete. If a new screen has lateral crosstalk later, then the pixel structure of this screen is different from the existing one, and the timing controller cannot detect it either. In addition, the lateral crosstalk phenomenon of different liquid crystals is inconsistent, and the unified setting cannot be fully compatible, which requires more debugging time.

[0078] In this embodiment, the waveform recognition unit 310 is connected to the common electrode of the display panel 20 and the polarity partition control module 200. The waveform recognition unit 310 switches the display panel 20 to a conventional polarity mode or a polarity symmetric mode according to the common electrode voltage Vcom. Compared with the solution of using a timing controller to detect the display screen, it can be generally used to detect different lateral crosstalk phenomena.

[0079] Embodiment 2

[0080] See also Fig.12 As shown, the display device in this embodiment includes the driving module 10 and the display panel 20 disclosed in the first embodiment, and the display panel 20 is connected to the source driving chip 100 of the driving module 10 .

[0081] In this embodiment, the display device includes a driving module 10, the driving module 10 includes a source driving chip 100, a polarity partition control module 200, a picture detection module 300 and a frequency division selection module 400, the source driving chip 100 of the odd column is connected to the first signal line 501, the first signal line 501 is used to transmit a first polarity inversion signal, the source driving chip 100 of the even column is connected to the polarity partition control module 200 through the second signal line 502, the picture detection module 300 is connected to the display panel 20 and the polarity partition control module 200, The polarity partition control module 200 is used to control the operation of the polarity partition control module 200 according to the detected crosstalk degree of the display image, forming a conventional polarity mode and a polarity symmetry mode. The polarity partition control module 200 makes the polarity of the display area controlled by the adjacent source driver chip 100 symmetrical to offset the coupling, improve or eliminate the lateral crosstalk, and the frequency division selection module 400 is used to halve the frequency of the first polarity inversion signal and the second polarity inversion signal in the polarity symmetry mode, so that the coupling directions of the two rows are opposite and offset each other, thereby avoiding the formation of bright and dark lines at the boundary position, and improving the display effect of the display panel 20.

[0082] The terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0083] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0084] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0085] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A driving module, comprising a plurality of source driving chips, each of which is connected to a plurality of columns of data lines of a display panel, characterized in that: The driving module also includes: A polarity partition control module, wherein the source driver chips in the odd columns are connected to a first signal line, the first signal line is used to transmit a first polarity inversion signal, and the source driver chips in the even columns are connected to the polarity partition control module via a second signal line; A picture detection module, connected to the display panel and the polarity partition control module, for controlling the polarity partition control module to work according to the detected crosstalk degree of the display picture, forming a conventional polarity mode and a polarity symmetric mode, wherein in the conventional polarity mode, the polarity partition control module outputs the first polarity inversion signal to the second signal line, and controls the display panel to be single-point inversion in both the row direction and the column direction, and in the polarity symmetric mode, the polarity partition control module outputs the second polarity inversion signal to the second signal line, so that the polarities of the display areas controlled by the adjacent source driver chips are symmetric, and the first polarity inversion signal and the second polarity inversion signal have opposite phases; The frequency division selection module is used to halve the frequency of the first polarity inversion signal and the second polarity inversion signal in the polarity symmetry mode.

2. The driving module according to claim 1, characterized in that: The polarity partition control module includes a first transistor and a second transistor, wherein one of the first transistor and the second transistor is an N-type field effect transistor and the other is a P-type field effect transistor, the control ends of the first transistor and the second transistor are both connected to the picture detection module, the first end of the first transistor is connected to the timing controller, the second end of the first transistor is connected to the second signal line, the first end of the second transistor is connected to the timing controller, and the second end of the second transistor is connected to the second signal line.

3. The driving module according to claim 2, characterized in that: The polarity partition control module further includes an inverter, and the inverter is connected to the timing controller and the first end of the second transistor.

4. The driving module according to claim 3, characterized in that: The frequency division selection module includes a frequency division selection unit and a comparison unit. The first ends of the inverter and the first transistor are connected to the timing controller through the frequency division selection unit. The frequency division selection unit includes a frequency divider. The first input end of the comparison unit is connected to the first signal line, the second input end of the comparison unit is connected to the second signal line, and the output end of the comparison unit is connected to the frequency division selection unit. When the first signal line signal and the second signal line signal have different phases, the first polarity inversion signal is output through the frequency divider.

5. The driving module according to claim 4, characterized in that: The comparison unit includes a comparator, an operational amplifier or an XOR gate circuit.

6. The driving module according to claim 4, characterized in that: The frequency division selection unit also includes a third transistor and a fourth transistor, the third transistor is an N-type field effect transistor, the fourth transistor is a P-type field effect transistor, the control ends of the third transistor and the fourth transistor are both connected to the comparison unit, the first end of the third transistor and the first end of the fourth transistor are both connected to the timing controller, the second end of the third transistor is connected to the polarity partition control module through the frequency divider, and the second end of the fourth transistor is connected to the polarity partition control module.

7. The driving module according to claim 4, characterized in that: The frequency division selection module also includes a fifth transistor, which is a triode. The control end of the fifth transistor is connected to the comparison unit, the first end of the fifth transistor is connected to the switching power supply, and the second end of the fifth transistor is connected to the frequency division selection unit.

8. The driving module according to claim 3, characterized in that: The frequency division selection module includes a frequency division selection unit and a comparison unit. The first signal line is connected to the source driver chip of the odd column through one frequency division selection unit, and the second signal line is connected to the source driver chip of the even column through another frequency division selection unit. The frequency division selection unit includes a frequency divider. The first input end of the comparison unit is connected to the first signal line, the second input end of the comparison unit is connected to the second signal line, and the output end of the comparison unit is connected to the frequency division selection unit. When the first signal line signal and the second signal line signal are in different phases, the first signal line signal and the second signal line signal are output through their respective corresponding frequency dividers.

9. The driving module according to claim 1, characterized in that: The picture detection module includes a timing controller, which includes a waveform recognition unit. The waveform recognition unit is connected to the common electrode of the display panel and the polarity partition control module. The waveform recognition unit is used to control the polarity partition control module to output the second polarity inversion signal to the second signal line when the common electrode voltage exceeds a preset interval.

10. A display device, characterized in that: include: Display panel; The driving module according to any one of claims 1 to 9, connected to the display panel.

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