Semiconductor memory device

Abstract

An embodiment relates to a semiconductor memory device. A memory according to an embodiment includes a cell array. The first wiring is connected to the memory cells arranged in the first direction. The second wiring is connected to the memory cells arranged in the second direction. The plurality of third wirings are provided corresponding to each of the plurality of second wirings arranged in the third direction. The first sensing circuit is connected to a first pair of the third wirings. The second sensing circuit is connected to a second pair of the third wirings. The switching circuit is connected to the first and second sensing circuits and selectively outputs signals of the first and second sensing circuits. The switching control circuit stores the addresses of the second and third wirings connected to the defective cell, and outputs a control signal for controlling the switching circuit on the basis of the addresses of the second and third wirings connected to the selected cell to be read.

Description

[0001] Related Applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-113315 (filing date: July 10, 2023). This application incorporates all the contents of the basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] A semiconductor memory device such as DRAM (Dynamic Random Access Memory) has been developed that arranges memory cells three-dimensionally. The three-dimensional memory cell array has a hierarchical bit line structure that hierarchizes the bit lines into global bit lines and local bit lines to reduce the bit line capacitance and ensure the sensing margin. In such a memory cell array, when a defective cell is generated, the defective cell needs to be replaced (remedied) by a redundant cell. Summary of the invention

[0005] The semiconductor memory device of the present embodiment has a cell array including a plurality of memory cells. In the cell array, a plurality of first wirings are commonly connected to a plurality of memory cells arranged in a first direction. In the cell array, a plurality of second wirings are commonly connected to a plurality of memory cells arranged in a second direction intersecting with the first direction. A plurality of third wirings are provided corresponding to each of a plurality of second wirings arranged in a third direction intersecting with the first and second directions. The first sensing circuit is connected to a first pair of two third wirings. The second sensing circuit is connected to a second pair of the other two third wirings. The switch circuit is connected to the first and second sensing circuits, and selectively outputs an output signal of either the first or second sensing circuit. The switch control circuit stores the addresses of the second wiring and the third wiring connected to the defective cell, and outputs a control signal for controlling the switch circuit based on the addresses of the second wiring and the third wiring connected to the read object, that is, the selected cell.

[0006] According to one embodiment, it is possible to provide a semiconductor memory device in which, even if a defective cell occurs, the defective cell can be replaced with a redundant cell with high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic perspective view showing a configuration example of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a schematic three-dimensional diagram showing one bit line and its surrounding structure.

[0009] Figure 3 This is a block diagram showing a configuration example of a semiconductor memory device according to the first embodiment.

[0010] Figure 4 This is a conceptual diagram showing a configuration example and an operation example of a switching circuit.

[0011] Figure 5 This is a conceptual diagram showing a configuration example and an operation example of a switching circuit.

[0012] Figure 6 This is a conceptual diagram showing a configuration example and an operation example of a switching circuit.

[0013] Figure 7 This is a circuit diagram showing a configuration example of a switching element.

[0014] Figure 8 This is a conceptual diagram showing a configuration example and an operation example of a switch control circuit.

[0015] Fig. 9 This is a block diagram showing a configuration example of a gate circuit.

[0016] Fig.10 : is a block diagram showing a configuration example of a shift circuit.

[0017] Fig.11 It is a conceptual diagram showing a configuration example and an operation example of a switch control circuit according to the second embodiment.

[0018] Fig.12 It is a schematic plan view showing an example of the arrangement of bit lines.

[0019] Fig.13 It is a schematic plan view showing another example of the arrangement of the bit lines. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments do not limit the present invention. The accompanying drawings are schematic or conceptual. In the specification and the accompanying drawings, the same elements are marked with the same symbols.

[0021] (First embodiment)

[0022] Figure 1 1 is a schematic three-dimensional diagram showing a configuration example of a semiconductor memory device 1 according to a first embodiment. The semiconductor memory device 1 according to this embodiment is, for example, a DRAM having a three-dimensional memory cell array MCA in which memory cells MC are arranged three-dimensionally (stereoscopically). The memory cell MC is used as a memory cell for storing 1-bit data or multi-bit data.

[0023] A plurality of memory cells MC are arranged in a matrix in a plane in the XY plane to form a memory cell layer LYR. In addition, a memory cell array MCA is formed by stacking a plurality of memory cell layers LYR in the Z direction. In the memory cell array MCA, a plurality of memory cell layers LYR are stacked approximately parallel to each other. Thus, a plurality of memory cells MC are arranged in three dimensions.

[0024] The semiconductor memory device 1 of the present embodiment includes a memory cell array MCA, a plurality of word lines WL, a plurality of bit lines VBL, a plurality of global bit lines GBL, a plurality of bit line selection transistors Tbls, and a plurality of memory cell layer selection transistors Tlys and bTlys.

[0025] A plurality of word lines WL extend in the X direction within the surface of the memory cell layer LYR and are connected to a plurality of memory cells MC arranged in the X direction. In the memory cell layer LYR, a plurality of word lines WL are arranged in the Y direction. One end of the plurality of word lines WL is connected to a word line driver (not shown) via a memory cell layer selection transistor Tlys. The other end of the plurality of word lines WL is connected to a non-selection voltage source of the word line WL via a memory cell layer selection transistor bTlys. The word line WL is similarly configured in each memory cell layer LYR.

[0026] The layer selection word line MWL is connected to the gate of the memory cell layer selection transistor Tlys, and the memory cell layer selection transistor Tlys is set to the on state when the memory cell layer LYR is selected. The layer selection word line bMWL is connected to the gate of the memory cell layer selection transistor bTlys, and the memory cell layer selection transistor bTlys is set to the non-conducting state when the memory cell layer LYR is selected. Conversely, the layer selection word line MWL sets the memory cell layer selection transistor Tlys to the non-conducting state when the memory cell layer LYR is not selected. The layer selection word line bMWL sets the memory cell layer selection transistor bTlys to the on state when the memory cell layer LYR is not selected. The layer selection word line bMWL transmits an inverted (inverse logic) signal to the layer selection word line MWL. Therefore, when one of the memory cell layer selection transistors Tlys and bTlys is in the on state, the other is in the non-conducting state.

[0027] A plurality of bit lines (local bit lines) VBL extend in the stacking direction (Z direction) of the plurality of memory cell layers LYR and are connected to a plurality of memory cells MC arranged in the Z direction. The plurality of memory cells MC arranged in the Z direction are connected to a common bit line VBL. The plurality of bit lines VBL are arranged two-dimensionally in a matrix in the XY direction corresponding to the memory cells MC in the memory cell layer LYR when viewed from above in the Z direction. One end of the plurality of bit lines VBL is connected to the global bit line GBL via the bit line selection transistor Tbls.

[0028] A plurality of global bit lines GBL extend in the Y direction in the XY plane and are connected to one end of a plurality of bit lines VBL arranged in the Y direction via a bit line selection transistor Tbls. A plurality of bit lines VBL arranged in the Y direction are connected to a common global bit line GBL. A plurality of global bit lines GBL are arranged in the X direction. One end of a plurality of global bit lines GBL is connected to a sensing circuit SAC. The global bit line GBL is provided in common with respect to a plurality of memory cell layers LYR in the memory cell array MCA.

[0029] The sensing circuit SAC is connected to a plurality of global bit lines GBL. Figure 3 As shown, the sensing circuit SAC includes a plurality of sense amplifiers SA connected to two global bit lines GBL. The sensing circuit SAC receives a read voltage corresponding to the data stored in the selected memory cell MC via one of the selected global bit lines GBL pair, and receives a reference voltage corresponding to the reference signal from the other global bit line GBL. In addition, the sensing circuit SAC compares the read voltage with the reference voltage and amplifies the voltage difference between them to detect the logic of the data.

[0030] Figure 2 1 is a schematic three-dimensional diagram showing a bit line VBL and its surrounding structure. Each memory cell MC includes a cell transistor Tmc and a cell capacitor Cmc. The gate of the cell transistor Tmc is connected to any word line WL. One of the source and drain of the cell transistor Tmc is connected to the bit line VBL, and the other of the source and drain is connected to one end of the cell capacitor Cmc. The cell capacitor Cmc is connected between the other of the source and drain of the cell transistor Tmc and a reference voltage source (e.g., ground, or intermediate voltage VDD / 2).

[0031] The memory cell MC can store logic data by accumulating charges in the cell capacitor Cmc or releasing charges from the cell capacitor Cmc through the cell transistor Tmc.

[0032] Figure 3 1 is a block diagram showing a configuration example of a semiconductor memory device 1 according to a first embodiment. The semiconductor memory device 1 includes a memory cell array MCA, a sense amplifier SA, a switch circuit SWC, a switch control circuit SSC, and a controller CNT. Figure 3 In the figure, for convenience, the word line WL is omitted.

[0033] A plurality of memory cells MC arranged in the Z direction are commonly connected to a bit line (local bit line) VBL extending in the Z direction. A plurality of bit lines VBL arranged in the Y direction are arranged corresponding to a global bit line GBL extending in the Y direction for every n (n is an integer greater than or equal to 2), and are commonly connected to the corresponding global bit line GBL. A plurality of global bit lines GBL are connected to a sense amplifier SA in pairs of two. In this way, the semiconductor memory device 1 has a hierarchical bit line structure including bit lines VBL and global bit lines GBL. In addition, in the present embodiment, as an example, the memory cell array MCA is listed as a three-dimensional memory cell array. However, as long as the memory cell array MCA has a hierarchical bit line structure, it can also be a planar memory cell array in which a plurality of memory cells MC are arranged in a two-dimensional plane.

[0034] like Figure 3 As shown in FIG. 1 , a pair of global bit lines GBL is connected to one sense amplifier SA. The n bit lines VBL corresponding to each of the pair of global bit lines GBL connected to each sense amplifier SA are connected to a plurality of memory cells MC storing data. When each sense amplifier SA reads data from a memory cell MC connected to a bit line VBL of one global bit line GBL, it transmits a reference signal of an intermediate voltage between "1" and "0" to another global bit line GBL. Figure 3 In the example, n is 4, but n may be 3 or less or 5 or more.

[0035] The bit line selection transistors Tbls are respectively provided between the bit line VBL and the global bit line GBL. The bit line selection transistors Tbls selectively connect one bit line VBL to one global bit line GBL at a time in each memory unit MU. That is, the bit line selection transistors Tbls selectively connect the bit line VBL to one global bit line GBL in each memory unit MU during a data read operation or a data write operation. The bit line selection transistors Tbls do not connect any bit line VBL to another global bit line GBL.

[0036] In addition, among the memory cells MC connected to one bit line VBL connected to one of the global bit lines GBL pair, one memory cell MC connected to the word line WL selected by the row address RADD is used as the selected memory cell MC, and data is output. Alternatively, data is written to the selected memory cell MC. The other of the global bit lines GBL pair is not connected to the bit line VBL, and a reference signal is transmitted from the sense amplifier SA.

[0037] Each of the plurality of sense amplifiers SA is connected to a pair of global bit lines GBL. Each sense amplifier SA compares data obtained from one global bit line GBL with a reference signal obtained from another global bit line GBL, and detects logic of the data based on the reference signal. The reference signal is, for example, data of an intermediate voltage between "1" and "0".

[0038] Conversely, when the memory cell MC connected to one bit line VBL connected to the other of the global bit line GBL pair is selected, the reference signal is transmitted from the sense amplifier SA without connecting the bit line VBL to one of the global bit line GBL pair.

[0039] The plurality of bit lines VBL and the plurality of memory cells MC corresponding to the global bit line GBL are also referred to as columns CL. In addition, two data columns CL corresponding to one sense amplifier SA constitute one memory unit MU.

[0040] One redundant unit RDD is provided for one or more memory units MU. The redundant unit RDD has the same structure as the memory unit MU. Therefore, one of the multiple memory units MU can be set as the redundant unit RDD. In addition, in order to distinguish the redundant unit RDD from the memory unit MU, the reference symbol of the structure of the redundant unit RDD is marked with "_RDD". For example, the sense amplifier SA_RDD is connected to the global bit line GBL_RDD pair of the redundant unit RDD.

[0041] When there is a defective cell in the bit line VBL of the memory unit MU, the bit line VBL_RDD of the redundant unit RDD replaces the bit line VBL of the defective cell and is used to store data. At this time, the entire bit line VBL of the defective cell is replaced with the bit line VBL_RDD of the redundant unit RDD. Therefore, in the data read operation, data is read from the bit line VBL_RDD of the redundant unit RDD instead of the bit line VBL of the defective cell.

[0042] For example, Figure 3The bit line VBLf1 in which the defective cell MCf1 is located is replaced by the bit line VBLf1_RDD in which the memory cell MCf1_RDD is located in the redundant cell RDD. In the above case, since the bit line VBL is replaced as a whole, the other memory cells connected to the bit line VBLf1 are also replaced by the memory cells connected to the bit line VBLf1_RDD. The memory cell of the bit line VBLf1 and the memory cell of the bit line VBLf1_RDD of the redundant cell RDD share the word line WL. The defective cell MCf1 is replaced by the MCf1_RDD of the bit line VBLf1_RDD of the redundant cell RDD connected to the same word line WL. That is, the row address RADD of the defective cell MCf1 and the MCf1_RDD of the bit line VBLf1_RDD are the same.

[0043] In addition, the bit line VBLf2 of the defective cell MCf2 is replaced by the bit line VBLf2_RDD of the redundant cell RDD. In the above case, since the bit line VBL is replaced as a whole, the other memory cells connected to the bit line VBLf2 are also replaced by the memory cells connected to the bit line VBLf2_RDD. The memory cell of the bit line VBLf2 and the memory cell of the bit line VBLf2_RDD of the redundant cell RDD share the word line WL. The defective cell MCf2 is replaced by the MCf2_RDD of the bit line VBLf2_RDD of the redundant cell RDD connected to the same word line WL. That is, the row address RADD of the defective cell MCf2 and the MCf2_RDD of the bit line VBLf2_RDD are the same.

[0044] In the data read operation, the switch circuit SWC selectively outputs the output signal from the sense amplifier SA_RDD in order to read data from the bit line VBL_RDD of the redundant cell RDD in place of the bit line VBL of the defective cell as described above.

[0045] When there is no defective cell in the bit line VBL to be read from each memory unit MU, the switch circuit SWC selects only the output signal from the sense amplifier SA of the memory unit MU and does not select the output signal of the sense amplifier SA_RDD of the redundant cell RDD.

[0046] In this way, the switch circuit SWC of the present embodiment switches the output signals of the sense amplifiers SA and SA_RDD for each bit line (local bit line) VBL. For example, in a read operation, when the addresses of the bit lines VBLf1 and VBLf2 of the defective cells MCf1 and MCf2 are specified, the switch circuit SWC selectively outputs the output signal of the sense amplifier SA_RDD of the redundant unit RDD instead of the bit lines VBLf1 and VBLf2. Thus, the data of the bit line VBLf1_RDD is output instead of the bit line VBLf1, and the data of the bit line VBLf2_RDD is output instead of the bit line VBLf2. When the addresses of the bit lines VBL other than the bit lines VBLf1 and VBLf2 are specified, the switch circuit SWC does not select the sense amplifier SA_RDD of the redundant unit RDD, but only selects the sense amplifier SA of the memory unit MU. A more detailed configuration of the switch circuit SWC will be described later.

[0047] The switch control circuit SSC stores the address of the defective cell in advance, and controls the switch circuit SWC based on the address specified in the read operation. That is, the switch control circuit SSC stores the address of the global bit line GBL and the address of the bit line (local bit line) VBL of the defective cell in advance, and outputs the control signal CNT_SW based on the address of the global bit line GBL and the address of the bit line VBL of the selected cell to be read. The more detailed structure of the switch control circuit SSC will be described later.

[0048] The controller CNT sends the row address RADD of the selected word line WL designated in the read operation to the switch control circuit SSC. The controller CNT may use, for example, a CPU (Central Processing Unit) and software, or a logic circuit such as a PLC (Programmable Logic Controller).

[0049] Figures 4 to 6: This is a conceptual diagram showing a configuration example and an operation example of a switch circuit SWC. n (n is an integer greater than or equal to 2) memory units MU1 to MUn are provided corresponding to one redundant unit RDD. In the case described above, the switch circuit SWC is provided with the same number of switch elements SW1 to SWn as the memory units MU1 to MUn or the corresponding sense amplifiers SA1 to SAn. The switch circuit SWC is provided corresponding to the memory units MU1 to MUn or the sense amplifiers SA1 to SAn. The switch element SWk (k = any integer from 1 to n-1) can be connected to two adjacent memory units MUk and MUk+1. The switch element SWn can be connected to the memory unit MUn and the redundant unit RDD. That is, the switch element SWn can perform switching between the sense amplifier SA_RDD of the redundant unit RDD and the sense amplifier SAn adjacent to the sense amplifier SA_RDD.

[0050] Figure 4 Indicates the state of the switch circuit SWC when there is no defective cell in the bit line VBL of the read target of each memory unit MU. In the above case, the switch elements SW1 to SWn are connected to the sense amplifiers SA of the memory units MU1 to MUn, respectively. That is, the switch elements SW1 to SWn are in the initial state, and the switch elements SW1 to SWn are not switched. Therefore, the switch circuit SWC selectively outputs the output signal from the sense amplifier SA of all memory units MU1 to MUn. The output signal of the sense amplifier SA_RDD of the redundant unit RDD is not selected.

[0051] Figure 5 Indicates the state of the switch circuit SWC when the bit line VBLf1 with the defective cell MCf1 is the object of reading. In the above case, in order to set the memory unit MU1 with the bit line VBLf1 as non-selected, the switch elements SW1~SWn are respectively switched to the sense amplifier SA of the memory units MU2~MUn and the redundant unit RDD. That is, the switch circuit SWC switches all the switch elements SW1~SWn from the switch element SW1 corresponding to the memory unit MU1 with the bit line VBLf1 and the sense amplifier SA1 to the switch element SWn corresponding to the sense amplifier SAn adjacent to the sense amplifier SA_RDD. As a result, the switch elements SW1~SWn are respectively switched to the sense amplifiers SA and SA_RDD connected to the memory units MU2~MUn and the redundant unit RDD. Therefore, the switch circuit SWC selectively outputs the output signals from the sense amplifiers SA of the memory units MU2~MUn and the SA_RDD of the redundant unit RDD. The signal from the sense amplifier SA1 of the memory unit MU1 is not output.

[0052] The switch element SWn outputs data from the bit line VBLf1_RDD of the redundant cell RDD. The memory cell MCf1_RDD of the bit line VBLf1_RDD stores data instead of the defective cell MCf1. Therefore, the switch element SWn can output data that should be stored in the defective cell MCf1.

[0053] Figure 6 Indicates the state of the switch circuit SWC when the bit line VBLf2 of the defective cell MCf2 is the read target. In the above case, in order to set the memory unit MU2 with the bit line VBLf2 as non-selected, the switch elements SW2 to SWn are switched to the memory units MU3 to MUn and the sense amplifier SA of the redundant unit RDD, respectively. That is, the switch circuit SWC switches all the switch elements SW2 to SWn from the switch element SW2 corresponding to the memory unit MU2 with the bit line VBLf2 and the sense amplifier SA2 to the switch element SWn corresponding to the sense amplifier SAn adjacent to the sense amplifier SA_RDD. On the other hand, the switch element SW1 is switched to Figure 4 Similarly, the switch element SW1 of the memory unit MU1 remains connected to the sense amplifier SA. Therefore, the switch circuit SWC selectively outputs output signals from the sense amplifiers SA of the memory units MU1, MU3 to MUn and the sense amplifier SA_RDD of the redundant unit RDD.

[0054] The switch element SWn outputs data from the bit line VBLf2_RDD of the redundant cell RDD. The memory cell MCf2_RDD of the bit line VBLf2_RDD stores data instead of the defective cell MCf2. Therefore, the switch element SWn can output data that should be stored in the defective cell MCf2.

[0055] Similarly, when there is a memory cell MUj (j=any integer from 1 to n) having a bit line VBL with a defective cell among the bit lines VBL to be read out of each memory cell MU1 to MUn, in order to set the bit line VBL of the memory cell MUj as non-selected, the switch elements SWj to SWn are switched to the sense amplifier SA of the memory cells MUj+1 to MUn and the redundant cell RDD, respectively. That is, the switch elements SWj to SWn switch all the switch elements SWj to SWn corresponding to the memory cell MUj with the bit line VBLj and the sense amplifier SAj to the switch element SWn corresponding to the sense amplifier SAn adjacent to the sense amplifier SA_RDD. On the other hand, the switch elements SW1 to SWj-1 are switched to the sense amplifier SA of the redundant cell RDD. Figure 4Similarly, the switch element SW1 of the memory unit MU1 to MUj-1 remains connected to the sense amplifiers SA1 to SAj-1. Thus, the switch circuit SWC selectively outputs the output signals from the sense amplifiers SA of the memory units MU1 to MUj-1, MUJ+1 to MUn, and SA_RDD of the redundant unit RDD. The signal from the sense amplifier SAj of the memory unit MUj is not output.

[0056] The switch element SWn outputs data from the redundant cell RDD. The selected memory cell of the redundant cell RDD stores data instead of the defective cell. Therefore, the switch element SWn can output data that should have been stored in the defective cell.

[0057] Figure 7 : is a circuit diagram showing an example of the configuration of the switching element SWj. The switching element SWj includes transistors TrL and TrR. One end of the transistor TrL is connected to the output of the sense amplifier SA of the memory unit MUj, and the other end is connected to the transistor TrR. The gate of the transistor TrL is connected to the switch control circuit SSC via the inverter INV, and receives the inversion signal of the control signal CNT_SW. One end of the transistor TrR is connected to the output of the sense amplifier SA of the memory unit MUj+1, and the other end is connected to the transistor TrL. The gate of the transistor TrR is connected to the switch control circuit SSC, and receives the control signal CNT_SW. Therefore, the transistor TrR becomes a non-conducting state (off state) when the transistor TrL is in the conducting state (on state), and becomes an on state when the transistor TrL is in the off state. That is, the transistors TrR and TrL complement each other to perform on / off operations.

[0058] The transistors TrL and TrR are connected in series between the outputs of two adjacent sense amplifiers SAj and SAj+1. Or, the transistors TrL and TrR are connected in series between the outputs of two adjacent sense amplifiers SAn and SA_RDD. The node between the transistor TrL and the transistor TrR connected in series becomes the output SWout. Therefore, when the transistor TrL is in the on state, the switch element SWj outputs the data from the memory unit MUj. When the transistor TrR is in the on state, the switch element SWj outputs the data from the memory unit MUj+1 or the redundant unit RDD. In this way, the switch element SWj outputs the data from any one of the sense amplifiers SAj of the memory unit MUj and the sense amplifiers SAj+1 of the memory unit MUj+1. Among them, the switch element SWn between the memory unit MUn and the redundant unit RDD is connected to the sense amplifier SAn of the memory unit MUn and the sense amplifier SA_RDD of the redundant unit RDD, and outputs the data from any one of the sense amplifiers SAn and SA_RDD.

[0059] The transistors TrL and TrR may be n-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistor). By setting the transistors TrL and TrR to MOSFETs of the same conductivity type, the design is easy. The transistor TrL may be formed of a p-type MOSFET. Thus, the switch element SW may be formed of a CMOS (Complementary Metal Oxide Semiconductor). In the above case, the inverter INV connected to the gate of the transistor TrL is omitted.

[0060] Figure 8 1 is a conceptual diagram showing a configuration example and an operation example of a switch control circuit SSC. The switch control circuit SSC includes a memory NVM, a multiplexer MUX, a decoder DC, a latch circuit LAT, a gate circuit GT, and a shift circuit SHC. The switch control circuit SSC can use, for example, a CPU and software, or a logic circuit such as a PLC.

[0061] The memory NVM stores the address information of the defective cell. The address information of the defective cell is, for example, the address ADD_GBLf of the global bit line GBL connected to the bit line VBL having the defective cell. The address information ADD_GBLf of the defective cell can store the addresses ADD_VBL (VBL0, VBL1, VBL2, ...) of the bit lines VBL one by one. The address ADD_VBL of the bit line VBL to be read out is specified by the row address RADD. Therefore, in the extension direction ( Figure 3 The plurality of bit lines VLB arranged in the X direction (in the X direction) are designated by the address ADD_VBL. For example, when the address ADD_VBL of the bit line VBL to be read is VBL0, the bit line VLB located at Figure 3 Any one of the bit lines VBL0 at the head of each memory unit MU and any one of the VBL_RDD0 at the head of the redundant unit RDD. Data from the multiple selected bit lines VBL0 and / or VBL_RDD0 selected by each of the multiple memory units MU are output from the global bit lines GBL of the corresponding columns at once. The address information ADD_GBLf of the defective cell is the address of the global bit line GBL connected to the bit line VBL having the defective cell among the multiple selected bit lines VBL0 specified by the address ADD_VBL of the bit line VBL.

[0062] When there are no defective cells in the bit lines VBLk (k is an integer) connected to the same word line WL (that is, designated by the same row address RADD), the address information ADD_GBLf may be arbitrary.

[0063] On the other hand, the memory NVM stores valid information Valid indicating whether there is a defective cell for each address ADD_VBL. In the address ADD_VBL with a defective cell, the valid information Valid is set to "1", and in the address ADD_VBL without a defective cell, the valid information Valid is set to "0". For example, when the address ADD_VBL is VBLk, since there is no defective cell, the valid information Valid becomes "0". In this case, as described above, the address information ADD_GBLf corresponding to the bit line VBLk can be arbitrary.

[0064] The memory NVM is, for example, a nonvolatile memory such as a fuse or a flash memory. The memory NVM may be provided in common with respect to the plurality of memory units MU and the redundant unit RDD.

[0065] The multiplexer MUX receives the row address RADD of the selected word line WL of the read object from the controller CNT. Based on the row address RADD of the selected word line WL, the multiplexer MUX selectively sends the address ADD_GBLf of the global bit line GBL corresponding to the address ADD_VBL of the bit line VBL of the read object to the decoder DC. In addition, the multiplexer MUX selectively sends the valid information Valid corresponding to the address ADD_VBL of the bit line VBL of the read object to the gate circuit GT.

[0066] For convenience, the switch circuit SWC is composed of 16 switch elements SW. Figure 8 As shown, the address ADD_GBLf can be expressed by 4-bit data. The sent address ADD_GBLf (4-bit data) indicates the position of the global bit line GBL connected to the bit line VBL0 including the defective cell among the multiple bit lines VBL0 specified by the row address RADD. For example, when the address of the selected bit line VBL is VBL0, the multiplexer MUX sends the address ADD_GBLf "0010" to the decoder DC. The address ADD_GBLf "0010" indicates, for example, that there is a defective cell in the bit line VBL0 connected to the global bit line GBL in the third column from the right among the global bit lines GBL.

[0067] The decoder DC decodes the address ADD_GBLf from the multiplexer MUX and sends it to the latch circuit LAT. For example, the decoder DC converts the 4-bit data "0010" of the address ADD_GBLf into 16-bit data. The 16-bit data is conversion data indicating the position of the switch element SWj corresponding to the global bit line GBL including the defective cell.

[0068] The latch circuit LAT latches the conversion data decoded by the decoder DC. For example, the latch circuit LAT latches 16-bit data as conversion data based on the 4-bit data "0010" of the address ADD_GBLf. Figure 8 The 16-bit data will be inverted to "1" at the third bit from the right, and the other bits will be "0". Therefore, it can be known that there is a defective cell in the bit line VBL0 connected to the third column of global bit lines GBL from the right among the global bit lines GBL. The latch circuit LAT is, for example, a volatile memory such as an SRAM (Static Random Access Memory) or a flip-flop.

[0069] Based on the valid information Valid, the gate circuit GT effectively sends the conversion data (16-bit data) latched in the latch circuit LAT to the shift circuit SHC, or sets the conversion data latched in the latch circuit LAT to be invalid and not sent to the shift circuit SHC. For example, when the valid information Valid is "1", the gate circuit GT effectively sends the conversion data latched in the latch circuit LAT to the shift circuit SHC. On the other hand, when the valid information Valid is "0", the gate circuit GT sets the conversion data latched in the latch circuit LAT to be invalid and not sent to the shift circuit SHC. The case where the valid information Valid is "0" will be described later.

[0070] Fig. 9 : is a block diagram showing an example of the configuration of a gate circuit. The gate circuit GT includes an AND circuit Ga corresponding to each bit of the conversion data. For example, when the conversion data is 16-bit data, the gate circuit GT includes 16 AND circuits Ga. One input terminal of the AND circuit Ga inputs the corresponding bit of the conversion data. The other input terminal of the AND circuit Ga commonly inputs the valid information Valid. Thus, when the valid information Valid is "1", the AND circuit Ga effectively outputs the conversion data (16-bit data). On the other hand, when the valid information Valid is "0", the AND circuit Ga sets the conversion data to invalid and does not output it. In addition, the configuration of the gate circuit GT is not limited to this.

[0071] The shift circuit SHC converts the conversion data sent from the gate circuit GT into the control signal CNT_SW of the transistors TrL and TrR of the switch element SW. Figure 8Among the 16-bit data of the conversion data, only the third bit from the right is inverted to "1". In the above case, the shift circuit SHC sets the control signal CNT_SW of the transistor TrR to the same 16-bit data as the conversion data, and generates a control signal CNT_SW in which the bits from the right end to the third bit are "1" and the other bits are "0". In the above case, in the switch element SWj, a signal that becomes the inversion signal of the control signal CNT_SW input to the gate of the transistor TrR is input to the gate of the transistor TrL. That is, the control signal input to the gate of the transistor TrL is "0" from the right end to the third bit, and the other bits become "1". The shift circuit SHC sends the control signal CNT_SW to the switch circuit SWC.

[0072] Fig.10 This is a block diagram showing an example of the configuration of a shift circuit. The shift circuit SHC includes an OR circuit Gor corresponding to each bit of conversion data. For example, when the conversion data is 16-bit data, the shift circuit SHC includes 16 OR circuits Gor. One input terminal of the OR circuit Gor inputs the corresponding bit of the conversion data. The other input terminal of the OR circuit Gor inputs 0 or the output of the OR circuit Gor in the adjacent previous column. Thus, all the OR circuits Gor from the OR circuit Gor of the first column to which 0 is input at the other input terminal to the OR circuit Gor to which "0" of the conversion data is input output "0". All the OR circuits Gor of the column after the OR circuit Gor to which "1" of the conversion data is input output "1". Thus, the shift circuit SHC converts the conversion data from the gate circuit GT into the control signal CNT_SW of the transistor TrR. The control signal CNT_SW of the transistor TrL can be obtained by inverting the logic of the control signal CNT_SW of the transistor TrR by an inverter or the like. In addition, in Fig.10 In FIG. 1 , the output signal from the OR circuit Gor is output to the switch circuit SWC side via the buffer, but the buffer can be omitted.

[0073] When all bits of the conversion data are “0” (that is, when there is no defective cell), all control signals CNT_SW of the transistor TrR become “0”, and all signals input to the gate of the transistor TrL become “1”.

[0074] In addition, for example, when the control signal CNT_SW of the transistor TrR is "1" from the right end to the third bit and the other bits are "0", the switch circuit SWC turns on the transistor TrR from the right end to the third bit and turns off the other transistors TrR. On the other hand, because the control signal input to the gate of the transistor TrL is "0" from the right end to the third bit and the other bits are "1", the switch circuit SWC turns off the transistor TrL from the right end to the third bit and turns on the other transistors TrL. As a result, the switch circuit SWC does not output data from the sense amplifier SA in the third column from the right. That is, the switch circuit SWC does not output data from the bit line VBL0 and the global bit line GBL with a defective cell, but outputs data from the sense amplifier SA_RDD of the redundant cell RDD instead.

[0075] Similarly, when the address ADD_VBL of the selected bit line VBL designated by the row address RADD is VBL1, the multiplexer MUX sends the address ADD_GBLf "1010" to the decoder DC. The address ADD_GBLf "1010" indicates, for example, that there is a defective cell in the bit line VBL1 connected to the global bit line GBL in the 11th column from the right.

[0076] When the decoder DC decodes the address ADD_GBLf "1010", the 16-bit data becomes "0000010000000000".

[0077] When the address ADD_VBL is VBL1, since the valid information Valid is "1", the gate circuit GT effectively transmits the conversion data latched in the latch circuit LAT to the shift circuit SHC.

[0078] When the shift circuit SHC changes the 16-bit data, the control signal CNT_SW of the transistor TrR becomes "0000011111111111". The control signal input to the gate of the transistor TrL becomes "11111000000000000".

[0079] As a result, the switch circuit SWC turns on the transistors TrR from the right end to the 11th one, and turns off the other transistors TrR. On the other hand, the switch circuit SWC turns off the transistors TrL from the right end to the 11th one, and turns on the other transistors TrL. As a result, the switch circuit SWC does not output data from the sense amplifier SA in the 11th column from the right. That is, the switch circuit SWC does not output data from the bit line VBL1 and the global bit line GBL with a defective cell, but outputs data from the sense amplifier SA_RDD of the redundant cell RDD instead.

[0080] Similarly, when the address of the selected bit line VBL designated by the row address RADD is VBL2, the switch control circuit SSC sends the address ADD_GBLf "1000" to the multiplexer MUX. The address ADD_GBLf "1000" indicates, for example, that there is a defective cell in the bit line VBL2 connected to the global bit line GBL in the ninth column from the right.

[0081] When the latch circuit LAT decodes the address ADD_GBLf “1000”, 16-bit data becomes “0000000100000000”.

[0082] When the address ADD_VBL is VBL2, since the valid information Valid is "1", the gate circuit GT effectively transmits the conversion data latched in the latch circuit LAT to the shift circuit SHC.

[0083] When the shift circuit SHC changes the 16-bit data, the control signal CNT_SW of the transistor TrR becomes "0000000111111111". The control signal input to the gate of the transistor TrL becomes "1111111000000000".

[0084] Thus, the switch circuit SWC turns on the transistors TrR from the right end to the 9th one and turns off the other transistors TrR. On the other hand, the switch circuit SWC turns off the transistors TrL from the right end to the 9th one and turns on the other transistors TrL. Thus, the switch circuit SWC does not output data from the sense amplifier SA in the 9th column from the right. That is, the switch circuit SWC does not output data from the bit line VBL2 and the global bit line GBL with a defective cell, but outputs data from the sense amplifier SA_RDD of the redundant cell RDD instead.

[0085] When the address ADD_VBL of the selection bit line VBL specified by the row address RADD is VBLk, the switch control circuit SSC sends an arbitrary address ADD_GBLf "****" to the multiplexer MUX. The arbitrary address ADD_GBLf "****" is decoded in the decoder DC via the multiplexer MUX and latched by the latch circuit LAT. However, since the valid information Valid is "0", the gate circuit GT sets all bits of the conversion data to 0 regardless of the address ADD_GBLf. In the case, the shift circuit SHC sets all bits of the control signal CNT_SW of the transistor TrR to "0". In the case, in the switch element SWj, the control signal input to the gate of the transistor TrL is set to the inversion signal of the control signal CNT_SW to the transistor TrR. That is, all bits of the control signal CNT_SW of the transistor TrL become "1".

[0086] Thus, the switch circuit SWC turns on the transistors TrL of all the columns. Thus, the switch circuit SWC outputs data from the sense amplifiers SA of all the columns, and does not output data from the sense amplifier SA_RDD of the redundant cell RDD.

[0087] In addition, the configuration of the shift circuit SHC is not limited to this.

[0088] In this way, the semiconductor memory device 1 of the present embodiment specifies the global bit line GBL connected to the local bit line VBL with a defective cell based on the row address RADD that specifies the local bit line VBL in the read operation of the memory cell array MCA having the hierarchical bit line structure. The switch circuit SWC selects the redundant cell RDD instead of the global bit line GBL connected to the local bit line VBL with the defective cell. Thus, in the read operation, the switch circuit SWC is switched for each local bit line VBL specified by the row address RADD, and the global bit line GBL_RDD of the redundant cell RDD can be selected instead of the global bit line GBL connected to the local bit line VBL with the defective cell. As a result, even if a plurality of defective cells exist across a plurality of local bit lines VBL, as long as the row address RADD is different, the redundant cell RDD can be used to remedy the situation.

[0089] When the switch circuit SWC is fixed by a fuse or the like, the redundant cell RDD can repair a defective cell located on one global bit line GBL, but cannot repair a defective cell located on another global bit line GBL. In addition, since the normal local bit line VBL that shares the defective cell with the global bit line GBL cannot be used, it is relatively wasteful.

[0090] In contrast, the switch circuit SWC of the present embodiment switches the switch element SW according to the local bit line VBL specified by the row address RADD. Therefore, in the present embodiment, even if a plurality of defective cells span a plurality of global bit lines GBL or a plurality of local bit lines VBL, they can be remedied with the redundant cell RDD as long as the row address RADD is different. In addition, the normal local bit line VBL that shares the local bit line VBL with the defective cell and the global bit line GBL can be used without waste.

[0091] However, when there are multiple defective cells in multiple bit lines VBL0 of the same row address sharing a word line, the redundant array RDD cannot be used to remedy the situation. Figure 3 , Fig.12 or Fig.13 In the Y direction, a redundant array, redundant word line, and redundant bit line VBL (not shown) are added, and the row address of the redundant word line is specified instead of the row address of the bit line VBL0. Thus, even if there are multiple defective cells in multiple bit lines VBL0 of the same row address, the multiple defective cells can be repaired.

[0092] In addition, the gate circuit GT may be provided between the decoder DC and the latch circuit LAT. When the gate circuit GT is located between the decoder DC and the latch circuit LAT, the gate circuit GT directly transmits the data from the decoder DC to the latch circuit LAT when the valid information Valid is "1". When the valid information Valid is "0", the gate circuit GT does not transmit the data from the decoder DC to the latch circuit LAT. Even with this configuration, the effect of this embodiment is not lost.

[0093] (Second embodiment)

[0094] Fig.11 1 is a conceptual diagram showing a configuration example and an operation example of a switch control circuit SSC according to the second embodiment. In the second embodiment, the switch control circuit SSC decodes the address ADD_GBLf of the global bit line GBL and the address ADD_VBL of the bit line VBL of the defective cell in advance and stores them in the latch circuit LAT in advance. In addition, the valid information Valid is also stored in advance in another latch circuit not shown in the figure.

[0095] The multiplexer MUX transmits the address ADD_GBLf of the global bit line GBL connected to the bit line VBL to be read from the latch circuit LAT to the gate circuit GT based on the row address RADD. The gate circuit GT transmits the conversion data latched in the latch circuit LAT to the shift circuit SHC effectively, or sets the conversion data latched in the latch circuit LAT to be invalid and not to be transmitted to the shift circuit SHC based on the valid information Valid of the corresponding row address RADD.

[0096] In this way, the multiplexer MUX can selectively output the address ADD_GBLf of the global bit line GBL connected to the local bit line VBL having the defective cell from the latch circuit LAT.

[0097] In the above case, the multiplexer MUX is disposed between the latch circuit LAT and the gate circuit GT. The gate circuit GT is disposed between the multiplexer MUX and the shift circuit SHC.

[0098] The other configurations and operations of the second embodiment may be the same as the corresponding configurations and operations of the first embodiment. Thus, the second embodiment can obtain the same effects as the first embodiment.

[0099] (Configuration of Bit Line VBL)

[0100] Fig.12 It is a schematic plan view showing an example of the arrangement of the bit lines VBL. Fig.12 1 shows a top view viewed from the Z direction. In the example, the bit line VBL is intermittently arranged at the intersection of the word line WL and the global bit line GBL. For example, the bit line VBL is arranged at every other intersection along the word line WL in the X direction, and is arranged at every other intersection along the global bit line GBL in the Y direction.

[0101] In the above case, the two input terminals of the sense amplifier SA are respectively connected to two adjacent global bit line GBL pairs electrically connected to one memory cell array. The bit line VBL connected to one word line WL selected by the row address is connected to only one of the adjacent global bit line GBL pairs. The other of the global bit line GBL pair is not connected to the bit line VBL, but transmits a reference signal. The sense amplifier SA_RDD also has the same connection configuration.

[0102] In this way, the sense amplifiers SA and SA_RDD can be connected to a pair of global bit lines GBL electrically connected to one memory cell array. This bit line structure is also called a so-called folded bit line structure.

[0103] Fig.13 FIG. 1 is a schematic plan view showing another configuration example of the bit lines VBL. Fig.131 shows a top view viewed from the Z direction. In the example, the bit line VBL is arranged at each of the intersections of the word line WL and the global bit line GBL. For example, the bit line VBL is arranged at each of the intersections arranged along the word line WL in the X direction, and is arranged at each of the intersections arranged along the global bit line GBL in the Y direction.

[0104] In the above case, the two input terminals of the sense amplifier SA are connected to two global bit line GBL pairs electrically connected to two memory cell arrays located on both sides thereof. The bit line VBL connected to one word line WL selected by the row address is connected to one of the global bit line GBL pairs. The other of the global bit line GBL pair is not connected to the bit line VBL, but transmits a reference signal. The sense amplifier SA_RDD also has the same connection configuration.

[0105] In this way, the sense amplifiers SA and SA_RDD can be connected to a pair of global bit lines GBL electrically connected to two memory cell arrays. This bit line configuration is also called an open type bit line configuration.

[0106] The bit line structure of the above-described embodiment may be either a folded bit line structure or an open bit line structure.

[0107] Although several embodiments of the present invention have been described, the embodiments are provided as examples and are not intended to limit the scope of the invention. The embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The embodiments or their variations are included in the scope or spirit of the invention, and are also included in the invention described in the claims and their equivalents.

[0108] [Explanation of Symbols]

[0109] 1: Semiconductor storage device

[0110] MCA: Memory Cell Array

[0111] WL: Word Line

[0112] VBL: Bit Line

[0113] GBL: Global Bit Line

[0114] SA: Sense Amplifier

[0115] MU: Memory Unit

[0116] RDD: Redundant Unit

[0117] SWC: Switching Circuit

[0118] SSC: Switch Control Circuit

[0119] CNT:Controller

[0120] SW: Switching element

[0121] TrL,TrR:Transistor

[0122] NVM: Memory

[0123] DC:Decoder

[0124] MUX: Multiplexer

[0125] GT: Gate circuit

[0126] LAT: Latch circuit

[0127] SHC: shift circuit.

Claims

1. A semiconductor storage device comprising: A cell array comprising a plurality of memory cells; a plurality of first wirings, in the cell array, commonly connected to the plurality of memory cells arranged in a first direction; a plurality of second wirings, in the cell array, commonly connected to the plurality of memory cells arranged in a second direction intersecting with the first direction; a plurality of third wirings provided corresponding to each of the plurality of second wirings arranged in a third direction intersecting the first and second directions; a first sensing circuit connected to a first pair of the two third wirings; a second sensing circuit connected to the second pair of the other two third wirings; A switch circuit connected to the first and second sensing circuits, selectively outputting an output signal of either the first or second sensing circuit; and The switch control circuit stores the addresses of the second and third wirings connected to the defective cell, and outputs a control signal for controlling the switch circuit based on the addresses of the second and third wirings connected to the selected cell to be read.

2. The semiconductor memory device according to claim 1, wherein a plurality of the first sensing circuits are provided. The switch circuit includes a plurality of switch elements provided corresponding to the plurality of first sensing circuits, the switch element corresponding to the first sensing circuit adjacent to the second sensing circuit being capable of switching between the first sensing circuit and the second sensing circuit, and The switch control circuit generates conversion data representing the switch element corresponding to the first sensing circuit connected to the third wiring connected to the defective cell from the addresses of the second wiring and the third wiring connected to the defective cell, and switches the switch element from the switch element represented by the conversion data to the switch element corresponding to the first sensing circuit adjacent to the second sensing circuit.

3. The semiconductor memory device according to claim 2, wherein the control signal is generated based on the conversion data, includes bits corresponding to the plurality of switch elements, and is a control signal for inverting bits corresponding to the switched switch elements among the plurality of switch elements relative to other bits.

4. The semiconductor memory device according to claim 2 or 3, wherein the switch control circuit does not switch the plurality of switch elements of the switch circuit when the address corresponding to the second wiring connected to the selected cell is an address without the defective cell.

5. The semiconductor memory device according to claim 2, wherein the switch control circuit comprises: a memory storing addresses of the second wiring and the third wiring connected to the defective cell; a multiplexer that selectively outputs the address of the third wiring corresponding to the second wiring connected to the selected cell from the memory based on the address of the first wiring connected to the selected cell; a decoder that converts the address of the third wiring from the multiplexer into the conversion data; A latch circuit for latching the conversion data; and The shift circuit generates the control signal indicating switching of the switch element from the switch element indicated by the conversion data to the switch element corresponding to the first sensing circuit adjacent to the second sensing circuit.

6. The semiconductor memory device according to claim 2, wherein the switch control circuit comprises: a memory storing addresses of the second wiring and the third wiring connected to the defective cell; a decoder that converts the address of the third wiring of the memory into the conversion data; A latch circuit for latching the conversion data; a multiplexer that selectively outputs the conversion data corresponding to the second wiring connected to the selected cell from the latch circuit based on the address of the first wiring connected to the selected cell; and The shift circuit generates the control signal indicating switching of the switch element from the switch element indicated by the conversion data from the multiplexer to the switch element corresponding to the first sensing circuit adjacent to the second sensing circuit.

7. The semiconductor storage device according to claim 5 or 6, wherein the memory further stores valid information indicating whether or not the defective cell exists for each address of the second wiring, and the semiconductor storage device further comprises: A gate circuit that sends or does not send the conversion data to the shift circuit based on the valid information. 8 . The semiconductor memory device according to claim 2 , wherein the switch element outputs data from either one of the two adjacent first sensing circuits or data from either one of the adjacent first sensing circuit and the second sensing circuit.

9. A semiconductor memory device according to claim 8, wherein the switching element includes two transistors connected in series between two adjacent first sensing circuits or between the first sensing circuit and the second sensing circuit, which operate complementarily to each other and output data from a node between the two transistors. 10 . The semiconductor memory device according to claim 1 , wherein the cell array includes the plurality of memory cells three-dimensionally arranged along the first to third wirings.

11. The semiconductor memory device according to claim 1 or 2, wherein the memory cell comprises: a first transistor having a gate connected to the first wiring, and one of a source and a drain connected to the second wiring (VBL); and a first capacitor connected to the other of the source and the drain of the first transistor.

12. The semiconductor memory device according to claim 1 or 2, wherein one of the third wiring pairs connected to the first and second sensing circuits transmits data in a read operation, and the other transmits a reference signal for detecting logic of the data.

13. The semiconductor memory device according to claim 1 or 2, wherein the two third wirings of the first pair are electrically connected to the same cell array, The two third wirings of the second pair are electrically connected to the same cell array.

14. The semiconductor memory device according to claim 1 or 2, wherein the two third wirings of the first pair are electrically connected to each of the two cell arrays, and The two third wirings of the second pair are electrically connected to each of the two cell arrays.

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