Method for creating ohmic contact on high-power electrical diode

Abstract

The invention relates to a method for creating an ohmic contact on a high-power electrical diode. A method for forming an ohmic contact on a semiconductor component, such as a high-power electrical diode, is provided. An example method includes depositing a first metal layer on a top surface of a semiconductor drift layer having an electrical contact, the first metal layer having a high reflectivity to laser light. The method further includes depositing a second metal layer on a portion of the first metal layer aligned with the electrical contact, the second metal selected to absorb the laser light. The method further includes exposing the first metal layer and the second metal layer to a laser during a laser annealing process, resulting in a significant increase in temperature of the second metal layer due to the laser. An increase in temperature of the second metal layer results in an ohmic contact being formed between the electrical contact and the first metal layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to creating ohmic contacts on high power electrical diodes, and more particularly to creating ohmic contacts electrically connected to implanted regions of merged-PN Schottky (MPS) diodes. Background Art

[0002] Many semiconductor components, such as MOSFETs, diodes, Schottky devices and other transistors, require contact to be formed between the semiconductor component and the metal. In order to improve the efficiency of the semiconductor component, the most commonly formed is an ohmic contact. An ohmic contact refers to an electrical contact that has low resistance between the metal and the semiconductor material and exhibits linear behavior over a wide range of voltage and current. The ohmic contact allows efficient transmission of current between the metal and the semiconductor component.

[0003] One specific application utilizing ohmic contacts is the merged PN Schottky (MPS) diode. Applicants have discovered many technical challenges and difficulties associated with forming ohmic contacts between semiconductors and metals. Through dedicated effort, ingenuity, and innovation, Applicants have solved the problems involved in forming ohmic contacts on high power electrical diodes, which are described in detail below. Summary of the invention

[0004] Various embodiments relate to example methods for forming an ohmic contact on a semiconductor component, such as a high power electrical diode. According to some embodiments of the present disclosure, an example method is provided. In some embodiments, the example method includes depositing a first metal layer on a top surface of a semiconductor drift layer including an electrical contact, wherein the first metal layer reflects laser light. The method also includes depositing a second metal layer on a portion of the first metal layer, wherein the second metal layer is aligned with the electrical contact, and wherein the second metal layer absorbs the laser light. The method also includes exposing the first metal layer and the second metal layer to a laser during a laser annealing process, wherein the temperature of the second metal layer is significantly increased due to the laser light. In some embodiments, the increase in temperature causes an ohmic contact to be formed between the electrical contact and the first metal layer.

[0005] In some embodiments, the semiconductor component is a merged PN Schottky diode.

[0006] In some embodiments, the electrical contact is an implant well in the top surface of the semiconductor drift layer.

[0007] In some embodiments, a portion of the second metal layer is positioned on a top surface of the first metal layer directly opposite the implantation well.

[0008] In some embodiments, a first reflectivity of the first metal layer is greater than a second reflectivity of the second metal layer.

[0009] In some embodiments, the implantation well comprises a p-type semiconductor, and the semiconductor drift layer comprises an n-type semiconductor.

[0010] In some embodiments, the ohmic contact makes electrical contact with the implant well.

[0011] In some embodiments, the method may further include removing the second metal layer, and depositing a front side metal on the ohmic contact.

[0012] In some embodiments, the front side metal is the anode of the semiconductor component.

[0013] In some embodiments, the method may further include removing the front side metal from all areas except for areas of the semiconductor component on and immediately adjacent to the ohmic contact.

[0014] In some embodiments, the method may further include depositing a passivation layer on and around the front side metal; and etching an access via through the passivation layer to the front side metal.

[0015] In some embodiments, the method may further include depositing a dielectric layer on the ohmic contact and the top surface of the semiconductor drift layer, removing the dielectric layer directly above the top surface of the semiconductor drift layer of the semiconductor component so that the ohmic contact is exposed, and depositing a front side metal on the ohmic contact and the dielectric layer.

[0016] In some embodiments, the method may further include removing the front side metal from all areas except for areas of the semiconductor component on and immediately adjacent to the ohmic contact.

[0017] In some embodiments, the method may further include depositing a passivation layer on the surface and adjacent to the front side metal, and etching an access via through the passivation layer to the front side metal.

[0018] In some embodiments, the method may further include creating a back ohmic contact on a surface opposite the passivation layer, wherein the back metal is in electrical contact with the back ohmic contact.

[0019] In some embodiments, the backside ohmic contact is the cathode of the semiconductor component.

[0020] In some embodiments, the semiconductor drift layer is formed by an epitaxial growth process on a semiconductor substrate.

[0021] In some embodiments, both the semiconductor substrate and the semiconductor drift layer include silicon carbide.

[0022] In some embodiments, the first metal layer includes aluminum.

[0023] In some embodiments, the second metal layer includes titanium. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Reference will now be made to the drawings. The components illustrated in the drawings may or may not be present in certain embodiments described herein. According to example embodiments of the present disclosure, some embodiments may include fewer (or more) components than those shown in the drawings.

[0025] Figure 1A-1G An exemplary conventional process for creating ohmic contacts on semiconductor components is illustrated.

[0026] Figure 2 A cross-sectional view of an example Merged PN Schottky (MPS) diode is illustrated in accordance with one or more embodiments of the present disclosure.

[0027] Figure 3 A flow chart illustrating an example process for forming an ohmic contact on an electrical diode in accordance with one or more embodiments of the present disclosure is shown.

[0028] Figure 4 A flow chart illustrating an example process for forming an ohmic contact on an electrical diode having a field plate edge termination according to one or more embodiments of the present disclosure is shown.

[0029] Figure 5A-5U A cross-sectional view is shown of an example process for fabricating an MPS diode having a field plate edge termination formed with one or more ohmic contacts, in accordance with one or more embodiments of the present disclosure.

[0030] Figure 6 A flow chart illustrating an example process for forming an ohmic contact on an electrical diode without a field plate edge termination according to one or more embodiments of the present disclosure is shown.

[0031] Figure 7A-7R A cross-sectional view is shown of an example process for fabricating an MPS diode formed with one or more ohmic contacts without field plate edge termination in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] Example embodiments will be described more fully below with reference to the accompanying drawings, in which some but not all embodiments of the invention of the present disclosure are shown. Indeed, embodiments of the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0033] As used herein, and in the examples provided below, terms such as "front," "rear," "back," "top," "vertical," "horizontal," "above," "below," "over," "below," and the like are used for explanation purposes to describe the relative position of certain components or component portions relative to a local reference system of an electrical diode using an arbitrary global reference system.

[0034] In some examples, a Cartesian (three-axis) reference system is provided. Unless otherwise specified, generally speaking, a positive y direction corresponds to "up," "above," or "on top." Conversely, a negative y direction corresponds to "down," "below," "under," or "below."

[0035] Various example embodiments address technical issues associated with forming ohmic contacts on electrical components. As will be appreciated by those skilled in the art to which the present disclosure pertains, there are numerous example scenarios in which ohmic contacts may be formed on electrical components.

[0036] For example, many semiconductor components (such as MOSFET, power diodes, Schottky diodes and other transistors) require contact between the semiconductor component and the metal. In order to improve the efficiency of the component, the most common contact is formed by ohmic contact. Ohmic contact refers to an electrical contact with low resistance between metal and semiconductor material and exhibits linear behavior over a wide range of voltage and current. Ohmic contact allows efficient transmission of current between metal and semiconductor components.

[0037] One specific application utilizing ohmic contacts is the merged PN Schottky (MPS) diode. The MPS diode includes one or more isolated implant regions (or doped wells) implanted in the drift layer of the Schottky device. In general, the conductivity type (e.g., p-type) of the implant region is different from the conductivity type (e.g., n-type) of the drift layer of the MPS diode. The implant region produces a PN junction dispersed within the Schottky diode. The result is that the diode has the advantages of both a Schottky diode and a PN junction diode. Some of these advantages may include lower leakage current, improved surge current capability at high power, and improved performance at high frequencies. In order to improve performance, an ohmic contact can be formed at the junction of the front side contact metal and each doped well of the MPS diode. The placement and efficiency of these ohmic contacts play an important role in the overall efficiency of the semiconductor component.

[0038] Reference now Figure 1A-1G , shows an example conventional process 100 for creating an ohmic contact. Figure 1AAs shown, an example conventional process 100 includes disposing a dielectric 106 on a top surface of a drift layer 102 of a semiconductor component 116 , wherein the drift layer 102 includes a plurality of electrical contacts 104 (eg, doped wells of an MPS diode) to which electrical connections may be formed.

[0039] like Figure 1B As shown, mask 108 is disposed on the top surface of dielectric 106 and aligned with underlying electrical contacts 104 of semiconductor component 116. Aligning mask 108 enables removal of dielectric 106 directly above electrical contacts 104 of semiconductor component 116, as shown in FIG. Figure 1C shown.

[0040] like Figure 1D As shown, additional layers of dielectric 106 material are placed on the surface of semiconductor component 116 such that a thin layer of dielectric covers exposed portions of drift layer 102 and covers electrical contacts 104 defining semiconductor component 116 , while a thicker layer of dielectric 106 covers the surrounding surface.

[0041] like Figure 1E As shown, a mask 110 is deposited on the surface of dielectric 106, wherein the openings in mask 110 are aligned with electrical contacts 104 beneath the layer of dielectric 106. Mask 110 enables dielectric 106 to be etched so that electrical contacts 104 are exposed.

[0042] like Figure 1F As shown, the mask 110 is removed and a contact metal 112 (e.g., nickel) is deposited on the entire surface of the dielectric 106, and an annealing process is performed to create an ohmic contact. The annealing process generally includes heating the semiconductor component 116 to an annealing temperature at or above 1000° C. Heating the semiconductor component 116 to a high annealing temperature is necessary to initiate a reaction between the contact metal 112 and the electrical contact 104. Heating the semiconductor component 116 to the annealing temperature can promote the formation of silicide between the doped silicon electrical contact 104 and the contact metal 112 at the electrical contact 104. However, the high annealing temperature may cause the contact metal 112 to react with other portions of the semiconductor component 116, making it difficult to remove the contact metal 112, or even damaging the underlying layer of the semiconductor component 116.

[0043] like Figure 1G As shown, the contact metal 112 is removed from the semiconductor component 116 everywhere except directly above the electrical contact 104. Figure 1GAs further shown in FIG. 1 , the formation of the silicide has produced an ohmic contact 114 in electrical contact with each electrical contact point 104. Removing the contact metal 112 from the surface of the semiconductor component 116 can be particularly complicated. In addition, the removal of the contact metal 112 can negatively affect the base layer of the semiconductor component 116.

[0044] like Figure 1A-1G The conventional process 100 shown may have many disadvantages. For example, the formation of ohmic contacts requires an annealing temperature at or above 1000° C. Such high temperatures may damage the base structure of the semiconductor component. In addition, the metal layer (e.g., nickel) used to react with the electrical contacts and promote the growth of silicide must be removed from each place that is not in direct contact with the electrical contacts. The process for removing the metal layer may be complicated. In addition, these reactions may extend beyond the limits of the electrical contacts and enter other areas of the semiconductor component. The extension of the ohmic contact into the semiconductor component may have a negative impact on the performance of the semiconductor component. As the feature size of the semiconductor component continues to shrink, this extension of the ohmic contact becomes even more problematic.

[0045] Various example embodiments described herein utilize various techniques to create an ohmic contact to a semiconductor component, such as an MPS diode. For example, in some embodiments, a first metal is deposited on a surface of a semiconductor component having one or more electrical contacts. The first metal may be selected based on its ability to reflect light emitted from a laser. Generally speaking, the more reflective the first metal is, the less the first metal will heat up when encountering the laser.

[0046] A second metal may also be deposited on the surface of the first metal. In some embodiments, the second metal may be patterned based on the desired location of the ohmic contact. For example, the second metal may be placed at a position aligned with the electrical contact below. The second metal may be selected based on the absorption characteristics of the second metal. Generally speaking, the more light from the laser is absorbed by the second metal, the hotter the second metal will become. By strategically patterning the second metal only at the desired location of the ohmic contact, the second metal and the portion of the first metal below will significantly increase the temperature only at the desired location of the ohmic contact. The local increase in temperature may promote the reaction between the second metal, the first metal, and the semiconductor contact below, thereby forming a silicide at the contact point and creating an ohmic contact to the electrical contact below.

[0047] As an effect of the example embodiments described herein, and in some examples, the complexity of ohmic contact formation (particularly on MPS diodes) can be significantly reduced. In addition, the example embodiments described herein can limit the extension of the ohmic contact outside the desired electrical contact point. Limiting the extension of the ohmic contact can result in higher performance of the semiconductor component. In addition, limiting the extension of the ohmic contact can enable the ohmic contact to be formed on a semiconductor component having electrical contacts that are smaller in size and separated by a smaller distance.

[0048] Reference now Figure 2 , an example merged PN Schottky (MPS) diode 200 is provided. Figure 2 As shown, the exemplary MPS diode 200 includes a substrate 220 having a top surface 220a and a bottom surface 220b opposite the top surface 220a. Figure 2 As further shown in , the example MPS diode 200 includes a semiconductor drift layer 224 on a top surface 220 a of a substrate 220 , the semiconductor drift layer 224 also including a top surface 224 a opposite to the substrate 220 . Figure 2 The MPS diode 200 further includes an anode terminal 226 disposed on the top surface 224 a of the semiconductor drift layer 224 , the anode terminal 226 and the top surface 224 a of the semiconductor drift layer 224 forming a Schottky diode 234 . Figure 2 As further shown in FIG. 2 , the MPS diode 200 includes a plurality of junction barrier elements 228 at the junction of the top surface 224a of the semiconductor drift layer 224 and the anode terminal 226. Each junction barrier element 228 includes an implantation well 230 implanted in the top surface 224a of the semiconductor drift layer 224 and an ohmic contact 232, forming an electrical connection between the anode terminal 226 and the implantation well 230. The illustrated MPS diode 200 also includes a cathode terminal 222 adjacent to the bottom surface 220b of the substrate 220, opposite the semiconductor drift layer 224.

[0049] like Figure 2 As shown, the example MPS diode 200 includes a substrate 220. The substrate (e.g., wafer) 220 can be any semiconductor material that serves as a base layer for a semiconductor component (e.g., MPS diode 200). The substrate 220 can include silicon, germanium, gallium arsenide, gallium nitride, silicon carbide (SiC), or other similar semiconductor materials. The substrate 220 can serve as a base layer for epitaxial growth of additional semiconductor materials. Epitaxial growth can be used to grow additional crystalline layers, such as a semiconductor drift layer 224, on the substrate 220.

[0050] In some embodiments, substrate 220 may include SiC. SiC may provide a number of advantages in high power applications. For example, SiC-based semiconductor components may dissipate heat more efficiently, be more tolerant to higher frequencies, have low reverse leakage current and power dissipation, be more stable over a wide temperature range, have lower electromagnetic radiation, and may provide other related advantages.

[0051] In some embodiments, substrate 220 may be doped with a first dopant type to create a semiconductor having a particular conductivity type. A dopant may be any impurity intentionally added to a semiconductor to change the conductivity of the semiconductor. Adding a dopant with excess valence electrons to substrate 220 creates a semiconductor having n-type doping or an n-doped semiconductor. Dopants with excess valence electrons may include phosphorus, arsenic, antimony, etc. Adding a dopant lacking valence electrons to substrate 220 creates a semiconductor having p-type doping or a p-doped semiconductor. Dopants lacking valence electrons may include boron, aluminum, gallium, etc. As Figure 2 As shown, the substrate 220 of the example MPS diode 200 is an n-type semiconductor substrate 220 .

[0052] In some embodiments, the substrate 220 may include a doping concentration. The doping concentration may indicate the amount of impurities introduced into the structure of the semiconductor substrate 220 relative to the amount of intrinsic semiconductor atoms. A high doping concentration means that a greater amount of impurities are introduced into the semiconductor substrate 220 relative to the amount of intrinsic semiconductor atoms. In some embodiments, the doping concentration of the substrate 220 may be higher than the doping concentration of the semiconductor drift layer 224.

[0053] like Figure 2 As further shown in , the example MPS diode 200 includes a semiconductor drift layer 224. The semiconductor drift layer 224 can be any semiconductor material configured to enable current to flow from the anode terminal 226 to the cathode terminal 222 due to drift of majority carriers. When the barrier voltage of the MPS diode 200 is exceeded, the semiconductor drift layer 224 enables current to flow from the anode terminal 226 to the cathode terminal 222. In addition, the semiconductor drift layer prevents or limits current from flowing in the opposite direction (e.g., from the cathode terminal 222 to the anode terminal). As shown in FIG. Figure 2 As shown, the semiconductor drift layer 224 has the same dopant type as the substrate 220, for example, an n-type semiconductor. Figure 2 As further shown in FIG. 2 , the semiconductor drift layer 224 may have a different doping concentration than the substrate 220 . For example, the semiconductor drift layer 224 may have a lower doping concentration than the substrate 220 .

[0054] like Figure 2As further shown, the example MPS diode 200 includes an anode terminal 226. The anode terminal 226 can be any conductive material (e.g., a front metal) through which current enters the MPS diode 200 or equivalently, through which electrons leave the MPS diode 200. In some embodiments, the anode terminal 226 can include a metal or combination of metals, such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. In some embodiments, the anode terminal 226 can be disposed atop the junction barrier element 228 and can provide a conductive path from an external power source to an injection well 230 of the MPS diode 200.

[0055] like Figure 2 As shown, the anode terminal 226 can provide a metal contact to the top surface 224a of the semiconductor drift layer 224. The portion of the semiconductor drift layer 224 that contacts the anode terminal 226 can create a Schottky diode 234. The Schottky diode 234 can be any semiconductor diode formed by a junction of a semiconductor and a metal. Generally speaking, the Schottky diode 234 has a low forward voltage and a very fast switching action. Therefore, the Schottky diode 234 may be less likely to overheat at high voltages, may allow current to be transmitted with higher efficiency, and may perform well at high frequencies.

[0056] like Figure 2 As further shown, the example MPS diode 200 also includes a cathode terminal 222. The cathode terminal 222 can be any conductive material (e.g., back metal) through which current leaves the MPS diode 200 or equivalently, through which electrons enter the MPS diode 200. In some embodiments, the cathode terminal 222 can include a metal or combination of metals, such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. In some embodiments, the cathode terminal 222 can be disposed below the substrate 220, adjacent to the bottom surface 220b of the substrate.

[0057] like Figure 2 As further shown, the MPS diode 200 includes a junction barrier element 228. The junction barrier element 228 can be any portion of the top surface 224a of the semiconductor drift layer 224 that has been altered or doped so that a PN junction is formed between the junction barrier element 228 and the semiconductor drift layer 224. In some embodiments, the junction barrier element 228 can include an implantation well 230 (e.g., an electrical contact). The implantation well 230 can include a region of the top surface 224a of the semiconductor drift layer 224 that has been doped with a dopant having a conductivity type opposite to that of the semiconductor drift layer 224. Figure 2 As shown, semiconductor drift layer 224 is an n-type doped semiconductor, and implant well 230 is a p-type doped semiconductor. In some embodiments, implant well 230 may be doped with a higher concentration of doping than the surrounding semiconductor drift layer 224.

[0058] like Figure 2 As further shown, the junction barrier element 228 includes an ohmic contact 232 between the anode terminal 226 and the injection well 230 of the junction barrier element 228. The ohmic contact 232 can be any electrical contact between a metal and a semiconductor having a low contact resistance and a linear current-voltage (IV) behavior. The ohmic contact 232 can be formed by performing an annealing process at the surface of the injection well 230 and the anode terminal 226. Annealing can produce silicide, thereby forming an alloy between the semiconductor (e.g., the injection well 230) and the metal at the junction (e.g., the anode terminal 226), which can reduce the barrier height.

[0059] Reference now Figure 3 , an example process 300 is provided for forming an ohmic contact (e.g., ohmic contact 114, 232) on a semiconductor component (e.g., semiconductor component 116, MPS diode 200). At block 302, a first metal layer is deposited on a top surface of a semiconductor drift layer (e.g., semiconductor drift layer 224) including an electrical contact point (e.g., injection well 230), wherein the first metal layer exhibits a high reflectivity (e.g., first reflectivity) characteristic and low absorption to a laser used in a laser annealing process when compared to a reflectivity characteristic of a second metal layer.

[0060] As described herein, the first metal layer includes any conductive material configured to form an ohmic contact with a semiconductor drift layer of an underlying semiconductor component. In addition, the first metal layer is configured to be highly reflective to laser light directed toward the first metal layer during the laser annealing process.

[0061] For example, Figure 5A-5U and Figure 7A-7R As shown in the embodiment shown in , the first metal layer may include aluminum. In some embodiments, the first metal layer may include an aluminum compound, such as silicon-doped aluminum, aluminum silicide, or other similar compounds. Aluminum is a highly reflective material, especially for lasers, such as ultraviolet (UV) lasers. By reflecting the laser, the temperature of the first metal layer does not increase significantly when compared to materials that are not as reflective.

[0062] In some embodiments, the first metal layer may be deposited on the surface of the semiconductor component using physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or other similar processes. In some embodiments, the first metal layer may cover the entire surface of the semiconductor component, including electrical contacts (such as injection wells in MPS diodes) and other portions of exposed silicon (e.g., at the semiconductor drift layer). The first metal layer may form an ohmic contact with the underlying highly doped electrical contacts through an annealing or heating process. In such a process, a reaction between the first metal layer and the electrical contacts may be induced, for example, the formation of silicide may be induced through an annealing or heating process.

[0063] In instances where the temperature of the first metal layer is elevated at other portions of exposed silicon (e.g., at the semiconductor drift layer), undesirable reactions may occur between the first metal layer and the underlying semiconductor components. Therefore, it is desirable to avoid reactions between the first metal layer and other portions of exposed silicon, as described with reference to the embodiments herein.

[0064] At block 304, a second metal layer is deposited on a portion of the first metal layer, wherein the second metal layer is aligned with the electrical contact point, and wherein the second metal layer absorbs the laser light. The second metal layer is selected based in part on low reflectivity (e.g., second reflectivity) or high absorption characteristics when exposed to a laser, particularly a laser commonly used in annealing. The temperature increase of the second metal layer that absorbs the laser light is more significant when compared to a more reflective material (such as the first metal layer). Although in Figure 5A-5U and Figure 7A-7R Although shown as titanium in the example embodiment of , the second metal layer may include any material having a higher absorptivity than the first metal layer, which may enable local heating of the first metal layer at the portion where the first metal layer is in direct contact with the second metal layer.

[0065] In some embodiments, the second metal layer may be deposited on a portion of the first metal layer. For example, the second metal layer may be aligned with one or more electrical contacts. The semiconductor component may include an electrical contact (such as an injection well) configured to receive electrical contact through an ohmic contact. The portion of the second metal layer aligned with the electrical contact below the first metal layer may enable an ohmic contact to be formed between the first metal layer and the electrical contact during the laser annealing process.

[0066] At block 306, during a laser annealing process, the first metal layer and the second metal layer are exposed to a laser, wherein the second metal layer increases in temperature due to the laser, and wherein the increase in temperature causes an ohmic contact to be formed between the electrical contact and the first metal layer. By positioning a portion of the second metal layer on the first metal layer so that the portion of the second metal layer is aligned with the electrical contact below the first metal layer, the second metal layer can enable the ohmic contact to be positioned to the electrical contact during the laser annealing process. In an example in which the surface of the semiconductor component (including the first metal layer and the portion of the first metal layer covered by the second metal layer) is exposed to the laser during the laser annealing process, a portion of the second metal layer absorbs the laser and increases in temperature. The increase in temperature of the second metal layer causes the portion of the first metal layer between the second metal layer and the electrical contact below to also increase in temperature, enabling a reaction with the electrical contact below. Ohmic contact is formed between the second metal layer, the first metal layer, and the electrical contact below.

[0067] Due to the reflective properties of the first metal layer, the temperature of the portion of the first metal layer that is not in contact with the second metal layer does not rise as significantly as the portion of the first metal layer that is in contact with the second metal layer. Therefore, the first metal layer does not react with the exposed portion of the underlying semiconductor drift layer, so that the ohmic contact is limited to the portion of the first metal layer below the second metal layer.

[0068] Reference now Figure 4 , an example process 400 for manufacturing a power diode using a field plate edge termination structure according to one or more embodiments of the present disclosure is provided. At block 402, the first metal layer is removed. In some embodiments, an ohmic contact can be formed between a portion of the second metal layer, the underlying first metal layer, and an underlying electrical contact, such as in combination with Figure 3 The first metal layer can be removed via wet etching, dry etching, or another similar process for removing metal layers on semiconductors. In some embodiments, a masking process can be used to protect the ohmic contact. In some embodiments, an etching process can be used to retain the ohmic contact while removing other portions of the first metal layer.

[0069] At block 404, a dielectric layer is deposited on the top surface of the ohmic contact and the semiconductor drift layer. The dielectric layer can be any insulating material configured to electrically isolate portions of the semiconductor component. The dielectric layer can be formed on the semiconductor component by thermal oxidation, deposition, or another similar process. In some embodiments, the dielectric layer can include silicon oxide, silicon nitride, or another similar insulator. In some embodiments, the dielectric can be deposited or grown on the entire surface of the semiconductor component.

[0070] At block 406, a dielectric layer directly above the top surface of the semiconductor drift layer of the semiconductor component is removed so that the ohmic contact is exposed. In some embodiments, the semiconductor component may include a transmission region where an electrical contact may be formed by an anode terminal and current transfer may occur. For example, in an MPS diode (e.g., MPS diode 200), the transmission region may include a junction barrier element (e.g., junction barrier element 228) and a contact region between an anode terminal (e.g., anode terminal 226) and a semiconductor drift layer (e.g., semiconductor drift layer 224) that forms one or more Schottky diodes (e.g., Schottky diode 234). The deposited or grown dielectric layer may be removed so that the transmission region of the semiconductor component is exposed. In some embodiments, the dielectric layer may be removed by masking and etching or other similar processes.

[0071] At block 408, a front metal is deposited over the ohmic contacts and dielectric layer. Figure 2 As described, the front metal (e.g., anode terminal 226) can be any conductive material through which current enters the semiconductor component or, equivalently, through which electrons leave the semiconductor component. In some embodiments, the front metal can include a combination of multiple layers of metals, such as molybdenum, platinum, chromium, tungsten, titanium, nickel, etc. In some embodiments, the front metal can be deposited across the surface of the semiconductor component using physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or another similar process. The front metal covers the surface of the transmission region, forming electrical contact with the exposed semiconductor drift layer and the ohmic contact.

[0072] At block 410, the front metal is removed from all areas except the electrical diode area on and immediately adjacent to the ohmic contact. In some embodiments, the front metal remains such that the front metal provides electrical contact with the top surface of the semiconductor component, for example, with the exposed semiconductor drift layer and the ohmic contact. In addition, the front metal may overlap with portions of the dielectric layer.

[0073] At block 412, a passivation layer is deposited on the surface and adjacent to the front metal. The passivation layer may include any material configured to coat the semiconductor component and protect the semiconductor from corrosion, chemical reactivity, and electrical contact. The passivation layer may be formed by thermal oxidation or other similar processes. In some embodiments, the passivation layer may cover the entire surface of the semiconductor component.

[0074] At block 414, an access via is etched through the passivation layer to the front metal. The access via may be etched using a mask and a wet etch or dry etch process. The access via may be any path, passage, wire, or opening that enables access from outside the passivation layer to the conductive front metal.

[0075] Reference now Figure 5A-5U, shows an example process 500 for forming an ohmic contact on an example MPS diode. Figure 5A-5U The illustrated example process 500 also includes a process for forming a field plate edge termination structure. Figure 5A In the embodiment of the present invention, one or more heavily doped regions (eg, implantation wells 530) are formed in a surface of a semiconductor drift layer 524 (eg, semiconductor drift layer 224) of a semiconductor component 568. Figure 5A As shown, the heavily doped region forms an injection well 530. As described in conjunction with FIG. 1, the injection well 530 may include a region of the top surface 524a of the semiconductor drift layer 524 that has been doped with a p-type doping opposite to the n-type doping of the semiconductor drift layer 224. In addition, in some embodiments, the injection well 530 can be doped at a higher concentration than the surrounding semiconductor drift layer 524. The semiconductor drift layer 524 can be formed on the substrate 520 by an epitaxial growth process. Like the semiconductor drift layer 524, the substrate 520 includes an n-type semiconductor. In some embodiments, the substrate 520 can be doped at a higher concentration than the semiconductor drift layer 524. In some embodiments, both the substrate 520 and the semiconductor drift layer 524 may include silicon carbide. Silicon carbide may be particularly beneficial in high power and / or high frequency devices.

[0076] The injection well 530 can be formed by Figure 5A The ion implantation process 552 shown is formed. The implantation well 530 is defined by a mask 550, which prevents the implantation of ions except in the implantation well 530 and the guard ring forming the periphery of the semiconductor component 568. The implantation well 530 forms a PN junction diode with the semiconductor drift layer 524. In the MPS diode, the implantation well 530 can relieve some of the stress imposed on the diode at high power. When it is high power, the implantation well 530 can carry some current through the diode. In the absence of the implantation well 530, a pure Schottky diode may be overstressed and enter thermal runaway. Therefore, the implantation well 530 enables the MPS diode to obtain some benefits of both Schottky diodes and PN diodes.

[0077] Reference now Figure 5B , the mask 550 is removed from the top surface 524 a of the semiconductor drift layer 524 .

[0078] like Figure 5CAs shown, the semiconductor component 568 is subjected to an annealing process to activate the dopants in the implantation well 530 in the semiconductor drift layer 524. The annealing process may include exposing the semiconductor component 568 to a high temperature and allowing the semiconductor component 568 to cool slowly. Such an annealing process may fix the implanted ions in the lattice sites of the semiconductor drift layer 524 structure. In some embodiments, damage caused by the ion implantation may be repaired during this process.

[0079] like Figure 5D As shown, an aluminum layer (e.g., a first metal layer) 554 is deposited on the semiconductor component 568. The aluminum layer 554 can be deposited on the top surface 524a of the semiconductor drift layer 524 by a process such as physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or other similar processes. As described herein, aluminum can be selected as the first metal layer because it reflects laser light. Therefore, when exposed to laser light during the annealing process, the temperature of the aluminum layer 554 does not increase significantly. Due to the reflective properties of aluminum, the underlying components are protected during the laser annealing process. In addition, the aluminum can be reacted with the underlying injection well 530 to create an ohmic contact (e.g., as Fig.5I Ohmic contact 532 is shown).

[0080] like Figure 5E As shown, a titanium layer 556 is deposited on the top surface 554a of the aluminum layer 554. The titanium layer 556 can be deposited on the top surface 554a of the aluminum layer 554 by a process such as physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or other similar processes. As described herein, titanium can be selected as the second metal layer based at least in part on the absorption of laser light by titanium. Due to the absorption of laser light by titanium when exposed to the laser light source, the temperature of the titanium layer 556 will increase when exposed to the laser light source.

[0081] like Fig. 5F As shown, a mask 558 is deposited on the top surface 556a of the titanium layer 556. The mask 558 protects the portion of the titanium layer 556 below the mask 558 from being removed during etching or another process for removing the titanium layer 556. Fig. 5F As shown, mask 558 is aligned with implant well 530 beneath aluminum layer 554 .

[0082] like Figure 5G As shown, titanium layer 556 of semiconductor component 568 is removed from the surface of semiconductor component 568 except for the areas of titanium layer 556 that are protected by mask 558 .

[0083] like Figure 5H As shown, mask 558 is removed from semiconductor component 568, leaving only the portion of titanium layer 556 protected by mask 558 on the surface of aluminum layer 554. Figure 5HAs shown, the remaining portion of the titanium layer 556 is aligned with an implant well 530 implanted in the semiconductor drift layer 524 beneath the aluminum layer 554 .

[0084] like Fig.5I As shown, during the laser annealing process, the laser 562 directs the laser 564 across the surface of the semiconductor component 568. The laser annealing process can be used to heat the portion of the semiconductor component 568 that is configured to absorb the laser 564 (e.g., the portion of the titanium layer 556). By generating the laser 564 having a wavelength that is absorbed by the titanium layer 556 but reflected by the aluminum layer 554, the temperature at the remaining portion of the titanium layer 554 and the portion of the aluminum layer 556 below that is in contact with the titanium layer 556 increases. However, the portion of the aluminum layer 554 that is not in contact with the titanium layer 556 reflects the laser 564 and the temperature does not increase significantly. In some embodiments, the laser annealing process is performed using a laser 562 that emits an ultraviolet (UV) laser 564. In such an embodiment, the wavelength of the UV laser 564 can be between 290 nanometers and 370 nanometers; preferably between 300 nanometers and 360 nanometers; more preferably between 310 nanometers and 350 nanometers. In some embodiments, as the wavelength moves above 370 nanometers, titanium layer 556 may begin to increasingly reflect laser light 564. Increased reflectivity may mean that less laser light 564 is absorbed by titanium layer 556 and that titanium layer 564 does not reach a sufficient temperature to facilitate formation of ohmic contact 532.

[0085] The temperature increase of the titanium layer 556 and the portion of the aluminum layer 554 below enables a reaction to occur between the titanium layer 556, the aluminum layer 554, and the injection well 530. The reaction creates an ohmic contact 532 between the titanium of the titanium layer 556, the aluminum of the aluminum layer 554, and the injection well 530 of the semiconductor drift layer 524. Such a titanium / aluminum ohmic contact is one of the most known ohmic contacts for p-type or n-type implant regions. Because the temperature increase is localized based on the location of the titanium layer 556 portion, the portion of the aluminum layer 554 that does not have a significantly increased temperature does not react with the semiconductor below.

[0086] like Figure 5J As shown, the aluminum layer 554 is removed from the surface of the semiconductor component 568, leaving the ohmic contact 532 formed by the titanium layer 556 and the underlying aluminum layer 554 intact over the implant well 530.

[0087] like Figure 5K As shown, a dielectric layer 566 is formed on the top surface 524 a of the semiconductor drift layer 524 (including the ohmic contact 532 ) by thermal oxidation, deposition or other similar processes.

[0088] like Figure 5LAs shown, a mask 558 is disposed on top of the dielectric layer 566 such that a portion of the dielectric layer 566 directly above the semiconductor component 568 (including the ohmic contact 532) is opened and exposed. Figure 5L As shown, mask 558 is aligned with a p-type doped guard ring indicating the peripheral extent of semiconductor component 568 .

[0089] like Figure 5M As shown, dielectric layer 566 is removed directly above semiconductor component 568 (including ohmic contact 532). Figure 5M As shown, dielectric layer 566 remains over the portion of the semiconductor outside of semiconductor component 568 as indicated by the p-type doped guard ring. At least a portion of dielectric layer 566 overlaps the guard ring at the outer extent of semiconductor component 568. Dielectric layer 566 at the edge of semiconductor component 568 at least partially forms a field plate edge termination structure with front metal 526, as shown in FIG. Fig.5O shown.

[0090] like Figure 5N As shown, mask 558 is removed from the surface of dielectric layer 566 .

[0091] like Fig.5O As shown, a front metal 526 (eg, anode terminal 226) is deposited on the surface of semiconductor component 568. Figure 2 As described, front metal 526 can be any conductive material through which current passes into semiconductor component 568 or equivalently, through which electrons leave semiconductor component 568. In some embodiments, front metal 526 can include a metal or combination of metals such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. Fig.5O As shown, front side metal 526 is disposed on top of ohmic contact 532 and provides a conductive path from an external power source to implant well 530 of semiconductor component 568. Front side metal 526 also creates a Schottky junction 570 between front side metal 526 and semiconductor drift layer 524.

[0092] like Figure 5P As shown, a mask 560 is deposited on the surface of the front metal 526. The mask 560 defines the outer dimensions of the front metal relative to the semiconductor component 568. Figure 5P As shown, mask 560 overlaps at least a portion of dielectric layer 566 beneath front side metallization 526 .

[0093] like Figure 5Q As shown, portions of the front metal 526 not protected by the mask 560 are removed from the surface of the dielectric layer 566. Figure 5QAs further shown in FIG. 5 , mask 560 is removed from the surface of front metal 526. As shown, front metal 526 at least partially overlaps dielectric layer 566. Front metal 526 forms a field plate edge termination structure together with dielectric layer 566 that defines the peripheral edge of semiconductor component 568. In some embodiments, field plate edge termination structure can create a high resistivity region and reduce electric field crowding near the edge of semiconductor component 568. Reducing electric field crowding near the edge of semiconductor component 568 can reduce stress on portions of semiconductor component 568.

[0094] like Figure 5R As shown, a passivation layer 576 is deposited across the surface of semiconductor component 568 , including front side metallization 526 and portions of dielectric layer 566 that are exposed.

[0095] As combined Figure 4 As depicted, passivation layer 576 may include any material configured to coat semiconductor component 568 to protect semiconductor component 568 from corrosion, chemical reactivity, and electrical contact. Passivation layer 576 may be formed by thermal oxidation or another similar process.

[0096] like Figure 5S As shown, a mask 578 is placed on the surface of the passivation layer 576. The mask 578 is aligned with the surface of the front metal 526 to define a path through the passivation layer 576 to the surface of the front metal 526.

[0097] like Figure 5T As shown, an access via 572 is etched through the passivation layer 576 to the front side metal 526. The access via 572 provides an opening through the passivation layer 576, enabling access to the conductive front side metal 526 from outside the passivation layer 576.

[0098] like Figure 5U As shown, mask 578 is removed from the surface of passivation layer 576. Figure 5U As further shown in FIG. 5 , a backside ohmic contact 574 is formed on the bottom surface of the substrate 520. In addition, a backside metal 522 (eg, cathode terminal 222) is disposed on the surface of the backside ohmic contact 574.

[0099] like Figure 5U As shown, the resulting semiconductor component 568 is a MPS diode with field plate edge termination.

[0100] Reference now Figure 6 , an example process 600 for manufacturing a power diode without a field plate edge termination structure according to one or more embodiments of the present disclosure is provided. At block 602, the first metal layer is removed. Figure 4As described in block 402 of , an ohmic contact may be formed between a portion of the second metal layer, the underlying first metal layer, and the underlying electrical contact. The first metal layer may be removed via wet etching, dry etching, or another similar process for removing metal layers on semiconductors.

[0101] At block 604, a front metal is deposited on the ohmic contact. Figure 2 As described, the front metal (e.g., anode terminal 226) can be any conductive material through which current enters the semiconductor component or, equivalently, through which electrons leave the semiconductor component. In some embodiments, the front metal can include a combination of multiple layers of metals, such as molybdenum, platinum, chromium, tungsten, nickel, titanium, etc. As further shown in process 600, the front metal is deposited across the surface of the semiconductor. The front metal can be deposited using physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or another similar process. The front metal covers the surface of the transmission region, making electrical contact with the exposed semiconductor drift layer and ohmic contacts and other semiconductor regions external to the semiconductor component.

[0102] At block 606, the front side metal is removed from all areas except for the semiconductor component area on and immediately adjacent to the ohmic contact. In some embodiments, the front side metal remains such that the front side metal provides electrical contact with the top surface of the semiconductor component (e.g., the exposed semiconductor drift layer and the ohmic contact). However, the front side metal beyond the extent of the semiconductor component is removed.

[0103] At block 608, a passivation layer is deposited on and around the front metal. The passivation layer may include any material configured to coat the semiconductor component and protect the semiconductor from corrosion, chemical reactivity, and electrical contact. The passivation layer may be formed by thermal oxidation or other similar processes. In some embodiments, the passivation layer may cover the entire surface of the semiconductor component.

[0104] At block 610, an access via is etched through the passivation layer to the front metal. The access via may be etched using a mask and a wet etch or dry etch process. The access via may be any path, passage, wire, or opening that enables access from outside the passivation layer to the conductive front metal.

[0105] Reference now Figure 7A-7R , shows an example process 700 for forming an ohmic contact on an example MPS diode. Figure 7A-7R The example process 700 shown illustrates a process for creating an MPS diode without forming a field plate edge termination structure. Fig. 7A In the embodiment of the present invention, one or more heavily doped regions (eg, implantation wells 730) are formed in a surface of a semiconductor drift layer 724 (eg, semiconductor drift layer 224, 524) of a semiconductor component 768. Fig. 7AAs shown, the heavily doped region forms an injection well 730. As described in conjunction with FIG. 1, the injection well 730 may include a region of the top surface 724a of the semiconductor drift layer 724 that has been doped with a p-type doping opposite to the n-type doping of the semiconductor drift layer 724. In addition, in some embodiments, the injection well 730 can be doped at a higher concentration than the surrounding semiconductor drift layer 724. The semiconductor drift layer 724 can be formed by an epitaxial growth process on the substrate 720. Like the semiconductor drift layer 724, the substrate 720 includes an n-type semiconductor. In some embodiments, the substrate 720 can be doped at a higher concentration than the semiconductor drift layer 724. In some embodiments, both the substrate 720 and the semiconductor drift layer 724 may include silicon carbide. Silicon carbide may be particularly beneficial in high power and / or high frequency devices.

[0106] The implant well 730 may be formed by Fig. 7A The ion implantation process 752 shown is formed. The implantation well 730 is defined by a mask 750, which prevents the implantation of ions except in the implantation well 730 and the guard ring forming the periphery of the semiconductor component 768. The implantation well 730 forms a PN junction diode with the semiconductor drift layer 724. In the MPS diode, the implantation well 730 can relieve some of the stress imposed on the diode at high power. When it is high power, the implantation well 730 can carry some current through the diode. In the absence of the implantation well 730, a pure Schottky diode may be overstressed and enter thermal runaway. Therefore, the implantation well 730 enables the MPS diode to obtain some benefits of both Schottky diodes and PN diodes.

[0107] Reference now Figure 7B , the mask 750 is removed from the top surface 724 a of the semiconductor drift layer 724 .

[0108] like Figure 7C As shown, the semiconductor component 768 is subjected to an annealing process to fix the implanted well 730 in the semiconductor drift layer 724. The annealing process may include exposing the semiconductor component 768 to a high temperature and allowing the semiconductor component 768 to slowly cool. Such an annealing process may fix the implanted ions in the semiconductor drift layer 724 structure.

[0109] like Fig.7DAs shown, an aluminum layer (e.g., a first metal layer) 754 is deposited on the semiconductor component 768. The aluminum layer 754 can be deposited on the top surface 724a of the semiconductor drift layer 724 by a process such as physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or other similar processes. As described herein, aluminum can be selected as the first metal layer because it reflects laser light. Therefore, when exposed to laser light during the annealing process, the temperature of the aluminum layer 754 does not increase significantly. Due to the reflective properties of aluminum, the underlying components are protected during the laser annealing process. In addition, the aluminum can be reacted with the underlying injection well 730 to create an ohmic contact (e.g., as Fig.7I Ohmic contact 732 shown).

[0110] like Fig. 7E As shown, a titanium layer 756 is deposited on the top surface 754a of the aluminum layer 754. The titanium layer 756 can be deposited on the top surface 754a of the aluminum layer 754 by a process such as physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or other similar processes. As described herein, titanium can be selected as the second metal layer based at least in part on the absorption of laser light by titanium. Due to the absorption of laser light by titanium when exposed to the laser light source, the temperature of the titanium layer 756 will increase when exposed to the laser light source.

[0111] like Figure 7F As shown, a mask 758 is deposited on the top surface 756a of the titanium layer 756. The mask 758 protects the portion of the titanium layer 756 below the mask 758 from being removed during etching or another process for removing the titanium layer 756. Figure 7F As shown, mask 758 is aligned with implant well 730 beneath aluminum layer 754 .

[0112] like Figure 7G As shown, the titanium layer 756 of the semiconductor component 768 is removed from the surface of the semiconductor component 768 except for the areas of the titanium layer 756 that were protected by the mask 758 .

[0113] like Figure 7H As shown, mask 758 is removed from semiconductor component 768, leaving only the portion of titanium layer 756 protected by mask 758 on the surface of aluminum layer 754. Figure 7H As shown, the remaining portion of the titanium layer 756 is aligned with an implant well 730 implanted in the semiconductor drift layer 724 beneath the aluminum layer 754 .

[0114] like Fig.7IAs shown, during the laser annealing process, laser 762 directs laser light 764 across the surface of semiconductor component 768. The laser annealing process can be used to heat portions of semiconductor component 768 that are configured to absorb laser light 764 (e.g., portions of titanium layer 756). By generating laser light 764 having a wavelength that is absorbed by titanium layer 756 but reflected by aluminum layer 754, the temperature at the remaining portions of titanium layer 756 and portions of the underlying aluminum layer 754 that are in contact with titanium layer 756 increases. However, portions of aluminum layer 754 that are not in contact with titanium layer 756 reflect laser light 764 and the temperature does not increase significantly.

[0115] The temperature increase of the titanium layer 756 and the portion of the aluminum layer 754 below enables a reaction to occur between the titanium layer 756, the aluminum layer 754, and the injection well 730. The reaction creates an ohmic contact 732 between the titanium of the titanium layer 756, the aluminum of the aluminum layer 754, and the injection well 730 of the semiconductor drift layer 724. Such a titanium / aluminum ohmic contact is one of the most known ohmic contacts for p-type or n-type implant regions. Because the temperature increase is localized based on the location of the portion of the titanium layer 756, the portion of the aluminum layer 754 that does not have a significant temperature increase does not react with the semiconductor below.

[0116] like Figure 7J As shown, the aluminum layer 754 is removed from the surface of the semiconductor component 768, leaving the ohmic contact 732 formed by the titanium layer 756 and the underlying aluminum layer 754 intact over the implant well 730.

[0117] like Figure 7K As shown, a front metal 726 (eg, anode terminal 226) is deposited on the surface of semiconductor component 768. Figure 2 As described, the front metal 726 can be any conductive material through which current passes into the semiconductor component 568 or, equivalently, through which electrons leave the semiconductor component 768. In some embodiments, the front metal 726 can include a metal or combination of metals such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. Figure 7K As shown, the front side metal 726 is disposed on top of the ohmic contact 732 and provides a conductive path from an external power source to the implant well 730 of the semiconductor component 768. The front side metal 726 also creates a Schottky diode 770 between the front side metal 726 and the semiconductor drift layer 724.

[0118] like Figure 7L As shown, a mask 760 is deposited on the surface of the front metal 726. The mask 760 defines the outer dimensions of the front metal relative to the semiconductor component 768. Figure 7L As shown, the mask 760 overlaps at least a portion of a guard ring that establishes a periphery of the semiconductor component 768 beneath the front side metallization 726 .

[0119] like Figure 7M As shown, portions of the front metal 726 not protected by the mask 760 are removed from the surface of the semiconductor component 768. Figure 7M As further described in , the front metal 726 at least partially overlaps the guard ring defining the peripheral edge of the semiconductor component 768. The front metal 726 provides a Schottky diode 770 contact between the front metal 726 and the exposed portion of the semiconductor drift layer 724. The front metal 726 also provides an electrical connection to the PN junction diode between the implant well 730 and the semiconductor drift layer 724.

[0120] like Figure 7N As shown, mask 760 is removed from the surface of front side metal 726 .

[0121] like Fig.7O As shown, a passivation layer 776 is deposited across the surface of the semiconductor component 768 (including the exposed portions of the front metal 726 and the semiconductor drift layer 724 and any other exposed surfaces). Figure 4 As depicted, the passivation layer 776 may include any material configured to coat the semiconductor component 768 to protect the semiconductor component 768 from corrosion, chemical reactivity, and electrical contact. The passivation layer 776 may be formed by thermal oxidation or another similar process.

[0122] like Figure 7P As shown, a mask 778 is placed on the surface of the passivation layer 776. The mask 778 is aligned with the surface of the front metal 726 to define a path through the passivation layer 776 to the surface of the front metal 726.

[0123] like Figure 7Q As shown, an access via 772 is etched through the passivation layer 776 to the front side metal 726. The access via 772 provides an opening through the passivation layer 776 to enable access to the conductive front side metal 726 from outside the passivation layer 776.

[0124] like Figure 7R As shown, mask 778 is removed from the surface of passivation layer 776. Figure 7R As further shown in FIG. 7 , a backside ohmic contact 774 is formed on the bottom surface of the substrate 720. In addition, a backside metal 722 (eg, cathode terminal 222) is disposed on the surface of the backside ohmic contact 774.

[0125] like Figure 7R As shown, the resulting semiconductor component 768 is an MPS diode without field plate edge termination.

[0126] Although this detailed description has set forth some embodiments of the invention, the appended claims cover other embodiments of the invention that differ from the described embodiments according to various modifications and improvements. For example, those skilled in the art will recognize that such principles can be applied to any semiconductor device that benefits from the precise placement of ohmic contacts. For example, any semiconductor device that utilizes a merged PN Schottky diode or other PN diode that utilizes an ohmic contact.

[0127] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim, it is not intended that the claim be interpreted under 35 USC §112, paragraph 6.

[0128] Use of broader terms such as "comprising," "including," and "having" should be understood to provide support for narrower terms such as "consisting of," "consisting substantially of," and "consisting essentially of." Use of the terms "optionally," "may," "might," "possibly," and the like with respect to any element of an embodiment means that the element is not required, or that the element is required instead, both alternatives being within the scope of the embodiment(s). Furthermore, references to examples are provided for illustrative purposes only and are not intended to be exclusive.

Claims

1. A method for forming an ohmic contact on a semiconductor component, the method comprising: depositing a first metal layer on a top surface of the semiconductor drift layer including electrical contacts, wherein the first metal layer reflects the laser light; depositing a second metal layer on portions of the first metal layer, wherein the second metal layer is aligned with the electrical contacts, and The second metal layer absorbs the laser light; as well as exposing the first metal layer and the second metal layer to laser light in a laser annealing process, The temperature of the second metal layer increases significantly due to the laser. The increase in temperature causes an ohmic contact to be formed between the electrical contact point and the first metal layer.

2. The method of claim 1, wherein the semiconductor component is a merged PN Schottky diode. The method of claim 2 , wherein the electrical contact is an implantation well in the top surface of the semiconductor drift layer. 4 . The method of claim 3 , wherein a portion of the second metal layer is positioned on a top surface of the first metal layer directly opposite the implantation well. The method according to claim 4 , wherein a first reflectivity of the first metal layer is greater than a second reflectivity of the second metal layer. The method of claim 4 , wherein the implant well comprises a p-type semiconductor, and the semiconductor drift layer comprises an n-type semiconductor. The method of claim 4 , wherein the ohmic contact makes electrical contact with the implant well.

8. The method according to claim 1, further comprising: removing the second metal layer; as well as Front side metal is deposited on the ohmic contact.

9. The method of claim 8, wherein the front side metal is an anode of the semiconductor component.

10. The method according to claim 8, further comprising: The front side metal is removed from all areas except the areas of the semiconductor component over and immediately adjacent to the ohmic contacts.

11. The method according to claim 10, further comprising: depositing a passivation layer on and around the front metal; as well as Access vias are etched through the passivation layer to the front side metal.

12. The method according to claim 8, further comprising: depositing a dielectric layer on the ohmic contact and the top surface of the semiconductor drift layer; removing a dielectric layer directly above a top surface of a semiconductor drift layer of the semiconductor component such that an ohmic contact is exposed; as well as Front side metal is deposited over the ohmic contact and dielectric layers.

13. The method according to claim 12, further comprising: The front side metal is removed from all areas except the areas of the semiconductor component over and immediately adjacent to the ohmic contacts.

14. The method according to claim 13, further comprising: depositing a passivation layer on the surface and adjacent to the front metal; as well as Access vias are etched through the passivation layer to the front side metal.

15. The method of claim 14, further comprising creating a backside ohmic contact on a surface opposite the passivation layer, The back metal is in electrical contact with the back ohmic contact. The method of claim 15 , wherein the backside ohmic contact is a cathode of the semiconductor component.

17. The method of claim 1, wherein the semiconductor drift layer is formed by an epitaxial growth process on a semiconductor substrate. The method of claim 17 , wherein the semiconductor substrate and the semiconductor drift layer both comprise silicon carbide. The method of claim 1 , wherein the first metal layer comprises aluminum.

20. The method of claim 1, wherein the second metal layer comprises titanium.

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