A power management circuit and control method based on programmable output reference voltage

Abstract

The present application discloses a power management circuit based on programmable output reference voltage and a control method thereof. The circuit comprises: a first power supply voltage input terminal (VCC) for inputting power supply; an NMOS tube (Q1) for controlling output voltage (V_OUT) according to changes in a reference voltage input terminal (IN_REF); a current limiting resistor (R1) connected in series with a source of the NMOS tube (Q1) for detecting output current; a base of a transistor (Q2) connected to one end of the current limiting resistor (R1), and when it is detected that the current exceeds a preset value, the transistor (Q2) is turned on to reduce the reference voltage; an optical coupler (U1) is connected to an external control unit, and the external control unit generates an overcurrent alarm signal by detecting the voltage on the current limiting resistor, and controls the reference voltage input terminal (IN_REF) to 0V to shut down the power output, thereby protecting the circuit.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a power management circuit and a control method based on a programmable output reference voltage. Background Art

[0002] With the continuous improvement of electronic equipment and system integration, power management and overcurrent protection have become key issues in design. Especially in high-power electronic equipment, the stability and safety of the power system directly affect the performance and service life of the equipment. In traditional power management and overcurrent protection methods, mechanical circuit breakers or fuses are often used to prevent overcurrent. However, these traditional methods have problems such as slow response speed, inaccurate protection, and difficulty in integration with modern intelligent systems. They cannot meet the needs of highly integrated electronic devices for real-time response and programmable control.

[0003] In the production process of large-size display screens, the power module needs to provide the display screen with an output capacity of up to 25V / 6A. However, due to the frequent problems of internal short circuit of the display screen or short circuit of the screen FPC connector crimping, once the power output module is turned on, it may directly cause an ultra-large current of tens of amperes to be generated, thereby burning the screen or FPC connector. Traditional overcurrent protection schemes usually rely on the ADC sampling current size to determine whether to trigger overcurrent protection (OCP). However, due to the slow ADC sampling conversion time, the response time is usually above the millisecond level, and in high-power output scenarios, a short circuit will instantly cause the output current to surge to tens of amperes, causing the screen to burn in a short time. Therefore, the traditional OCP solution cannot meet the rapid protection requirements in this scenario.

[0004] In order to solve the problem of high-power power modules burning the screen due to short circuit during the display screen process, it is particularly important to design a protection method that can quickly respond and shut down the power output. This method must be able to detect high current abnormalities within milliseconds and cut off the power output in time to avoid damage to the screen or FPC connector. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a power management circuit and control method based on programmable output reference voltage. The technical solution in the present application is described below:

[0006] In a first aspect, the present application provides a power management circuit based on a programmable output reference voltage, comprising:

[0007] The first power supply voltage input terminal (VCC), NMOS tube (Q1), reference voltage input terminal (IN_REF), current limiting resistor (R1), transistor (Q2), optical coupler (U1), external control unit (U2) and voltage output terminal, wherein:

[0008] The first power supply voltage input terminal (VCC) is used to input a power supply voltage, and the reference voltage input terminal (IN_REF) is used to input a reference voltage;

[0009] The drain (D) of the NMOS tube is electrically connected to the first power supply voltage input terminal (VCC),

[0010] One end of the current limiting resistor (R1) is connected to the emitter (E) of the transistor (Q2) and the voltage output terminal (V_OUT), and the other end is connected to the base (B) of the transistor (Q2) and the source (S) of the NMOS transistor (Q1), and the gate (G) of the NMOS transistor is electrically connected to the reference voltage input terminal (IN_REF);

[0011] The collector (C) of the transistor (Q2) is electrically connected to the reference voltage input terminal (IN_REF);

[0012] The anode of the input end of the optical coupler (U1) is electrically connected to the reference voltage input end (IN_REF), and the cathode of the input end of the optical coupler (U1) is electrically connected to the collector (C) of the transistor (Q2); the collector of the output end of the optical coupler (U1) is electrically connected to the external control unit (U2), and the emitter of the output end of the optical coupler (U1) is grounded.

[0013] The external control unit is used to determine whether an overcurrent alarm signal is triggered according to the conduction state of the optical coupler (U1), and if the overcurrent alarm signal is triggered, the reference voltage input terminal (IN_REF) is controlled to be 0V.

[0014] Optionally, the external control unit comprises an FPGA, a pull-up resistor (R2) and a second power supply voltage input terminal, one end of the pull-up resistor (R2) is electrically connected to the FPGA and the anode of the input terminal of the optical coupler (U1), and the other end of the pull-up resistor (R2) is electrically connected to the second power supply voltage input terminal.

[0015] Optionally, the transistor (Q2) is turned on when the voltage drop across the current limiting resistor (R1) exceeds 0.6V.

[0016] Optionally, when the current on the current limiting resistor (R1) exceeds 6A, the optical coupler (U1) reduces the reference voltage input terminal (IN_REF) to make the NMOS tube (Q1) enter a semi-conducting state.

[0017] Optionally, the external control unit is connected to a 3.3V power supply via a pull-up resistor (R2) and is used to detect changes in the IO level when the optocoupler (U1) is turned on.

[0018] A second aspect of the present application provides a control method for a power management circuit based on a programmable output reference voltage, which is applied to the power management circuit based on a programmable output reference voltage as described in the first aspect and any one of the first aspects, and the control method includes:

[0019] The external control unit detects the power supply output current in real time through the optical coupler (U1) and determines the current size based on the voltage difference across the current limiting resistor (R1);

[0020] When the current on the current limiting resistor (R1) exceeds a preset current threshold, the reference voltage input terminal (IN_REF) is controlled to decrease through the optical coupler (U1), thereby reducing the gate voltage of the NMOS tube (Q1);

[0021] Control the NMOS tube (Q1) to enter the semi-conducting state, reducing the output voltage (V_OUT);

[0022] The external control unit generates an overcurrent alarm signal according to the collected IO level signal, and turns off the NMOS tube (Q1) to cut off the power output by reducing the reference voltage input terminal (IN_REF) to 0V.

[0023] Optionally, the external control unit samples the IO level signal once every 1 μs.

[0024] Optionally, the external control unit calculates the duration during which the IO level signal is continuously 0 by means of a counter.

[0025] Optionally, the length threshold of the counter is configured by a host computer.

[0026] Optionally, the voltage drop threshold on the current limiting resistor (R1) is set to 0.6V.

[0027] Optionally, the fixed voltage drop of the optocoupler (U1) is 1.2V.

[0028] Optionally, the length threshold is configured as 10 μs through a host computer.

[0029] It can be seen from the above technical solutions that this application has the following advantages:

[0030] 1. Using a transistor (Q2) as a current detection element, when the current on the current limiting resistor (R1) exceeds the preset value, it can be turned on quickly, thereby quickly reducing the reference voltage input terminal (IN_REF). This fast response feature ensures that in the event of a short circuit or overcurrent, the power output can be turned off within microseconds to protect the screen and other components from damage.

[0031] 2. Through the design of the current limiting resistor (R1), the circuit can accurately monitor the output current and start the protection mechanism when the current exceeds the preset value (such as 6A). This can effectively prevent the device from burning due to excessive current and enhance the safety of power management.

[0032] 3. The circuit achieves isolation between control and output through the NMOS tube (Q1) and the reference voltage input terminal (IN_REF), reduces the interference of the power control signal on the output voltage, and ensures the stability and reliability of the power supply.

[0033] 4. The external control unit can be configured according to actual needs, detect current in real time and generate alarm signals. Its programmability enables the circuit to adapt to different working conditions and application scenarios, improving the flexibility of the circuit.

[0034] 5. FPGA configures a detection delay mechanism through a counter, which can filter out pulse currents in non-short circuit conditions and avoid false alarms. This enhances the stability and reliability of the system, enabling it to operate effectively in various working environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solution in the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0036] Figure 1 A schematic diagram of the structure of an embodiment of a power management circuit based on programmable output reference voltage provided by the present application;

[0037] Figure 2 A flow chart of an embodiment of a control method for a power management circuit based on a programmable output reference voltage provided in the present application. DETAILED DESCRIPTION

[0038] See also Figure 1 The present application first provides an embodiment of a power management circuit based on a programmable output reference voltage, the embodiment comprising:

[0039] The first power supply voltage input terminal VCC, NMOS transistor Q1, reference voltage input terminal IN_REF, current limiting resistor R1, transistor Q2, optical coupler U1, external control unit U2 and voltage output terminal, wherein,

[0040] The first power supply voltage input terminal VCC is used to input a power supply voltage, and the reference voltage input terminal IN_REF is used to input a reference voltage;

[0041] The drain electrode D of the NMOS tube is electrically connected to the first power supply voltage input terminal VCC,

[0042] One end of the current limiting resistor R1 is connected to the emitter E of the transistor Q2 and the voltage output terminal V_OUT, and the other end is connected to the base B of the transistor Q2 and the source S of the NMOS transistor Q1, and the gate G of the NMOS transistor is electrically connected to the reference voltage input terminal IN_REF;

[0043] The collector C of the transistor Q2 is electrically connected to the reference voltage input terminal IN_REF;

[0044] The anode of the input end of the optocoupler U1 is electrically connected to the reference voltage input end IN_REF, and the cathode of the input end of the optocoupler U1 is electrically connected to the collector C of the transistor Q2; the collector of the output end of the optocoupler U1 is electrically connected to the external control unit U2, and the emitter of the output end of the optocoupler U1 is grounded.

[0045] The external control unit is used to determine whether to trigger an over-current alarm signal according to the conduction state of the optical coupler U1, and if the over-current alarm signal is triggered, control the reference voltage input terminal IN_REF to 0V.

[0046] This embodiment provides a power management circuit based on programmable output reference voltage, which is intended to achieve fast and safe power output, and is particularly suitable for overcurrent protection of high-power power modules. The power management circuit structure and its functions are described in detail below:

[0047] First power supply voltage input terminal VCC:

[0048] The first power supply voltage input terminal VCC serves as the input power supply of the entire power management circuit, providing necessary voltage and current support. The first power supply voltage input terminal VCC can provide a stable voltage output to ensure the normal operation of subsequent circuit components.

[0049] NMOS tube Q1:

[0050] Drain D: connected to the first power supply voltage input terminal VCC, receiving input power.

[0051] The source S is connected to the output terminal of the first power supply voltage input terminal VCC, and provides an output voltage V_OUT to the load.

[0052] Gate G: connected to the programmable reference voltage terminal IN_REF.

[0053] According to the change of reference voltage IN_REF, NMOS tube Q1 controls the size of output voltage V_OUT. The voltage change of gate G determines the conduction and cutoff of NMOS tube, thereby realizing accurate regulation of output voltage.

[0054] Current limiting resistor R1:

[0055] The current limiting resistor R1 is connected in series with the source of the NMOS tube Q1. It is used to detect the magnitude of the output current in real time. When current flows through the resistor, a voltage drop will be generated at both ends of it, and the voltage drop is proportional to the current flowing through. By monitoring this voltage drop, it can be determined whether the output current in the circuit exceeds the set current limit value.

[0056] Transistor Q2:

[0057] Base B: connected to one end of the current limiting resistor R1, and detects the voltage on the current limiting resistor R1 in real time.

[0058] Emitter E: Grounded to provide a stable reference level.

[0059] Collector C: connected to the reference voltage terminal IN_REF.

[0060] When the current voltage drop on the current limiting resistor R1 exceeds the preset current threshold, such as 6A, the transistor Q2 will be turned on, causing the reference voltage IN_REF to decrease. In this way, the voltage of the gate G of the NMOS transistor Q1 decreases, thereby reducing the output voltage V_OUT, thereby limiting the output current and preventing the circuit from overloading.

[0061] Optocoupler U1:

[0062] Input of optocoupler U1:

[0063] Anode: connected to the reference voltage input terminal IN_REF, which is the power signal input and is used to provide voltage to activate the light-emitting diode of the optocoupler.

[0064] Cathode: connected to the collector of transistor Q2, so that the working state of the optocoupler is correlated with the conduction state of transistor Q2.

[0065] Output of optocoupler U1:

[0066] Collector: electrically connected to the external control unit U2. The optocoupler outputs the signal to the external control unit for further processing or control of other circuits.

[0067] Emitter: Ground (GND) to ensure that the output reference level of the optocoupler is the ground potential, forming electrical isolation and avoiding interference from the ground potential.

[0068] External control unit U2: The external control unit U2 is responsible for real-time monitoring of the voltage change on the current limiting resistor R1 and generating an overcurrent alarm signal. When the voltage is detected to exceed the threshold, the reference voltage IN_REF is controlled to 0V, and the power output is quickly shut down to protect the subsequent circuits and loads from damage.

[0069] FPGA has extremely high speed and flexibility. It can detect current at a sampling rate of 1μs. Combined with the counter function, it can be configured to filter out pulse current caused by non-short circuits to ensure the reliability of power management.

[0070] The following describes the working process of the circuit structure of this embodiment:

[0071] Under normal working conditions, the first power supply voltage input terminal (VCC) provides a stable voltage, and the NMOS tube Q1 controls the output voltage V_OUT according to the reference voltage IN_REF, thereby achieving a stable current output.

[0072] Once the current exceeds the set value, the voltage drop on the current limiting resistor R1 will change, and the transistor Q2 will turn on, reducing IN_REF, which in turn affects the conduction state of Q1. The external control unit U2 monitors the voltage change of the current limiting resistor R1 in real time. Once it detects that the overcurrent threshold exceeds the set value, it quickly sends an alarm signal and sets IN_REF to 0V, cutting off the power output to protect the safety of the equipment.

[0073] In an optional embodiment, when the voltage drop across the current limiting resistor R1 exceeds 0.6V, the transistor Q2 is turned on.

[0074] In this optional embodiment, the conduction condition of the transistor Q2 is set as follows: when the voltage drop across the current limiting resistor R1 exceeds 0.6V, the transistor Q2 is turned on.

[0075] The function of the current limiting resistor R1 is to detect the current size. When the output current is too large, the current flowing through the current limiting resistor will generate a voltage drop across its two ends.

[0076] According to Ohm's law, voltage drop V=I×R, assuming that the resistance of the current limiting resistor R1 is a known small resistance, the current flowing through the resistor can be known by measuring the voltage drop. When the voltage drop exceeds 0.6V, it means that the current flowing through the resistor has exceeded the set current limiting threshold.

[0077] The base of transistor Q2 is connected to both ends of the current limiting resistor. When the voltage drop across the current limiting resistor reaches or exceeds 0.6V, the base-emitter voltage V_BE reaches the turn-on voltage, which is generally about 0.6V-0.7V, and transistor Q2 starts to conduct.

[0078] When the voltage on the current limiting resistor exceeds 0.6V, that is, the current reaches the set value, the transistor Q2 is turned on, thereby lowering the voltage on the reference voltage terminal IN_REF. When the reference voltage IN_REF decreases, the gate voltage of the NMOS tube Q1 decreases, thereby reducing the output voltage V_OUT. This design enables the circuit to respond quickly, limit the current from continuing to increase, and protect the load.

[0079] In an optional embodiment, when the current on the current limiting resistor R1 exceeds 6A, the optical coupler U1 reduces the reference voltage IN_REF to make the NMOS transistor Q1 enter a semi-conducting state.

[0080] In this optional embodiment, the optocoupler U1 controls the working state of the circuit by detecting whether the current on the current limiting resistor R1 exceeds 6A.

[0081] When current flows through the current limiting resistor R1, a corresponding voltage drop will occur across R1. Assuming that the resistance of R1 is 0.1Ω, when the current flowing through R1 reaches 6A, the voltage drop across R1 will be V=I×R=6A×0.1Ω=0.6V.

[0082] When the voltage drop across R1 reaches or exceeds 0.6V, the optocoupler U1 detects this change and responds. The optocoupler (U1) can achieve electrical signal isolation through its internal optical conduction mechanism according to the current size, and transmit the signal to the external control unit U2 or directly control the reference voltage IN_REF.

[0083] When the optocoupler detects that the current on the current limiting resistor exceeds 6A, it will reduce the reference voltage IN_REF through the output signal. The reduction of the reference voltage directly affects the gate voltage of the NMOS tube Q1, because the conduction degree of Q1 is related to the voltage difference V_GS between the gate (G) and the source (S).

[0084] As IN_REF decreases, the V_GS of the NMOS tube Q1 gradually decreases, causing Q1 to switch from a fully on state to a semi-on state. When Q1 is in a semi-on state, the output voltage V_OUT will drop, thereby reducing the current passing through the circuit and limiting the current from continuing to increase.

[0085] This state is equivalent to providing the circuit with an automatic current limiting function, ensuring that when the current is too large, the output voltage can be reduced in time to avoid damage to the circuit or load due to overcurrent.

[0086] In an optional embodiment, the external control unit U2 includes an FPGA, a pull-up resistor R2 and a second power supply voltage input terminal VDD, one end of the pull-up resistor R2 is electrically connected to the FPGA and the anode of the input terminal of the optocoupler U1, and the other end of the pull-up resistor R2 is electrically connected to the second power supply voltage input terminal VDD.

[0087] In an optional embodiment, the external control unit U2 may include:

[0088] FPGA: This unit is FPGA (Field Programmable Gate Array) which is used to receive and process the signal from the optocoupler U1 and execute the control logic.

[0089] Pull-up resistor R2: One end of the pull-up resistor is connected to the collector (C pole) of the output terminal of the optocoupler U1. This connection ensures that the output signal of the optocoupler can be effectively read, and at the same time, the voltage of the output terminal is pulled up through the pull-up resistor R2 to maintain a stable state. The other end is connected to the second power supply voltage input terminal VDD. This connection provides power to the pull-up resistor R2, enabling it to pull the voltage of the input terminal up to the voltage level of VDD.

[0090] Second power supply voltage input terminal VDD: The second power supply voltage input terminal VDD is an external power supply voltage source, which is used to provide the required operating voltage for the optocoupler and FPGA. Its voltage value can be 3.3V, 5V, etc.

[0091] In this embodiment, the function of the pull-up resistor R2 is to ensure that the output of the optocoupler U1 is maintained at a high level when there is no signal. By connecting the C pole to VDD, the pull-up resistor R2 pulls the output high to prevent an unstable state caused by floating.

[0092] When the input end of the optocoupler U1 is turned on, the signal is converted by U1 and output from the C pole of the output end, and the FPGA can receive the signal and perform subsequent processing. This enables the FPGA to make corresponding logical responses according to the state of the optocoupler.

[0093] In this optional embodiment, the external control unit U2 is connected to a 3.3V power supply via a pull-up resistor R2 and is used to detect changes in the IO level when the optical coupler U1 is turned on.

[0094] In this embodiment, the pull-up resistor R2 is connected between the input IO port of the FPGA and the 3.3V power supply, and its function is to keep the IO port at a high level of 3.3V when there is no signal input. When the optical coupler U1 is not turned on, the IO pin of the FPGA will be kept at a high level of 3.3V through the pull-up resistor.

[0095] When the current on the current limiting resistor R1 reaches or exceeds the set overcurrent threshold, such as 6A, the optocoupler U1 is turned on. After the optocoupler is turned on, its output terminal will be pulled down to the ground potential.

[0096] At this time, the IO port of the FPGA will be pulled to a low level of 0V through the conduction path of the optocoupler U1, thereby detecting the level change.

[0097] When the optocoupler U1 is turned on, the IO pin of the FPGA changes from a high level of 3.3V to a low level of 0V. This level change can be detected by the FPGA in real time.

[0098] Based on this level change, the FPGA determines that the optocoupler has detected an overcurrent condition on the current limiting resistor R1, and thereby triggers subsequent control actions, such as further reducing the reference voltage IN_REF or directly shutting down the power output.

[0099] Through the cooperation of pull-up resistor R2 and optocoupler U1, FPGA can detect whether the current exceeds the current limiting threshold. If overcurrent is detected, FPGA can make corresponding protection decisions, such as shutting down the power supply or switching to protection mode. The external control unit U2 can accurately control the working state of the circuit by monitoring the conduction state of the optocoupler to ensure rapid response in case of overcurrent, thereby protecting the load and power supply. This design can respond to the current changes on the current limiting resistor in real time. The FPGA can immediately execute the corresponding protection measures according to the changes in the IO level to avoid circuit damage caused by delays.

[0100] See also Figure 2 The present application also provides an embodiment of a control method for a power management circuit based on a programmable output reference voltage. The control method of this embodiment is applied to the power management circuit based on a programmable output reference voltage in any of the above embodiments. The embodiment of the control method includes:

[0101] S101, the external control unit U2 detects the power supply output current in real time through the optical coupler U1, and determines the current size according to the voltage difference on the current limiting resistor R1;

[0102] In this step, the external control unit U2 uses the optocoupler U1 to detect the current.

[0103] The current limiting resistor R1 is connected in series in the power supply output circuit. By detecting the voltage difference across R1, the current passing through the resistor can be calculated. According to Ohm's law, the voltage difference ΔV=I×R1, where I is the current passing through the resistor. The current value can be determined by the voltage difference.

[0104] When the voltage difference on the current limiting resistor reaches a certain value, the optocoupler U1 will be turned on and transmit the signal to the FPGA. Through the isolation function of the optocoupler U1, the FPGA can monitor the current signal in real time and reliably, avoiding interference or damage caused by direct electrical contact.

[0105] The FPGA uses the output signal of the optocoupler to determine whether the current on the current limiting resistor exceeds the preset threshold. When the current reaches the overcurrent threshold, the FPGA can further respond.

[0106] S102, when the current on the current limiting resistor R1 exceeds the preset current threshold, the reference voltage IN_REF is controlled to decrease through the optical coupler U1, thereby reducing the gate voltage of the NMOS tube Q1;

[0107] In this step, when the current on the current limiting resistor R1 exceeds a preset threshold, such as 6A, the FPGA confirms that the current has exceeded the limit through the collected voltage signal.

[0108] If the current threshold is exceeded, the FPGA sends a control signal through the optical coupler U1 to reduce the reference voltage IN_REF. The reduction of the reference voltage IN_REF will directly affect the gate G voltage of the NMOS tube Q1.

[0109] The voltage of the gate G of the NMOS tube controls the conduction state of the NMOS tube. As the reference voltage decreases, the voltage of the gate G will also decrease accordingly, reducing the conduction degree of the NMOS tube and gradually limiting the output current of the power supply.

[0110] S103, controlling the NMOS tube Q1 to enter a semi-conducting state, thereby reducing the output voltage V_OUT;

[0111] In this step, by reducing the reference voltage, the NMOS tube Q1 gradually enters a semi-conducting state from a fully-conducting state. At this time, the NMOS tube will not be completely turned off, but its conduction impedance will increase, thereby reducing the output current and voltage.

[0112] Since the gate voltage of the NMOS tube is reduced, the conduction capability of the NMOS tube is weakened, causing the output voltage V_OUT to drop. This is the first stage of circuit protection, which avoids overcurrent damage by reducing the output current.

[0113] The main purpose of this stage is to prevent the screen or other loads from being damaged due to short circuit or overcurrent. By reducing the output current, the impact of the current on the screen is reduced.

[0114] S104 , the external control unit U2 generates an over-current alarm signal according to the collected IO level signal, and turns off the NMOS tube Q1 to cut off the power output by reducing the reference voltage IN_REF to 0V.

[0115] In this step, the FPGA determines the overcurrent status based on the IO level signal collected from the optocoupler U1. If the FPGA detects continuous overcurrent, it will generate an overcurrent alarm signal to remind the system that the current has exceeded the safe range.

[0116] While sending out the over-current alarm signal, the FPGA further reduces the reference voltage IN_REF to 0 V. At this time, the gate voltage of the NMOS tube Q1 will drop to zero, causing the NMOS tube to be completely turned off.

[0117] As the NMOS tube Q1 is turned off, the power output circuit is cut off and V_OUT becomes 0. This operation ensures that the load in the circuit, such as the screen, will not be burned due to continuous overcurrent.

[0118] Through the current limiting resistor R1, this method can accurately detect the output current. The external control unit U2 monitors the voltage difference across the current limiting resistor in real time through the optocoupler U1 and calculates the current. Since the detection process is continuous, it can ensure real-time response when the current changes, effectively reducing the potential overcurrent risk in the circuit.

[0119] In this embodiment, specifically, the voltage drop threshold on the current limiting resistor R1 can be set to 0.6V, and the fixed voltage drop of the optical coupler U1 can be 1.2V.

[0120] The method regulates the current in a hierarchical manner through multiple control steps. For example, in step S102, when the current exceeds a preset threshold, the voltage of the gate G of the NMOS tube Q1 is first reduced by reducing the reference voltage IN_REF, so that the power output gradually decreases, rather than immediately shutting down the power completely.

[0121] This method avoids the impact caused by sudden power failure, which is beneficial to extend the service life of loads such as screens, while reducing the electrical impact of overcurrent in the system. In addition, the setting of the semi-conduction state can provide flexible power control, ensuring that the system can still maintain a certain output while protecting the load.

[0122] If the current continues to exceed the threshold, the FPGA will reduce the reference voltage IN_REF to 0V, thereby completely shutting down the NMOS tube Q1 and cutting off the power output. This design ensures that in extreme cases, such as continuous short circuit or severe overcurrent, the power output can be cut off in a timely and reliable manner to prevent further damage to the circuit and load.

[0123] This embodiment not only realizes the gradual reduction of current, but also sets a final power off operation, providing a double protection mechanism. This design is more comprehensive in protecting the circuit and effectively prevents the load from being burned in an overcurrent state.

[0124] Since this method relies on FPGA to perform current detection and control, the system is highly programmable. FPGA can flexibly configure the overcurrent threshold, reference voltage adjustment strategy, and output current change curve according to different application scenarios.

[0125] In an optional embodiment, the external control unit U2 samples the IO level signal once every 1 μs.

[0126] In this embodiment, sampling is performed every 1 microsecond, which can ensure that the state changes of the circuit can be captured in real time, especially when the current or voltage fluctuates violently, the FPGA can quickly sense and respond. Since the sampling rate reaches 1μs, the external control unit U2 can detect and handle overcurrent in a very short time. Compared with the traditional power management system with a lower sampling rate, this embodiment can react at the moment of current exceeding the limit, and quickly control the reduction of the reference voltage IN_REF through the optical coupler U1 to ensure that the NMOS tube Q1 enters a semi-conducting or fully shut-off state, thereby achieving more timely and reliable protection.

[0127] In an optional embodiment, the external control unit U2 calculates the duration during which the IO level signal is continuously 0 through a counter.

[0128] In this embodiment, by calculating the duration of the IO level signal being continuously 0, the FPGA can accurately determine the duration of the overcurrent. If the IO signal is continuously 0, it means that the circuit is in an overcurrent state. By calculating the duration of this state, the system can avoid short-term false triggering and ensure that the protection operation is performed only when the overcurrent situation persists, thereby improving the accuracy of the overcurrent protection.

[0129] In many cases, the instantaneous fluctuation of current may be temporary, such as due to load changes, instantaneous interference, etc. If the level duration is not considered, the system may trigger the protection too early, resulting in unnecessary power shutdown. By counting the duration of the IO level signal being 0, the system can effectively filter out transient interference and only perform protection actions when a continuous overcurrent does occur.

[0130] Specifically, the length threshold of the counter can be configured by a host computer, and the length threshold can be configured to be 10 μs.

[0131] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0132] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0133] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0134] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0135] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, read-only memory), random access memory (RAM, random access memory), disk or optical disk and other media that can store program code.

Claims

1. A power management circuit based on programmable output reference voltage, characterized in that: include: The first power supply voltage input terminal (VCC), NMOS tube (Q1), reference voltage input terminal (IN_REF), current limiting resistor (R1), transistor (Q2), optical coupler (U1), external control unit (U2) and voltage output terminal, wherein: The first power supply voltage input terminal (VCC) is used to input a power supply voltage, and the reference voltage input terminal (IN_REF) is used to input a reference voltage; The drain (D) of the NMOS tube is electrically connected to the first power supply voltage input terminal (VCC), One end of the current limiting resistor (R1) is connected to the emitter (E) of the transistor (Q2) and the voltage output terminal (V_OUT), and the other end is connected to the base (B) of the transistor (Q2) and the source (S) of the NMOS transistor (Q1), and the gate (G) of the NMOS transistor is electrically connected to the reference voltage input terminal (IN_REF); The anode of the input end of the optical coupler (U1) is electrically connected to the reference voltage input end (IN_REF), and the cathode of the input end of the optical coupler (U1) is electrically connected to the collector (C) of the transistor (Q2); the collector of the output end of the optical coupler (U1) is electrically connected to the external control unit (U2), and the emitter of the output end of the optical coupler (U1) is grounded; The external control unit (U2) is used to determine whether an overcurrent alarm signal is triggered according to the conduction state of the optical coupler (U1), and if the overcurrent alarm signal is triggered, the reference voltage input terminal (IN_REF) is controlled to be 0V.

2. The power management circuit based on programmable output reference voltage according to claim 1, characterized in that: The external control unit (U2) comprises an FPGA, a pull-up resistor (R2) and a second power supply voltage input terminal (VDD), one end of the pull-up resistor (R2) is electrically connected to the FPGA and the anode of the input terminal of the optical coupler (U1), and the other end of the pull-up resistor (R2) is electrically connected to the second power supply voltage input terminal (VDD).

3. The power management circuit based on programmable output reference voltage according to claim 1, characterized in that: When the voltage drop across the current limiting resistor (R1) exceeds 0.6V, the transistor (Q2) is turned on.

4. The power management circuit based on programmable output reference voltage according to claim 1, characterized in that: When the current on the current limiting resistor (R1) of the optical coupler (U1) exceeds 6A, the reference voltage input terminal (IN_REF) is reduced to make the NMOS tube (Q1) enter a semi-conducting state.

5. A control method for a power management circuit based on a programmable output reference voltage, characterized in that: Applied to a power management circuit based on a programmable output reference voltage as claimed in any one of claims 1 to 4, the control method comprises: The external control unit (U2) detects the power supply output current in real time through the optical coupler (U1) and determines the current size based on the voltage difference on the current limiting resistor (R1); When the current on the current limiting resistor (R1) exceeds a preset current threshold, the reference voltage input terminal (IN_REF) is controlled to decrease through the optical coupler (U1), thereby reducing the gate voltage of the NMOS tube (Q1); Control the NMOS tube (Q1) to enter the semi-conducting state, reducing the output voltage (V_OUT); The external control unit (U2) generates an over-current alarm signal according to the collected IO level signal, and reduces the reference voltage input terminal (IN_REF) to 0V.

6. The control method of the power management circuit based on programmable output reference voltage according to claim 5, characterized in that: The external control unit (U2) samples the IO level signal every 1 μs.

7. The control method of the power management circuit based on programmable output reference voltage according to claim 5, characterized in that: The external control unit (U2) calculates the duration during which the IO level signal is continuously 0 through a counter.

8. The control method of the power management circuit based on programmable output reference voltage according to claim 7, characterized in that: The length threshold of the counter is configured by the host computer.

9. The control method of the power management circuit based on programmable output reference voltage according to claim 5, characterized in that: The voltage drop threshold across the current limiting resistor (R1) is set to 0.6V.

10. The control method of the power management circuit based on programmable output reference voltage according to claim 5, characterized in that: The optocoupler (U1) has a fixed voltage drop of 1.2V.

11. The control method of the power management circuit based on programmable output reference voltage according to claim 8, characterized in that: The length threshold is configured as 10 μs by the host computer.

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