Active clamping flyback converter and control IC

Abstract

The invention relates to an active clamp flyback converter and a control IC. An ACF converter (10) has: a transformer (T) having a secondary winding (Ns) electromagnetically coupled to a primary winding (Np); a first series circuit in which the primary winding (Np) and the main switch (QL) are connected in series to both ends of the DC power supply (Vin); a second series circuit in which a switch (QH) and a capacitor (Cac) are connected in series to both ends of the primary winding (Np); a control unit (100a) that turns on and off the main switch (QL) and the switch (QH); a rectifying and smoothing circuit of the secondary winding; and an output voltage detection unit that detects the output voltage of the circuit. The control unit has a first drive signal for turning on and off the main switch, and second and third drive signals for turning on and off the switch (QH) during the main switch off period, and controls a first off period from the off of the first drive signal to the on of the second drive signal, and a second off period from the off of the second drive signal to the on of the third drive signal.

Description

Technical Field

[0001] The invention relates to an active clamp flyback converter and a control IC. Background Art

[0002] Conventionally, a flyback converter has been proposed as a power supply circuit for an isolated DC-DC converter. When the main switch of the flyback converter is turned on, a current flows through the primary winding of the transformer, and energy is stored in the inductance of the transformer. Then, when the main switch is turned off, the energy stored in the excitation inductance is taken out from the secondary winding of the transformer, thereby transmitting power from the primary side to the secondary side.

[0003] In order to improve the efficiency of the flyback converter, an active clamp flyback converter (ACF converter) has been proposed, which includes an RCD snubber circuit (RCD snubber circuit) formed by a clamp switch and a clamp capacitor. In addition, the RCD snubber circuit uses a capacitor to recover leakage energy and a resistor to dissipate the leakage energy, thereby suppressing surge voltage.

[0004] The ACF converter can regenerate leakage energy accumulated in the leakage inductance of the transformer and can also realize ZVS (zero volt switching) that reduces switching loss of the main switch.

[0005] As an example of such an ACF converter, a non-complementary control ACF is described in Patent Document 1. The non-complementary control ACF disclosed in Patent Document 1 does not operate the main switch and the clamp switch complementarily, but turns on the clamp switch once for a set fixed time before the main switch is turned on and after the transformer excitation current drops to zero.

[0006] In the non-complementary control ACF, when the load current decreases, the current of the leakage inductance decreases, and the voltage drop of the voltage resonance capacitor due to the shorter resonance period of the voltage resonance capacitor and the leakage inductance decreases, and ZVS cannot be achieved. In the non-complementary control ACF shown in Patent Document 1, the peak current of the excitation inductance is controlled to be approximately constant even if the load current decreases, and the off (vibration) period is extended according to the decrease in the load current, thereby achieving ZVS even if the output current decreases.

[0007] Patent Document 1: Chinese Patent Application Publication No. 101572490

[0008] However, in the power conversion device described in Patent Document 1, since the current of the excitation inductor is controlled to be constant, there is a problem that when the load is light, the energy consumption is reduced, the off period is prolonged, and the frequency is reduced to the audible range. Therefore, it is necessary to reduce the excitation inductor current according to the load current and reduce the operating frequency. Summary of the invention

[0009] The present invention is made in view of the problems of the prior art. Moreover, the present invention aims to provide an active clamp flyback converter and a control IC that can reduce the operating frequency fluctuations associated with changes in output voltage and output current and maintain zero-volt switching operation.

[0010] The active clamp flyback converter and control IC of the present invention include: a first series circuit, in which a main switch and a primary winding are connected in series at both ends of a DC power supply; a second series circuit, in which a clamp switch and a clamp capacitor are connected in series at both ends of the primary winding; a transformer, which has a secondary winding electromagnetically coupled to the primary winding; a control unit, which turns on and off the main switch and the clamp switch; a rectifying and smoothing circuit, which rectifies and smoothes the voltage of the secondary winding; and an output voltage detection unit, which detects the output voltage of the rectifying and smoothing circuit, and the control unit has a first drive signal, a second drive signal, and a third drive signal. The control unit controls a first off period and a second off period, wherein the first off period is a period during which both the main switch and the clamp switch are off from the off time of the first drive signal to the on time of the second drive signal, and the second off period is a period during which both the main switch and the clamp switch are off from the off time of the second drive signal to the on time of the third drive signal.

[0011] According to the present invention, an active clamp flyback converter and a control IC can be provided, which can reduce the fluctuation of the operating frequency accompanying the change of the output voltage and the output current and maintain the zero-volt switching operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a diagram showing the structure of the ACF converter according to the first embodiment.

[0013] Figure 2 It is a diagram showing the configuration of a control unit of the ACF converter according to the first embodiment.

[0014] Figure 3 It is a diagram showing the configuration of an enable signal generating unit of the ACF converter according to the first embodiment.

[0015] Figure 4 It is a diagram showing an operation waveform of the enable signal generating unit according to the first embodiment.

[0016] Figure 5 It is a diagram showing the characteristics of the enable signal generating unit according to the first embodiment.

[0017] Fig. 6A This is a diagram showing an example of an operation waveform of the ACF converter in the first embodiment.

[0018] Figure 6B This is a diagram showing an example of an operation waveform of the ACF converter in the first embodiment.

[0019] Figure 6C This is a diagram showing an example of an operation waveform of the ACF converter in the first embodiment.

[0020] Fig.6D This is a diagram showing an example of an operation waveform of the ACF converter in the first embodiment.

[0021] Figure 7 : is a figure which shows the structure of the exciting current detection means.

[0022] Figure 8 This is a diagram showing an example of an operation waveform when the output voltage is variable in the ACF converter according to the first embodiment.

[0023] Fig. 9 It is a diagram showing the structure of an ACF converter according to the second embodiment.

[0024] Fig.10 It is a diagram showing the configuration of an enable signal generating unit of the ACF converter according to the second embodiment.

[0025] Fig.11 This is a diagram showing an example of an operation waveform of the enable signal generating unit according to the second embodiment.

[0026] Fig.12 It is a diagram showing the characteristics of the enable signal generating unit according to the second embodiment.

[0027] Fig.13 This is a diagram showing an example of an operation waveform of the ACF converter in the second embodiment.

[0028] Fig.14 It is a diagram showing an example of the operation waveform of the ACF converter in the first embodiment and the second embodiment.

[0029] Fig.15 It is a diagram showing the change in operating frequency with respect to output current in the first embodiment and the second embodiment.

[0030] Description of symbols

[0031] Vin: DC power supply; QL: main switch; QH: clamp switch; T: transformer; Np: primary winding; Ns: secondary winding; Na: auxiliary winding; Lm: excitation inductance; Llk: leakage inductance; Cac: clamp capacitor; Cv: voltage resonance capacitor; BDL, BDH: body diode; Ds: rectifier element; Co: output capacitor; Ca: capacitor; Ra1, Ra2: resistor; Rs: Id detection unit; VgsL, VgsH: drive signal; 10: ACF converter; 100a, 100b: control unit; 111: Output voltage detection unit; 112: zero-crossing detection unit; 113: excitation current detection unit; 114, COMosc; comparator; 115: SR latch; 121: P1 generation unit; 122: P2 generation unit; 130a, 130b: enable signal generation unit; 131: subtraction circuit; 141: P0 timing generation unit; 142: disable signal generation unit; 143: P2 delay unit; 144: P1 threshold generation unit; 151: 1st drive unit; 152: 2nd drive unit; 200: output voltage detection unit. DETAILED DESCRIPTION

[0032] Hereinafter, active clamp flyback converters (ACF converters 10) according to several embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same or corresponding parts in the drawings of the drive circuits of the various embodiments are marked with the same reference numerals and their descriptions are omitted. In addition, in the present embodiment, the active clamp flyback converter corresponds to the ACF converter 10.

[0033] The present invention relates to a main switch QL (refer to Figure 1 ) during the off period of the clamp switch QH (refer to Figure 1 ) The structure of ACF and its control method in ACF control (hybrid ACF control) that is turned on and off twice.

[0034] (ACF converter 10)

[0035] The flyback converter is one of the power supply circuit topologies of the isolated DC-DC converter. When the main switch of the flyback converter is turned on, the current flows through the primary winding of the transformer, and energy is stored in the inductance of the transformer. Then, when the main switch is turned off, the energy stored in the excitation inductance is taken out from the secondary winding of the transformer, thereby transmitting power from the primary side to the secondary side.

[0036] However, there is uncoupled leakage inductance between the primary winding and the secondary winding of the transformer. In the flyback converter, when the main switch is turned on, current flows through the leakage inductance, and energy is stored.

[0037] Since the leakage energy accumulated in the leakage inductance does not generate a back electromotive force in the direction of turning on the rectifier connected to the secondary winding after the main switch is turned off, the leakage energy cannot be transferred from the secondary winding to the secondary side. Therefore, the back electromotive force of the leakage inductance may generate a high surge voltage at both ends of the turned-off main switch, causing damage to the main switch.

[0038] For example, when a MOSFET is used as the main switch, when the surge voltage exceeds the withstand voltage of the MOSFET, an avalanche breakdown occurs, and the MOSFET may be damaged. In general, in order to suppress the surge voltage, an RCD snubber circuit consisting of a capacitor, a resistor, and a diode is connected to both ends of the primary winding of the transformer.

[0039] The RCD snubber circuit recovers leakage energy using a capacitor and dissipates the leakage energy using a resistor, thereby suppressing surge voltage. Therefore, one of the issues regarding improving the efficiency of a flyback converter is the regeneration of leakage energy.

[0040] Another issue for improving the efficiency of a flyback converter is the reduction of switching losses. For example, when a MOSFET is used as the main switch in a flyback converter, a parasitic capacitance Coss of the MOSFET exists between the drain and source of the MOSFET. When the MOSFET is turned on, a voltage Vds(0) is present across the drain and source, and 1 / 2Coss×Vds(0) is accumulated in the parasitic capacitance Coss. 2 energy.

[0041] When the MOSFET is turned on, this energy becomes a loss due to the on-resistance of the MOSFET. As a method to reduce this switching loss, a zero-volt switch (ZVS) is known, which makes the voltage across the switch zero volts when the switch is turned on. ZVS makes the voltage Vds(0) across the switch zero volts when the switch is turned on. Therefore, 1 / 2Coss×Vds(0) 2 Therefore, ZVS can be used as a problem for improving the efficiency of the flyback converter.

[0042] In order to improve the efficiency of a flyback converter, an active clamp flyback converter (ACF converter) has been proposed in which an RCD snubber circuit is constituted by a clamp switch and a clamp capacitor.

[0043] The first advantage of the ACF converter is that it can regenerate the leakage energy accumulated in the leakage inductance of the transformer. In addition, the second advantage of the ACF converter is that it can achieve ZVS of the main switch. Therefore, the ACF converter is effective as a topology of an efficient power supply circuit.

[0044] The regeneration of leakage energy of the ACF converter temporarily moves the leakage energy accumulated during the on-time of the main switch to the clamp capacitor after the main switch is turned off. When the clamp switch is turned on, the energy moved to the clamp capacitor is applied to the primary winding of the transformer. The voltage applied to the primary winding is in a direction that turns on the diode connected to the secondary winding, so the leakage energy can be regenerated as output.

[0045] In addition, ZVS requires discharging the capacitive components equivalently connected to both ends of the main switch. For example, when the main switch and clamp switch are MOSFETs, the capacitive components are equivalent to their respective Coss, and when the secondary-side rectifier is a diode, the capacitive components are equivalent to its coupling capacitance, the transformer winding capacitance, etc.

[0046] In the ACF converter, by turning on the clamp switch, the voltage of the clamp capacitor can be applied to the primary winding of the transformer in the opposite direction to the power supply voltage, and a negative current can flow through the magnetizing inductance and leakage inductance. The voltage resonance capacitor can be discharged by the current flowing through the magnetizing inductance and leakage inductance in the negative direction, and ZVS can be achieved.

[0047] However, in the ACF converter, when the clamp switch is turned on, the resonance between the leakage inductance and the resonance period Tcalk of the clamp capacitor occurs, and the difference between the resonance current and the excitation current flows from the secondary winding as the secondary side current. Therefore, various problems arise in relation to the resonance period Tcalk and the on-period of the clamp switch.

[0048] The ACF converter 10 of the present embodiment can overcome the above-mentioned problems, and can reduce the fluctuation of the operating frequency accompanying the change of the output voltage and the output current, and can maintain the zero-volt switching operation.

[0049] (First embodiment)

[0050] Figure 1 1 is a diagram showing the structure of the ACF converter 10 according to the first embodiment. Figure 2 2 is a block diagram of a control unit 100a that controls the ACF converter 10. The control unit 100a corresponds to a control IC.

[0051] The ACF converter 10 of the first embodiment includes a first series circuit in which a main switch QL and a primary winding Np of a transformer T are connected in series at both ends of a DC power supply Vin. In addition, the ACF converter 10 includes a second series circuit in which a clamp switch QH and a clamp capacitor Cac are connected in series at both ends of the primary winding Np.

[0052] The main switch QL and the clamp switch QH are formed of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and have body diodes BDL and BDH between the drain and the source, respectively.

[0053] In addition, MOSFET has a parasitic capacitance Coss between the drain and source, and this capacitance appears in the resonant operation. Figure 1 In FIG. 1 , an example is shown in which the parasitic capacitance Coss is connected to both ends of the main switch QL as the voltage resonance capacitor Cv, but it is also possible to use a capacitor other than the parasitic capacitance Coss of the MOSFET without adding another capacitor.

[0054] In addition, the main switch QL and the clamp switch QH may also be switch elements of compound semiconductors such as GaN (Gallium Nitride) and SiC (silicon carbide). In addition, the main switch QL and the clamp switch QH may also be composed of IGBT (Insulated Gate Bipolar Transistor). In addition, when the element structure does not have a body diode, it can be replaced by adding BDL and BDH. In this specification, for the sake of convenience, the main switch QL and the clamp switch QH are set to MOSFET.

[0055] Furthermore, the ACF converter 10 includes a transformer T including a primary winding Np and a secondary winding Ns electromagnetically coupled to the primary winding Np. The transformer T is configured to have an excitation inductance Lm and a leakage inductance Llk in the primary winding Np, and to have a coupling coefficient between the primary winding Np and the secondary winding Ns that is less than 1. Furthermore, a first rectifier circuit is connected to both ends of the secondary winding Ns, in which a rectifier element Ds and an output capacitor Co are connected in series and the voltage of the secondary winding Ns is rectified and smoothed. Furthermore, the first rectifier circuit corresponds to a rectifier-smoothing circuit.

[0056] Furthermore, the transformer T includes an auxiliary winding Na, and a second rectifying circuit including a rectifying element Da and a capacitor Ca connected in series is connected to both ends of the auxiliary winding Na.

[0057] Furthermore, the ACF converter 10 includes an output voltage detection unit 200 that detects an output capacitor voltage, a winding voltage detection unit that detects a winding voltage, and an Id detection unit Rs that detects a current of the main switch QL.

[0058] Furthermore, the ACF converter 10 includes a control unit 100a for controlling the main switch QL and the clamp switch QH. The controller 100a controls the main switch QL and the clamp switch QH based on the Vfb signal detected by the output voltage detector 200, the voltage Vcc detected by the winding voltage detection unit, and the ISense signal which is the output signal detected by the Id detection unit Rs. Specifically, the control unit 100a turns on and off the main switch QL, and turns on and off the clamp switch QH twice by the first pulse and the second pulse during the off period of the main switch QL.

[0059] The control unit 100a includes a current source Icc, and generates a Vfb signal indicating a feedback voltage based on an output signal of the output voltage detection unit 200. The control unit 100a further includes a comparator 114 for comparing the ISense signal with the Vfb signal.

[0060] The comparator 114 is connected so that when the value of the ISense signal exceeds the value of the Vfb signal, it becomes High (high level) and is output to the R terminal of the SR-FF 115 (SR flip-flop). In addition, the POS signal is input to the S terminal of the SR-FF 115, so that a P0 signal is output that sets the output of the SR-FF 115 to High using the falling edge of the POS signal and sets the output of the SR-FF 115 to Low (low level) using the output of the comparator 114.

[0061] In addition, the control unit 100a includes a first drive unit 151, which receives the P0 signal and generates a signal for driving the main switch QL. The first drive unit 151 controls the on-width of the drive signal VgsL for the main switch QL, thereby controlling the output voltage to a constant voltage. In addition, the drive signal VgsL corresponds to the first drive signal.

[0062] Furthermore, the control unit 100a includes an output voltage detection unit 111 that receives the auxiliary winding voltage Vna, generates a VoD signal indicating a voltage proportional to the output voltage, and outputs the VoD signal to the P1 threshold generation unit 144. The VoD signal corresponds to the second voltage signal.

[0063] In addition, the control unit 100a has a zero-crossing detection unit 112, which receives the auxiliary winding voltage Vna and outputs a ZCD signal to the P2 delay unit 143. The ZCD signal is a pulse signal of zero voltage that detects that the voltage of the auxiliary winding Na changes from a negative voltage to a positive voltage. In addition, the ZCD signal is equivalent to a zero-crossing signal.

[0064] Furthermore, the control unit 100a includes an excitation current detection unit 113 that receives the auxiliary winding voltage Vna, generates an LmC signal indicating a voltage proportional to the excitation current, and outputs the LmC signal to the P1 generation unit 121. The LmC signal corresponds to the first voltage signal.

[0065] The P1 threshold value generating unit 144 generates a threshold value signal Vth1 multiplied by a preset ratio based on the VoD signal outputted from the output voltage detecting unit 111, and outputs the threshold value to the P1 generating unit 121 so that the threshold value becomes a value represented by the threshold value signal Vth1 described later. That is, when the value of the VoD signal increases or decreases, the value of the threshold value signal Vth1 also increases or decreases proportionally. In addition, the P1 threshold value generating unit 144 is equivalent to the first pulse threshold value generating unit.

[0066] The P1 generating unit 121 turns the signal P1 High and sends a signal of a preset pulse width based on the LmC signal of the exciting current detecting unit 113 and the threshold signal Vth1 of the P1 threshold generating unit 144. The P1 generating unit 121 corresponds to the first pulse generating unit.

[0067] Here, the preset ratio in the P1 threshold value generating unit 144 and the preset pulse width in the P1 generating unit 121 are determined as follows: In addition, the time when the excitation current becomes zero is referred to as time tz.

[0068] The timing at which the P1 signal generated by the P1 generation unit 121 becomes High is 0.5×Tcalk to 1.22×Tcalk before the time tz. In the present embodiment, Tcalk represents the resonance period. The P1 signal corresponds to the first pulse signal.

[0069] The timing at which the P1 signal goes Low is made earlier than time tz. The pulse width of the P1 signal is set to be greater than 0.5×Tcalk. The threshold signal Vth1 of the P1 threshold generation unit 144 and the pulse width of the P1 generation unit 121 are determined so as to generate the P1 signal of such a pulse width.

[0070] By making the above settings, even if the output voltage changes, the timing when the P1 signal becomes High is earlier than the above 0.5×Tcalk to 1.22×Tcalk, and the timing when the P1 signal becomes Low is earlier than the time tz when the excitation current becomes zero. In addition, when the output voltage does not change, the threshold signal Vth1 can be a threshold voltage predetermined in a manner to achieve the timing described above. The predetermined threshold voltage is equivalent to the third voltage signal.

[0071] Furthermore, the control unit 100a includes a disable signal generating unit 142. The disable signal generating unit 142 outputs a disable signal Dis to the P2 delay unit 143. The disable signal Dis becomes High by the POS signal and becomes Low after a preset delay time after receiving the P1 signal.

[0072] Furthermore, the control unit 100a includes a P2 delay unit 143. The P2 delay unit 143 is reset by the POS signal and outputted with an Enb signal which is a pulse signal based on the Vfb signal indicating the feedback voltage.

[0073] In addition, the P2 delay unit 143 receives the Dis signal, the Enb signal, and the ZCD signal, and uses the ZCD signal when the Dis signal is Low and the Enb signal is High as a trigger to output the P2Dy signal to the P2 generation unit 122. The P2 delay unit 143 corresponds to a second pulse delay unit.

[0074] Furthermore, the control unit 100a includes a P2 generation unit 122, which receives the P2Dy signal, outputs a P2 signal of a preset pulse width, and outputs it to the second driving unit 152. The P2 generation unit 122 corresponds to a second pulse generation unit, and the P2 signal corresponds to a second pulse signal.

[0075] In addition, the control unit 100a has a second driving unit 152, which receives the P1 signal and the P2 signal and outputs a driving signal VgsH twice, and the driving signal VgsH drives the clamp switch QH of the ACF converter 10. The first driving signal VgsH is output according to the P1 signal. In addition, the second driving signal VgsH is output according to the P2 signal. In addition, the first driving signal VgsH is equivalent to the second driving signal, and the second driving signal VgsH is equivalent to the third driving signal.

[0076] Figure 3 1 is a diagram showing a configuration of an enable signal generating unit 130a of the control unit 100a according to the first embodiment. The enable signal generating unit 130a includes a reference voltage Vosc and a subtraction circuit 131 that outputs a voltage VT obtained by subtracting a value of a Vfb signal indicating a feedback voltage from the reference voltage Vosc.

[0077] Furthermore, the enable signal generating unit 130a includes a VRamp circuit. The VRamp circuit includes a reference current Iosc, a capacitor Cosc charged by the reference current Iosc, and a switch Sosc for resetting the capacitor Cosc, which are connected in parallel.

[0078] In the VRamp circuit, when the POS signal becomes L, the reference current Iosc charges the capacitor Cosc to generate the ramp voltage VR. In addition, the enable signal generating unit 130a has a comparator COMosc that connects VT to the -terminal (negative terminal) and the ramp voltage VR to the +terminal (positive terminal), and sends out the Enb signal as a pulse signal. When the ramp voltage VR exceeds the voltage VT, the Enb signal becomes High.

[0079] Figure 4 2 is a diagram showing an operation waveform of the enable signal generating unit 130 a .

[0080] exist Figure 4 In FIG. 1 , (a) to (d) show the operation waveforms when the output current increases as the output current increases toward the right side of the drawing. Figure 4 In the example shown, it is shown that the value of the Vfb signal rises as the output current increases according to the configuration of the output voltage detection unit 200 and the control unit 100 a .

[0081] Since the reference current Iosc is a preset current source, Figure 4 , the slope of the ramp voltage VR increases constantly. As the output current increases, the value of the Vfb signal increases. When the difference with the reference voltage Vosc decreases, the voltage VT decreases, and thus the time required for the Enb signal to become High becomes shorter. When the value of the Vfb signal is higher than the reference voltage Vosc, it becomes High at the time when the POS signal becomes Low.

[0082] Figure 5 It is shown Figure 3 The horizontal axis is the value of the Vfb signal showing the feedback voltage, and the vertical axis is the time Enb_Delay from when the switch Sosc is turned off to when the Enb signal becomes High.

[0083] As described above, the reference current Iosc is a preset current source, and the slope of the ramp voltage VR increases constantly. In addition, the voltage VT is the difference between the preset reference voltage Vosc and the value of the Vfb signal. Therefore, Figure 5 As shown, the characteristics of the enable signal generating unit 130a are controlled so that the time Enb_Delay from the time when the switch Sosc is turned off to the time when the Enb signal becomes High is proportional to the negative value of the Vfb signal. In addition, the time Enb_Delay is expressed by the following formula (1). In addition, a and b are values ​​that satisfy the conditions of a<0, B>0, and are expressed by the following formulas (2) and (3).

[0084] [Formula 1]

[0085] Enb_Delay=a×Vfb+b…(1)

[0086] [Formula 2]

[0087] a=-(Cosc / Iosc)…(2)

[0088] [Formula 3]

[0089] b=Cosc·(Vosc / Iosc)…(3)

[0090] Figure 6A to Figure 6D 1 is a diagram showing the operation waveform of the ACF converter 10 according to the first embodiment. Figure 6A to Figure 6D In the figure, it is shown that as Fig. 6A Go Fig.6D The operation waveform when the output current decreases. According to the configuration of the output voltage detection unit 200 and the control unit 100a, the value of the Vfb signal indicating the feedback voltage decreases as the output current decreases.

[0091] Fig. 6A An example of a case where the output current is large is shown, and an operation waveform is shown when the value of the Vfb signal is higher than the reference voltage Vosc.

[0092] In period T1, at time t1, the P0S signal changes from High to Low, and the SR-FF 115 is set. When the P0 signal becomes High, the drive signal VgsL becomes High, and the main switch QL is turned on, the current of the main switch QL increases, and the value of the ISense signal rises.

[0093] When the value of the ISense signal reaches the value of the Vfb signal at time t2 , the output of the comparator 114 becomes High, the SR-FF 115 is reset, the P0 signal becomes Low, the drive signal VgsL becomes Low, and the main switch QL is turned off.

[0094] In the period T1, the DC power supply Vin is connected to a series circuit of the leakage inductance Llk and the excitation inductance Lm, so the current Itran of the primary winding Np of the transformer T increases with time as expressed by the following equation (4). In addition, the leakage inductance Llk and the excitation inductance both accumulate the current Itran.

[0095] [Formula 4]

[0096] Regarding Itran, Itran = {Vin / (Lm+Llk)}×t…(4)

[0097] In addition, the auxiliary winding voltage Vna generates a negative voltage proportional to the input voltage.

[0098] Figure 7The excitation current detection unit 113 is composed of an operational amplifier. Figure 7 The integration circuit shown in the figure integrates the auxiliary winding voltage Vna, and the excitation current detection unit 113 outputs an LmC signal representing a voltage proportional to the excitation current.

[0099] exist Figure 6A to Figure 6D In the example shown, the auxiliary winding voltage Vna changes from negative to positive through zero crossing at time t2.

[0100] exist Fig. 6A In the example, since the value of the Vfb signal is higher than the reference voltage Vosc, the voltage VT of the enable signal generating unit 130a is zero, and the Enb signal indicating enablement becomes High. However, since the Dis signal indicating disablement is High, the output of the P2 delay unit 143 remains zero.

[0101] In the period T2, when the main switch QL is turned off at time t2, the energy accumulated in the magnetizing inductance Lm and the leakage inductance Llk generates a counter electromotive force.

[0102] Since the leakage inductance Llk is not coupled to the secondary winding Ns, it is charged into the clamp capacitor Cac together with a part of the energy of the exciting inductance Lm, and is not output from the secondary winding Ns to the first rectifier circuit.

[0103] On the other hand, since the magnetizing inductance Lm is an inductance coupled to the secondary winding Ns, the counter electromotive force is generated in a direction to turn on the rectifier element Ds, which is a diode connected to the secondary winding Ns of the transformer T. In addition, the surplus energy of the magnetizing inductance Lm charged in the clamp capacitor Cac is output to the first rectifier circuit. Then, when the leakage energy is fully charged in the clamp capacitor Cac at time t3, the energy of the magnetizing inductance Lm is fully output to the secondary side.

[0104] In the conventional complementary control, the clamp switch QH is turned on during the period T2 , but in the ACF converter 10 of the present embodiment, the clamp switch QH is not turned on during the period T2 , which is different from the conventional complementary control.

[0105] However, when the load current decreases and the value of the Vfb signal decreases, the period T1 becomes shorter. As a result, when the maximum value of the LmC signal approaches the value of the threshold signal Vth1, the clamp switch QH may be turned on during the period T2. However, such an operation is also included in the scope of this embodiment.

[0106] In the period T3, at time t3, the energy accumulated in the leakage inductance Llk becomes zero, and the energy accumulated in the magnetizing inductance Lmz is output from the secondary winding Ns to the first rectifier circuit.

[0107] Since the energy stored in the excitation inductance Lm is output from the secondary winding Ns to the first rectifier circuit during the periods T2 and T3, a voltage proportional to the output voltage is generated in the auxiliary winding voltage Vna, and the output of the excitation current detection unit 113 decreases in proportion to the excitation current.

[0108] In the period T4 , at time t4 , when the value of the LmC signal decreases and becomes equal to the value of the threshold signal Vth1 , the P1 generating unit 121 turns on the clamp switch QH.

[0109] Since the energy of the magnetizing inductance Lm is output to the secondary side, when the clamp switch QH is turned on, a resonant current flows between the clamp capacitor Cac and the leakage inductance Llk.

[0110] Therefore, the P1 generation unit 121 has an on width of 1 / 2 or more of Tcalk, where Tcalk represents the resonance period of the clamp capacitor Cac and the leakage inductance Llk. In addition, the time t6 when the excitation current becomes zero is set as time tz, the P1 threshold generation unit 144 sets the threshold signal Vth1, and the P1 generation unit 121 sets the pulse width of the P1 signal so that the P1 signal is turned off between (tz-0.72Tcalk) and time tz.

[0111] In period T5, after 1 / 2Tcalk has passed since the clamp switch QH was turned on, the resonant current is limited by the excitation current and flows to the clamp capacitor Cac through the clamp switch QH. The P1 signal is generated as described above to turn on the clamp switch QH, so that the resonant current does not flow when the clamp switch QH is turned on for the second time.

[0112] Furthermore, during the period T5 , current flows from the source to the drain of the clamp switch QH.

[0113] Since the P1 signal is generated under the above conditions, the P1 signal is turned off during period T5. Even if the clamp switch QH is turned off during this period, the current path does not change because the current is commutated to the body diode BDH after turning off. At time t6, when the excitation current becomes zero, period T5 ends.

[0114] Regarding the period T6, at time t6, the excitation current becomes zero, but since the clamp switch QH is turned off, the excitation current does not flow in the negative direction as in the complementary control. Therefore, resonance occurs between the voltage resonance capacitor Cv and the excitation inductance Lm and leakage inductance Llk of the primary winding Np of the transformer T. As a result, the main switch QL, the clamp switch QH, and the voltage of each winding vibrate at the resonance period Tcvlm.

[0115] The disable signal generating unit 142 is set to become Low after a preset delay time has passed since the P1 signal is turned off. In this embodiment, since the P1 signal is turned off based on the time when the excitation current becomes zero, the preset delay time is set to detect the first zero crossing after the excitation current becomes zero. Figure 6A to Figure 6D In the example shown, the delay time is set immediately after time t6 when the exciting current becomes zero.

[0116] exist Fig. 6A In the example, since the value of the Vfb signal indicating the feedback voltage is higher than the reference voltage Vosc, the voltage VT of the enable signal generating unit 130a is zero, and the Enb signal has become High.

[0117] The P2 delay unit 143 receives the ZCD signal after the Enb signal is High and the Dis signal becomes Low, and sends a signal with a preset pulse width. Fig. 6A In the embodiment, a signal P2Dy having a preset pulse width is outputted based on the ZCD signal after the Dis signal becomes Low. The signal P2Dy corresponds to the second pulse delay signal.

[0118] Here, regarding the preset pulse width, since the ZCD signal detects the zero crossing from negative to positive of the auxiliary winding voltage Vna oscillating with a period of Tcvlm, the pulse width of the P2Dy signal is preset to Tcvlm / 4. As a result, the time t7 of the edge of the pulse signal of the P2Dy signal becomes the minimum value of the voltage across the clamp switch QH.

[0119] In this example, the case where the zero-crossing detection unit 112 detects the zero-crossing of the auxiliary winding voltage Vna from negative to positive and the P2Dy signal is Tcvlm / 4 is described. The zero-crossing detection unit 112 detects the zero-crossing of the auxiliary winding voltage Vna from positive to negative, and even if the pulse width of the P2Dy signal is set to (3 / 4)×Tcvlm, the edge of the pulse signal of the P2Dy signal becomes the time t7. In addition, the edge of the pulse signal of the P2Dy signal becomes the minimum value of the voltage across the clamp switch QH. That is, the P2 delay unit 143 sets the pulse width of the P2 signal according to the polarity of the ZCD signal.

[0120] The clamp switch QH is turned on during the period T7 to flow the negative excitation current. The time t7 is the edge of the P2Dy signal. The P2 generation unit 122 generates a signal P2 of a preset pulse width using the edge of the P2Dy signal and outputs it to the second drive unit 152 .

[0121] Here, the preset pulse width is set so that all the energy charged in the voltage resonance capacitor Cv can be discharged by utilizing the energy accumulated by the negative current flowing through the primary winding inductance of the transformer T in the period T7.

[0122] The on timing of the clamp switch QH of the ACF converter 10 of the first embodiment is the same as that of the general non-complementary control, but the resonant current does not flow. Therefore, when the voltage of the clamp capacitor Cac is set to Vac, the on width Ton2 of the P2 signal for the voltage resonant capacitor Cv to become zero is expressed by the following formula (5).

[0123] [Formula 5]

[0124]

[0125] Here, when the minimum value of the input voltage is Vinmin and the maximum value is Vinmax, Ton2max when the input voltage is the maximum value is expressed by the following equation (6).

[0126] [Formula 6]

[0127]

[0128] Thus, the P2 generation unit 122 generates a P2 signal having a preset pulse width Ton2max using the edge of the P2Dy signal and outputs it to the second driving unit 152 , thereby achieving ZVS even when the input voltage drops.

[0129] In addition, the above is an example of setting, and the on-width given by the above formula when the input voltage is Vintyp smaller than Vinmax can also be pre-set to Ton2typ. In this case, when the input voltage is at the maximum value, it is turned on at the minimum point of the voltage instead of at ZVS, but it has the advantage of being able to reduce the current in the negative direction and achieve higher efficiency when the input voltage is below Vtyp.

[0130] Furthermore, since the voltage Vac of the clamp capacitor is N=Np / Ns times the output voltage Vo, Vac=N·Vo becomes, and Ton2 is expressed by the following equation (7).

[0131] [Formula 7]

[0132]

[0133] Therefore, the P2 generation unit 122 uses a unit that detects the input voltage and the output voltage and corrects Ton2 under the input and output conditions, thereby achieving the best ZVS, and the input voltage changes, which can form a high-efficiency power supply.

[0134] In period T8, the P0 timing generating unit 141 sends a P0S signal of a preset pulse width according to the edge of the P2 signal. The P0 signal becomes High by the edge of the P0S signal, and the main switch QL is turned on, thereby ending.

[0135] When the clamp switch QH is turned off at time t8, the voltage resonance capacitor Cv is discharged by the negative current flowing through the inductance of the primary winding Np.

[0136] During this period T8, the inductance component of the primary winding Np resonates with the voltage resonance capacitor Cv. When the resonance period is set to Tcvlm, the time DT from when the voltage of the main switch QL drops due to the voltage resonance and the clamp switch QH is turned off to when the resonance voltage reaches the minimum point is expressed by the following equation (8).

[0137] [Formula 8]

[0138]

[0139] Here, when Vac=N·Vo, Vo=20V, Vin=300V, and N=7, DT=Tcvlm / 3 is achieved, and the P0 timing generation unit 141 sends a POS signal with a preset pulse width of Tcvlm / 3 according to the edge of the P2 signal, thereby achieving ZVS.

[0140] Furthermore, since Vac=N·Vo, the P0 timing generating unit 141 detects the input voltage and the output voltage and corrects the pulse width of the POS signal under the input and output conditions, thereby achieving the best ZVS and varying the input voltage to form an efficient power supply.

[0141] Figure 6B and Figure 6C Shows the output current ratio Fig. 6A An example of a small case is an operation waveform when the value of the Vfb signal becomes a value slightly lower than the reference voltage Vosc.

[0142] As the value of the Vfb signal decreases, the current peak value of IdL decreases accordingly, shortening the period T1. In addition, the peak value of the LmC signal of the excitation current detection unit 113 also decreases, shortening the discharge period of the excitation current, that is, the period from time t2 to time t6.

[0143] Since the value of the Vfb signal is less than the reference voltage Vosc, the enable signal generating unit 130a outputs a voltage VT based on the difference between the reference voltage Vosc and the value of the Vfb signal. Fig. 6A In the example, at time t1, the Enb signal is High, but Figure 6BIn the example, after time t3 after time Enb_Delay from time t1, Enb signal becomes High. However, since P1 signal is not sent at this time, and Dis signal is released after P1 signal, Figure 6B Also in FIG. 1 , the clamp switch QH is turned on at the timing when the voltage oscillation first reaches the maximum value after the Dis signal becomes Low.

[0144] Even if the output current changes, the resonant period Tcvlm, the leakage inductance Llk and the resonant period Tcalk of the clamping capacitor Cac remain unchanged.

[0145] Period T2 is approximately 1 / 4 of Tcalk, period T4 is 1 / 2 of Tcalk, and period T6 is Tcvlm, which is almost unchanged even if the output current changes. In addition, the pulse width of the P2 signal and the POS signal and period T5 are also preset and unchanged, but periods T1 and T3 are shortened, and the operating frequency increases.

[0146] exist Figure 6C The example shown shows the output current ratio Figure 6B The example shown is further reduced in the operation waveform when the value of the Vfb signal becomes lower than the reference voltage Vosc. As the value of the Vfb signal decreases, the current peak value of IdL further decreases, and the period T1 further shortens.

[0147] However, since the value of the Vfb signal is smaller than the reference voltage Vosc, the voltage VT based on the difference between the reference voltage Vosc and the value of the Vfb signal increases in the enable signal generating unit 130a, and the Enb_Delay time increases. In addition, Enb becomes High at a time later than the time when the Dis signal becomes Low. Therefore, according to the ZCD signal after the Enb signal becomes High, the P2Dy signal is sent out, and the P2 signal that is turned on is output. Figure 6C In the example shown, the clamp switch QH is turned on at the maximum value of the third voltage oscillation. Therefore, the periods T1 and T3 are shortened, but the period T6 is lengthened, and the operating frequency is reduced.

[0148] Fig.6D Shows the output current ratio Figure 6C As an example of a further decrease, an operation waveform is shown when the value of the Vfb signal becomes lower than the reference voltage Vosc.

[0149] As the value of the Vfb signal decreases, the current peak value of IdL further decreases accordingly, the period T1 further shortens, and the periods T1 and T3 shorten. However, the period T6 lengthens, and the operating frequency further decreases.

[0150] As described above, the active clamp converter and its control IC in the present invention control the on width of the main switch as in the conventional control technique when the value of the Vfb signal decreases along with the decrease in the output current, and controls the first off period from time t2 when the main switch QL is turned off to time t4 (turn-on time) when the clamp switch QH is turned on. The second off period from time t5 when the clamp switch QH is turned off to time t7 when the clamp switch QH is turned on is controlled. In addition, in the first off period and the second off period, both the main switch QL and the clamp switch QH are turned off.

[0151] Therefore, when the output current is lowered compared to the conventional non-complementary control ACF, the peak current of IdL can be reduced and the frequency can be lowered, thereby suppressing the frequency fluctuation.

[0152] In addition, the ACF converter 10 turns on the clamp switch QH for the second time in order to make the main switch QL perform ZVS, but it is not affected by the resonant current Tcalk representing the resonant period. Therefore, the ACF converter 10 can control the second turn-on width in response to the input and output voltages using the input voltage and the output voltage. That is, the ACF converter 10 of this embodiment has the following advantages: ZVS can be achieved in a wide input range, and a high-efficiency and low-noise power supply can be achieved.

[0153] (Variation Example)

[0154] Furthermore, the ACF converter 10 of the present embodiment proposes that even a power supply device with a variable output voltage can realize control such as ZVS. Figure 8 The operation waveforms when the output voltage is increased or decreased without changing the output current in the first embodiment are shown.

[0155] Figure 8 (b) is related to Figure 6B The same conditions. In addition, Figure 8 (a) is the operating waveform when the output voltage is set to 2 times. And, Figure 8 (c) is the operating waveform when the output voltage is set to 1 / 2.

[0156] When the output voltage increases or decreases, the output voltage of the excitation current detection unit 113, ie, the slope of the LmC signal when it decreases, also increases or decreases in proportion to the output voltage.

[0157] However, the P1 threshold value generating unit 144 generates the threshold signal Vth1 obtained by multiplying the VoD signal representing the output of the output voltage detecting unit 111 by a preset ratio. Therefore, when the value of the VoD signal as the output voltage increases or decreases, the value of the threshold signal Vth1 also increases or decreases proportionally. Therefore, even if the value of the VoD signal as the output voltage changes, the P1 generating unit 121 turns the clamp switch QH on and off at the same timing.

[0158] In the enable signal generating unit 130a of the first embodiment, as shown in FIG. Figure 8 As shown in (c), the output voltage decreases, and the power transmitted to the secondary side decreases. Therefore, Vfb decreases, which reduces the peak value of IdL and becomes a control to adjust the power transmitted to the secondary side. In addition, the value of the Vfb signal decreases, so Enb_Delay becomes longer.

[0159] As the output voltage drops, the period T1 becomes shorter and the period T3 becomes longer, but since the time Enb_Delay becomes longer, the period T6 becomes longer unnecessarily, and the frequency decreases. That is, when the operating frequency is low, the components such as capacitors and transformers become larger, so it is preferred that the operating frequency fluctuates less. Therefore, in a power supply device that needs to make the output voltage variable, the operating frequency is required to fluctuate less.

[0160] (Second embodiment)

[0161] In the enable signal generating unit 130b (see Fig. 9 ) in which the operating frequency is controlled with little variation in response to changes in the output voltage, thereby forming a compact and efficient power supply.

[0162] Fig. 9 FIG. 1 is a block diagram of a control unit 100 b of an ACF converter 10 according to the second embodiment. Figure 2 The difference is that the VoD signal is added as an input to the enable signal generating unit 130b. That is, the enable signal generating unit 130b of the second embodiment obtains the value of the VoD signal.

[0163] also, Fig.10 1 is a diagram showing a configuration of an enable signal generating unit 130 b of a control unit 100 b according to the second embodiment.

[0164] Fig.10 and Figure 3The difference between the enable signal generating units 130a and 130b is that the reference voltage Vosc is set to a voltage k·VoD and Voffset proportional to the value of the VoD signal. In addition, the difference between the enable signal generating units 130a and 130b is that the reference current Iosc is set as a current source proportional to the reference voltage Vosc, and is set to n·Vosc=n·(k·VoD+Voffset).

[0165] The characteristic lies in that the reference voltage Vosc and the reference current Iosc to be compared with the value of the Vfb signal are controlled by the VoD signal of the output voltage detection unit 111 .

[0166] Fig.11 yes Fig.10 The action waveform of the enable signal generating unit. Fig.11 (a) to (c) are the operating waveforms when the value of the Vfb signal is zero. Fig.11 (a) shows the operating waveform when the output voltage is 2×Vo. Fig.11 (b) shows the action waveform when the output voltage is Vo. Fig.11 (c) shows the operation waveform when the output voltage is Vo / 2.

[0167] The reference voltage Vosc is a voltage obtained by adding the voltage of the VoD signal to the Voffset voltage by multiplying it by k. The ramp voltage VR charges the capacitor Cosc by a current source proportional to the voltage of the reference voltage Vosc, so the higher the reference voltage Vosc, the greater the slope.

[0168] Since the voltage VT is equal to the reference voltage Vosc when the value of the Vfb signal is zero, the time required for the ramp voltage VR to be equal to the voltage VT does not change even if the output voltage changes. In addition, the value of the Vfb signal at the time when the time Enb_Delay becomes zero is when the voltage VT is zero, so the lower the value of the VoD signal is, that is, the lower the output voltage Vo is, the smaller it is.

[0169] therefore, Fig.10 The characteristics of the enable signal generating unit 130b are as follows Fig.12 shown. Fig.12 is a diagram showing the characteristics of the enable signal generating unit 130 b , wherein the horizontal axis represents the value of the Vfb signal and the vertical axis represents the time Enb_Delay.

[0170] like Fig.12 As shown, the characteristics of the enable signal generating unit 130b of the second embodiment have the following features.

[0171] The time Enb_Delay from when the switch Sosc is turned off to when the Enb signal becomes High is controlled to be negatively proportional to the value of the Vfb signal. In addition, it is characterized in that the time Enb_Delay when the value of the Vfb signal is zero is constant even if the output voltage changes, and the absolute value of the proportionality coefficient decreases as the output voltage increases.

[0172] Fig.13 Shown in Fig. 9 Operation waveforms when the output voltage is increased or decreased without changing the output current in the control unit 100b of the second embodiment.

[0173] Fig.13 (b) is the output voltage of Figure 8 (b) The action waveform at the same Vo. Fig.13 (a) is the output voltage and Figure 8 (a) The same action waveform at 2Vo. Fig.13 (c) is the output voltage of Figure 8 (c) The action waveform at the same Vo / 2.

[0174] exist Fig.13 In (a), the output voltage is doubled, so the reference voltage Vosc is Fig.13 (b) is high. When compared with the first embodiment Figure 8 When comparing (a) Figure 8 In (a), the value of the Vfb signal is higher than the reference voltage Vosc, so the time Enb_Delay is zero. Fig.13 In (a), the value of the Vfb signal is lower than the reference voltage Vosc, so the voltage VT increases. Therefore, the slope of the ramp voltage VR increases, but the time Enb_Delay becomes longer, so the frequency can be reduced.

[0175] exist Fig.13 In (c), since the output voltage is 1 / 2 times, the reference voltage Vosc is Fig.13 (b) low.

[0176] Compared with the first embodiment Figure 8 Compared with (c), since the difference between the value of the Vfb signal and the reference voltage Vosc decreases, the slope of the ramp voltage VR decreases, but since the voltage VT decreases, the time Enb_Delay becomes shorter and the frequency increases.

[0177] Therefore, it is possible to suppress frequency fluctuations when the output voltage changes, thereby realizing a highly efficient and compact power supply device.

[0178] Fig.141 is a diagram showing the operation of the ACF converter 10 and the operation of the control units 100a and 100b in the first and second embodiments of the present invention. The value of the Vfb signal increases as the output current increases, thereby reducing the voltage VT and shortening the time Enb_Delay of the Enb signal as the enable signal. As a result, the period T6 becomes shorter and the frequency increases.

[0179] When the output current is further increased, the time Enb_Delay becomes shorter than the edge of the Dis signal. In the absence of the Dis signal, control cannot be performed, but the upper limit of the frequency is determined by the Dis signal, and the clamp switch QH is turned on at the first maximum point in the resonant vibration of Tcvlm. In addition, when the output current is increased, the periods T1 and T3 become longer, so the frequency decreases.

[0180] Therefore, the change of the operating frequency when the output current changes between the first embodiment and the second embodiment is as follows: Fig.15 As shown in the figure, when the output current decreases from the maximum output current, the frequency increases, and after reaching the maximum frequency, when the output current decreases, the frequency decreases.

[0181] Furthermore, as is well known, there is a problem that high-frequency sound waves are generated from the power supply circuit when the operating frequency becomes lower than the audible frequency. Therefore, a burst mode may be set before the operating frequency becomes the audible frequency.

[0182] As described above, the control method of the ACF converter 10 of the present embodiment improves the disadvantages of complementary control and non-complementary control, can realize ZVS in a wide output voltage and current range, and can realize efficient and low-noise ACF operation.

[0183] (Other embodiments)

[0184] With reference to the accompanying drawings, the embodiments are described in detail, but the embodiments are not limited by the contents described in the above embodiments. In addition, the structural elements described above include structural elements and substantially the same structural elements that can be easily thought of by a person skilled in the art. Moreover, the structures described above can be appropriately combined. In addition, various omissions, substitutions or changes of the structure can be made within the scope of the gist of the embodiments.

[0185] The following describes the features of the active clamp flyback converter and the control IC.

[0186] The active clamp flyback converter and control IC of the first embodiment have: a first series circuit, in which a main switch QL and a primary winding Np are connected in series at both ends of a DC power supply Vin; and a second series circuit, in which a clamp switch QH and a clamp capacitor Cac are connected in series at both ends of the primary winding Np. In addition, the active clamp flyback converter and control IC have: a transformer T, which has a secondary winding Ns electromagnetically coupled to the primary winding Np; and a control unit 100a, which turns on and off the main switch QL and the clamp switch QH. In addition, the active clamp flyback converter and control IC have: a rectifying and smoothing circuit, which rectify and smoothes the voltage of the secondary winding Ns; and an output voltage detection unit 200, which detects the output voltage of the rectifying and smoothing circuit. The control unit 100a has a first drive signal, a second drive signal, and a third drive signal, wherein the first drive signal turns the main switch QL on and off, the second drive signal turns the clamp switch QH on and off during a period when the main switch QL is off, and the third drive signal turns the clamp switch QH on and off after the second drive signal. In addition, the control unit controls a first off period, which is a period during which both the main switch QL and the clamp switch QH are off from the off time of the first drive signal to the on time of the second drive signal, and a second off period, which is a period during which both the main switch QL and the clamp switch QH are off from the off time of the second drive signal to the on time of the third drive signal.

[0187] With this configuration, the ACF converter 10 can reduce fluctuations in operating frequency associated with changes in output voltage and output current, and maintain zero-volt switching operation.

[0188] The control unit 100a of the active clamp flyback converter and control IC of the second embodiment may also include: an excitation current detection unit 113 that detects the excitation current of the transformer T and outputs a first voltage signal proportional to the excitation current; and an output voltage detection unit 111 that outputs a second voltage signal proportional to the output voltage. In addition, the control unit 100a may set the on timing of the second drive signal based on the first voltage signal and a threshold value set based on the second voltage signal, thereby controlling the first drive signal and controlling the first off period based on the feedback voltage detected by the output voltage detection unit.

[0189] According to this configuration, the ACF converter 10 can achieve ZVS even if the peak current of the magnetizing inductance is reduced and the frequency is lowered in frequency control when the load current decreases, and can realize high-efficiency and low-noise ACF operation in the entire load range.

[0190] The control unit 100a of the active clamp flyback converter and control IC of the third embodiment may also include: an excitation current detection unit 113 that detects the excitation current of the transformer T and outputs a first voltage signal proportional to the excitation current; and a predetermined third voltage signal. In addition, the control unit 100a may set the on timing of the second drive signal based on the first voltage signal and the third voltage signal, thereby controlling the first drive signal and the first off period based on the feedback voltage detected by the output voltage detection unit 200.

[0191] According to this configuration, in a power supply whose output voltage is constant, the threshold value to be compared with the exciting current only needs to be constant, and therefore the ACF converter 10 can reduce the number of components.

[0192] The control unit 100a of the active clamp flyback converter and control IC of the fourth embodiment may also include an enable signal generating unit 130a that generates an enable signal based on the feedback voltage detected by the output voltage detecting unit 200, and a disable signal generating unit 142 that generates a disable signal based on the second drive signal. In addition, the control unit 100a may control the third drive signal based on the enable signal and the disable signal, thereby controlling the second off period.

[0193] With this configuration, the ACF converter 10 can reduce fluctuations in operating frequency associated with changes in output voltage and output current, and maintain zero-volt switching operation.

[0194] The active clamp flyback converter and control unit 100a of the control IC of the fifth embodiment may also include: an output voltage detection unit 111 that outputs a second voltage signal proportional to the output voltage; an enable signal generation unit 130a that generates an enable signal based on the second voltage signal and the feedback voltage detected by the output voltage detection unit 200; and a disable signal generation unit 142 that generates a disable signal based on the second drive signal. In addition, the control unit 100a may control the third drive signal based on the enable signal and the disable signal, thereby controlling the second off period.

[0195] With this structure, the ACF converter 10 can achieve control with less fluctuation of the operating frequency in response to changes in the output voltage, and can realize a compact and efficient power supply structure. For example, in a power supply device that needs to change the output voltage, it is required that the operating frequency fluctuate less, but the ACF converter 10 is more suitable for such a structure.

[0196] The active clamp flyback converter and the enable signal generating unit 130a of the control IC of the sixth aspect may be controlled so that the time Enb_Delay from when the main switch QL is turned on to when the Enb signal becomes High is proportional to the negative value of the Vfb signal.

[0197] With this configuration, the ACF converter 10 can reduce fluctuations in operating frequency associated with changes in output voltage and output current, and maintain zero-volt switching operation.

[0198] The active clamp flyback converter and the enable signal generating unit 130a of the control IC of the seventh embodiment may be controlled so that the time Enb_Delay from when the main switch QL is turned on to when the Enb signal becomes High is negatively proportional to the Vfb signal, and the absolute value of the proportionality coefficient decreases as the output voltage increases.

[0199] With this configuration, the ACF converter 10 can reduce fluctuations in operating frequency associated with changes in output voltage and output current, and maintain zero-volt switching operation.

Claims

1. An active clamp flyback converter and a control IC, wherein: The active clamp flyback converter and control IC features: a first series circuit having a main switch and a primary winding connected in series at both ends of a DC power supply; a second series circuit having a clamp switch and a clamp capacitor connected in series at both ends of the primary winding; a transformer having a secondary winding electromagnetically coupled to the primary winding; a control unit that turns the main switch and the clamp switch on and off; a rectifying and smoothing circuit, which rectifies and smoothes the voltage of the secondary winding; and an output voltage detection unit, which detects the output voltage of the rectifying and smoothing circuit, The control unit has a first drive signal, a second drive signal, and a third drive signal, wherein the first drive signal turns the main switch on and off, the second drive signal turns the clamp switch on and off while the main switch is off, and the third drive signal turns the clamp switch on and off after the second drive signal. The control unit controls the first disconnection period and the second disconnection period. The first off period is a period during which both the main switch and the clamp switch are off from the off time of the first drive signal to the on time of the second drive signal. The second off period is a period during which both the main switch and the clamp switch are off from the off time of the second drive signal to the on time of the third drive signal.

2. The active clamp flyback converter and control IC according to claim 1, wherein: The control unit includes: an excitation current detection unit that detects the excitation current of the transformer and outputs a first voltage signal proportional to the excitation current; and an output voltage detection unit, which outputs a second voltage signal proportional to the output voltage, The control unit sets the on timing of the second drive signal according to the first voltage signal and a threshold value set based on the second voltage signal, thereby controlling the first drive signal and the first off period according to the feedback voltage detected by the output voltage detection unit.

3. The active clamp flyback converter and control IC according to claim 1, wherein: The control unit includes: an excitation current detection unit that detects the excitation current of the transformer and outputs a first voltage signal proportional to the excitation current; and a predetermined third voltage signal. The control unit sets the on timing of the second drive signal based on the first voltage signal and the third voltage signal, thereby controlling the first drive signal and the first off period based on the feedback voltage detected by the output voltage detection unit.

4. The active clamp flyback converter and control IC according to claim 1, wherein: The control unit includes: an enable signal generating unit that generates an enable signal based on the feedback voltage detected by the output voltage detecting unit; and a disable signal generating unit that generates a disable signal based on the second drive signal. The control unit controls the third drive signal based on the enable signal and the disable signal, thereby controlling the second OFF period.

5. The active clamp flyback converter and control IC according to claim 1, wherein: The control unit includes: an output voltage detection unit that outputs a second voltage signal proportional to the output voltage; an enable signal generation unit that generates an enable signal based on the second voltage signal and a feedback voltage detected by the output voltage detection unit; and a disable signal generation unit that generates a disable signal based on the second drive signal. The control unit controls the third drive signal based on the enable signal and the disable signal, thereby controlling the second OFF period.

6. The active clamp flyback converter and control IC according to claim 4, wherein: The enable signal generating unit is controlled so that a time Enb_Delay from when the main switch is turned on until the Enb signal becomes High, ie, a high level, is proportional to a negative value of the Vfb signal.

7. The active clamp flyback converter and control IC according to claim 5, wherein: The enable signal generating unit is controlled so that the time Enb_Delay from when the main switch is turned on until the Enb signal becomes High is negatively proportional to the Vfb signal, and the absolute value of the proportionality coefficient decreases as the output voltage increases.

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