Reinforced latch circuit structure capable of resisting double-node upset

Abstract

The invention discloses a reinforced latch circuit structure capable of resisting double-node upset. An inverter circuit is used for inverting an input data signal D, generating a clock signal CLKNN and outputting Q; the delay circuit is used for delaying the transient pulse; the C unit structure is used for filtering; the clock control input structure is used for controlling propagation of a signal in the latch; the latch circuit is used for ensuring that a signal is kept in a correct state when the circuit is subjected to single-particle radiation; the clock control C-cell structure is used for filtering and controlling an output signal of the latch circuit. The circuit structure designed by the invention is good in dual-node overturning reinforcing effect, few in sensitive nodes, simple in circuit design and easy to realize.

Description

Technical Field

[0001] The present invention relates to a latch circuit structure with dual-node flip resistance reinforcement, and in particular to a latch circuit structure with dual-node flip resistance reinforcement achieved through internal node feedback. Background Art

[0002] Single Event Upset (SEU) refers to the phenomenon that the timing unit of an integrated circuit used in a space environment is bombarded by high-energy particles and the stored data is erroneous. In digital storage circuits, single event upset is becoming a serious challenge facing advanced nano-CMOS technology. When ionized particles hit the sensitive area of ​​the integrated circuit, a large number of electron-hole pairs are generated and collected in the loss region of the device. When the collected charge is greater than the critical charge Q stored in the sensitive node, the SEU will be generated and collected in the loss region of the device. crit When a single event upset occurs, the ionized particles generate transient pulses, which may change the storage value of such sensitive nodes. Single event upsets seriously affect the reliability of aerospace systems and threaten their normal operation.

[0003] Sequential units such as latches are the most basic units of integrated circuits, and their radiation resistance is critical. With the reduction of transistor feature size, the reduction of power supply voltage and node capacitance, and the increase of integration complexity, the performance of integrated circuits has also improved. However, the double node flip caused by the charge sharing effect is becoming a major reliability problem in the design of nano latches. Currently, the commonly used reinforcement design methods include dual interlocked storage cells (DICE) and triple modular redundancy (TMR). However, the reinforcement methods of DICE and TMR are generally only effective for single node flips, and cannot achieve double node flip reinforcement. Although some existing double node flip-resistant reinforced latch circuit structures have good fault tolerance, they generally have a large number of sensitive nodes and a large area overhead, which leads to increased circuit power consumption and delay, and are not suitable for the application of high-performance integrated circuits. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a latch circuit structure with dual-node flip resistance reinforcement, to achieve dual-node flip reinforcement, while having a small number of sensitive nodes, a simple circuit design, and easy implementation.

[0005] The technical solution of the present invention is:

[0006] The present invention discloses a latch circuit structure with double-node flip resistance reinforcement, comprising: a first inverter circuit, a first delay circuit, a first C unit structure, a second inverter circuit, a first clock control input circuit, a second clock control input circuit, a third clock control input circuit, a fourth clock control input circuit, a fifth clock control input circuit, a latch circuit, a clock control C unit structure, a third inverter circuit, a second delay circuit, a second C unit structure and a fourth inverter circuit; wherein,

[0007] The input end of the first inverter circuit is used to receive an external input signal D, and the output end of the first inverter circuit is connected to the input end of the first delay circuit and the input end Input1 of the first C unit structure;

[0008] The output end of the first delay circuit is connected to the input end Input2 of the first C unit structure;

[0009] The output end of the first C unit structure is connected to the input end of the second inverter circuit, the input end Input2 of the third clock control input circuit, the input end Input2 of the fourth clock control input circuit and the input end Input2 of the fifth clock control input circuit;

[0010] The output end of the second inverter circuit is connected to the input end Input2 of the first clock control input circuit and the input end Input2 of the second clock control input circuit;

[0011] An input terminal Input1 of the first clock control input circuit is connected to the clock signal CLKN, an input terminal Input3 of the first clock control input circuit is connected to the clock signal CLKNN, and an output terminal of the first clock control input circuit is connected to an input terminal Input2 of the latch circuit;

[0012] An input terminal Input1 of the second clock control input circuit is connected to the clock signal CLKN, an input terminal Input3 of the second clock control input circuit is connected to the clock signal CLKNN, and an output terminal of the second clock control input circuit is connected to an input terminal Input4 of the latch circuit;

[0013] An input terminal Input1 of the third clock control input circuit is connected to the clock signal CLKN, an input terminal Input3 of the third clock control input circuit is connected to the clock signal CLKNN, and an output terminal of the third clock control input circuit is connected to an input terminal Input1 of the latch circuit;

[0014] An input terminal Input1 of the fourth clock control input circuit is connected to the clock signal CLKN, an input terminal Input3 of the fourth clock control input circuit is connected to the clock signal CLKNN, and an output terminal of the fourth clock control input circuit is connected to an input terminal Input3 of the latch circuit;

[0015] The input terminal Input1 of the fifth clock control input circuit is connected to the clock signal CLKN, the input terminal Input3 of the fifth clock control input circuit is connected to the clock signal CLKNN, and the output terminal of the fifth clock control input circuit is connected to the input terminal of the third inverter circuit and the output terminal of the clock control C unit structure;

[0016] The output terminal Output1 of the latch circuit is connected to the input terminal Input1 of the clock control C unit structure, and the output terminal Output2 of the latch circuit is connected to the input terminal Input4 of the clock control C unit structure;

[0017] An input terminal Input2 of the clock control C unit structure is connected to the clock signal CLKNN, an input terminal Input3 of the clock control C unit structure is connected to the clock signal CLKN, and an output terminal of the clock control C unit structure is connected to an input terminal of the third inverter circuit;

[0018] The output end of the third inverter circuit outputs a signal Q to the outside;

[0019] The input end of the second delay circuit is connected to the external input clock signal CLK and the input end Input1 of the second C unit structure, and the output end of the second delay circuit is connected to the input end Input2 of the second C unit structure;

[0020] The output end of the second C unit structure is connected to the input end of the fourth inverter circuit and generates a clock signal CLKN;

[0021] The output end of the fourth inverter circuit is a clock signal CLKNN which is inverted from the clock signal CLKN.

[0022] Furthermore, in the above circuit structure, the circuit structures of the first delay circuit and the second delay circuit are consistent.

[0023] Furthermore, in the above circuit structure, the first delay circuit is composed of a plurality of stacked inverters of the same structure in cascade connection; the stacked inverters include PMOS tubes PMOS201, PMOS202, PMOS203 and NMOS tubes NMOS204, NMOS205, NMOS206; wherein,

[0024] The gates of the PMOS tubes PMOS201, PMOS202, PMOS203 and NMOS204, NMOS205, NMOS206 are connected together as a signal input terminal input; the source of the PMOS tube PMOS201 is connected to the power supply VDD, and the drain is connected to the source of PMOS202, the source of NMOS205 and the drain of NMOS206; the drain of PMOS202 is connected to the source of PMOS203, the source of NMOS204 and the drain of NMOS205; the drain of PMOS203 is connected to the drain of NMOS204 and is connected to the input terminal of the second stage stacked inverter as the output terminal of the first stage stacked inverter; the source of NMOS206 is grounded GND.

[0025] Further, in the above circuit structure, the latch circuit includes PMOS tubes PMOS601, PMOS602, PMOS605, PMOS608, PMOS611, PMOS614, PMOS617, PMOS618 and NMOS tubes NMOS603, NMOS604, NMOS606, NMOS607, NMOS609, NMOS610, NMOS612, NMOS613, NMOS615, NMOS616, NMOS619, NMOS620; wherein,

[0026] The source of PMOS601 is connected to the power supply VDD; the gate of PMOS601 is connected to the gate of NMOS609, the gate of NMOS615, the drain of PMOS617 and the source of PMOS618; the drain of PMOS601 is connected to the source of PMOS602, the gate of NMOS606, the gate of NMOS612 and the gate of PMOS617; the gate of PMOS602 is connected to the source of NMOS606, the drain of NMOS607, the gate of PMOS608 and the gate of NMOS616 and serves as the input terminal Input1; the drain of PMOS602 is connected to the drain of NMOS603; the gate of NMOS603 is connected to the input signal Input2; the source of NMOS603 is connected to the drain of NMOS604; the gate of NMOS604 is connected to the input signal Input4; the source of NMOS604 is grounded GND;

[0027] The gate of PMOS605 is connected to the gate of PMOS618; the source of PMOS605 is connected to the power supply VDD; the drain of PMOS605 is connected to the drain of NMOS606; the gate of NMOS607 is connected to the source of NMOS609, the drain of NMOS610, and the gate of PMOS611 and serves as the input terminal Input2 and the output terminal Output1, and the source of NMOS607 is grounded GND;

[0028] The source of PMOS 608 is connected to the power supply VDD; the drain of PMOS 608 is connected to the drain of NMOS 609; the gate of NMOS 610 is connected to the source of NMOS 612, the drain of NMOS 613, the gate of PMOS 614 and the input signal Input3; the source of NMOS 610 is grounded GND;

[0029] The source of PMOS611 is connected to the power supply VDD; the drain of PMOS611 is connected to the drain of NMOS612; the gate of NMOS613 is connected to the source of NMOS615, the drain of NMOS616, the gate of PMOS618 and the gate of PMOS605, and is connected to the input signal Input4 and serves as the output terminal Output2; the source of NMOS613 is grounded GND;

[0030] The source of PMOS614 is connected to the power supply VDD; the drain of PMOS614 is connected to the drain of NMOS615; the source of NMOS616 is connected to the ground GND;

[0031] The source of PMOS617 is connected to the power supply VDD; the drain of PMOS618 is connected to the drain of NMOS619; the gate of NMOS619 is connected to the input signal Input1; the source of NMOS619 is connected to the drain of NMOS620; the gate of NMOS620 is connected to the input signal Input3; the source of NMOS620 is connected to the ground GND.

[0032] Furthermore, in the above circuit structure, the first C unit structure includes: PMOS tubes PMOS301, PMOS302 and NMOS tubes NMOS303, NMOS304; wherein,

[0033] The source of the PMOS tube PMOS301 is connected to the power supply VDD, the gate of the PMOS301 is connected to the gate of the PMOS303 and the input terminal input1 of the first C unit structure; the drain of the PMOS301 is connected to the source of the PMOS302;

[0034] The gate of PMOS 302 is connected to the gate of PMOS 304 and the input terminal input2 of the first C unit structure, and the drain of PMOS 302 is connected to the drain of PMOS 303 as the output terminal output of the first C unit structure;

[0035] The source of the PMOS 303 is connected to the drain of the PMOS 304 , and the source of the PMOS 304 is connected to the ground GND.

[0036] Furthermore, in the above circuit structure, the first clock control input circuit includes PMOS tubes PMOS501 and PMOS502 and NMOS tubes NMOS503 and NMOS504; wherein,

[0037] The source of the PMOS tube PMOS501 is connected to the power supply VDD, and the gate of the PMOS501 is connected to the input terminal input1 of the first clock control input circuit; the drain of the PMOS501 is connected to the source of the PMOS502;

[0038] The gate of PMOS502 is connected to the gate of PMOS503 and the input terminal input2 of the first C unit structure, and the drain of PMOS502 is connected to the drain of PMOS503 as the output terminal output of the first clock control input circuit;

[0039] The source of PMOS503 is connected to the drain of PMOS504, and the source of PMOS504 is grounded GND;

[0040] The gate of the PMOS 504 is connected to the input terminal input3 of the first clock control input circuit.

[0041] Furthermore, in the above circuit structure, the circuit structures of the first clock control input circuit, the second clock control input circuit, the third clock control input circuit, the fourth clock control input circuit and the fifth clock control input circuit are the same.

[0042] The beneficial effects of the present invention relative to the prior art are:

[0043] 1) The present invention provides a latch circuit structure with double-node flip resistance reinforcement, which implements double-node flip reinforcement of internal nodes based on feedback.

[0044] 2) In the circuit structure provided by the present invention, some internal nodes can only be pulled up or pulled down, which is different from other structures in which all internal nodes can be pulled up and pulled down, thereby reducing the flip probability of a single particle. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a circuit structure principle diagram of the present invention;

[0046] Figure 2 is a structural diagram of a delay circuit in the circuit structure of the present invention;

[0047] Figure 3 It is a structural diagram of the C unit in the circuit structure of the present invention;

[0048] Figure 4 The filtering principle diagram implemented by the present invention;

[0049] Figure 5 is a structural diagram of a clock control input circuit in the circuit structure of the present invention;

[0050] Figure 6 is a structural diagram of a latch circuit in the circuit structure of the present invention;

[0051] Figure 7 It is a structural diagram of the clock control C unit in the circuit structure of the present invention. DETAILED DESCRIPTION

[0052] The present invention will be further described below in conjunction with the accompanying drawings.

[0053] All features disclosed in this specification, or steps in all methods or processes disclosed, except mutually exclusive features and / or steps, can be combined in any manner.

[0054] Any feature disclosed in this specification, unless otherwise stated, may be replaced by other alternative features that are equivalent or have similar purposes.

[0055] The present invention discloses a latch circuit structure with double-node flip resistance reinforcement, comprising: a first inverter circuit 101, a first delay circuit 102, a first C unit structure 103, a second inverter circuit 104, a first clock control input circuit 105, a second clock control input circuit 106, a third clock control input circuit 107, a fourth clock control input circuit 108, a fifth clock control input circuit 109, a latch circuit 110, a clock control C unit structure 111, a third inverter circuit 112, a second delay circuit 113, a second C unit structure 114 and a fourth inverter circuit 115; wherein,

[0056] The input end of the first inverter circuit 101 is used to receive an external input signal D, and the output end of the first inverter circuit 101 is connected to the input end of the first delay circuit 102 and the input end Input1 of the first C unit structure 103;

[0057] The output end of the first delay circuit 102 is connected to the input end Input2 of the first C unit structure 103;

[0058] The output end of the first C unit structure 103 is connected to the input end of the second inverter circuit 104, the input end Input2 of the third clock control input circuit 107, the input end Input2 of the fourth clock control input circuit 108 and the input end Input2 of the fifth clock control input circuit 109;

[0059] The output end of the second inverter circuit 104 is connected to the input end Input2 of the first clock control input circuit 105 and the input end Input2 of the second clock control input circuit 106;

[0060] An input terminal Input1 of the first clock control input circuit 105 is connected to the clock signal CLKN, an input terminal Input3 of the first clock control input circuit 105 is connected to the clock signal CLKNN, and an output terminal of the first clock control input circuit 105 is connected to an input terminal Input2 of the latch circuit 110;

[0061] An input terminal Input1 of the second clock control input circuit 106 is connected to the clock signal CLKN, an input terminal Input3 of the second clock control input circuit 106 is connected to the clock signal CLKNN, and an output terminal of the second clock control input circuit 106 is connected to an input terminal Input4 of the latch circuit 110;

[0062] An input terminal Input1 of the third clock control input circuit 107 is connected to the clock signal CLKN, an input terminal Input3 of the third clock control input circuit 107 is connected to the clock signal CLKNN, and an output terminal of the third clock control input circuit 107 is connected to an input terminal Input1 of the latch circuit 110;

[0063] An input terminal Input1 of the fourth clock control input circuit 108 is connected to the clock signal CLKN, an input terminal Input3 of the fourth clock control input circuit 108 is connected to the clock signal CLKNN, and an output terminal of the fourth clock control input circuit 108 is connected to an input terminal Input3 of the latch circuit 110;

[0064] The input terminal Input1 of the fifth clock control input circuit 109 is connected to the clock signal CLKN, the input terminal Input3 of the fifth clock control input circuit 109 is connected to the clock signal CLKNN, and the output terminal of the fifth clock control input circuit 109 is connected to the input terminal of the third inverter circuit 112 and the output terminal of the clock control C unit structure 111;

[0065] The output terminal Output1 of the latch circuit 110 is connected to the input terminal Input1 of the clock control C unit structure 111, and the output terminal Output2 of the latch circuit 110 is connected to the input terminal Input4 of the clock control C unit structure 111;

[0066] The input terminal Input2 of the clock control C unit structure 111 is connected to the clock signal CLKNN, the input terminal Input3 of the clock control C unit structure 111 is connected to the clock signal CLKN, and the output terminal of the clock control C unit structure 111 is connected to the input terminal of the third inverter circuit 112;

[0067] The output terminal of the third inverter circuit 112 outputs a signal Q to the outside;

[0068] An input end of the second delay circuit 113 is connected to an external input clock signal CLK and an input end Input1 of the second C unit structure 114 , and an output end of the second delay circuit 113 is connected to an input end Input2 of the second C unit structure 114 ;

[0069] The output terminal of the second C unit structure 114 is connected to the input terminal of the fourth inverter circuit 115 and generates a clock signal CLKN;

[0070] The output terminal of the fourth inverter circuit 115 is a clock signal CLKNN after the clock signal CLKN is inverted.

[0071] Preferably, the circuit structures of the first delay circuit 102 and the second delay circuit 113 are consistent.

[0072] Preferably, the first delay circuit 102 is composed of a plurality of stacked inverters of the same structure in cascade connection; the stacked inverters include PMOS tubes PMOS201, PMOS202, PMOS203 and NMOS tubes NMOS204, NMOS205, NMOS206; wherein,

[0073] The gates of the PMOS tubes PMOS201, PMOS202, PMOS203 and NMOS204, NMOS205, NMOS206 are connected together as a signal input terminal input; the source of the PMOS tube PMOS201 is connected to the power supply VDD, and the drain is connected to the source of PMOS202, the source of NMOS205 and the drain of NMOS206; the drain of PMOS202 is connected to the source of PMOS203, the source of NMOS204 and the drain of NMOS205; the drain of PMOS203 is connected to the drain of NMOS204 and is connected to the input terminal of the second stage stacked inverter as the output terminal of the first stage stacked inverter; the source of NMOS206 is grounded GND.

[0074] Preferably, the latch circuit 110 includes PMOS transistors PMOS601, PMOS602, PMOS605, PMOS608, PMOS611, PMOS614, PMOS617, PMOS618 and NMOS transistors NMOS603, NMOS604, NMOS606, NMOS607, NMOS609, NMOS610, NMOS612, NMOS613, NMOS615, NMOS616, NMOS619, NMOS620; wherein,

[0075] The source of PMOS601 is connected to the power supply VDD; the gate of PMOS601 is connected to the gate of NMOS609, the gate of NMOS615, the drain of PMOS617 and the source of PMOS618; the drain of PMOS601 is connected to the source of PMOS602, the gate of NMOS606, the gate of NMOS612 and the gate of PMOS617; the gate of PMOS602 is connected to the source of NMOS606, the drain of NMOS607, the gate of PMOS608 and the gate of NMOS616 and serves as the input terminal Input1; the drain of PMOS602 is connected to the drain of NMOS603; the gate of NMOS603 is connected to the input signal Input2; the source of NMOS603 is connected to the drain of NMOS604; the gate of NMOS604 is connected to the input signal Input4; the source of NMOS604 is grounded GND;

[0076] The gate of PMOS605 is connected to the gate of PMOS618; the source of PMOS605 is connected to the power supply VDD; the drain of PMOS605 is connected to the drain of NMOS606; the gate of NMOS607 is connected to the source of NMOS609, the drain of NMOS610, and the gate of PMOS611 and serves as the input terminal Input2 and the output terminal Output1, and the source of NMOS607 is grounded GND;

[0077] The source of PMOS 608 is connected to the power supply VDD; the drain of PMOS 608 is connected to the drain of NMOS 609; the gate of NMOS 610 is connected to the source of NMOS 612, the drain of NMOS 613, the gate of PMOS 614 and the input signal Input3; the source of NMOS 610 is grounded GND;

[0078] The source of PMOS611 is connected to the power supply VDD; the drain of PMOS611 is connected to the drain of NMOS612; the gate of NMOS613 is connected to the source of NMOS615, the drain of NMOS616, the gate of PMOS618 and the gate of PMOS605, and is connected to the input signal Input4 and serves as the output terminal Output2; the source of NMOS613 is grounded GND;

[0079] The source of PMOS614 is connected to the power supply VDD; the drain of PMOS614 is connected to the drain of NMOS615; the source of NMOS616 is connected to the ground GND;

[0080] The source of PMOS617 is connected to the power supply VDD; the drain of PMOS618 is connected to the drain of NMOS619; the gate of NMOS619 is connected to the input signal Input1; the source of NMOS619 is connected to the drain of NMOS620; the gate of NMOS620 is connected to the input signal Input3; the source of NMOS620 is connected to the ground GND.

[0081] Preferably, the first C unit structure 103 includes: PMOS transistors PMOS301 and PMOS302 and NMOS transistors NMOS303 and NMOS304; wherein,

[0082] The source of the PMOS tube PMOS301 is connected to the power supply VDD, the gate of the PMOS301 is connected to the gate of the PMOS303 and the input terminal input1 of the first C unit structure 103; the drain of the PMOS301 is connected to the source of the PMOS302;

[0083] The gate of the PMOS 302 is connected to the gate of the PMOS 304 and the input terminal input2 of the first C unit structure 103 , and the drain of the PMOS 302 is connected to the drain of the PMOS 303 as the output terminal output of the first C unit structure 103 ;

[0084] The source of the PMOS 303 is connected to the drain of the PMOS 304 , and the source of the PMOS 304 is connected to the ground GND.

[0085] Preferably, the first clock control input circuit 105 includes PMOS transistors PMOS501 and PMOS502 and NMOS transistors NMOS503 and NMOS504; wherein,

[0086] The source of the PMOS tube PMOS501 is connected to the power supply VDD, and the gate of the PMOS501 is connected to the input terminal input1 of the first clock control input circuit 105; the drain of the PMOS501 is connected to the source of the PMOS502;

[0087] The gate of the PMOS 502 is connected to the gate of the PMOS 503 and the input terminal input2 of the first C unit structure 105 , and the drain of the PMOS 502 is connected to the drain of the PMOS 503 as the output terminal output of the first clock control input circuit 105 ;

[0088] The source of PMOS503 is connected to the drain of PMOS504, and the source of PMOS504 is grounded GND;

[0089] The gate of the PMOS 504 is connected to the input terminal input3 of the first clock control input circuit 105 .

[0090] Preferably, the circuit structures of the first clock control input circuit 105 , the second clock control input circuit 106 , the third clock control input circuit 107 , the fourth clock control input circuit 108 and the fifth clock control input circuit 109 are the same.

[0091] The present invention utilizes a filter circuit composed of a delay circuit 102 or 113 and a C unit structure 103 or 114; utilizes a first clock control input circuit 105, a second clock control input circuit 106, a third clock control input circuit 107, and a fourth clock control input circuit 108; and utilizes a designed latch circuit 110 to achieve double-node flip reinforcement of the storage node inside the circuit.

[0092] Figure 1 The figure shows a schematic diagram of a latch circuit structure with dual-node flip resistance reinforcement provided by an example of the present invention, including a first inverter circuit 101, a first delay circuit 102, a first C unit structure 103, a second inverter circuit 104, a first clock control input circuit 105, a second clock control input circuit 106, a third clock control input circuit 107, a fourth clock control input circuit 108, a fifth clock control input circuit 109, a latch circuit 110, a clock control C unit structure 111, a third inverter circuit 112, a second delay circuit 113, a second C unit structure 114, and a fourth inverter circuit 115.

[0093] Figure 2 The circuit implementation form of the delay circuit 102 and 113 is shown. It is realized by stacking inverter cascade, and the main purpose is to input the input signal D of the latch after passing through the first inverter circuit 101 and the clock input signal CLK into the C unit structure 103 and 114 respectively after a certain delay. The delay time can be greater than the width of the instantaneous pulse. By adjusting the size and number of stages of the transistor, the filter design for the radiation characteristics under different processes can be easily realized. The delay circuit structure proposed by the present invention can increase the circuit delay on the basis of reducing the number of cascade stages, reduce the number of transistors, and reduce circuit overhead.

[0094] Figure 3 The circuit implementation of the C unit structures 103 and 114 is shown. There is a certain delay between the input terminals Input1 and Input2, and their transmission characteristics make the instantaneous pulses appearing be filtered out.

[0095] Figure 4 The figure shows the filtering principle of the filtering circuit composed of the delay circuit and the C unit structure.

[0096] Figure 5The circuit implementation form of the first clock control input circuit 105, the second clock control input circuit 106, the third clock control input circuit 107, the fourth clock control input circuit 108 and the fifth clock control input circuit 109 of the circuit structure of the present invention is shown. There are three input terminals in total, wherein Input1 is all connected to the clock signal CLKN, and Input2 is all connected to the clock signal CLKNN. The input terminals Input2 of the first clock control input circuit 105 and the second clock control input circuit 106 are connected to the output terminal of the second inverter circuit 104, and the input terminals Input2 of the third clock control input circuit 107, the fourth clock control input circuit 108 and the fifth clock control input circuit 109 are connected to the output terminal of the first C unit structure 103. When the clock signal CLK is at a high level, the first clock control input circuit 105, the second clock control input circuit 106, the third clock control input circuit 107, the fourth clock control input circuit 108 and the fifth clock control input circuit 109 are all turned on, the first clock control input circuit 105 passes the output data of the second inverter circuit 104 to the input terminal Input2 of the latch circuit 110, the second clock control input circuit 106 passes the output data of the second inverter circuit 104 to the input terminal Input4 of the latch circuit 110, the third clock control input circuit 107 passes the output data of the first C unit structure 103 to the input terminal Input1 of the latch circuit 110, and the fourth clock control input circuit 108 passes the output data of the first C unit structure 103 to the input terminal Input3 of the latch circuit 110, so the data is stored in the latch circuit 110. At the same time, the fifth clock control input circuit 109 transmits the output data of the first C unit structure 103 to the input terminal of the third inverter circuit 112, and the third inverter circuit 112 outputs a signal Q. In this way, a latch circuit structure with high level validity is realized.

[0097] Figure 6 The circuit implementation of the reinforced latch is shown in the figure. The reinforcement method of the designed latch will be explained in detail below. Since only high-energy particles bombarding the active area of ​​the MOS tube will cause a flip, Figure 6 There are 14 nodes in the latch structure of the present invention, which are marked as n1-n6 and A1-A8 in the figure. In this example, the 28nm process is used as an example.

[0098] When Input1=Input3=1, Input2=Input4=0, then nodes n1=n3=n6=1, n2=n4=n5=0. In this case, among the 14 nodes n1-n6, A1-A8, there are 7 sensitive nodes, namely n1, n3, n5, A1, A2, A4, A6, and the rest of the nodes are insensitive. Among them, n2 and n4 nodes are connected to the active area of ​​the NMOS tube, but not to the active area of ​​the PMOS tube. Therefore, if high-energy particles bombard the n2 or n4 nodes, the potential of the two nodes will be pulled down, but it will still be a low level, and will not flip from a low level to a high level. The n6 node is only connected to the active area of ​​the PMOS tube, so the potential of the n6 node will not flip from a high level to a low level after being bombarded by particles. And in the case of Input1 = Input3 = 1, Input2 = Input4 = 0, the MOS tubes connected to the A3, A5, A7 and A8 nodes are all in the open state. In this case, they are not sensitive to high-energy particle incidence, so the A3, A5, A7 and A8 nodes are not sensitive nodes. The following will analyze the anti-double-node flip characteristics of the latch circuit for the sensitive nodes n1, n3, n5, A1, A2, A4 and A6 nodes in combination with specific situations.

[0099] If a single-particle flip occurs at the sensitive nodes n1 and n3 at the same time, their potentials flip from a high level to a low level. At this time, NMOS619 and NMOS620 are turned off, and PMOS618 is turned on, so the n5 node remains at a low level, and then PMOS601 is turned on, and the n6 node remains at a high level. At the same time, since the n4 node is at a low level, PMOS605 is turned on, NMOS606 is turned on, and the potential of the n1 node is pulled back to a high level. Because the n2 node is at a low level, PMOS611 is turned on, NMOS612 is turned on, so the n3 node is also pulled back to a high level.

[0100] If a single-particle flip occurs at the sensitive nodes n1 and n5 at the same time, the potential of the n1 node flips from a high level to a low level, and the potential of the n5 node flips from a low level to a high level. At this time, PMOS601 is turned off, and the n6 node remains at a high level, so PMOS605 is turned on, NMOS606 is turned on, and the potential of the n1 node is pulled back to a high level. At the same time, NMOS619 and NMOS620 are turned on, PMOS618 is turned on, and PMOS617 is turned off, and the potential of the n5 node is pulled down to a low level.

[0101] If a single-particle flip occurs at the sensitive nodes n3 and n5 at the same time, the potential of the n3 node flips from a high level to a low level, and the potential of the n5 node flips from a low level to a high level. The n4 node is at a low level, PMOS601 is turned on, the n6 node is at a high level, and the n2 node remains at a low level, so PMOS611 is turned on, NMOS612 is turned on, and the n3 node is pulled back to a high level. At this time, NMOS619, NMOS620 and PMOS618 are all turned on, and the n5 node is pulled back to a low level.

[0102] If a single particle flip occurs in any node pair of n1 and A1, n1 and A2, n1 and A4, n1 and A6, because the n6 node remains at a high level, PMOS605 and NMOS606 are both turned on, and the n1 node is pulled back to a high level. If a single particle flip occurs in any node of A1 or A2, PMOS602 is briefly turned on when a single particle flip occurs in the n1 node, but because the n1 node is quickly pulled back to a high level, PMOS602 is turned off, and the storage data of the A1 or A2 node changes and cannot be transmitted to other nodes, and will not affect the storage status of other nodes. If a single particle flip occurs in any node of A4 or A6, because the n5 node is at a low level, NMOS609 and NMOS615 are both turned off, so the erroneous data of A4 or A6 cannot be transmitted to other nodes, and will not affect the output node data.

[0103] Similarly, if a single-particle upset occurs in any node pair among n3 and A1, n3 and A2, n3 and A4, n3 and A6, or any node pair among n5 and A1, n5 and A2, n5 and A4, n5 and A6, according to the above analysis ideas, it will not affect the data of the output node.

[0104] If a single-particle upset occurs in any node pair among A1, A2, A4 and A6, the output data remains unchanged because the erroneous data of the upset will not be transmitted to other nodes. For example, if a single-particle upset occurs in A1 and A4, since the n1 node is at a high level and the PMOS602 is turned off, the erroneous data of the A1 node will not be transmitted to the n6 node. Similarly, since the n5 node is at a low level and the NMOS609 is turned off, the erroneous data of A4 will not be transmitted to the n2 node.

[0105] Due to the symmetry of the latch circuit 110 design, when Input1=Input3=0, Input2=Input4=1, the analysis of each node is similar to that when Input1=Input3=1, Input2=Input4=0, and the conclusion of resistance to double node flipping can also be obtained.

[0106] Figure 7The circuit implementation form of the clock control C unit structure 111 is shown. Input1 is connected to the output terminal Output1 of the latch circuit 110, Input4 is connected to the output terminal Output4 of the latch circuit 110, input terminal Input2 is connected to the clock signal CLKNN, and Input3 is connected to the clock signal CLKN. When the external input clock signal CLK is at a high level, the clock control C unit structure is turned off, and data cannot be transmitted to the output terminal Q; when the external input clock signal CLK is at a low level, the clock control C unit structure is turned on, and the data latched in the latch circuit 110 is transmitted to the input terminal of the third inverter circuit 112, and the third inverter circuit 112 outputs Q.

[0107] Contents not described in detail in the specification of the present invention belong to the well-known technologies of professionals in the field. Although the embodiments of the present invention are described in conjunction with the drawings, ordinary technicians in the field can make various modifications or changes within the scope of the attached claims.

Claims

1. A latch circuit structure reinforced against double node upset, characterized in that: include: A first inverter circuit (101), a first delay circuit (102), a first C unit structure (103), a second inverter circuit (104), a first clock control input circuit (105), a second clock control input circuit (106), a third clock control input circuit (107), a fourth clock control input circuit (108), a fifth clock control input circuit (109), a latch circuit (110), a clock control C unit structure (111), a third inverter circuit (112), a second delay circuit (113), a second C unit structure (114) and a fourth inverter circuit (115); wherein, The input end of the first inverter circuit (101) is used to receive an external input signal D, and the output end of the first inverter circuit (101) is connected to the input end of the first delay circuit (102) and the input end Input1 of the first C unit structure (103); The output end of the first delay circuit (102) is connected to the input end Input2 of the first C unit structure (103); The output end of the first C unit structure (103) is connected to the input end of the second inverter circuit (104), the input end Input2 of the third clock control input circuit (107), the input end Input2 of the fourth clock control input circuit (108) and the input end Input2 of the fifth clock control input circuit (109); The output end of the second inverter circuit (104) is connected to the input end Input2 of the first clock control input circuit (105) and the input end Input2 of the second clock control input circuit (106); An input terminal Input1 of the first clock control input circuit (105) is connected to a clock signal CLKN, an input terminal Input3 of the first clock control input circuit (105) is connected to a clock signal CLKNN, and an output terminal of the first clock control input circuit (105) is connected to an input terminal Input2 of a latch circuit (110); An input terminal Input1 of the second clock control input circuit (106) is connected to a clock signal CLKN, an input terminal Input3 of the second clock control input circuit (106) is connected to a clock signal CLKNN, and an output terminal of the second clock control input circuit (106) is connected to an input terminal Input4 of a latch circuit (110); An input terminal Input1 of the third clock control input circuit (107) is connected to a clock signal CLKN, an input terminal Input3 of the third clock control input circuit (107) is connected to a clock signal CLKNN, and an output terminal of the third clock control input circuit (107) is connected to an input terminal Input1 of a latch circuit (110); An input terminal Input1 of the fourth clock control input circuit (108) is connected to the clock signal CLKN, an input terminal Input3 of the fourth clock control input circuit (108) is connected to the clock signal CLKNN, and an output terminal of the fourth clock control input circuit (108) is connected to an input terminal Input3 of the latch circuit (110); An input terminal Input1 of the fifth clock control input circuit (109) is connected to a clock signal CLKN, an input terminal Input3 of the fifth clock control input circuit (109) is connected to a clock signal CLKNN, and an output terminal of the fifth clock control input circuit (109) is connected to an input terminal of the third inverter circuit (112) and an output terminal of the clock control C unit structure (111); The output terminal Output1 of the latch circuit (110) is connected to the input terminal Input1 of the clock control C unit structure (111), and the output terminal Output2 of the latch circuit (110) is connected to the input terminal Input4 of the clock control C unit structure (111); An input terminal Input2 of the clock control C unit structure (111) is connected to a clock signal CLKNN, an input terminal Input3 of the clock control C unit structure (111) is connected to a clock signal CLKN, and an output terminal of the clock control C unit structure (111) is connected to an input terminal of a third inverter circuit (112); The output terminal of the third inverter circuit (112) outputs a signal Q to the outside; The input end of the second delay circuit (113) is connected to the external input clock signal CLK and the input end Input1 of the second C unit structure (114), and the output end of the second delay circuit (113) is connected to the input end Input2 of the second C unit structure (114); The output end of the second C unit structure (114) is connected to the input end of the fourth inverter circuit (115) and generates a clock signal CLKN; The output end of the fourth inverter circuit (115) is a clock signal CLKNN which is inverted from the clock signal CLKN.

2. The latch circuit structure with double-node upset resistance reinforcement according to claim 1, characterized in that: The circuit structures of the first delay circuit (102) and the second delay circuit (113) are consistent.

3. A latch circuit structure reinforced against double node upset according to claim 1 or 2, characterized in that: The first delay circuit (102) is composed of a plurality of stacked inverters of the same structure connected in cascade; the stacked inverters include PMOS tubes PMOS201, PMOS202, PMOS203 and NMOS tubes NMOS204, NMOS205, NMOS206; in, The gates of the PMOS tubes PMOS201, PMOS202, PMOS203 and NMOS204, NMOS205, NMOS206 are connected together as a signal input terminal input; the source of the PMOS tube PMOS201 is connected to the power supply VDD, and the drain is connected to the source of PMOS202, the source of NMOS205 and the drain of NMOS206; the drain of PMOS202 is connected to the source of PMOS203, the source of NMOS204 and the drain of NMOS205; the drain of PMOS203 is connected to the drain of NMOS204 and is connected to the input terminal of the second stage stacked inverter as the output terminal of the first stage stacked inverter; the source of NMOS206 is grounded GND.

4. The latch circuit structure with double-node upset resistance reinforcement according to claim 1, characterized in that: The latch circuit (110) comprises PMOS tubes PMOS601, PMOS602, PMOS605, PMOS608, PMOS611, PMOS614, PMOS617, PMOS618 and NMOS tubes NMOS603, NMOS604, NMOS606, NMOS607, NMOS609, NMOS610, NMOS612, NMOS613, NMOS615, NMOS616, NMOS619, NMOS620; wherein, The source of PMOS601 is connected to the power supply VDD; the gate of PMOS601 is connected to the gate of NMOS609, the gate of NMOS615, the drain of PMOS617 and the source of PMOS618; the drain of PMOS601 is connected to the source of PMOS602, the gate of NMOS606, the gate of NMOS612 and the gate of PMOS617; the gate of PMOS602 is connected to the source of NMOS606, the drain of NMOS607, the gate of PMOS608 and the gate of NMOS616 and serves as the input terminal Input1; the drain of PMOS602 is connected to the drain of NMOS603; the gate of NMOS603 is connected to the input signal Input2; the source of NMOS603 is connected to the drain of NMOS604; the gate of NMOS604 is connected to the input signal Input4; the source of NMOS604 is grounded GND; The gate of PMOS605 is connected to the gate of PMOS618; the source of PMOS605 is connected to the power supply VDD; the drain of PMOS605 is connected to the drain of NMOS606; the gate of NMOS607 is connected to the source of NMOS609, the drain of NMOS610, and the gate of PMOS611 and serves as the input terminal Input2 and the output terminal Output1, and the source of NMOS607 is grounded GND; The source of PMOS 608 is connected to the power supply VDD; the drain of PMOS 608 is connected to the drain of NMOS 609; the gate of NMOS 610 is connected to the source of NMOS 612, the drain of NMOS 613, the gate of PMOS 614 and the input signal Input3; the source of NMOS 610 is grounded GND; The source of PMOS611 is connected to the power supply VDD; the drain of PMOS611 is connected to the drain of NMOS612; the gate of NMOS613 is connected to the source of NMOS615, the drain of NMOS616, the gate of PMOS618 and the gate of PMOS605, and is connected to the input signal Input4 and serves as the output terminal Output2; the source of NMOS613 is grounded GND; The source of PMOS614 is connected to the power supply VDD; the drain of PMOS614 is connected to the drain of NMOS615; the source of NMOS616 is connected to the ground GND; The source of PMOS617 is connected to the power supply VDD; the drain of PMOS618 is connected to the drain of NMOS619; the gate of NMOS619 is connected to the input signal Input1; the source of NMOS619 is connected to the drain of NMOS620; the gate of NMOS620 is connected to the input signal Input3; the source of NMOS620 is connected to the ground GND.

5. The latch circuit structure with double-node upset resistance reinforcement according to claim 1, characterized in that: The first C unit structure (103) comprises: PMOS transistors PMOS301, PMOS302 and NMOS transistors NMOS303, NMOS304; wherein, The source of the PMOS tube PMOS301 is connected to the power supply VDD, the gate of the PMOS301 is connected to the gate of the PMOS303 and the input terminal input1 of the first C unit structure (103); the drain of the PMOS301 is connected to the source of the PMOS302; The gate of PMOS 302 is connected to the gate of PMOS 304 and the input terminal input2 of the first C unit structure (103), and the drain of PMOS 302 is connected to the drain of PMOS 303, serving as the output terminal output of the first C unit structure (103); The source of the PMOS 303 is connected to the drain of the PMOS 304 , and the source of the PMOS 304 is connected to the ground GND.

6. The latch circuit structure with double-node upset resistance reinforcement according to claim 1, characterized in that: The first clock control input circuit (105) comprises PMOS transistors PMOS501, PMOS502 and NMOS transistors NMOS503, NMOS504; wherein, The source of the PMOS tube PMOS501 is connected to the power supply VDD, the gate of the PMOS501 is connected to the input terminal input1 of the first clock control input circuit (105); the drain of the PMOS501 is connected to the source of the PMOS502; The gate of PMOS502 is connected to the gate of PMOS503 and the input terminal input2 of the first C unit structure (105), and the drain of PMOS502 is connected to the drain of PMOS503, serving as the output terminal output of the first clock control input circuit (105); The source of PMOS503 is connected to the drain of PMOS504, and the source of PMOS504 is grounded to GND; The gate of the PMOS 504 is connected to the input terminal input3 of the first clock control input circuit (105).

7. The latch circuit structure with double-node upset resistance reinforcement according to claim 1, characterized in that: The circuit structures of the first clock control input circuit (105), the second clock control input circuit (106), the third clock control input circuit (107), the fourth clock control input circuit (108) and the fifth clock control input circuit (109) are the same.

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