A method and device for aligning high-precision trigger signal and ADC sampling data

Abstract

The present application provides a method and device for aligning high-precision trigger signals and ADC sampling data. The method inputs a serial trigger signal into a high-speed transceiver, and the high-speed transceiver converts the serial trigger signal into parallel trigger data based on the line rate and the user data bit width, and outputs the user data and the corresponding user clock frequency; performs parallel edge detection on the user data and identifies the edge detection result; synchronizes the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain, and based on the matching result of the parallel trigger data and the sampling rate of the ADC, and the edge detection result in the synchronized parallel trigger data, determines from the user data a target trigger signal that matches the sampling data point time of the ADC, and aligns the target trigger signal with the ADC sampling data, thereby achieving accurate alignment of the external trigger signal with the high-speed ADC sampling data.

Description

Technical Field

[0001] The present application relates to the technical field of signal acquisition and processing, and in particular to a method and device for aligning a high-precision trigger signal with ADC sampling data. Background Art

[0002] With the growing demand for high-speed ADC (analog-to-digital converter) applications with sampling rates exceeding 10Gsps (Giga-bits per second), how to accurately capture the alignment relationship between the external trigger signal and the ADC sampling signal has become a technical challenge. For example, when the ADC is at a sampling rate of fs=32Gsps, if the time accuracy of the external trigger signal is only 1ns, this means that the trigger signal has a time deviation of 1ns, which will cause a deviation of 32 ADC sampling points, while a high-precision data acquisition system requires that the trigger time deviation should reach several or even one sampling point deviation. How to improve the processing time accuracy of the external trigger signal to a higher level than the sampling time accuracy of the ADC is a key technical issue that must be solved in engineering implementation.

[0003] In the prior art, limited by traditional trigger signal control methods, it is difficult for external trigger signals to achieve higher time resolution under ultra-high sampling rate conditions. Summary of the invention

[0004] In view of this, the purpose of this application is to provide a method and device for aligning high-precision trigger signals and ADC sampling data, which can achieve high-precision trigger signal sampling through a high-speed transceiver, thereby effectively improving the accuracy of the trigger signal to adapt to high-speed ADC data acquisition application scenarios.

[0005] The embodiment of the present application provides a method for aligning a high-precision trigger signal and ADC sampling data, comprising the following steps:

[0006] Acquire a serial trigger signal for triggering ADC sampling; the serial trigger signal is a differential signal;

[0007] Input the serial trigger signal to a high-speed transceiver, and the high-speed transceiver converts the serial trigger signal into parallel data based on a pre-configured line rate and user data bit width, and outputs user data and a corresponding user clock frequency; the line rate is greater than or equal to the sampling rate of the ADC;

[0008] Performing parallel edge detection on the user data in the user clock domain, and identifying edge detection results of the user data in the user clock domain; the edge detection results include a trigger mode and an index of each trigger edge in the user data;

[0009] Synchronize the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain, and obtain the synchronized parallel trigger data;

[0010] Based on the matching result of the parallel trigger data and the sampling rate of the ADC, and the edge detection result in the synchronized parallel trigger data, a target trigger signal that matches the sampling data point time of the ADC is determined from the user data of the parallel trigger data, and the target trigger signal is aligned with the ADC sampling data.

[0011] In some embodiments, in the method for aligning the high-precision trigger signal and ADC sampling data, obtaining a serial trigger signal for triggering ADC sampling includes:

[0012] Get the differential signal output by the external device;

[0013] Alternatively, a single-ended signal output by an external device is obtained, and the single-ended signal is converted into a differential signal by a single-ended to differential module.

[0014] In some embodiments, in the method for aligning the high-precision trigger signal with the ADC sampling data, the step of determining the target trigger signal that matches the sampling data point time of the ADC from the user data of the parallel trigger data based on the matching result of the parallel trigger data and the sampling rate of the ADC and the edge detection result in the synchronized parallel trigger data includes:

[0015] Calculate the trigger accuracy of the parallel trigger data relative to the ADC sampling data based on the line rate, user data bit width and user clock frequency of the high-speed transceiver, as well as the sampling rate, number of parallel sample points and ADC clock frequency of the ADC;

[0016] Based on the trigger accuracy of the parallel trigger data relative to the ADC sampling data, determining a target trigger signal corresponding to the ADC sampling point in time from the synchronized parallel trigger data;

[0017] Determine trigger signal information of the target trigger signal, where the trigger signal information includes a target trigger mode and a target index corresponding to the target trigger signal.

[0018] In some embodiments, in the method for aligning the high-precision trigger signal with the ADC sampling data, the triggering accuracy of the parallel trigger data relative to the ADC sampling data is less than or equal to one sampling point of the ADC sampling data.

[0019] In some embodiments, in the method for aligning the high-precision trigger signal and the ADC sampling data, synchronizing the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain, and acquiring the synchronized parallel trigger data, comprises:

[0020] The write port of the asynchronous FIFO module writes the parallel trigger data in the user clock domain;

[0021] The read port of the asynchronous FIFO module is connected to the ADC clock domain, and reads the parallel trigger data synchronized with the ADC sampling clock to obtain the synchronized parallel trigger data.

[0022] In some embodiments, in the method for aligning the high-precision trigger signal and the ADC sampling data, performing parallel edge detection on the user data in the user clock domain and identifying the edge detection result of the user data in the user clock domain include:

[0023] Storing the user data;

[0024] Comparing two adjacent bits of data in the user data, if the two adjacent bits of data are different, determining the trigger edge is a rising edge or a falling edge, if they are the same, determining the trigger edge is an invalid edge;

[0025] An index of a trigger edge is determined, and an edge detection result of the user data in a user clock domain is determined.

[0026] In some embodiments, in the method for aligning the high-precision trigger signal and the ADC sampling data, comparing two adjacent bits of data in the user data, and if the two adjacent bits of data are different, determining whether the trigger edge is a rising edge or a falling edge, includes:

[0027] If the first bit of the two adjacent data is 0 and the second bit is 1, the trigger edge is determined to be a rising edge;

[0028] If the first bit of two adjacent data is 1 and the second bit is 0, the trigger edge is determined to be a falling edge.

[0029] In some embodiments, in the method for aligning the high-precision trigger signal with the ADC sampling data, after aligning the target trigger signal with the ADC sampling data, the method further includes:

[0030] Recording the ADC sampling data from the first sampling point where the target trigger signal occurs, and rearranging the ADC sampling data according to the index of the target trigger signal;

[0031] and / or,

[0032] The target trigger signal and the ADC sampling data are stored independently and uploaded to a host computer for analysis, so as to determine the synchronization relationship between the target trigger signal and the ADC sampling data.

[0033] In some embodiments, the method for aligning the high-precision trigger signal and the ADC sampling data further includes:

[0034] The line rate, user data bit width and encoding method of the high-speed transceiver are configured.

[0035] In some embodiments, a device for aligning a high-precision trigger signal and ADC sampling data is also provided, the device comprising: a high-speed transceiver module, a data processing module, a clock cross-domain processing module, and a trigger signal synchronization module;

[0036] The high-speed transceiver module is used to receive a serial trigger signal for triggering ADC sampling; the serial trigger signal is a differential signal; and based on the pre-configured line rate and user data bit width, the high-speed transceiver converts the serial trigger signal into parallel data, and outputs user data and a corresponding user clock frequency; the line rate is greater than or equal to the sampling rate of the ADC;

[0037] The data processing module is used to perform parallel edge detection on the user data in the user clock domain, and identify the edge detection result of the user data in the user clock domain; the edge detection result includes the trigger mode and index of each trigger edge in the user data;

[0038] The clock cross-domain processing module is used to synchronize the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain, and obtain the synchronized parallel trigger data;

[0039] The trigger signal synchronization module is used to determine a target trigger signal that matches the sampling data point time of the ADC from the user data of the parallel trigger data based on the matching result of the parallel trigger data and the sampling rate of the ADC, and the edge detection result in the synchronized parallel trigger data, and align the target trigger signal with the ADC sampling data.

[0040] In an embodiment of the present application, a method and device for aligning a high-precision trigger signal and ADC sampling data are provided. The method for aligning a high-precision trigger signal and ADC sampling data obtains a serial trigger signal for triggering ADC sampling; inputs the serial trigger signal into a high-speed transceiver, and the high-speed transceiver converts the serial trigger signal into parallel data based on a pre-configured line rate and user data bit width, and outputs user data and a corresponding user clock frequency; the line rate is greater than or equal to the sampling rate of the ADC; parallel edge detection is performed on the user data in the user clock domain, and the edge detection result of the user data in the user clock domain is identified. ; The edge detection result includes the trigger mode and index of each trigger edge in the user data; the parallel trigger data including the user data and the edge detection result in the user clock domain are synchronized to the ADC clock domain to obtain the synchronized parallel trigger data; based on the matching result of the parallel trigger data and the sampling rate of the ADC, and the edge detection result in the synchronized parallel trigger data, a target trigger signal that matches the sampling data point time of the ADC is determined from the user data of the parallel trigger data, and the target trigger signal is aligned with the ADC sampling data, thereby achieving precise alignment of the external trigger signal with the high-speed ADC sampling data, significantly improving the time resolution of the trigger signal at an ultra-high sampling rate, and solving the problem of insufficient accuracy of traditional trigger signals in high-speed sampling scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 A flow chart showing a method for aligning a high-precision trigger signal and ADC sampling data according to an embodiment of the present application is shown;

[0043] Figure 2 A schematic diagram of the architecture of the high-precision trigger signal and ADC sampling data alignment system according to an embodiment of the present application is shown;

[0044] Figure 3 A schematic diagram of the original data output path of the high-speed transceiver according to an embodiment of the present application is shown;

[0045] Figure 4 A schematic diagram of waveforms of user data and ADC sampling data according to an embodiment of the present application is shown;

[0046] Figure 5A schematic diagram showing the principle of parallel processing of serial trigger signals and edge detection according to an embodiment of the present application is shown;

[0047] Figure 6 A structural schematic diagram of a high-precision trigger signal and ADC sampling data alignment device described in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0048] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0049] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0050] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0051] With the growing demand for high-speed ADC (analog-to-digital converter) applications with sampling rates exceeding 10Gsps (Giga-bits per second), how to accurately capture the alignment relationship between the external trigger signal and the ADC sampling signal has become a technical challenge. For example, when the ADC is at a sampling rate of fs=32Gsps, if the time accuracy of the external trigger signal is only 1ns, this means that the trigger signal has a time deviation of 1ns, which will cause a deviation of 32 ADC sampling points, while a high-precision data acquisition system requires that the trigger time deviation should reach several or even one sampling point deviation. How to improve the processing time accuracy of the external trigger signal to a higher level than the sampling time accuracy of the ADC is a key technical issue that must be solved in engineering implementation.

[0052] In the prior art, limited by traditional trigger signal control methods, it is difficult for external trigger signals to achieve higher time resolution under ultra-high sampling rate conditions.

[0053] Based on this, in an embodiment of the present application, a method and device for aligning a high-precision trigger signal and ADC sampling data are provided. The method for aligning a high-precision trigger signal and ADC sampling data obtains a serial trigger signal for triggering ADC sampling; inputs the serial trigger signal into a high-speed transceiver, and the high-speed transceiver converts the serial trigger signal into parallel data based on a pre-configured line rate and user data bit width, and outputs user data and a corresponding user clock frequency; the line rate is greater than or equal to the sampling rate of the ADC; parallel edge detection is performed on the user data in the user clock domain, and an edge detection result of the user data in the user clock domain is identified; the edge detection result includes a trigger edge of each trigger edge in the user data. The method comprises the steps of: 1. synchronizing the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain, and obtaining the synchronized parallel trigger data; 2. determining a target trigger signal that matches the sampling data point time of the ADC from the user data of the parallel trigger data based on the matching result of the sampling rate of the parallel trigger data and the ADC, and the edge detection result in the synchronized parallel trigger data, and aligning the target trigger signal with the ADC sampling data, thereby achieving accurate alignment of the external trigger signal with the high-speed ADC sampling data, significantly improving the time resolution of the trigger signal at an ultra-high sampling rate, and solving the problem of insufficient accuracy of the traditional trigger signal in the high-speed sampling scenario.

[0054] Please refer to Figure 1 , Figure 1 A flow chart showing a method for aligning a high-precision trigger signal and ADC sampling data according to an embodiment of the present application is shown; Figure 1 As shown, the method for aligning the high-precision trigger signal and the ADC sampling data includes the following steps S101-S105:

[0055] S101, obtaining a serial trigger signal for triggering ADC sampling; the serial trigger signal is a differential signal;

[0056] S102, inputting the serial trigger signal into a high-speed transceiver, wherein the high-speed transceiver converts the serial trigger signal into parallel data based on a pre-configured line rate and user data bit width, and outputs user data and a corresponding user clock frequency; the line rate is greater than or equal to the sampling rate of the ADC;

[0057] S103, performing parallel edge detection on the user data in the user clock domain, and identifying edge detection results of the user data in the user clock domain; the edge detection results include a trigger mode and an index of each trigger edge in the user data;

[0058] S104, synchronizing the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain, and acquiring the synchronized parallel trigger data;

[0059] S105. Based on the matching result of the parallel trigger data and the sampling rate of the ADC, and the edge detection result in the synchronized parallel trigger data, determine a target trigger signal that matches the sampling data point time of the ADC from the user data of the parallel trigger data, and align the target trigger signal with the ADC sampling data.

[0060] The step of acquiring a differential signal for triggering ADC sampling comprises:

[0061] Get the differential signal output by the external device;

[0062] Alternatively, a single-ended signal output by an external device is obtained, and the single-ended signal is converted into a differential signal by a single-ended to differential module.

[0063] That is, the external signal can be a single-ended signal or a differential signal. If it is a single-ended signal, it needs to be converted into a differential signal.

[0064] The method for aligning high-precision trigger signals and ADC sampling data is applied to a system for aligning high-precision trigger signals and ADC sampling data. The structure of the system is as follows: Figure 2 shown.

[0065] The method for aligning high-precision trigger signals and ADC sampling data described in the embodiment of the present application uses FPGA as the core controller to connect the ultra-high-speed ADC and the external trigger signal source; the external trigger signal is generally a single-ended signal, and after the single-ended signal is converted to differential, the high-speed differential signal is connected to the high-speed transceiver of the FPGA; taking Xilinx VirtexUltraScale+ series FPGA as an example, the GT Transceiver IP core is used to collect the external trigger signal, and the FPGA processes the trigger signal and aligns it with the ADC sampling data.

[0066] Please refer to Figure 2The main modules of the system include: a single-ended to differential module, a high-speed transceiver module, a data processing module, a clock cross-domain processing module, and a trigger signal synchronization module; the single-ended to differential module is used to convert the external input trigger signal from a single-ended signal to a high-speed differential signal; the high-speed transceiver module collects the high-speed differential trigger signal and performs serial-to-parallel conversion; the data processing module processes the trigger signal in parallel and detects the rising and falling edges of the trigger signal; the clock cross-domain processing module processes the cross-clock domain data transmission of the high-speed transceiver clock and the ADC clock through an asynchronous FIFO; the trigger signal synchronization module calculates the time when the trigger signal occurs, and calculates the ADC sampling data point position at the effective time of the trigger, and reorders the ADC sampling data or stores it independently; the analog input signal is input to the ADC through the conditioning circuit, and the ADC collects ADC sampling data based on the sampling frequency fs.

[0067] The high-precision trigger signal and ADC sampling data alignment method described in the embodiment of the present application also includes:

[0068] The line rate, user data bit width and encoding method of the high-speed transceiver are configured.

[0069] First, the external trigger signal is generally a single-ended signal. After the single-ended signal is converted to differential, the high-speed differential signal is connected to the high-speed transceiver of the FPGA. Taking Xilinx Virtex UltraScale+ FPGA as an example, use the GT TransceiverIP core to perform the following configuration:

[0070] Line rate: Set the line rate gt_lane_rate of the GT Transceiver IP core to ensure that the trigger signal can be sampled at a very high speed; gt_lane_rate is generally greater than or equal to the ADC sampling rate fs; illustratively, the line rate gt_lane_rate is set to 32Gbps.

[0071] Coding mode: Set the coding mode to Raw (no coding) mode, bypass all codecs inside the high-speed transceiver, and directly output the original parallel trigger data.

[0072] Data bit width: The bit width of the user data user_trig_data output by the high-speed transceiver is set to N to ensure sufficient time resolution to process the trigger signal of high-speed acquisition. Exemplarily, the bit width of the user data user_trig_data is set to N=160 bits.

[0073] Exemplarily, the user clock frequency user_trig_clk of the high-speed transceiver is 200 MHz.

[0074] The high-speed transceiver converts the serial trigger signal into parallel data based on the pre-configured line rate and user data bit width, and outputs the user data and the corresponding user clock frequency. Specifically, the high-speed transceiver receives the serial trigger signal and converts it into a parallel signal for output, and the parallel user data user_trig_data bit width of the output trigger signal is N bits.

[0075] At the same time, the high-speed transceiver outputs a user clock frequency user_trig_clk of a trigger signal, and the frequency of the user clock frequency user_trig_clk is determined according to the line rate gt_lane_rate. Specifically, the following relationship is satisfied: gt_lane_rate = user_trig_clk * N.

[0076] Specifically, among the N bits of user data user_trig_data[N-1:0], the lower bit is earlier in time than the higher bit; user_trig_data[0] is the trigger signal collected first, and user_trig_data[N-1] is the trigger signal collected last.

[0077] The calculation relationship is satisfied:

[0078] gt_lane_rate = user_trig_clk * width(user_trig_data[N-1:0])

[0079] An example is:

[0080] 32Gbps = 200MHz * 160bit.

[0081] Please refer to Figure 2 , using the high-speed transceiver of FPGA, the conversion purpose of the trigger input serial signal to parallel signal is equivalent to 1:N. Figure 2 The input signal is a high-speed serial signal (serial_IN 1bit), and the output signal is a low-speed serial signal (parallel _OUT Nbit).

[0082] Please refer to Figure 3 , Figure 3 A schematic diagram of the original data output path of the high-speed transceiver according to an embodiment of the present application is shown.

[0083] exist Figure 3 The schematic diagram shown includes two sub-block diagrams on the left and right, which respectively represent the physical medium adaptation layer (PMA) part and the physical coding sublayer (PCS) part.

[0084] The left block diagram is the PMA part, which is mainly used to process analog signals, including equalizer, serial-to-parallel converter and other modules. After serial-to-parallel conversion, the data is transmitted to the PCS part.

[0085] The right block diagram is the PCS part, which mainly processes the received parallel data, including polarity flipping, 8b / 10b decoding, elastic buffer and byte alignment module.

[0086] In the embodiment of the present application, the data transmission path is shown as the light-colored route in the block diagram. The data first completes the serial-to-parallel conversion in the PMA part and passes through the polarity control module; then bypasses the character detection alignment module, 8b / 10b decoding module, receiving elastic buffer and receiving synchronization gearbox, and is finally output to the user. The output data remains in its original state and is uncoded data.

[0087] In the step S103, parallel edge detection is performed on the user data in the user clock domain to identify edge detection results of the user data in the user clock domain; the edge detection results include a trigger mode and an index of each trigger edge in the user data.

[0088] Please refer to Figure 2 , perform edge detection on the output user data user_trig_data[N-1:0] and user clock frequency user_trig_clk.

[0089] Specifically, performing parallel edge detection on the user data in the user clock domain and identifying the edge detection result of the user data in the user clock domain includes:

[0090] Storing the user data;

[0091] Comparing two adjacent bits of data in the user data, if the two adjacent bits of data are different, determining the trigger edge is a rising edge or a falling edge, if they are the same, determining the trigger edge is an invalid edge;

[0092] An index of a trigger edge is determined, and an edge detection result of the user data in a user clock domain is determined.

[0093] The comparing two adjacent bits of data in the user data, and if the two adjacent bits of data are different, determining whether the trigger edge is a rising edge or a falling edge, comprises:

[0094] If the first bit of the two adjacent data is 0 and the second bit is 1, the trigger edge is determined to be a rising edge;

[0095] If the first bit of two adjacent data is 1 and the second bit is 0, the trigger edge is determined to be a falling edge.

[0096] Specifically, in order to detect the edge (rising edge and falling edge) of the trigger signal, the parallel trigger data is stored in a user clock user_trig_clk cycle, the data of the previous beat is recorded as pre_user_trig_data [N-1:0], and the data of the current beat is recorded as user_trig_data [N-1:0]; the specific edge detection steps are as follows:

[0097] Parallel trigger data storage:

[0098] The data of the previous clock beat is recorded as pre_user_trig_data [N-1:0], and the data of the current clock beat is recorded as user_trig_data [N-1:0].

[0099] In the N bits of user_trig_data[N-1:0], the lower bits are earlier in time than the higher bits. user_trig_data[0] is the first trigger signal collected, and user_trig_data[N-1] is the last trigger signal collected.

[0100] Rising and falling edge detection:

[0101] Compare pre_user_trig_data[0] and pre_user_trig_data[1]. If they are different, it is determined to be the rising edge or falling edge of the trigger signal.

[0102] If pre_user_trig_data[0]=0, pre_user_trig_data[1]=1, then record trig_index=1, and trig_mode=1 (rising edge).

[0103] If pre_user_trig_data[0]=1, pre_user_trig_data[1]=0, then record trig_index=0, and trig_mode=2 (falling edge).

[0104] If pre_user_trig_data[0]=0, pre_user_trig_data[1]=0, then record trig_index=0, and trig_mode=0 (invalid edge).

[0105] As described above, the comparison between pre_user_trig_data[1] and pre_user_trig_data[2], ..., the comparison between pre_user_trig_data[N-2] and pre_user_trig_data[N-1], until pre_user_trig_data[N-1] and user_trig_data[0] are performed in sequence, and the index trig_index of the trigger edge and the trigger mode trig_mode are recorded.

[0106] Through the above comparison operation, the precise edge information of the parallel trigger signal can be obtained to achieve high-precision detection of the trigger signal; illustratively, at a line rate of 32 Gbps, the data sampling interval for each bit is 31.25 ps, so extremely high time resolution can be achieved.

[0107] In the step S104, the parallel trigger data including the user data and the edge detection result in the user clock domain is synchronized to the ADC clock domain, and the synchronized parallel trigger data is acquired.

[0108] Specifically, synchronizing the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain, and acquiring the synchronized parallel trigger data includes:

[0109] The write port of the asynchronous FIFO module writes the parallel trigger data in the user clock domain;

[0110] The read port of the asynchronous FIFO module is connected to the ADC clock domain, and reads the parallel trigger data synchronized with the ADC sampling clock to obtain the synchronized parallel trigger data.

[0111] Since user_trig_clk and adc_clk belong to different clock domains, asynchronous FIFO is needed to handle cross-clock domain issues. The write port is connected to the user data user_trig_data, trigger signal index trig_index, and trigger edge trig_mode of the high-speed transceiver trigger signal, and the parallel trigger data under the high-speed transceiver clock domain user_trig_clk is written. The read port is connected to the ADC clock domain adc_clk to read the parallel trigger data synchronized with the ADC sampling clock: including the synchronized user data user_trig_data, the trigger edge index trig_index, and the trigger edge trigger mode trig_mode.

[0112] The data read from the FIFO is synchronized with the ADC sampling data adc_S0 / S1 / Sm-1 to achieve data synchronization processing to ensure that the clock domain conversion between the parallel trigger signal data and the ADC sampling data is correctly aligned.

[0113] In step S105, based on the matching result of the parallel trigger data and the sampling rate of the ADC, and the edge detection result in the synchronized parallel trigger data, a target trigger signal that matches the sampling data point time of the ADC is determined from the user data of the parallel trigger data, and the target trigger signal and the ADC sampling data are aligned.

[0114] Based on the matching result of the parallel trigger data and the sampling rate of the ADC, and the edge detection result in the synchronized parallel trigger data, determining a target trigger signal that matches the sampling data point time of the ADC from the user data of the parallel trigger data, including:

[0115] Calculate the trigger accuracy of the parallel trigger data relative to the ADC sampling data based on the line rate, user data bit width and user clock frequency of the high-speed transceiver, as well as the sampling rate, number of parallel sample points and ADC clock frequency of the ADC;

[0116] Based on the trigger accuracy of the parallel trigger data relative to the ADC sampling data, determining a target trigger signal corresponding to the ADC sampling point in time from the synchronized parallel trigger data;

[0117] Determine trigger signal information of the target trigger signal, where the trigger signal information includes a target trigger mode and a target index corresponding to the target trigger signal.

[0118] The trigger accuracy of the parallel trigger data relative to the ADC sampling data is less than or equal to a sampling point of the ADC sampling data. The edge position of the trigger signal can be obtained through parallel edge detection to achieve edge detection with a time resolution of 1 / gt_lane_rate; the ADC sampling rate fs is less than or equal to gt_lane_rate, therefore, it is necessary to adapt the parallel trigger data and different ADC sampling rates and ADC parallel sampling points.

[0119] In order to adapt to different ADC sampling rates, the method for aligning high-precision trigger signals and ADC sampling data described in the embodiment of the present application provides an adaptive module, which calculates the trigger accuracy of the trigger signal according to relevant parameters. The relevant parameters are as follows: the line rate gt_lane_rate of the high-speed transceiver, the user data user_trig_data bit width N and the user clock user_trig_clk after the trigger signal passes through the high-speed transceiver, the ADC sampling rate fs, the parallel sample points adc_S0 / S1 / Sm-1 transmitted by the ADC in the FPGA, the number of parallel sample points M, and the ADC parallel transmission clock frequency adc_clk.

[0120] The line rate gt_lane_rate of the high-speed transceiver needs to be greater than or equal to the sampling rate fs of the ADC, and generally the two are selected to be equal.

[0121] gt_lane_rate = user_trig_clk * N;

[0122] fs = gt_lane_rate;

[0123] fs = adc_clk x M;

[0124] From the above relationship, we can get:

[0125] user_trig_clk x N = adc_clk x M, generally M=N, that is, the number of samples N of the target trigger signal transmitted in parallel is equal to the number of samples M of the ADC sampling signal transmitted in parallel inside the FPGA, thus user_trig_clk is equal to adc_clk.

[0126] The equivalent time accuracy delta_trig_time of the target trigger signal is:

[0127] delta_trig_time = 1 / fs; when fs = gt_lane_rate, delta_trig_time = 1 / gt_lane_rate.

[0128] The equivalent time accuracy delta_trig_time of the target trigger signal is the trigger accuracy (or equivalent trigger accuracy) of the target trigger signal relative to the ADC sampling data.

[0129] Please refer to Figure 4 , Figure 4 Schematic diagram of waveforms of user data and ADC sampling data according to an embodiment of the present application is shown; Figure 4As shown, the user clock frequency user_trig_clk corresponds to the user data user_trig_data[N-1:0]; the ADC clock frequency adc_clk corresponds to the M sample points in the ADC sampling data parallel sample points adc_S0 / S1 / Sm-1.

[0130] According to the trigger accuracy and position of the target trigger signal relative to the ADC sampling data, the trigger signal is aligned with the sampling data, and the accuracy can reach no more than one sample point. Specifically, within each adc_clk clock cycle, each bit in the target trigger signal user_trig_data[M-1:0] corresponds one-to-one in time to M parallel ADC sampling points; if the transition position of 0 and 1 in user_trig_data[M-1:0] is trig_index=x, the corresponding ADC sampling point adc_Sx is the first sample point of the triggered acquisition.

[0131] After aligning the target trigger signal with the ADC sampling data, the method further includes:

[0132] Recording the ADC sampling data starting from the first sampling point where the target trigger signal occurs, and rearranging the ADC sampling data according to the index of the target trigger signal;

[0133] and / or,

[0134] The target trigger signal and the ADC sampling data are stored independently and uploaded to a host computer for analysis, so as to determine the synchronization relationship between the target trigger signal and the ADC sampling data.

[0135] According to the parallel trigger data user_trig_data, trig_index, and trig_mode read out from FIFO, the target trigger signal edge occurrence time is calculated and aligned with the ADC sampling data sample point.

[0136] Please refer to Figure 5 , Figure 5 FIG. 4 shows a schematic diagram of the principle of parallel processing and edge detection of serial trigger signals according to an embodiment of the present application. Figure 5As shown, the waveform of the serial trigger signal includes a rising edge and a falling edge, and is processed by the high-speed transceiver into an N-bit parallel trigger signal (0, 1...N-1). The N parallel sample points of the sampling signal of the adc_clk cycle are equal to the bit width of the parallel trigger signal, which is N; the N parallel sample points of the ADC sampling signal are S0, S1...SN-1; the parallel trigger signal is edge detected to determine that bit2 in the first parallel trigger signal corresponds to the trigger rising edge, then S2 in the first adc_clk cycle parallel N sampling point data is the ADC sampling point at the same time as the trigger rising edge; similarly, S1 in the second adc_clk cycle parallel N sampling point data is the ADC sampling point at the same time as the trigger falling edge.

[0137] After alignment, the sampled data can be reordered. Specifically, the ADC sampled data is rearranged according to the trigger signal index and recorded starting from the first sample point where the trigger signal occurs.

[0138] Alternatively, an independent storage mode may be used to independently store the target trigger signal and ADC data, and upload them to a host computer for analysis, thereby obtaining a synchronization relationship between the two.

[0139] The method for aligning high-precision trigger signals and ADC sampling data described in the embodiment of the present application is suitable for application scenarios that require precise control of the alignment of trigger signals and ultra-high-speed ADC sampling data, and has broad application prospects in the fields of high-precision measurement, scientific instruments, radar signal processing, etc.

[0140] Trigger signal capture: Accurately capture the synchronization moment of external trigger signal and ADC data.

[0141] Data acquisition: Through high-speed transceivers, accurate recording of ultra-high-rate ADC sampling signals is achieved.

[0142] Based on the same inventive concept, an embodiment of the present application also provides a high-precision trigger signal and ADC sampling data alignment device corresponding to the high-precision trigger signal and ADC sampling data alignment method. Since the principle of solving the problem by the device in the embodiment of the present application is similar to the above-mentioned high-precision trigger signal and ADC sampling data alignment method in the embodiment of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0143] Please refer to Figure 6 , Figure 6 The schematic diagram of the structure of the high-precision trigger signal and ADC sampling data alignment device according to the embodiment of the present application is shown; the high-precision trigger signal and ADC sampling data alignment device comprises: a high-speed transceiver module 601, a data processing module 602, a clock cross-domain processing module 603 and a trigger signal synchronization module 604;

[0144] The high-speed transceiver module 601 is used to receive a serial trigger signal for triggering ADC sampling; the serial trigger signal is a differential signal; and based on the pre-configured line rate and user data bit width, the high-speed transceiver converts the serial trigger signal into parallel data, and outputs user data and a corresponding user clock frequency; the line rate is greater than or equal to the sampling rate of the ADC;

[0145] The data processing module 602 is used to perform parallel edge detection on the user data in the user clock domain, and identify the edge detection result of the user data in the user clock domain; the edge detection result includes the trigger mode and index of each trigger edge in the user data;

[0146] The clock cross-domain processing module 603 is used to synchronize the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain, and obtain the synchronized parallel trigger data;

[0147] The trigger signal synchronization module 604 is used to determine a target trigger signal that matches the sampling data point time of the ADC from the user data of the parallel trigger data based on the matching result of the parallel trigger data and the sampling rate of the ADC, and the edge detection result in the synchronized parallel trigger data, and align the target trigger signal with the ADC sampling data.

[0148] In some embodiments, the high-precision trigger signal and ADC sampling data alignment device also includes: a single-ended to differential module, which obtains a single-ended signal output by an external device and converts the single-ended signal into a differential signal through the single-ended to differential module.

[0149] In some embodiments, in the high-precision trigger signal and ADC sampling data alignment device, the trigger signal synchronization module, when determining the target trigger signal that matches the sampling data point time of the ADC from the user data of the parallel trigger data based on the matching result of the parallel trigger data and the sampling rate of the ADC and the edge detection result in the synchronized parallel trigger data, is specifically used to:

[0150] Calculate the trigger accuracy of the parallel trigger data relative to the ADC sampling data based on the line rate, user data bit width and user clock frequency of the high-speed transceiver, as well as the sampling rate, number of parallel sample points and ADC clock frequency of the ADC;

[0151] Based on the trigger accuracy of the parallel trigger data relative to the ADC sampling data, determining a target trigger signal corresponding to the ADC sampling point in time from the synchronized parallel trigger data;

[0152] Determine trigger signal information of the target trigger signal, where the trigger signal information includes a target trigger mode and a target index corresponding to the target trigger signal.

[0153] In some embodiments, in the high-precision trigger signal and ADC sampling data alignment device, the triggering accuracy of the parallel trigger data relative to the ADC sampling data is less than or equal to one sampling point of the ADC sampling data.

[0154] In some embodiments, in the high-precision trigger signal and ADC sampling data alignment device, the clock cross-domain processing module, when synchronizing the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain and acquiring the synchronized parallel trigger data, is specifically used to:

[0155] The write port of the asynchronous FIFO module writes the parallel trigger data in the user clock domain;

[0156] The read port of the asynchronous FIFO module is connected to the ADC clock domain, and reads the parallel trigger data synchronized with the ADC sampling clock to obtain the synchronized parallel trigger data.

[0157] In some embodiments, in the high-precision trigger signal and ADC sampling data alignment device, the trigger signal synchronization module performs parallel edge detection on the user data in the user clock domain, and identifies the edge detection result of the user data in the user clock domain, specifically for:

[0158] Storing the user data;

[0159] Comparing two adjacent bits of data in the user data, if the two adjacent bits of data are different, determining the trigger edge is a rising edge or a falling edge, if they are the same, determining the trigger edge is an invalid edge;

[0160] An index of a trigger edge is determined, and an edge detection result of the user data in a user clock domain is determined.

[0161] In some embodiments, in the high-precision trigger signal and ADC sampling data alignment device, the trigger signal synchronization module, when comparing two adjacent bits of data in the user data, if the two adjacent bits of data are different, determines that the trigger edge is a rising edge or a falling edge, is specifically used to:

[0162] If the first bit of the two adjacent data is 0 and the second bit is 1, the trigger edge is determined to be a rising edge;

[0163] If the first bit of two adjacent data is 1 and the second bit is 0, the trigger edge is determined to be a falling edge.

[0164] In some embodiments, the high-precision trigger signal and ADC sampling data alignment device configures the line rate, user data bit width and encoding method of the high-speed transceiver.

[0165] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0166] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0167] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0168] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a platform server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0169] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for aligning a high-precision trigger signal and ADC sampling data, characterized in that: The following steps are involved: Acquire a serial trigger signal for triggering ADC sampling; the serial trigger signal is a differential signal; Input the serial trigger signal to a high-speed transceiver, and the high-speed transceiver converts the serial trigger signal into parallel data based on a pre-configured line rate and user data bit width, and outputs user data and a corresponding user clock frequency; the line rate is greater than or equal to the sampling rate of the ADC; Performing parallel edge detection on the user data in the user clock domain, and identifying edge detection results of the user data in the user clock domain; the edge detection results include a trigger mode and an index of each trigger edge in the user data; Synchronize the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain, and obtain the synchronized parallel trigger data; Based on the matching result of the parallel trigger data and the sampling rate of the ADC, and the edge detection result in the synchronized parallel trigger data, determine a target trigger signal that matches the sampling data point time of the ADC from the user data of the parallel trigger data, and align the target trigger signal with the ADC sampling data; Based on the matching result of the parallel trigger data and the sampling rate of the ADC, and the edge detection result in the synchronized parallel trigger data, determining a target trigger signal that matches the sampling data point time of the ADC from the user data of the parallel trigger data, including: Calculate the trigger accuracy of the parallel trigger data relative to the ADC sampling data based on the line rate, user data bit width and user clock frequency of the high-speed transceiver, as well as the sampling rate, number of parallel sample points and ADC clock frequency of the ADC; Based on the trigger accuracy of the parallel trigger data relative to the ADC sampling data, determining a target trigger signal corresponding to the ADC sampling point in time from the synchronized parallel trigger data; Determine trigger signal information of the target trigger signal, where the trigger signal information includes a target trigger mode and a target index corresponding to the target trigger signal.

2. The method for aligning a high-precision trigger signal and ADC sampling data according to claim 1, characterized in that: Get the serial trigger signal used to trigger ADC sampling, including: Get the differential signal output by the external device; Alternatively, a single-ended signal output by an external device is obtained, and the single-ended signal is converted into a differential signal by a single-ended to differential module.

3. The method for aligning high-precision trigger signals and ADC sampling data according to claim 1, characterized in that: The triggering accuracy of the parallel triggering data relative to the ADC sampling data is less than or equal to one sampling point of the ADC sampling data.

4. The method for aligning a high-precision trigger signal and ADC sampling data according to claim 1, characterized in that: The step of synchronizing the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain and acquiring the synchronized parallel trigger data comprises: The write port of the asynchronous FIFO module writes the parallel trigger data in the user clock domain; The read port of the asynchronous FIFO module is connected to the ADC clock domain, and reads the parallel trigger data synchronized with the ADC sampling clock to obtain the synchronized parallel trigger data.

5. The method for aligning high-precision trigger signals and ADC sampling data according to claim 1, characterized in that: The performing parallel edge detection on the user data in the user clock domain and identifying the edge detection result of the user data in the user clock domain includes: Storing the user data; Comparing two adjacent bits of data in the user data, if the two adjacent bits of data are different, determining the trigger edge is a rising edge or a falling edge, if they are the same, determining the trigger edge is an invalid edge; An index of a trigger edge is determined, and an edge detection result of the user data in a user clock domain is determined.

6. The method for aligning high-precision trigger signals and ADC sampling data according to claim 5, characterized in that: The comparing two adjacent bits of data in the user data, and if the two adjacent bits of data are different, determining whether the trigger edge is a rising edge or a falling edge, comprises: If the first bit of the two adjacent data is 0 and the second bit is 1, the trigger edge is determined to be a rising edge; If the first bit of two adjacent data is 1 and the second bit is 0, the trigger edge is determined to be a falling edge.

7. The method for aligning high-precision trigger signals and ADC sampling data according to claim 1, characterized in that: After aligning the target trigger signal with the ADC sampling data, the method further includes: Recording the ADC sampling data from the first sampling point where the target trigger signal occurs, and rearranging the ADC sampling data according to the index of the target trigger signal; and / or, The target trigger signal and the ADC sampling data are stored independently and uploaded to a host computer for analysis, so as to determine the synchronization relationship between the target trigger signal and the ADC sampling data.

8. The method according to claim 1, characterized in that The method further comprises: The line rate, user data bit width and encoding method of the high-speed transceiver are configured.

9. A device for aligning a high-precision trigger signal with ADC sampling data, characterized in that: The device comprises: a high-speed transceiver module, a data processing module, a clock cross-domain processing module and a trigger signal synchronization module; The high-speed transceiver module is used to receive a serial trigger signal for triggering ADC sampling; the serial trigger signal is a differential signal; and based on the pre-configured line rate and user data bit width, the high-speed transceiver converts the serial trigger signal into parallel data, and outputs user data and a corresponding user clock frequency; the line rate is greater than or equal to the sampling rate of the ADC; The data processing module is used to perform parallel edge detection on the user data in the user clock domain, and identify the edge detection result of the user data in the user clock domain; the edge detection result includes the trigger mode and index of each trigger edge in the user data; The clock cross-domain processing module is used to synchronize the parallel trigger data including the user data and the edge detection result in the user clock domain to the ADC clock domain, and obtain the synchronized parallel trigger data; The trigger signal synchronization module is used to determine a target trigger signal that matches the sampling data point time of the ADC from the user data of the parallel trigger data based on the matching result of the parallel trigger data and the sampling rate of the ADC and the edge detection result in the synchronized parallel trigger data, and align the target trigger signal with the ADC sampling data; Based on the matching result of the parallel trigger data and the sampling rate of the ADC, and the edge detection result in the synchronized parallel trigger data, determining a target trigger signal that matches the sampling data point time of the ADC from the user data of the parallel trigger data, including: Calculate the trigger accuracy of the parallel trigger data relative to the ADC sampling data based on the line rate, user data bit width and user clock frequency of the high-speed transceiver, as well as the sampling rate, number of parallel sample points and ADC clock frequency of the ADC; Based on the trigger accuracy of the parallel trigger data relative to the ADC sampling data, determining a target trigger signal corresponding to the ADC sampling point in time from the synchronized parallel trigger data; Determine trigger signal information of the target trigger signal, where the trigger signal information includes a target trigger mode and a target index corresponding to the target trigger signal.

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