Signal channel delay adjusting method and device of test equipment

Abstract

The invention relates to a signal channel delay adjusting method and device of test equipment. The method comprises the following steps: a processing module acquires respective corresponding delay compensation values when a plurality of signal channels of test equipment are compared with a reference channel; the delay compensation value is used for increasing or decreasing the delay amount when the signal channel outputs the target test signal; for each signal channel, according to the delay compensation value and the clock period of the clock signal of the test equipment, the compensation period number corresponding to the coarse delay compensation amount and the fine delay compensation amount are calculated, and the sum of the coarse delay compensation amount and the fine delay compensation amount is the delay compensation value; and controlling the reading time of the cross-clock domain data transmission module on the written test signal data based on the compensation period number and the fine delay compensation amount, so that the cross-clock domain data transmission module reads the test signal data at the reading time. According to the application, the delay amount when the signal channel outputs the target test signal can be increased, and the delay amount when the signal channel outputs the target test signal can also be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method and device for adjusting delay of a signal channel of a testing device. Background Art

[0002] In the field of semiconductor technology, automated test equipment (ATE for short) is a machine used to automatically test chips. According to the requirements of the chip, it is necessary to use ATE equipment to generate test signals of various waveforms, and send the corresponding test signals to different pins of the chip for testing. Different chips have different requirements for the timing of test signals. For example, some chips require the waveforms of the test signals of all signal channels to be aligned, that is, the delay amount of the test signals output by each signal channel is consistent, and some chips require that the test signals output between different signal channels have a fixed time difference. Affected by factors such as circuit structure, manufacturing process and temperature, the timing requirements cannot be met without calibrating the delay between the output signals of each channel. Before using the ATE equipment, the delay between the output signals of each channel needs to be calibrated so that the delay difference between the test signals meets specific requirements. Currently, TDL (Tap Delay Line) is commonly used to adjust the delay.

[0003] like Figure 1 As shown, TDL is to cascade L delay units DU, and the delay size can be configured by controlling the conduction level of the delay unit. Among them, the input end in is used to input the signal to be delayed, the output end out is used to output the delayed signal, and the MUX (Multiplexer) can control the selection of one of the multiple inputs to be connected to the output end out, and L is a positive integer.

[0004] The delay amount of each delay unit in TDL is d. If the MUX selects the Nth delay unit to output the test signal, the delay amount of the output test signal is Δt=N*d. Figure 2 As shown, the delay amount of the test signal OUT relative to the trigger signal IN is N*d.

[0005] However, by adjusting the delay of the test signal output through TDL to achieve signal phase adjustment, only positive compensation can be achieved, but negative compensation cannot be achieved. Here, positive compensation is defined as increasing the delay of the test signal output by the signal channel, and negative compensation is defined as reducing the delay of the test signal output by the signal channel.

[0006] When calibrating multiple signal channels of ATE equipment, since there are many signal channels that need to be calibrated, if a few signal channels need to perform reverse compensation on the output time of the test signal (these few signal channels will lag behind other channels in outputting the test signal, then the output time of these few signal channels needs to be advanced), if the existing TDL is used for delay adjustment, then other signal channels need to be uniformly forward compensated, which results in a large workload for compensation and more errors are easily introduced when performing delay compensation on most signal channels. Summary of the invention

[0007] The purpose of the present application is to provide a method and device for adjusting the delay of a signal channel of a test device, which can both increase the delay of a signal channel output signal and reduce the delay of a signal channel output signal, thereby reducing the workload of delay compensation and avoiding the introduction of more errors.

[0008] According to a first aspect of an embodiment of the present application, a method for adjusting signal channel delay of a test device is provided, comprising:

[0009] The processing module obtains the delay compensation values ​​corresponding to the multiple signal channels of the test device compared with the reference channels respectively; wherein the delay compensation values ​​are used to increase or decrease the delay amount when the signal channels output the target test signals;

[0010] For each signal channel, the processing module calculates the number of compensation cycles corresponding to the coarse delay compensation amount and the fine delay compensation amount according to the delay compensation value and the clock cycle of the clock signal of the test device, wherein the sum of the coarse delay compensation amount and the fine delay compensation amount is the delay compensation value;

[0011] The processing module controls the reading time of the written test signal data by the cross-clock domain data transmission module based on the number of compensation cycles and the fine delay compensation amount, so that the cross-clock domain data transmission module reads the test signal data at the reading time, so that different signal channels output the target test signal according to the delay amount compensated by the delay compensation value, thereby realizing delay compensation for different signal channels; wherein, the test signal data is used to generate the target test signal, and there is a time interval between the reading time and the time of writing the test signal data to the cross-clock domain data transmission module.

[0012] According to a second aspect of an embodiment of the present application, a signal channel delay adjustment device for a test device is provided, wherein the test device has multiple signal channels; the device comprises: a processing module and a cross-clock domain data transmission module electrically connected to the processing module;

[0013] The processing module is used to calculate the delay compensation values ​​corresponding to the multiple signal channels of the test device respectively compared with the reference channels; wherein the delay compensation value is used to increase or decrease the delay amount when the signal channel outputs the target test signal; and is also used to calculate the number of compensation cycles and the fine delay compensation amount corresponding to the coarse delay compensation amount for each signal channel according to the delay compensation value and the clock cycle of the clock signal of the test device, wherein the sum of the coarse delay compensation amount and the fine delay compensation amount is the delay compensation value; and is also used to control the reading time of the cross-clock domain data transmission module for the written test signal data based on the number of compensation cycles and the fine delay compensation amount;

[0014] The cross-clock domain data transmission module is used to read the test signal data at the reading time, so that different signal channels output the target test signal according to the delay amount compensated by the delay compensation value, thereby realizing delay compensation for different signal channels; wherein, the test signal data is used to generate the target test signal, and there is a time interval between the reading time and the time of writing the test signal data to the cross-clock domain data transmission module.

[0015] Compared with the prior art, the beneficial effect of the present application is that whether increasing or decreasing the delay amount when the signal channel outputs the target test signal, it can be achieved based on the processing module and the cross-clock domain data transmission module. Therefore, the technical solution of the present application can increase the delay amount of the signal channel output signal, and can also reduce the delay amount of the signal channel output signal, which is conducive to reducing the workload of delay compensation and avoiding the introduction of more errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of a tapped delay line according to the related art.

[0017] Figure 2 It is a schematic diagram showing the delay amount of a tapped delay line outputting a test signal according to the related art.

[0018] Figure 3 It is a structural schematic diagram of a signal channel delay adjustment device of a test device according to an exemplary embodiment.

[0019] Figure 4 The present invention is a schematic diagram showing a process of data buffer amount changing during asynchronous FIFO operation according to an exemplary embodiment.

[0020] Figure 5 The diagram is a schematic diagram showing a data reading principle according to an exemplary embodiment.

[0021] Figure 6The figure is a schematic diagram showing an asynchronous FIFO fine delay adjustment principle according to an exemplary embodiment.

[0022] Figures 7 and 8 It is a schematic diagram showing a delay reverse adjustment principle (delay reduction) of an asynchronous FIFO output according to an exemplary embodiment.

[0023] Fig. 9 The diagram is a schematic diagram showing a method of increasing the delay amount when a signal channel outputs a target test signal according to an exemplary embodiment.

[0024] Fig.10 The diagram is a schematic diagram showing a method of reducing the delay amount when a signal channel outputs a target test signal according to an exemplary embodiment.

[0025] Fig.11 The present invention is a flowchart of a method for adjusting signal channel delay of a test device according to an exemplary embodiment.

[0026] Fig.12 The present invention is a flowchart of a method for adjusting signal channel delay of a testing device according to another exemplary embodiment.

[0027] Fig.13 The present invention is a flowchart of a method for adjusting signal channel delay of a testing device according to another exemplary embodiment. DETAILED DESCRIPTION

[0028] Unless otherwise defined, the technical terms or scientific terms used in this specification and claims shall have the usual meanings understood by persons with ordinary skills in the technical field to which the invention belongs. The specific embodiments of the present invention will be described below in conjunction with the accompanying drawings. It should be noted that in the specific description of these embodiments, in order to provide a concise description, it is impossible for this specification to provide a detailed description of all the features of the actual embodiments. Without departing from the spirit and scope of the present invention, those skilled in the art may modify and replace the embodiments of the present invention, and the resulting embodiments are also within the scope of protection of the present invention.

[0029] In the related art, there are two defects in adjusting the delay by TDL to achieve signal phase adjustment. The first is that the delay adjustment range is small due to the limitation of the number of delay units. The second is that the delay cannot be reversely compensated (that is, the minimum delay value is 0, and negative values ​​cannot be compensated).

[0030] In order to solve the above technical problems, the present application proposes a signal channel delay adjustment method and device for a test device, which can both increase the delay of the signal channel output signal and reduce the delay of the signal channel output signal, which is beneficial to reduce the workload of delay compensation and avoid introducing more errors.

[0031] An embodiment of the present application provides a signal channel delay adjustment device for a test device. The test device has multiple signal channels, and the signal channel delay adjustment device is used to adjust the delay amount when the multiple signal channels in the test device output test signals to meet the delay requirements when the multiple signal channels output test signals, wherein the delay requirements include but are not limited to the delays of the signals in the multiple signal channels being consistent or maintaining a fixed delay interval between each other.

[0032] In some embodiments, the test equipment may be, for example, an ATE device for automatically testing chips, and the ATE device may generate various test signals for different chips to be tested and different test items. When performing a test operation, multiple signal channels in the ATE device are electrically connected to multiple pins in the chip to be tested, and the ATE device generates a test signal with a corresponding delay amount, and the test signal is transmitted to the corresponding multiple pins via each signal channel for testing.

[0033] In some embodiments, the chip under test requires that the signal waveforms of each test signal transmitted to multiple pins remain aligned (i.e., the delay of the test signal remains consistent). In some embodiments, the chip under test requires that the signal of each test signal transmitted to multiple pins maintain a fixed delay interval. Generally, the signal delays between the various signal channels in the ATE equipment are inconsistent and may not meet the delay requirements. Therefore, the delay amount of each signal channel needs to be adjusted accordingly before the ATE equipment is used to ensure that the waveform of the output signal remains aligned or has a fixed delay interval.

[0034] In some embodiments, the signal channel delay adjustment device of the test equipment may be located on an FPGA (Field Programmable Gate Array) chip, but is not limited thereto.

[0035] like Figure 3 As shown, the signal channel delay adjustment device of the test equipment may include a processing module 31, a cross-clock domain data transmission module 32, a delay chain module 33, a write module 34, a read module 35 and a digital comparator 36, and the processing module 31 is electrically connected with the cross-clock domain data transmission module 32, the delay chain module 33, the write module 34, the read module 35 and the digital comparator 36. Among them, the cross-clock domain data transmission module 32 includes a write port 321, a second storage module 322 and a read port 323.

[0036] In this embodiment, the cross-clock domain data transmission module 32 may be an asynchronous first-in first-out (ASYNC First In First Out, referred to as FIFO) module. In another embodiment, the cross-clock domain data transmission module 32 may be a dual-port RAM (Random Access Memory), but is not limited thereto.

[0037] In this embodiment, if Figure 3 As shown, the processing module 31 can respectively obtain the delay amount when the multiple signal channels Ch1, Ch2, Ch3, ..., Chn of the ATE device output the target test signal, wherein a delay amount measurement module (not shown in the figure) can also be included between the processing module 31 and Ch1, Ch2, Ch3 in the ATE device, and the transmission delay of each signal channel is measured by the delay amount measurement module.

[0038] First, the processing module 31 obtains the delay compensation values ​​corresponding to the multiple signal channels Ch1, Ch2, Ch3, ..., Chn of the test equipment compared with the reference channel, respectively. The delay compensation values ​​are used to increase or decrease the delay amount when the signal channels Ch1, Ch2, Ch3, ..., Chn output the target test signal.

[0039] The following specifically describes how the processing module 31 obtains the delay compensation values ​​corresponding to the multiple signal channels Ch1, Ch2, Ch3, ..., Chn of the test device, respectively, compared with the reference channel.

[0040] In this embodiment, the corresponding initial signals sig10, sig20, sig30, ..., sign0 can be respectively input into the multiple signal channels Ch1, Ch2, Ch3, ..., Chn of the ATE device, and the transmission delay of the multiple signal channels Ch1, Ch2, Ch3, ..., Chn to the initial signals sig10, sig20, sig30, ..., sign0 can be measured by the delay measurement module, and the processing module 31 can obtain the transmission delay. For example, for the signal channel Ch1, the corresponding initial signal sig10 can be input into the signal channel Ch1 of the ATE device, and the transmission delay of the signal channel Ch1 to the initial signal sig10 can be measured.

[0041] Then, the processing module 31 selects a reference channel from the multiple signal channels Ch1, Ch2, Ch3, ..., Chn, and calculates the time difference between each signal channel and the reference channel based on the transmission delay corresponding to each signal channel and the transmission delay of the reference channel as a delay compensation value.

[0042] In this embodiment, for each signal channel, the transmission delay of the signal channel minus the transmission delay of the reference channel may be calculated to obtain a time difference as the delay compensation value. In another embodiment, for each signal channel, the transmission delay of the reference channel minus the transmission delay of the signal channel may be calculated to obtain a time difference as the delay compensation value.

[0043] In this embodiment, the processing module 31 may select a signal channel with the largest transmission delay from multiple signal channels Ch1, Ch2, Ch3, ..., Chn as a reference channel. For example, if the transmission delay of signal channel Ch1 is the largest, signal channel Ch1 is selected as the reference channel.

[0044] In another embodiment, the processing module 31 may select any one signal channel from the multiple signal channels Ch1, Ch2, Ch3, . . . , Chn as a reference channel.

[0045] In another embodiment, the processing module 31 may read the delay compensation values ​​of the multiple signal channels Ch1 , Ch2 , Ch3 , . . . , Chn pre-stored in the first storage module compared with the reference channel.

[0046] In this embodiment, when the chip under test requires that the signal waveforms of each test signal transmitted to multiple pins remain aligned (that is, the delay of the test signal remains consistent), the delay when the multiple signal channels Ch1, Ch2, Ch3, ..., Chn output the test signal is consistent with the delay when the reference channel outputs the test signal. If the time difference obtained by subtracting the transmission delay of the reference channel from the transmission delay of the signal channel is used as the delay compensation value, the delay compensation value is a positive value, and it is necessary to reduce the time when the multiple signal channels Ch1, Ch2, Ch3, ..., Chn output the test signal. Delay, if the delay compensation value is a negative value, it is necessary to increase the delay when the multiple signal channels Ch1, Ch2, Ch3, ..., Chn output the test signal; if the time difference obtained by subtracting the transmission delay of each signal channel from the transmission delay of the reference channel is used as the delay compensation value, and the delay compensation value is a positive value, it is necessary to increase the delay when the multiple signal channels Ch1, Ch2, Ch3, ..., Chn output the test signal; if the delay compensation value is a negative value, it is necessary to reduce the delay when the multiple signal channels Ch1, Ch2, Ch3, ..., Chn output the test signal.

[0047] Next, for each signal channel, the processing module 31 calculates the coarse delay compensation amount (t c) corresponds to the number of compensation cycles and the fine delay compensation amount, wherein the sum of the coarse delay compensation amount and the fine delay compensation amount is the delay compensation value. It should be noted that the clock signal refers to the clock signal used by the signal channel delay adjustment device in the ATE device. Based on the clock signal, the write clock and the read clock can be obtained, thereby controlling the write module 34 to write the test signal data to the cross-clock domain data transmission module and the read module 35 to read the test signal data.

[0048] In this embodiment, the number of compensation cycles corresponding to the coarse delay compensation amount can be obtained by the processing module 31 according to formula (1):

[0049] n=Δt / T clock (1)

[0050] Where Δt represents the delay compensation value, T clock It represents the clock period of the clock signal of the test equipment, and n represents the number of compensation periods corresponding to the coarse delay compensation amount.

[0051] The processing module 31 obtains the fine delay compensation amount according to formula (2):

[0052] t r =Δt%T clock (2)

[0053] Among them, t r Indicates the fine delay compensation amount, t c +t r =Δt.

[0054] Next, the processing module 31 calculates the compensation cycle number (n) and the fine delay compensation amount (t r ) controls the reading time of the cross-clock domain data transmission module 32 for the written test signal data data, so that the cross-clock domain data transmission module 32 reads the test signal data data at the reading time, so that different signal channels Ch1, Ch2, Ch3, ..., Chn output corresponding target test signals sig1, sig2, sig3, ..., sign according to the delay amount compensated by the delay compensation value (Δt), thereby realizing the delay compensation for different signal channels Ch1, Ch2, Ch3, ..., Chn. Among them, the test signal data data is used to generate the corresponding target test signals sig1, sig2, sig3, ..., sign. It should be noted that there is a time interval between the reading time and the time of writing the test signal data to the cross-clock domain data transmission module, that is, when the time to write the test signal data is reached, the writing module 34 writes data to the cross-clock domain data transmission module, and when the time interval reaches the reading time, the reading module 35 reads the test signal data, that is, it can be that the processing module 31 can be based on the number of compensation cycles (n) and the fine delay compensation amount (t r) controls the time interval between the time of writing the test signal data data and the time of reading the test signal data data, thereby realizing the control of the reading time. In addition, the time interval described refers to the time interval between the time of writing and the time of reading the same test signal data data.

[0055] In this embodiment, the processing module 31 first calculates the reference value (M) of the digital comparator 36 based on the compensation cycle number (n), and sends the reference value (M) to the digital comparator 36 .

[0056] In this embodiment, the processing module 31 calculates the reference value (M) of the digital comparator 36 as follows: for each signal channel, the processing module 31 determines whether to increase the coarse delay compensation amount (t c ) or reduce the coarse delay compensation of the signal channel (t c ). When the processing module 31 determines to increase the coarse delay compensation amount (t c ), the sum of the initial data volume of the digital comparator 36 and the number of compensation cycles is calculated to obtain a reference value (M), where M=M0+n, and M0 is the initial data volume cached by the cross-clock domain data transmission module 32. When the processing module 31 determines to reduce the coarse delay compensation amount (t c ), the difference between the initial data amount of the digital comparator 36 and the number of compensation cycles is calculated to obtain a reference value (M), where M=M0-n.

[0057] In this embodiment, the time difference obtained by subtracting the transmission delay of the reference channel from the transmission delay of the signal channel is used as the delay compensation value as an example. When the coarse delay compensation value (t c ) is a positive value, the processing module 31 determines to reduce the coarse delay compensation amount (t c ), when the coarse delay compensation amount (t c ) is a negative value, the processing module 31 determines to increase the coarse delay compensation amount (t c ).

[0058] In this embodiment, M0 is set based on the maximum value of the product delay compensation plus a margin. For example, the maximum compensation values ​​of the product in the forward and reverse directions are both 50 clock cycles, and the margin is 10. Then M0 is set to 50+10=60, and the total depth D of the asynchronous FIFO is set to 2M0=120. It should be noted that M0 in this embodiment is only an example, and other values ​​of M0 can be selected according to actual application conditions.

[0059] In this embodiment, the delay of the output data of the signal channel can be adjusted over a wide range based on the coarse delay compensation amount, and both forward compensation and reverse compensation can be achieved.

[0060] The processing module 31 controls the delay chain module 33 based on the fine delay compensation amount (t r ) delays the write clock clock1 to generate the read clock clock2. The write clock clock1 is obtained based on the clock signal of the test equipment, and the clock period of the write clock clock1, the clock period of the read clock clock2 and the clock period of the clock signal (T clock ) are consistent.

[0061] In this embodiment, the processing module 31 controls the delay chain module 33 to delay the write clock clock1 based on the fine delay compensation amount to generate the read clock clock2 as follows: for each signal channel, the processing module 31 determines whether to increase the fine delay compensation amount (t r ) or reduce the fine delay compensation amount of the signal channel (t r ). When the processing module 31 determines to increase the fine delay compensation amount (t r ), the delay chain module 33 increases the delay of the write clock clock1 by t r , generating the read clock clock2. When the processing module 31 determines to reduce the fine delay compensation amount (t r ), the delay chain module 33 increases the delay of the write clock clock1 by T clock -t r , generating the read clock clock2. The principle of reducing the fine delay compensation amount of the signal channel by increasing the delay of the write clock clock1 will be described below.

[0062] In this embodiment, when the fine delay compensation amount (t r ) is a positive value, the processing module 31 determines to reduce the fine delay compensation amount (t r ), when the fine delay compensation amount (t r ) is a negative value, the processing module 31 determines to increase the fine delay compensation amount (t r ).

[0063] In this embodiment, the delay of the output data of the signal channel can be adjusted in a small range based on the fine delay compensation amount, and forward compensation and reverse compensation can be achieved.

[0064] In summary, in the present application, the reference value M and the fine delay compensation amount can be controlled to control the time interval between the reading time and the time when the test signal data is written into the cross-clock domain data transmission module, so that the cross-clock domain data transmission module reads the data at the reading time, that is, the data can be read when the rising edge of the read clock clock2 at the reading time arrives, so as to compensate the delay compensation value of each signal channel compared with the reference channel. The delay compensation value can be increased or decreased, that is, the delay amount when the signal channel outputs the target test signal can be increased, and the delay amount when the signal channel outputs the target test signal can be reduced. Moreover, the delay amount when the signal channel outputs the target test signal can be adjusted in a large range, and the delay amount when the signal channel outputs the target test signal can be adjusted in a small range. In summary, the present application can realize a bidirectional large-scale adjustment of the delay amount when the signal channel outputs the target test signal.

[0065] In this embodiment, the read clock clock2 and the write clock clock1 have the same frequency but different phases (delay causes waveform deviation); since the asynchronous FIFO reads the test signal data based on the read clock clock2 (data is read when the rising edge of the read clock clock2 arrives), adjusting the clock phase can achieve the purpose of fine-tuning the delay of the output signal.

[0066] In this embodiment, the delay chain module 33 may be a TDL, that is, the delay chain module 33 includes a plurality of cascaded delay units. The processing module 31 controls the delay chain module 33 based on the fine delay compensation amount (t r ) The method for delaying the write clock clock1 to generate the read clock clock2 is as follows: the processing module 31 determines the conduction level of the delay unit in the delay chain module 33 based on the fine delay compensation amount, and then the processing module 31 turns on the delay units of the corresponding level in the delay chain module 33 based on the conduction level, and outputs the read clock clock2.

[0067] In this embodiment, an asynchronous FIFO is used to adjust the delay of the signal channel output signal. The write port 321 writes data synchronously with the write clock clock1, and the read port 323 reads data synchronously with the read clock clock2. The data output delay is achieved by adjusting the time of reading data of the asynchronous FIFO.

[0068] It should be noted that, in the embodiments of the present application, the explanation is made while ignoring the delay caused by the data volume calculation and comparison of the read port 323. In some cases, in the asynchronous FIFO, even if the write port 321 and the read port 323 share the write clock clock1, the reading data has a delay of P clock cycles compared to the writing data itself, but the delay is an inherent delay (determined by the solution architecture itself). In the process of implementing the solution, when compensating for the delay, it is equivalent to that each signal channel has its own inherent delay. Therefore, in the present application, if the time for reading data is adjusted in this case, it is assumed by default that it is based on a delay of P clock cycles, and the delay caused by the device is no longer emphasized.

[0069] In this embodiment, the write module 34 writes the test signal data data into the second storage module 322 through the write port 321 based on the write clock clock1, and the write port 321 sends the write address corresponding to the written test signal data data to the read port 323. The read port 323 obtains the data amount in the second storage module 322 based on the received write address and read address, and sends the data amount to the digital comparator 36. The digital comparator 36 compares the reference value (M) with the above data amount, and sends the comparison result to the read module 35. When the comparison result indicates that the data amount is equal to the reference value (M), the read module 35 reads the test signal data data from the second storage module 322 through the read port 323 based on the read clock clock2, wherein the read test signal data data is written by the write module 34 before the clock cycles of the write clock clock1. In this way, different signal channels Ch1, Ch2, Ch3, ..., Chn can output corresponding target test signals sig1, sig2, sig3, ..., sign according to the delay amount compensated by the delay compensation value (Δt), thereby realizing delay compensation for different signal channels Ch1, Ch2, Ch3, ..., Chn.

[0070] In this embodiment, after the processing module 31 controls the reading time of the written test signal data by the cross-clock domain data transmission module 32 based on the number of compensation cycles and the fine delay compensation amount, it also generates a retest signal and performs a retest operation using the retest signal to determine whether the signal channels Ch1, Ch2, Ch3, ..., Chn meet the calibration requirements. When the signal channels Ch1, Ch2, Ch3, ..., Chn meet the calibration requirements, it is determined that the calibration is successful.

[0071] In this embodiment, the processing module 31 compensates for the delay of the output signals of the signal channels Ch1, Ch2, Ch3, ..., Chn and generates a re-measurement signal. The transmission delay of each signal channel is re-measured by the re-measurement signal, which is recorded as T1, T2, T3, ..., Tn, and the transmission delay of each signal channel obtained after the re-measurement is stored.

[0072] Then, it is determined whether the transmission delay of each signal channel retest meets the calibration requirements. If so, the calibration is successful. If not, the calibration is unsuccessful, and a prompt message may be output to indicate that the calibration has failed.

[0073] For example, when the chip under test requires that the signal waveforms of each test signal transmitted to multiple pins remain aligned (that is, the delay of the test signal remains consistent), it is determined whether the transmission delay of each signal channel retest is consistent. If they are consistent, the calibration is successful; if not, the calibration is unsuccessful.

[0074] In one embodiment, the specific method of the processing module 31 generating the retest signal is as follows:

[0075] After calculating and adjusting the reference value (M) of the digital comparator 36 according to the number of compensation cycles corresponding to the coarse delay compensation amount, and adjusting the conduction level of TDL according to the fine delay amount (the conduction level of the delay unit determined by the processing module 31 based on the fine delay compensation amount), the signal channel delay adjustment device of the test equipment is reset. After the reset, the data in the asynchronous FIFO41 is cleared, and the device restarts to work. At each rising edge of the write clock clock1, the write module 34 writes the test signal data data into the second storage module 322 through the write port 321. At the same time, at each rising edge of the write clock clock1, the write port 321 sends the write address corresponding to the written test signal data data to the read port 323. As the test signal data data is continuously written into the second storage module 322 at each rising edge of the write clock clock1, the test signal data data in the second storage module 322 increases continuously.

[0076] According to the above, after TDL adjustment, the read clock clock 2 with a certain delay is output (relative to the write clock clock 1 with a delay t r ), at the rising edge of the read clock clock2, the read port 323 acquires the write address sent by the write port 321, and obtains the data amount in the second storage module 322 based on the write address and the read address. The digital comparator 36 will also obtain the data amount in the second storage module 322 and compare the obtained data amount with the reference value to obtain a comparison result, and feed the comparison result back to the read module 35. The read module 35 determines whether to start the read operation according to the comparison result. When the comparison result shows that the data amount in the second storage module 322 reaches M, the read operation is started, that is, the test signal data data is read from the asynchronous FIFO41 at the rising edge of the read clock clock2. The read test signal data data is written by the write module 34 before the clock cycles of the write clock clock1.

[0077] Adjust the retention time of the test signal data data in the asynchronous FIFO41, including adjusting the amount of data in the asynchronous FIFO41 to reach M before starting to read the test signal data data and adjusting the TDL delay to adjust the rising edge position of the read clock clock2, so as to adjust the read-out time of the test signal data data, that is, the adjustment of the data delay. At this time, the time for reading the test signal data data from the asynchronous FIFO41 has passed M*T clock (the time period corresponding to the writing module 34 writing into the second storage module 322) and the difference t between the reading clock clock2 and the writing clock clock1 r , thus achieving a certain delay in the output retest signal.

[0078] In this embodiment, the processing module obtains the delay compensation values ​​corresponding to the multiple signal channels of the test device respectively compared with the reference channel, wherein the delay compensation value can be used to increase or decrease the delay amount when the signal channel outputs the target test signal, and then, for each signal channel, the processing module calculates the compensation cycle number and the fine delay compensation amount corresponding to the coarse delay compensation amount according to the delay compensation value and the clock cycle of the clock signal of the test device, wherein the sum of the coarse delay compensation amount and the fine delay compensation amount is the delay compensation value, and finally, the processing module controls the reading time of the cross-clock domain data transmission module for the written test signal data based on the compensation cycle number and the fine delay compensation amount, so that the cross-clock domain data transmission module reads the test signal data when the reading time is reached, so that different signal channels output the target test signal according to the delay amount compensated by the delay compensation value, and the delay compensation of different signal channels is realized. That is, based on the processing module and the cross-clock domain data transmission module, the delay amount when the signal channel outputs the target test signal can be increased, and the delay amount when the signal channel outputs the target test signal can also be reduced, which is conducive to reducing the workload of delay compensation and avoiding the introduction of more errors.

[0079] The above is an overall introduction to the signal channel delay adjustment device of the test equipment provided in the embodiment of the present application. The following is a detailed introduction to some parts thereof.

[0080] 1. The change process of data cache amount and the principle of coarse delay compensation in asynchronous FIFO work

[0081] 1.1. Data writing phase

[0082] like Figure 4 As shown, the amount of data that can be stored in the asynchronous FIFO 41 is D, the amount of data that has been stored is represented by shaded grids, and the amount of data that has not been stored is represented by white background grids.

[0083] At the first rising edge of the write clock clock1 , there is no data in the asynchronous FIFO 41 , and the write module 34 is writing the test signal data data into the asynchronous FIFO 41 through the write port 321 . At this time, there is no data in the asynchronous FIFO 41 .

[0084] At the second rising edge of the write clock clock1, there is 1 data in the asynchronous FIFO41, and the write module 34 is writing the next test signal data data into the asynchronous FIFO41 through the write port 321. At this time, the amount of data in the asynchronous FIFO41 is 1, that is, after the first rising edge of the write clock, the amount of data in the asynchronous FIFO41 is 1.

[0085] At the third rising edge of the write clock clock1, there are 2 test signal data in the asynchronous FIFO41, and the write module 34 is writing the next test signal data data to the asynchronous FIFO41 through the write port 321. At this time, the amount of data in the asynchronous FIFO41 is 2, that is, after the second rising edge of the write clock, the amount of data in the asynchronous FIFO41 is 2.

[0086] …

[0087] At the Mth rising edge of the write clock clock1, there are M-1 test signal data in the asynchronous FIFO41, and the write module 34 is writing the next test signal data data to the asynchronous FIFO41 through the write port 321. At this time, the amount of data in the asynchronous FIFO41 is M-1, that is, after the M-1th rising edge of the write clock, the amount of data in the asynchronous FIFO is M-1.

[0088] It should be noted that, at this stage, the amount of data in the asynchronous FIFO 41 has not reached M, and the read port 323 of the asynchronous FIFO 41 has not been triggered to read the test signal data data.

[0089] 1.2 Data reading principle

[0090] At each rising edge of the write clock clock1, in addition to receiving the data written by the write module 34, the write port 321 of the asynchronous FIFO41 also sends the write address corresponding to the written test signal data data to the read port 323, so that the read port 323 obtains the amount of data in the asynchronous FIFO41 based on the write address and the read address. At the rising edge of each read clock clock2, the read port 323 obtains the amount of data in the asynchronous FIFO41 based on the write address and the read address. The digital comparator 36 obtains the amount of data in the read port 323 of the asynchronous FIFO41, and compares the reference value with the data amount to obtain a comparison result, and feeds the comparison result back to the read module 35. The read module 35 determines whether to start reading data based on the comparison result. When the comparison result received by the read module is that the data amount is equal to the reference value (M), it is determined to start reading data. The read module 35 will read the test signal data written before M clock cycles of the write clock clock1 through the read port 323 at the rising edge of the read clock clock2 (this is the nature of the FIFO itself, and the data written first will be read out (the data amount is not transmitted in real time, and is refreshed once at each rising edge of the write clock clock1).

[0091] After reading out the data, the change in the amount of data in the asynchronous FIFO41 is described as follows:

[0092] like Figure 5 As shown, a test signal data data is written at the Mth clock rising edge R1 of the write clock clock1, and the amount of data in the asynchronous FIFO41 after the Mth clock rising edge R1 is M. At the Mth clock rising edge R2 of the read clock clock2, the read port 323 synchronously processes and calculates the data amount, and then compares it through the digital comparator 36, and triggers the read module 35 to read out a test signal data data written before M clock cycles of the write clock clock1 through the read port 323. When the test signal data data is read out, there are M-1 data left in the asynchronous FIFO41.

[0093] A test signal data data is written at the M+1th clock rising edge R3 of the write clock clock1. After the M+1th clock rising edge R3, there are M data in the asynchronous FIFO41. At the M+1th clock rising edge R4 of the read clock clock2, the read module 35 is triggered to read out a test signal data data written before M clock cycles of the write clock clock1 through the read port 323. After the test signal data data is read out, there are M-1 data left in the asynchronous FIFO41.

[0094] At the M+2th rising edge of the write clock clock1, a test signal data data is written. After the M+1th rising edge of the clock, there are M data in the asynchronous FIFO41. At the M+2th rising edge of the read clock clock2, the read module 35 is triggered to read out a test signal data data written before M clock cycles of the write clock clock1 through the read port 323. After the test signal data data is read out, there are M-1 data left in the asynchronous FIFO41.

[0095] …

[0096] In summary, without considering the fine delay compensation, after each test signal data is written into the asynchronous FIFO41, it is output after M clock cycles. The coarse delay of the test signal data after passing through the asynchronous FIFO41 is t c =M*T clock .

[0097] Therefore, adjusting the amount of data M buffered by the asynchronous FIFO 41 can achieve the purpose of adjusting the coarse delay.

[0098] 2. Asynchronous FIFO fine delay compensation description

[0099] 2.1、Principle of Asynchronous FIFO Delay Compensation

[0100] In the first part above, data is read without TDL adjustment, that is, without changing the delay amount of the read clock clock 2. The following further describes how to use the asynchronous FIFO 41 to achieve fine delay compensation:

[0101] That is, if fine delay control is required, it is only necessary to adjust the conduction level of the delay unit in the TDL so that a read clock clock 2 having a certain delay is generated relative to the write clock clock 1.

[0102] like Figure 6 As shown, the delay of the read clock clock2 compared to the write clock clock1 is t tdl The test signal data data will be obtained by the read module 35 at the read port 323 based on the write address and the read address. The first rising edge of the read clock clock2 after the data amount in the asynchronous FIFO41 is M (the first arrow t g The data is collected at the asynchronous FIFO 41, and then the read port 323 calculates the amount of data in the asynchronous FIFO 41 according to the collected information. After obtaining the data amount, the digital comparator 36 compares the data amount with the reference value M. When the data amount is greater than or equal to M, the read module 35 is triggered to read out a test signal data data written before M clock cycles of the write clock clock1.

[0103] 2.2. Delay reverse adjustment principle of asynchronous FIFO output (reducing delay)

[0104] According to the introduction in Section 2.1, Figure 7 As shown in Part A of FIG. 1 , if the read clock clock2 is delayed relative to the write clock clock1 by t tdl , the test signal data data will be obtained at the read port 323 based on the write address and the read address. After the data amount in the asynchronous FIFO41 is M, the first read clock clock2 rising edge (the first arrow t g ) is read out and collected.

[0105] like Figure 7 As shown in part B of the diagram, if the delay t of the read clock clock2 relative to the write clock clock1 is tdl Larger, for example, greater than one clock cycle and less than two clock cycles, Figure 7 The first arrow in part A of g exist Figure 7 Part B is moved to the second arrow t g1 Position, second arrow t g1 The previous clock rising edge (the first arrow t g The read port 323 first obtains the data amount M in the asynchronous FIFO based on the write address and the read address, and the digital comparator 36 compares the data amount with the reference value M, and then sends a read instruction to the read module 35, and the read module 35 reads the corresponding test signal data data through the read port 323. This realizes the data readout time shifting to the left by shifting the clock to the right.

[0106] like Figure 8 As shown, the delay of the read clock clock2 is increased by T clock –t, read clock clock2 and shift it to the right by T clock -t, original first arrow t g After moving, reach the second arrow t g1 Position, beyond the information collection boundary of the data volume M, that is, at the second arrow t g1 The read clock corresponding to the position, the read port 323 obtains the data amount in the asynchronous FIFO41 based on the write address and the read address is not M, then the digital comparator 36 compares the data amount is not the reference value M, then the read module will not be triggered to read the data, the previous clock edge (the third arrow t g2 ) enters the information collection range of the data volume M, that is, at the rising edge of the previous clock (the third arrow t g2) The read port 323 at the asynchronous FIFO obtains the data amount M based on the write address and the read address. After the digital comparator 36 compares the data amount with the reference value M, the read module 35 obtains the comparison result through the read port 323 and reads the data when it determines that the data amount is equal to M. Since the read data is synchronized with the read clock clock2, reverse regulation is achieved; in this way, it can be achieved by increasing T through clock delay clock -t, which reduces the delay of output data by t.

[0107] 3. Increase delay

[0108] like Fig. 9 As shown, when the delay compensation value Δt is used to increase the delay amount when the signal channel outputs the target test signal, the reference value M is obtained by increasing the initial data amount M0 of the asynchronous FIFO41 by n, M=M0+n, and the delay of the read clock clock2 is increased by t r Among them, the coarse delay compensation amount t c =n*T clock , M is an integer greater than 1.

[0109] Before increasing the delay of the signal channel outputting the target test signal, g3 Read out data at time t g4 Read data at any time. g4 Time and t g3 The time delay between the moments is Δt, Δt = t c +t r . Fig. 9 Clock20 is the initial read clock before increasing the delay amount when the signal channel outputs the target test signal.

[0110] 4. Reduce latency

[0111] like Fig.10 As shown, when the delay compensation value Δt is used to reduce the delay when the signal channel outputs the target test signal, the reference value M is obtained by reducing the initial data amount M0 of the asynchronous FIFO41 by n, M=M0-n, and the delay of the read clock clock2 is increased by T clock -t r , to reduce the delay of output data by t r Among them, the coarse delay compensation amount t c =n*T clock , M is an integer greater than 1.

[0112] Before reducing the delay of the signal channel outputting the target test signal, g3 Read out data at time t g4Read data at any time. g4 Time and t g3 The time delay between the moments is Δt, Δt = -(t c +t r ). Fig.10 Clock20 is the initial read clock before reducing the delay amount when the signal channel outputs the target test signal.

[0113] The above introduces the signal channel delay adjustment device of the test equipment provided in the embodiment of the present application. The following introduces the signal channel delay adjustment method of the test equipment provided in the embodiment of the present application.

[0114] Another embodiment of the present application provides a method for adjusting the delay of a signal channel of a test device. The method is used to cooperate with the signal channel delay adjustment device of the test device to adjust the delay amount when multiple signal channels in the test device output test signals. Fig.11 The signal channel delay adjustment method of the test device may include the following steps 1101 to 1103:

[0115] Step 1101, the processing module obtains the delay compensation values ​​corresponding to the multiple signal channels of the test equipment compared with the reference channels respectively; wherein the delay compensation values ​​are used to increase or decrease the delay amount when the signal channels output the target test signals.

[0116] In this step, the processing module 31 obtains the delay compensation values ​​corresponding to the multiple signal channels Ch1, Ch2, Ch3, ..., Chn of the test equipment respectively compared with the reference channel. The delay compensation values ​​are used to increase or decrease the delay amount when the signal channels Ch1, Ch2, Ch3, ..., Chn output the target test signal respectively.

[0117] In one embodiment, Fig.12 As shown, step 1101 may include the following steps 1201-1202:

[0118] Step 1201: input an initial signal to multiple signal channels, and measure the transmission delay of each of the multiple signal channels to the initial signal.

[0119] Step 1202: The processing module selects a reference channel from the multiple signal channels, and calculates the time difference between each signal channel and the reference channel based on the transmission delay corresponding to each signal channel and the transmission delay of the reference channel as a delay compensation value.

[0120] In one embodiment, the corresponding initial signals sig10, sig20, sig30, ..., sign0 can be input into the multiple signal channels Ch1, Ch2, Ch3, ..., Chn of the ATE device respectively, and the transmission delay of the multiple signal channels Ch1, Ch2, Ch3, ..., Chn to the initial signals sig10, sig20, sig30, ..., sign0 can be measured by the delay measurement module. The processing module 31 can obtain the transmission delay.

[0121] Then, the processing module 31 selects a reference channel from the multiple signal channels Ch1, Ch2, Ch3, ..., Chn, and calculates the time difference between each signal channel and the reference channel based on the transmission delay corresponding to each signal channel and the transmission delay of the reference channel as a delay compensation value.

[0122] In one embodiment, the method for selecting a reference channel from multiple signal channels by the processing module is as follows: the processing module selects any signal channel from the multiple signal channels as the reference channel, or the processing module selects the signal channel with the largest transmission delay from the multiple signal channels as the reference channel.

[0123] In one embodiment, for each signal channel, the transmission delay of the signal channel minus the transmission delay of the reference channel may be calculated to obtain a time difference as the delay compensation value. In another embodiment, for each signal channel, the transmission delay of the reference channel minus the transmission delay of the signal channel may be calculated to obtain a time difference as the delay compensation value.

[0124] In one embodiment, for each signal channel, the transmission delay of the signal channel minus the transmission delay of the reference channel may be calculated to obtain a time difference as the delay compensation value. In another embodiment, for each signal channel, the transmission delay of the reference channel minus the transmission delay of the signal channel may be calculated to obtain a time difference as the delay compensation value.

[0125] In another embodiment, the processing module 31 may read the delay compensation values ​​of the multiple signal channels Ch1 , Ch2 , Ch3 , . . . , Chn pre-stored in the first storage module compared with the reference channel.

[0126] In this embodiment, when the chip to be tested requires that the signal waveforms of each test signal transmitted to multiple pins remain aligned (that is, the delay of the test signal remains consistent), the delay when the multiple signal channels Ch1, Ch2, Ch3, ..., Chn output the test signal is made consistent with the delay when the reference channel outputs the test signal. If the time difference obtained by subtracting the transmission delay of the reference channel from the transmission delay of the signal channel is used as the delay compensation value, the delay compensation value is a positive value, and it is necessary to reduce the delay when the multiple signal channels Ch1, Ch2, Ch3, ..., Chn output the test signal. If the delay compensation value is a negative value, it is necessary to increase the delay when the multiple signal channels Ch1, Ch2, Ch3, ..., Chn output the test signal. If the time difference obtained by subtracting the transmission delay of each signal channel from the transmission delay of the reference channel is used as the delay compensation value, if the delay compensation value is a positive value, it is necessary to increase the delay when the multiple signal channels Ch1, Ch2, Ch3, ..., Chn output the test signal; if the delay compensation value is a negative value, it is necessary to reduce the delay when the multiple signal channels Ch1, Ch2, Ch3, ..., Chn output the test signal.

[0127] Step 1102, for each signal channel, the processing module calculates the number of compensation cycles corresponding to the coarse delay compensation amount and the fine delay compensation amount according to the delay compensation value and the clock period of the clock signal of the test equipment, wherein the sum of the coarse delay compensation amount and the fine delay compensation amount is the delay compensation value.

[0128] In one embodiment, the number of compensation cycles corresponding to the coarse delay compensation amount can be obtained by the processing module 31 according to formula (1):

[0129] n=Δt / T clock (1)

[0130] Where Δt represents the delay compensation value, T clock It represents the clock period of the clock signal of the test equipment, and n represents the number of compensation periods corresponding to the coarse delay compensation amount.

[0131] The processing module 31 obtains the fine delay compensation amount according to formula (2):

[0132] t r =Δt%T clock (2)

[0133] Among them, t r Indicates the fine delay compensation amount, t c +t r =Δt.

[0134] Step 1103, the processing module controls the reading time of the cross-clock domain data transmission module for the written test signal data based on the number of compensation cycles and the fine delay compensation amount, so that the cross-clock domain data transmission module reads the test signal data at the reading time, so that different signal channels output the target test signal according to the delay amount compensated by the delay compensation value, and the delay compensation of different signal channels is realized. Among them, the test signal data is used to generate the target test signal, and there is a time interval between the reading time and the time of writing the test signal data to the cross-clock domain data transmission module.

[0135] In one embodiment, Figure 3 As shown, the cross-clock domain data transmission module 32 includes a write port 321 , a second storage module 322 and a read port 323 .

[0136] In one embodiment, the cross-clock domain data transmission module 32 may be an asynchronous first-in first-out (FIFO) module. In another embodiment, the cross-clock domain data transmission module 32 may be a dual-port RAM (Random Access Memory), but is not limited thereto.

[0137] In one embodiment, Fig.13 As shown, step 1103 may include the following steps 1301 to 1306:

[0138] Step 1301: The processing module calculates a reference value M of the digital comparator based on a compensation period, and sends the reference value M to the digital comparator.

[0139] In one embodiment, for each signal channel, the processing module 31 determines whether to increase the coarse delay compensation amount (t c ) or reduce the coarse delay compensation of the signal channel (t c ). When the processing module 31 determines to increase the coarse delay compensation amount (t c ), the sum of the initial data volume of the digital comparator 36 and the number of compensation cycles is calculated to obtain a reference value (M), where M=M0+n, and M0 is the initial data volume cached by the cross-clock domain data transmission module 32. When the processing module 31 determines to reduce the coarse delay compensation amount (t c ), the difference between the initial data amount of the digital comparator 36 and the number of compensation cycles is calculated to obtain a reference value (M), where M=M0-n.

[0140] In this embodiment, the time difference obtained by subtracting the transmission delay of the reference channel from the transmission delay of the signal channel is used as the delay compensation value as an example. When the coarse delay compensation value (t c ) is a positive value, the processing module 31 determines to reduce the coarse delay compensation amount (tc ), when the coarse delay compensation amount (t c ) is a negative value, the processing module 31 determines to increase the coarse delay compensation amount (t c ).

[0141] In one embodiment, M0 is set based on the maximum value of the product delay compensation plus a margin. For example, the maximum compensation values ​​of the product in the forward and reverse directions are both 50 clock cycles, and the margin is 10. Then M0 is set to 50+10=60, and the total depth D of the asynchronous FIFO is set to 2M0=120. It should be noted that M0 in this embodiment is only an example, and other values ​​of M0 may be selected according to actual application conditions.

[0142] In one embodiment, the delay of the output data of the signal channel can be adjusted over a wide range based on the coarse delay compensation amount, and both forward compensation and reverse compensation can be achieved.

[0143] Step 1302: The processing module controls the delay chain module to delay the write clock based on the fine delay compensation amount to generate a read clock, wherein the write clock is obtained based on the clock signal, and the clock period of the write clock, the clock period of the read clock and the clock period of the clock signal are consistent.

[0144] In one embodiment, for each signal channel, the processing module 31 determines whether to increase the fine delay compensation amount (t r ) or reduce the fine delay compensation amount of the signal channel (t r ). When the processing module 31 determines to increase the fine delay compensation amount (t r ), the delay chain module 33 increases the delay of the write clock clock1 by t r , generate the read clock clock2. Wherein, the write clock clock1 is obtained based on the clock signal of the test equipment, and the clock period of the write clock clock1, the clock period of the read clock clock2 and the clock period of the clock signal (T clock ) is consistent. When the processing module 31 determines to reduce the fine delay compensation amount (t r ), the delay chain module 33 increases the delay of the write clock clock1 by T clock -t r , generating the read clock clock2. The principle of reducing the fine delay compensation amount of the signal channel by increasing the delay of the write clock clock1 has been introduced above and will not be repeated here.

[0145] In this embodiment, when the fine delay compensation amount (t r ) is a positive value, the processing module 31 determines to reduce the fine delay compensation amount (t r ), when the fine delay compensation amount (tr ) is a negative value, the processing module 31 determines to increase the fine delay compensation amount (t r ).

[0146] In one embodiment, the delay of the output data of the signal channel can be adjusted in a small range based on the fine delay compensation amount, so that both forward compensation and reverse compensation can be achieved.

[0147] In the present application, the delay compensation value can be increased or decreased, that is, the delay amount when the signal channel outputs the target test signal can be increased or decreased. Moreover, the delay amount when the signal channel outputs the target test signal can be adjusted over a large range, or the delay amount when the signal channel outputs the target test signal can be adjusted over a small range. In summary, the present application can achieve bidirectional and large-scale adjustment of the delay amount when the signal channel outputs the target test signal.

[0148] In one embodiment, the read clock clock2 and the write clock clock1 have the same frequency but different phases (delay causes waveform deviation); since the asynchronous FIFO reads the test signal data based on the read clock clock2 (data is read when the rising edge of the read clock clock2 arrives), adjusting the clock phase can achieve the purpose of fine-tuning the delay of the output signal.

[0149] In one embodiment, the delay chain module 33 may be a TDL, that is, the delay chain module 33 includes a plurality of cascaded delay units. The processing module 31 may determine the number of on-stage delay units in the delay chain module 33 based on the fine delay compensation amount, and then the processing module 31 turns on the delay units of the corresponding stages in the delay chain module 33 based on the number of on-stage delay units, and outputs the read clock clock2.

[0150] In the application, an asynchronous FIFO is used to adjust the delay of the signal channel output signal. The write port 321 writes data synchronously with the write clock clock1, and the read port 323 reads data synchronously with the read clock clock2. The data output delay can be achieved by adjusting the time of reading data of the asynchronous FIFO.

[0151] It should be noted that, in the embodiments of the present application, the explanation is made while ignoring the delay caused by the data volume calculation and comparison of the read port 323. In some cases, in the asynchronous FIFO, even if the write port 321 and the read port 323 share the write clock clock1, the reading data has a delay of P clock cycles compared to the writing data itself, but the delay is an inherent delay (determined by the solution architecture itself). In the process of implementing the solution, when compensating for the delay, it is equivalent to that each signal channel has its own inherent delay. Therefore, in the present application, if the time for reading data is adjusted in this case, it is assumed by default that it is based on a delay of P clock cycles, and the delay caused by the device is no longer emphasized.

[0152] Step 1303: The write module writes the test signal data into the second storage module through the write port based on the write clock, and sends the write address corresponding to the written test signal data to the read port through the write port.

[0153] In this step, the write module 34 writes the test signal data data into the second storage module 322 through the write port 321 based on the write clock clock1 , and the write port 321 sends the write address corresponding to the write test signal data data to the read port 323 .

[0154] Step 1304: The read port obtains the amount of data in the second storage module based on the write address and the read address, and sends the amount of data to the digital comparator.

[0155] In this step, the read port 323 obtains the amount of data in the second storage module 322 based on the received write address and read address, and sends the amount of data to the digital comparator 36 .

[0156] Step 1305: The digital comparator compares the reference value with the data amount and sends the comparison result to the reading module.

[0157] In this step, the digital comparator 36 compares the reference value (M) with the above-mentioned data amount and sends the comparison result to the reading module 35.

[0158] Step 1306, when the comparison result indicates that the data amount is equal to the reference value, the read module reads the test signal data from the second storage module through the read port based on the read clock, and the test signal data is written by the write module M write clock cycles ago.

[0159] In this step, when the comparison result indicates that the data amount is equal to the reference value (M), the read module 35 reads the test signal data data from the second storage module 322 through the read port 323 based on the read clock clock2, wherein the read test signal data data is written by the write module 34 before the clock cycles of the M write clock clock1. In this way, different signal channels Ch1, Ch2, Ch3, ..., Chn can output corresponding target test signals sig1, sig2, sig3, ..., sign according to the delay amount compensated by the delay compensation value (Δt), thereby realizing the delay compensation of different signal channels Ch1, Ch2, Ch3, ..., Chn.

[0160] In one embodiment, after step 1103, the following steps are also included: generating a retest signal, and performing a retest operation using the retest signal to determine whether the signal channel meets the calibration requirements; when the calibration requirements are met, it is determined that the calibration is successful.

[0161] In one embodiment, the processing module 31 generates a re-measurement signal after compensating for the delay of the output signals of the signal channels Ch1, Ch2, Ch3, ..., Chn, and re-measures the transmission delay of each signal channel through the re-measurement signal, which is recorded as T1, T2, T3, ..., Tn, and stores the transmission delay of each signal channel obtained after the re-measurement.

[0162] Then, it is determined whether the transmission delay of each signal channel retest meets the calibration requirements. If so, the calibration is successful. If not, the calibration is unsuccessful, and a prompt message may be output to indicate that the calibration has failed.

[0163] For example, when the chip under test requires that the signal waveforms of each test signal transmitted to multiple pins remain aligned (that is, the delay of the test signal remains consistent), it is determined whether the transmission delay of each signal channel retest is consistent. If they are consistent, the calibration is successful; if not, the calibration is unsuccessful.

[0164] In one embodiment, the specific method of generating the retest signal is as follows:

[0165] After calculating and adjusting the reference value (M) of the digital comparator 36 according to the number of compensation cycles corresponding to the coarse delay compensation amount, and adjusting the conduction level of TDL according to the fine delay amount (the conduction level of the delay unit determined by the processing module 31 based on the fine delay compensation amount), the signal channel delay adjustment device of the test equipment is reset. After the reset, the data in the asynchronous FIFO41 is cleared, and the device restarts to work. At each rising edge of the write clock clock1, the write module 34 writes the test signal data data into the second storage module 322 through the write port 321. At the same time, at each rising edge of the write clock clock1, the write port 321 sends the write address corresponding to the written test signal data data to the read port 323. As the test signal data data is continuously written into the second storage module 322 at each rising edge of the write clock clock1, the test signal data data in the second storage module 322 increases continuously.

[0166] According to the above, after TDL adjustment, the read clock clock 2 with a certain delay is output (relative to the write clock clock 1 with a delay t r ), at the rising edge of the read clock clock2, the read port 323 acquires the write address sent by the write port 321, and obtains the data amount in the second storage module 322 based on the write address and the read address. The digital comparator 36 will also obtain the data amount in the second storage module 322 and compare the obtained data amount with the reference value to obtain a comparison result, and feed the comparison result back to the read module 35. The read module 35 determines whether to start the read operation according to the comparison result. When the comparison result shows that the data amount in the second storage module 322 reaches M, the read operation is started, that is, the test signal data data is read from the asynchronous FIFO41 at the rising edge of the read clock clock2. The read test signal data data is written by the write module 34 before the clock cycles of the write clock clock1.

[0167] Adjust the retention time of the test signal data data in the asynchronous FIFO41, including adjusting the amount of data in the asynchronous FIFO41 to reach M before starting to read the test signal data data and adjusting the TDL delay to adjust the rising edge position of the read clock clock2, so as to adjust the read-out time of the test signal data data, that is, the adjustment of the data delay. At this time, the time for reading the test signal data data from the asynchronous FIFO41 has passed M*T clock (the time period corresponding to the writing module 34 writing into the second storage module 322) and the difference t between the reading clock clock2 and the writing clock clock1 r , thus achieving a certain delay in the output retest signal.

[0168] The above introduces the signal channel delay adjustment method of the test equipment provided in the embodiment of the present application. It should be noted that the signal channel delay adjustment method of the test equipment in this embodiment cooperates with the signal channel delay adjustment device of the test equipment mentioned above to achieve the adjustment of the delay amount when the multiple signal channels in the test equipment output test signals. The introduction contents of the two parts can complement each other.

[0169] In this embodiment, the processing module obtains the delay compensation values ​​corresponding to the multiple signal channels of the test device respectively compared with the reference channel, wherein the delay compensation value can be used to increase or decrease the delay amount when the signal channel outputs the target test signal, and then, for each signal channel, the processing module calculates the number of compensation cycles corresponding to the coarse delay compensation amount and the fine delay compensation amount according to the delay compensation value and the clock cycle of the clock signal of the test device, wherein the sum of the coarse delay compensation amount and the fine delay compensation amount is the delay compensation value, and finally, the processing module controls the reading time of the cross-clock domain data transmission module for the written test signal data based on the number of compensation cycles and the fine delay compensation amount, so that the cross-clock domain data transmission module reads the test signal data at the reading time, so that different signal channels output the target test signal according to the delay amount compensated by the delay compensation value, and realizes the delay compensation for different signal channels. That is, based on the processing module and the cross-clock domain data transmission module, the delay amount when the signal channel outputs the target test signal can be increased, and the delay amount when the signal channel outputs the target test signal can also be reduced, which is conducive to reducing the workload of delay compensation and avoiding the introduction of more errors.

[0170] In the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0171] The above description of the embodiments is to facilitate those of ordinary skill in the art to understand and apply the present application. It is obvious that those familiar with the art can easily make various modifications to these embodiments and apply the general principles described herein to other embodiments without having to pay creative labor. Therefore, the present application is not limited to the embodiments herein, and improvements and modifications made by those skilled in the art based on the contents disclosed in the present application without departing from the scope and spirit of the present application are within the scope of the present application.

Claims

1. A method for adjusting signal channel delay of a test device, characterized in that: include: The processing module obtains the delay compensation values ​​corresponding to the multiple signal channels of the test device compared with the reference channels respectively; wherein the delay compensation values ​​are used to increase or decrease the delay amount when the signal channels output the target test signals; For each signal channel, the processing module calculates the number of compensation cycles corresponding to the coarse delay compensation amount and the fine delay compensation amount according to the delay compensation value and the clock cycle of the clock signal of the test device, wherein the sum of the coarse delay compensation amount and the fine delay compensation amount is the delay compensation value; The processing module controls the reading time of the written test signal data by the cross-clock domain data transmission module based on the number of compensation cycles and the fine delay compensation amount, so that the cross-clock domain data transmission module reads the test signal data at the reading time, so that different signal channels output the target test signal according to the delay amount compensated by the delay compensation value, thereby realizing delay compensation for different signal channels; wherein, the test signal data is used to generate the target test signal, and there is a time interval between the reading time and the time of writing the test signal data to the cross-clock domain data transmission module.

2. The signal channel delay adjustment method of the test equipment according to claim 1, characterized in that: The processing module obtains the delay compensation values ​​corresponding to the multiple signal channels of the test device compared with the reference channels, respectively, including: Inputting an initial signal to the plurality of signal channels, and measuring the transmission delay of each of the plurality of signal channels to the initial signal; The processing module selects the reference channel from the multiple signal channels, and based on the transmission delay corresponding to each signal channel and the transmission delay of the reference channel, calculates the time difference between each signal channel and the reference channel as the delay compensation value.

3. The signal channel delay adjustment method of the test equipment according to claim 2, characterized in that: The processing module selects the reference channel from the multiple signal channels, including: The processing module selects any one of the signal channels from the multiple signal channels as the reference channel, or, The processing module selects the signal channel with the largest transmission delay from the multiple signal channels as the reference channel.

4. The signal channel delay adjustment method of the test equipment according to claim 1, characterized in that: The processing module obtains the delay compensation values ​​corresponding to the multiple signal channels of the test device compared with the reference channels, respectively, including: The processing module reads the respective delay compensation values ​​of the plurality of signal channels compared with the reference channel pre-stored in the first storage module.

5. The signal channel delay adjustment method of the test equipment according to claim 1, characterized in that: The processing module obtains the number of compensation cycles corresponding to the coarse delay compensation amount according to formula (1): n=Δt / T clock (1) Wherein, Δt represents the delay compensation value, T clock represents the clock period of the clock signal of the test device, and n represents the number of compensation periods corresponding to the coarse delay compensation amount; The processing module obtains the fine delay compensation amount according to formula (2): t r =Δt%T clock (2) Among them, t r Indicates the fine delay compensation amount.

6. The signal channel delay adjustment method of the test equipment according to claim 1, characterized in that: The cross-clock domain data transmission module comprises a write port, a second storage module and a read port; the processing module controls the reading time of the cross-clock domain data transmission module for the written test signal data based on the number of compensation cycles and the fine delay compensation amount, so that the cross-clock domain data transmission module reads the test signal data at the reading time, including: The processing module calculates a reference value M of the digital comparator based on the compensation period, and sends the reference value M to the digital comparator; The processing module controls the delay chain module to delay the write clock based on the fine delay compensation amount to generate a read clock, wherein the write clock is obtained based on the clock signal, and the clock period of the write clock, the clock period of the read clock and the clock period of the clock signal are consistent; The writing module writes the test signal data into the second storage module through the writing port based on the writing clock, and sends the writing address corresponding to the writing of the test signal data to the reading port through the writing port; The read port obtains the amount of data in the second storage module based on the write address and the read address, and sends the amount of data to the digital comparator; The digital comparator compares the reference value with the data amount and sends the comparison result to a reading module; When the comparison result indicates that the data amount is equal to the reference value, the read module reads the test signal data from the second storage module through the read port based on the read clock, and the test signal data is written by the write module before M clock cycles of the write clock.

7. The signal channel delay adjustment method of the test equipment according to claim 6, characterized in that: The processing module calculates the reference value M of the digital comparator based on the number of compensation cycles, including: The processing module determines whether to increase the coarse delay compensation amount of the signal channel or to decrease the coarse delay compensation amount of the signal channel; When the processing module determines to increase the coarse delay compensation amount of the signal channel, the sum of the initial data amount of the digital comparator and the number of compensation cycles is calculated to obtain the reference value, wherein M=M0+n, M0 is the initial data amount; When the processing module determines to reduce the coarse delay compensation amount of the signal channel, the difference between the initial data amount of the digital comparator and the number of compensation cycles is calculated to obtain the reference value, wherein M=M0-n.

8. The signal channel delay adjustment method of the test equipment according to claim 6, characterized in that: The processing module controls the delay chain module to delay the write clock based on the fine delay compensation amount to generate a read clock, including: The processing module determines whether to increase or decrease the fine delay compensation amount of the signal channel; When the processing module determines to increase the fine delay compensation amount of the signal channel, the delay chain module increases the delay of the write clock by t r , generating the read clock; When the processing module determines to reduce the fine delay compensation amount of the signal channel, the delay chain module increases the delay of the write clock by T clock -t r , generating the read clock.

9. The signal channel delay adjustment method of the test equipment according to claim 6, characterized in that: The delay chain module includes a plurality of cascaded delay units; The processing module controls the delay chain module to delay the write clock based on the fine delay compensation amount to generate a read clock, including: The processing module determines the conduction level of the delay unit in the delay chain module based on the fine delay compensation amount; The processing module turns on the delay unit in the delay chain module based on the turn-on level number.

10. The signal channel delay adjustment method of the test equipment according to claim 1, characterized in that: After the processing module controls the reading time of the cross-clock domain data transmission module for the written test signal data based on the number of compensation cycles and the fine delay compensation amount, the method further includes: A retest signal is generated, and a retest operation is performed using the retest signal to determine whether the signal channel meets the calibration requirements; when the calibration requirements are met, it is determined that the calibration is successful.

11. A signal channel delay adjustment device for a test device, characterized in that: The test equipment has multiple signal channels; the device comprises: a processing module and a cross-clock domain data transmission module electrically connected to the processing module; The processing module is used to calculate the delay compensation values ​​corresponding to the multiple signal channels of the test device respectively compared with the reference channels; wherein the delay compensation value is used to increase or decrease the delay amount when the signal channel outputs the target test signal; and is also used to calculate the number of compensation cycles and the fine delay compensation amount corresponding to the coarse delay compensation amount for each signal channel according to the delay compensation value and the clock cycle of the clock signal of the test device, wherein the sum of the coarse delay compensation amount and the fine delay compensation amount is the delay compensation value; and is also used to control the reading time of the cross-clock domain data transmission module for the written test signal data based on the number of compensation cycles and the fine delay compensation amount; The cross-clock domain data transmission module is used to read the test signal data at the reading time, so that different signal channels output the target test signal according to the delay amount compensated by the delay compensation value, thereby realizing delay compensation for different signal channels; wherein, the test signal data is used to generate the target test signal, and there is a time interval between the reading time and the time of writing the test signal data to the cross-clock domain data transmission module.

12. The signal channel delay adjustment device of the test equipment according to claim 11, characterized in that: Also includes: A delay chain module, a write module, a read module and a digital comparator, the cross-clock domain data transmission module includes a write port, a second storage module and a read port; the processing module is electrically connected to the delay chain module, the write module, the read module and the digital comparator respectively; The processing module is further used to calculate the compensation cycle number n of the coarse delay compensation amount based on the delay compensation value and the clock cycle; and calculate the reference value M of the digital comparator based on the compensation cycle number n, and send the reference value M to the digital comparator; and is also used to control the delay chain module to delay the write clock based on the fine delay compensation amount to generate a read clock; wherein the write clock is obtained based on the clock signal, and the clock cycle of the write clock, the clock cycle of the read clock and the clock cycle of the clock signal are consistent; The write module is used to write the test signal data into the second storage module through the write port based on the write clock; The write port is used to send a write address corresponding to the test signal data to the read port; The read port is used to obtain the amount of data in the second storage module based on the write address and the read address, and send the amount of data to the digital comparator; The digital comparator is used to compare the reference value M with the data amount and send the comparison result to the reading module; The read module is used to read the test signal data from the second storage module through the read port based on the read clock when the comparison result indicates that the data amount is equal to the reference value, and the test signal data is written by the write module before M clock cycles of the write clock.

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