Method and equipment for realizing hardware delay of inserted optical module

Abstract

The invention provides a method and equipment for realizing hardware delay for an inserted optical module. The method further comprises the following steps of: respectively providing an in-place register positioned on the logic control device for the plurality of optical module ports; defining an optical module insertion pin located on the logic control device for each of the plurality of optical module ports; a logic control module located on the logic control device detects the initial input level change of each connected optical module insertion pin, and calculates hardware delay time based on a frequency division clock signal provided by a frequency division clock signal circuit located on the logic control device; and after the initial input level change of each optical module insertion pin reaches hardware delay time, the logic control module modifies the in-place register corresponding to each optical module insertion pin to be in-place and outputs a hardware interrupt signal to the processor.

Description

Technical Field

[0001] The present application relates to electronic circuit technology, and more specifically to a method and device for implementing hardware delay of an inserted optical module. Background Art

[0002] The different types of optical module ports provided by the network device are used to connect to various types of optical modules. After the port of the network device is connected to the optical module, the inserted optical module must be initialized before the network device can read the data of the optical module. Otherwise, the reading of the data fails or is incorrect. Therefore, after the network device senses that the optical module is inserted, it needs to wait for a time greater than the initialization time of the optical module before reading the inserted optical module data and identifying the inserted optical module.

[0003] Currently, network equipment uses software delay to read the data of the inserted optical module, ensuring that the data of the inserted optical module is read after the initialization of the inserted optical module is completed.

[0004] In one software delay mode, the processor of the network device starts the software task, and reads the in-place register of each port in a fixed order. When the in-place register is read to indicate that the value is in place, the software delays the initialization time for example 2 seconds, reads the data of the optical module, and then reads the in-place register status of the next optical module, and waits for the initialization time of 2 seconds until all polling is completed. In this way, n ports of the network device are simultaneously plugged with optical modules. In this way, the software task completes the data reading of n plugged in optical modules, and the software needs to delay n*2 seconds, resulting in an increase in the delay time. Summary of the invention

[0005] The purpose of the present application is to provide a method and device for implementing a hardware delay for an inserted optical module, and after an optical module is inserted into an optical module port and the hardware delay is reached, the in-place status of the optical module is recorded.

[0006] To achieve the above-mentioned purpose, the present application provides a method for implementing hardware delay for an inserted optical module, the method also includes: providing an in-place register located in a logic control device for each of the multiple optical module ports; defining an optical module insertion pin located in the logic control device for each of the multiple optical module ports; a logic control module located in the logic control device detects the initial input level change of each connected optical module insertion pin, and calculates the hardware delay time based on a divided clock signal provided by a divided clock signal circuit located in the logic control device; after the initial input level change of each optical module insertion pin reaches the hardware delay time, the logic control module modifies the in-place register corresponding to each optical module insertion pin to output a hardware interrupt signal to the processor in-place.

[0007] In this method, the initial input level of each optical module plug-in pin is a high level.

[0008] In the method, the high level of the initial input of the optical module insertion pin of each optical module port is pulled down to a low level by the ground of the optical module inserted into each optical module port; the logic control module located in the logic control device detects that the initial input level of each connected optical module insertion pin changes from a high level to a low level.

[0009] In the method, the initial not-in-place state of the in-place register of each optical module port is represented by a logic value of 1; the in-place state of the in-place register of each optical module port is represented by a logic value of 0.

[0010] In the method, a corresponding power supply unit switch-on signal pin is defined for an optical module insertion pin of each optical module port; a low level is input to the optical module insertion pin of each optical module port, so that the corresponding power supply unit switch-on signal pin outputs a high level; a high level is output from each power supply unit switch-on signal pin, so that the switch of the power supply unit connected to each optical module port is turned on; and power is supplied to the optical module inserted into each optical module port.

[0011] To achieve the above-mentioned purpose, the present application also provides a device for implementing hardware delay of an inserted optical module, the device has a crystal oscillator, and the device also includes a logic control device, multiple optical module ports and a power supply unit corresponding to each optical module port; the logic control device defines an optical module insertion pin located in the logic control device for each of the multiple optical module ports; the logic control device is provided with multiple in-place registers and each in-place register records an initial out-of-place state; the initial input level of the optical module insertion pin of each corresponding optical module insertion port corresponds; the logic control module of the logic control device detects the change in the initial input level of each connected optical module insertion pin, and calculates the hardware delay time based on the divided clock signal provided by the divided clock signal circuit located in the logic control device; the logic control module modifies the in-place state of the in-place register corresponding to each optical module insertion pin after the initial input level change of each optical module insertion pin reaches the hardware delay time.

[0012] In this device, the initial input level of each optical module plug-in pin is high.

[0013] In the device, the high level of the initial input of the optical module insertion pin of each optical module port is pulled down to a low level by the ground of the optical module inserted into each optical module port; the logic control module located in the logic control device detects that the initial input level of each connected optical module insertion pin changes from a high level to a low level.

[0014] In the device, the initial not-in-place state of the in-place register of each optical module port is represented by a logic value of 1; the in-place state of the in-place register of each optical module port is represented by a logic value of 0.

[0015] In the device, the logic control device defines a corresponding power supply unit switch conduction signal pin for each optical module insertion pin; the low level input to the optical module insertion pin of each optical module port causes the corresponding power supply unit switch conduction signal pin to output a high level; the high level output by each power supply unit switch conduction signal pin of the logic control device turns on the switch connected to each power supply unit, so that the power supply supplies power to the optical module inserted into the corresponding optical module port. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flowchart of an embodiment of a method for implementing a hardware delay of inserting an optical module is provided for the present application;

[0017] Figure 2 A schematic diagram of a device for implementing a hardware delay for inserting an optical module provided in the present application. DETAILED DESCRIPTION

[0018] The present invention will be described in detail with multiple examples shown in multiple figures. In the following detailed description, multiple specific details are used to provide a comprehensive understanding of the present application. Known methods, steps, components and circuits are not described in detail in the examples to avoid making these examples difficult to understand.

[0019] Among the terms used, the term "include" means including but not limited to; the term "contain" means including but not limited to; the terms "above", "within" and "below" are inclusive of the number; the terms "greater than" and "less than" are exclusive of the number. The term "based on" means based on at least a part thereof.

[0020] Figure 1 The flowchart of an embodiment of a method for implementing a hardware delay of an inserted optical module provided by the present application is shown, and the method includes:

[0021] Step 101, providing an in-place register located in a logic control device for each of the multiple optical module ports;

[0022] Step 102, defining an optical module insertion pin located at a logic control device for each of the plurality of optical module ports;

[0023] Step 103, the logic control module located in the logic control device detects the change of the initial input level of each optical module plug-in pin connected, and calculates the hardware delay time based on the divided clock signal provided by the divided clock signal circuit located in the logic control device;

[0024] Step 104 , after the initial input level of each optical module plug-in pin changes to a hardware delay time, the logic control module modifies the in-position register corresponding to each optical module plug-in pin to output a hardware interrupt signal to the processor.

[0025] Figure 2 A schematic diagram of a device for implementing a hardware delay of inserting an optical module provided in the present application. The device has a logic control device CPLD (Complex Programmable Logic Device) 21, a processor 22, and a machine-readable storage medium 23; the machine-readable storage medium 23 is used to store machine-readable instructions. The device also has multiple optical module ports (not shown) for providing reference clock signals and a power supply unit E1 corresponding to each optical module port.

[0026] The frequency-divided clock signal circuit of CPLD21 divides the clock signal outputted by YI of the device into a frequency-divided clock signal of 2 Hz, and outputs it to the logic control module 211 of CPLD21 for calculating the hardware delay time.

[0027] A pair of GPIO pins 1 and GPIO pins 11 are defined on the CPLD 21 for the optical module port 20A. The CPLD 21 provides an in-position register 211 for the optical module port 20A.

[0028] Figure 2 Taking the insertion of optical module port 20A into optical module 20 as an example, the implementation method of realizing the hardware delay of inserting the optical module is explained. Other optical module ports, the inserted optical module, a pair of GPIO pins corresponding to other optical module ports, and in-place registers are not shown in the figure.

[0029] GPIO pin 1 is an optical module insertion pin of optical module port 20A; GPIO pin 1 is connected to a DC power supply via resistor R1. The initial input level of GPIO pin 1 is a high level. GPIO pin 1 is connected to the in-position register 211 of optical module port 20A, and the initial out-of-position state in the in-position register 211 is written as a logic value 1.

[0030] After the optical module 20 is inserted into the optical module port 20A, the ground (GND) pin of the optical module 20 is connected to the GPIO pin 1, the switch S1 is turned on, and the initial input level of the GPIO pin 1 changes from a high level to a low level.

[0031] The GPIO pin 1 is connected to the logic control module 212 of the CPLD 21 , and the input level of the GPIO pin 1 changes from a high level to a low level.

[0032] The value 1 in the in-position register 211 indicating the out-of-position state is modified to the value 0 indicating the in-position state; the GPIO pin 11 outputs a high level.

[0033] The logic control module 212 of the CPLD 21 reads that the level of the GPIO pin 11 input changes to a high level, and calculates the hardware delay time, for example, 2 seconds, based on the 2HZ divided clock signal provided by the divided clock signal circuit of the CPLD 21 .

[0034] After the hardware delay time is reached, the logic control module 212 of the CPLD 21 rewrites the logic value 1 of the in-position register 211 of the optical module port 20A to a logic value 0, that is, changes the initial out-of-position state to the in-position state.

[0035] In the power supply E1, the high level output by the GPIO pin 11 turns on the switch S2, and the output end (output) of the common power supply E1 is connected to the input end (input), supplying power to the power supply VCC201 of the optical module 21. The optical module 20 starts to initialize. In the power supply E1, a switch circuit is built by an NMOS tube and a PMOS tube; the input end of the power supply E1 is the power supply, and the output end is connected to the power supply end VCC201 of the optical module 20. Therefore, when the high level output by the GPIO pin 11, the NMOS is turned on, the output end of the power supply E1 is connected to the input end, and the optical module 20 is powered; before the optical module 20 is inserted, the low level output by the GPIO pin 11, the NMOS tube is turned off, the output end is disconnected from the input end, and no power is supplied to the outside.

[0036] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for implementing hardware delay of an inserted optical module, characterized in that: The method further comprises, Provide a position register located in the logic control device for each of the multiple optical module ports; Defining an optical module insertion pin located at the logic control device for each of the plurality of optical module ports; The logic control module located in the logic control device detects the change of the initial input level of each optical module plug-in pin connected, and calculates the hardware delay time based on the divided clock signal provided by the divided clock signal circuit located in the logic control device; After the initial input level change of each optical module plug-in pin reaches the hardware delay time, the logic control module modifies the in-place register corresponding to each optical module plug-in pin to output a hardware interrupt signal to the processor in-place.

2. The method according to claim 1, characterized in that The method further comprises, The initial input level of each optical module plug-in pin is a high level.

3. The method according to claim 2, characterized in that The method further comprises, The high level of the initial input of the optical module insertion pin of each optical module port is pulled down to a low level by the ground of the optical module inserted into each optical module port; The logic control module located in the logic control device detects that the initial input level of each optical module plug-in pin connected changes from a high level to a low level.

4. The method according to claim 1, characterized in that The initial not-in-place state of the in-place register of each optical module port is represented by a logic value of 1; the in-place state of the in-place register of each optical module port is represented by a logic value of 0.

5. The method according to claim 3, characterized in that: The method further comprises, Define a corresponding power supply unit switch on signal pin for the optical module insertion pin of each optical module port; The optical module insertion pin of each optical module port inputs a low level, so that the corresponding power supply unit switch conduction signal pin outputs a high level; The high level output by the switch-on signal pin of each power supply unit turns on the switch of the power supply unit connected to each optical module port, thereby supplying power to the optical module inserted into each optical module port.

6. A device implemented as a hardware delay of an inserted optical module, the device having a crystal oscillator, characterized in that: The device also includes a logic control device, a plurality of optical module ports, and a power supply unit corresponding to each of the optical module ports; The logic control device defines an optical module insertion pin located on the logic control device for each of the plurality of optical module ports; The logic control device is provided with a plurality of in-place registers and each of the in-place registers records an out-of-place initial state; the initial input level of the optical module insertion pin of each corresponding optical module insertion port corresponds; The logic control module of the logic control device detects the change of the initial input level of each optical module plug-in pin connected, and calculates the hardware delay time based on the divided clock signal provided by the divided clock signal circuit located in the logic control device; The logic control module modifies the in-place state of the in-place register corresponding to each optical module plug-in pin after the initial input level change of each optical module plug-in pin reaches the hardware delay time.

7. The device according to claim 6, characterized in that The initial input level of each optical module plug-in pin is a high level.

8. The device according to claim 6, characterized in that The high level of the initial input of the optical module insertion pin of each optical module port is pulled down to a low level by the ground of the optical module inserted into each optical module port; The logic control module located in the logic control device detects that the initial input level of each optical module plug-in pin connected changes from a high level to a low level.

9. The device according to claim 6, characterized in that The initial not-in-place state of the in-place register of each optical module port is represented by a logic value of 1; the in-place state of the in-place register of each optical module port is represented by a logic value of 0.

10. The device according to claim 8, characterized in that The logic control device defines a corresponding power supply unit switch conduction signal pin for each optical module insertion pin; The optical module insertion pin of each optical module port inputs a low level, so that the corresponding power supply unit switch conduction signal pin outputs a high level; The high level output by the switch conduction signal pin of each power supply unit of the logic control device turns on the switch connected to each power supply unit, so that the power supply supplies power to the optical module inserted into the corresponding optical module port.

Images