Storage unit and memory manufacturing method

Abstract

The present disclosure relates to a preparation method of a memory cell and a memory, and relates to the field of integrated circuit design and manufacturing technology. The memory cell includes an active column, a capacitor, a first gate, and a second gate. The active column has a first end face and a second end face that are mutually opposite in a first direction, and the first end face is used to connect to a bit line; the active column includes a first doping region, a channel region, and a second doping region arranged in sequence along the first direction, the channel region has a first outer surface and a second outer surface that are mutually opposite in a second direction, and the channel region includes a stress structure that penetrates the active column along a third direction; the first direction intersects with the second direction and is both perpendicular to the third direction; the capacitor covers the second end face and circumferentially surrounds part of the side surface of the active column; the first gate is located on the first outer surface of the channel region; the second gate is located on the second outer surface of the channel region, and the memory cell can at least improve performance and reliability while reducing the volume of the memory cell.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a method for preparing a storage unit and a memory. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the market has put forward higher requirements on the storage capacity and storage performance of semiconductor storage products.

[0003] How to improve the performance and reliability of storage units while reducing the size of storage units is one of the research and development goals that relevant researchers are constantly pursuing. Summary of the Invention

[0004] Based on this, the present disclosure provides a method for preparing a memory cell and a memory, which can at least improve the performance and reliability of the memory cell while reducing the volume of the memory cell.

[0005] According to various embodiments of the present disclosure, on the one hand, a storage cell is provided, including an active pillar, a capacitor, a first gate and a second gate, the active pillar having a first end face and a second end face that are opposite to each other along a first direction, the first end face being used to connect to a bit line; the active pillar including a first doped region, a channel region and a second doped region arranged in sequence along the first direction, the channel region having a first outer surface and a second outer surface that are opposite to each other along a second direction, the channel region including a stress structure that penetrates the active pillar along a third direction; the first direction intersects with the second direction and is both perpendicular to the third direction; the capacitor covers the second end face and circumferentially surrounds a portion of the side surface of the active pillar; the first gate is located on the first outer surface of the channel region; the second gate is located on the second outer surface of the channel region.

[0006] In the memory cell of the above-described embodiment, since the first gate and the second gate are respectively formed on two outer surfaces of the channel region on the active pillar that are mutually opposed along the second direction, and the first gate and the second gate share a common channel region, the volume of the memory cell can be reduced while reducing the power consumption of the device. The threshold voltage of the other gate can be modulated by applying a bias voltage to one gate, effectively improving the performance and reliability of the memory cell. One of the first and second gates can serve as a control gate. The stress exerted by the control gate on the channel region can increase the effective carrier mass and reduce gate-induced drain leakage current. The stress exerted on the active pillar by the stress structure buried in the channel region and located between the first and second gates can buffer the stress exerted by the first and second gates on the active pillar, thereby preventing damage to the first and second gates due to excessive stress on the active pillar, thereby effectively improving the reliability of the memory cell.

[0007] According to some embodiments, the memory cell further includes a buried gate structure located within the channel region; the buried gate structure is located between the first end surface and the stress structure, the buried gate structure includes a gate conductive layer and a gate dielectric layer, the gate conductive layer of the buried gate structure is located between the first end surface of the active pillar and the stress structure; the gate dielectric layer of the buried gate structure is located between the gate conductive layer of the buried gate structure and the active pillar, circumferentially surrounds the gate conductive layer of the buried gate structure and has an opening, and the gate conductive layer of the buried gate structure is connected to the stress structure via the opening. The ring gate structure can further increase the contact area between the gate conductive layer and the channel region in the buried gate structure, thereby further improving the performance of the memory cell.

[0008] According to some embodiments, the stress structure is an insulating block; or the stress structure includes an insulating block and an annular stress layer circumferentially surrounding the insulating block, wherein the annular stress layer is located between the insulating block and the active pillar.

[0009] According to some embodiments, the insulating block includes a first sub-insulating block made of different materials and a second sub-insulating block located between the first sub-insulating block and the capacitor, so as to jointly adjust the stress of the stress structure through the first sub-insulating block and the second sub-insulating block to avoid damage to the stress structure due to excessive stress, and to avoid the stress of the stress structure being too small to offset the stress of the first gate and the second gate on the active column.

[0010] According to some embodiments, the active column also includes a first internal support structure and a second internal support structure, the first internal support structure penetrates the active column along a third direction and is located on the side of the first doped region away from the channel region along the first direction; and / or the second internal support structure penetrates the active column along the third direction and is located between the second doped region and the capacitor.

[0011] According to some embodiments, the first inner support structure includes a first support layer and a first support ring, the first support layer penetrates the active column along the third direction and is located between the first end face and the channel region; the first support ring circumferentially surrounds the first support layer and is located between the first support layer and the active column; and / or, the second inner support structure includes a second support layer and a second support ring, the second support layer penetrates the active column along the third direction and is located between the second end face and the channel region; the second support ring circumferentially surrounds the second support layer and is located between the second support layer and the active column.

[0012] According to some embodiments, the first gate includes a gate dielectric layer and a gate conductive layer, the gate dielectric layer of the first gate is located on the first outer surface of the channel region; the gate conductive layer of the first gate is located on the surface of the gate dielectric layer of the first gate away from the channel region along the second direction; the second gate includes a gate dielectric layer and a gate conductive layer, the gate dielectric layer of the second gate is located on the second outer surface of the channel region; the gate conductive layer of the second gate is located on the surface of the gate dielectric layer of the second gate away from the channel region along the second direction.

[0013] According to some embodiments, the present disclosure provides a memory on another aspect, including a word line isolation structure located on a substrate, a first outer support structure and a second outer support structure spaced along a first direction and extending along a second direction, and a plurality of memory cells in any one embodiment of the present disclosure stacked along a third direction; the active pillar passes through the first outer support structure and the second outer support structure along the first direction; the first inner support structure is located inside the first outer support structure, and the second inner support structure is located inside the second outer support structure; the word line isolation structure is located between the first outer support structure and the second outer support structure, and is at least located between the word lines of the memory cells adjacent along the second direction; the memory cells adjacent along the second direction share a bit line extending along the second direction; and the memory cells adjacent along the third direction share a word line extending along the third direction.

[0014] According to some embodiments, the bottom electrodes of different active pillar capacitors are insulated from each other via the second inner support structure; and the different active pillar capacitors share a top electrode and a dielectric layer between the top electrode and the corresponding bottom electrode.

[0015] According to some embodiments, the present disclosure further provides a method for preparing a memory, comprising:

[0016] A substrate is provided, on which a wordline isolation structure, a first outer support structure and a second outer support structure spaced apart along a first direction and extending along a second direction, and a stacked structure are formed. The stacked structure includes dielectric layers and semiconductor layers alternately stacked in sequence along a third direction, with one dielectric layer adjacent to the substrate. The semiconductor layer includes a plurality of active pillars extending along the first direction, penetrating the first and second outer support structures, and spaced apart along the second direction. The wordline isolation structure is located between the first and second outer support structures and defines a dual-gate trench together with the active pillars adjacent to the second direction. The dual-gate trench exposes portions of the first and second outer surfaces of the active pillars, which are mutually opposed in the second direction, and portions of the substrate. The active pillars include a target trench extending along the third direction to the substrate and located between the dual-gate trenches.

[0017] A first gate and a second gate are formed on the first outer surface of the active pillar and the second outer surface of the active pillar in the double-gate trench respectively;

[0018] A stress structure is formed at least in the target trench.

[0019] According to some embodiments, the process of forming the first gate and the second gate further includes:

[0020] A buried gate structure is formed in the target trench and is located between the first outer support structure and the stress structure.

[0021] According to some embodiments, before forming the word line isolation structure, the method further includes:

[0022] forming a first hole penetrating the active pillar and the first outer support structure along a third direction, and a second hole penetrating the active pillar and the second outer support structure along the third direction;

[0023] Performing a target doping process on the active pillar through the first hole and the second hole to obtain a first doping region, a channel region, and a second doping region sequentially arranged along a first direction; a target trench penetrates the channel region along a third direction;

[0024] A first inner support structure is formed in the first hole, and a second inner support structure is formed in the second hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 A schematic flow chart of a method for preparing a memory provided in one embodiment of the present disclosure;

[0027] Figure 2 is a schematic diagram of a three-dimensional structure obtained after an initial stacked structure is formed on a substrate in one embodiment of the present disclosure;

[0028] Figure 3 is a schematic diagram of a three-dimensional structure obtained after forming a first semiconductor pillar and a second semiconductor pillar on a substrate in one embodiment of the present disclosure;

[0029] Figure 4 Schematic diagram of a three-dimensional structure obtained after forming a first trench and a second trench on a substrate in one embodiment of the present disclosure;

[0030] Figure 5 For Figure 4 A schematic diagram of the three-dimensional structure obtained after forming the first outer supporting structure and the second outer supporting structure in the three-dimensional structure;

[0031] Figure 6 for Figure 5 A schematic diagram of the three-dimensional structure obtained after removing the sacrificial material from the three-dimensional structure shown;

[0032] Figure 7 For Figure 6 A schematic diagram of a three-dimensional structure obtained after a dielectric material layer is formed in the gap of the three-dimensional structure;

[0033] Figure 8 For Figure 7 A schematic diagram of the three-dimensional structure obtained after forming the first hole and the second hole in the three-dimensional structure;

[0034] Figure 9a For Figure 8 A schematic top view of a memory cell in the three-dimensional structure obtained after the first ion implantation region and the second ion implantation region are formed in the three-dimensional structure;

[0035] Figure 9b For Figure 8 A schematic diagram of a top view of a memory cell in the three-dimensional structure obtained after forming the first doping region and the second doping region in the three-dimensional structure;

[0036] Figure 10 For Figure 8 A schematic diagram of the three-dimensional structure obtained after forming the first inner supporting structure and the second inner supporting structure in the three-dimensional structure;

[0037] Figure 11 For Figure 10 A schematic diagram of the three-dimensional structure obtained after forming a dummy word line structure and an isolation trench in the three-dimensional structure;

[0038] Figure 12 For Figure 11 A schematic diagram of a three-dimensional structure obtained after forming a word line isolation structure in the three-dimensional structure shown;

[0039] Figure 13 For Figure 12 A schematic diagram of the three-dimensional structure obtained after forming double gate trenches and burying the gate trenches in the three-dimensional structure;

[0040] Figure 14 For Figure 13 A schematic diagram of the three-dimensional structure obtained after forming the first gate, the second gate and the buried gate structure in the three-dimensional structure;

[0041] Figure 15 For Figure 14 A schematic diagram of the three-dimensional structure obtained after forming a target groove in the three-dimensional structure shown;

[0042] Figure 16 For Figure 15 A schematic diagram of the three-dimensional structure obtained after a stress structure is formed in the three-dimensional structure shown;

[0043] Figure 17 For Figure 16 A schematic diagram of a three-dimensional structure obtained after forming a bit line in the three-dimensional structure;

[0044] Figure 18 For Figure 17 A schematic diagram of the three-dimensional structure obtained after the capacitor region is exposed in the three-dimensional structure shown;

[0045] Figure 19 For Figure 18A schematic diagram of the three-dimensional structure obtained after forming a lower electrode in the three-dimensional structure shown;

[0046] Figure 20 For Figure 18 A schematic diagram of the three-dimensional structure obtained after forming a capacitor in the three-dimensional structure shown;

[0047] Figure 21 A schematic top view of a storage unit provided in the first embodiment of the present disclosure;

[0048] Figure 22 A schematic top view of a storage unit provided in a second embodiment of the present disclosure;

[0049] Figure 23 A schematic top view of a storage unit provided in a third embodiment of the present disclosure;

[0050] Figure 24 A schematic top view of a storage unit provided in a fourth embodiment of the present disclosure;

[0051] Figure 25 It is a schematic top view of a storage unit provided in the fifth embodiment of the present disclosure.

[0052] Description of reference numerals:

[0053] 10. Substrate; 20. Wordline isolation structure; 211. Pseudo-wordline structure; 212. Isolation trench; 30. First outer support structure; 31. First trench; 40. Second outer support structure; 41. Second trench; 50', initial stack structure; 50. Stack structure; 501. Sacrificial material layer; 502. Semiconductor material layer; 100. Cap layer; 511. First sacrificial pillar; 512. Second sacrificial pillar; 521. First semiconductor pillar; 522. Second semiconductor pillar; 521', active pillar; 531. Dielectric material layer; 53. Dielectric layer; 21. Double-gate trench; 22. First gate; 22', second gate; 221 / 221' / 71. Gate dielectric layer; 222 / 222' / 72. Gate conductive layer; 61 ', target groove; 60', target groove; 60, stress structure; 61, insulating block; 611, first sub-insulating block; 612, second sub-insulating block; 62, annular stress layer; 70, buried gate structure; 11, first hole; 12, second hole; 131, first ion implantation region; 141, second ion implantation region; 13, first doping region; 14, second doping region; 15, channel region; 16, capacitor region; 111, first inner support structure; 1111, first support layer; 1112, first support ring; 121, second inner support structure; 1211, second support layer; 1212, second support ring; 171, third inner support structure; 80, capacitor; 81, lower electrode; 83, upper electrode; 90, bit line. DETAILED DESCRIPTION

[0054] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0056] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0057] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0058] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present disclosure. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complex.

[0060] Please note that the mutual insulation between the two described in the embodiments of the present disclosure includes but is not limited to at least one of the presence of an insulating material layer, an insulating atmosphere or a gap between the two; the A and B described in the embodiments of the present disclosure forming "conformal coverage" or "conformal superposition" on the substrate are intended to express the following meanings: the orthographic projection of A on the top surface of the substrate completely overlaps with the orthographic projection of B on the top surface of the substrate.

[0061] Please refer to Figure 1 In some embodiments of the present disclosure, a preparation method is provided, comprising the following steps:

[0062] Step S20: providing a substrate, and forming a word line isolation structure, a first outer support structure and a second outer support structure spaced apart along a first direction and extending along a second direction, and a stacked structure on the substrate, wherein the stacked structure includes dielectric layers and semiconductor layers alternately stacked in sequence along a third direction, with one dielectric layer adjacent to the substrate; the semiconductor layer includes a plurality of active pillars extending along the first direction, penetrating the first outer support structure and the second outer support structure, and spaced apart along the second direction; the word line isolation structure is located between the first outer support structure and the second outer support structure, and defines a dual-gate trench together with the active pillars adjacent to the second direction, the dual-gate trench exposing portions of the first outer surface and the second outer surface of the active pillars that are mutually opposed along the second direction, and portions of the substrate; the active pillars include a target trench extending along the third direction to the substrate and located between the dual-gate trenches;

[0063] Step S40: forming a first gate and a second gate on a first outer surface of the active pillar and a second outer surface of the active pillar in the dual-gate trench, respectively;

[0064] Step S60: forming a stress structure at least in the target trench.

[0065] Specifically, please refer to Figure 1 Because the first gate and the second gate are respectively formed on two outer surfaces of the channel region on the active pillar that are separated from each other along the second direction, the first gate and the second gate share a channel region, which can reduce the volume of the memory cell while reducing the power consumption of the device. The threshold voltage of the other gate can be modulated by applying a bias voltage to one gate, which can effectively improve the performance and reliability of the memory cell. One of the first and second gates can serve as a control gate. The stress exerted by the control gate on the channel region can increase the effective carrier mass and reduce gate-induced drain leakage current. The stress exerted on the active pillar by the stress structure buried in the channel region and located between the first and second gates can buffer the stress exerted by the first and second gates on the active pillar, preventing damage to the first and second gates due to excessive stress on the active pillar, thereby effectively improving the reliability of the memory cell.

[0066] For example, as shown in the following figure, the ox direction is parallel to the first direction, the oy direction is parallel to the second direction, and the oz direction is parallel to the third direction. The second direction can be set to be parallel to the bit line extension direction, and the third direction is perpendicular to the top surface of the substrate, for example, parallel to the word line extension direction. The first direction is parallel to the top surface of the substrate and intersects with the second direction.

[0067] As an example, please refer to Figure 1-Figure 2The substrate 10 provided in step S20 can be made of semiconductor material, insulating material, conductive material or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 10 should not limit the scope of protection of the present disclosure.

[0068] As an example, please refer to Figure 1-Figure 2 In step S20, an initial stacked structure 50' and a cap layer 100 are formed on the substrate 10. The initial stacked structure 50' is located between the substrate 10 and the cap layer 100. The initial stacked structure 50' includes sacrificial material layers 501 and semiconductor material layers 502 alternately stacked in sequence along a third direction. The sacrificial material layers 501 are adjacent to the substrate 10. The sacrificial material layers 501 may include semiconductor materials, such as silicon germanium. The material of the semiconductor material layer 502 may include, but is not limited to, silicon. The sacrificial material layer 501 of silicon germanium can completely transfer the silicon lattice of the substrate 10 to the channel region of the stacked silicon material, ensuring that the channel region of each layer of silicon material can have the same silicon lattice as the substrate 10.

[0069] As an example, see Figure 3 The initial stacked structure 50' can be etched using a dry etching process and / or a wet etching process to obtain conformally covered first sacrificial pillars 511 and first semiconductor pillars 521, as well as conformally covered second sacrificial pillars 512 and second semiconductor pillars 522. The orthographic projection of the first sacrificial pillar 511 on the top surface of the substrate 10 completely overlaps with the orthographic projection of the first semiconductor pillar 521 on the top surface of the substrate 10, and the orthographic projection of the second sacrificial pillar 512 on the top surface of the substrate 10 completely overlaps with the orthographic projection of the second semiconductor pillar 522 on the top surface of the substrate 10. The first semiconductor pillar 521 extends in a first direction, and the second semiconductor pillar 522 extends in a second direction. The second semiconductor pillar 522 in the same layer can be connected to multiple first semiconductor pillars 521. The dry etching process can include, but is not limited to, at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), and high-density plasma etching (HDP).

[0070] As an example, see Figure 4-Figure 5 , you can Figure 3A sacrificial material (not shown) is deposited within the three-dimensional structure shown in FIG to fill the gap within the three-dimensional structure. The top surface of the sacrificial material is then planarized, and the sacrificial material is etched until its top surface is flush with the top surface of the remaining cap layer 100, thereby forming a first trench 31 and a second trench 41. Both the first trench 31 and the second trench 41 extend along the third direction to the substrate 10. A supporting material is then filled within each of the first trench 31 and the second trench 41, and the top surface of the supporting material is planarized until its top surface is flush with the top surface of the remaining cap layer 100, thereby forming a first outer support structure 30 filling the first trench 31 and a second outer support structure 40 filling the second trench 41. The first and second outer support structures 30 and 40 are spaced apart along the first direction and extend along the second direction. The materials of the first and second outer support structures 30 and 40 may include, but are not limited to, at least one of silicon nitride, silicon oxynitride, and silicon carbide nitride. The materials of the sacrificial material may include, but are not limited to, silicon oxide. The deposition process may include but is not limited to at least one of a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition (HDP), a plasma enhanced deposition process, and a spin-on dielectric layer (SOD).

[0071] As an example, see Figure 6-Figure 7 , can be removed by dry etching process and / or wet etching process Figure 5 The sacrificial material in the three-dimensional structure shown in Figure 6 The three-dimensional structure shown, then Figure 6 A dielectric material layer 531 is filled in the gaps of the three-dimensional structure, resulting in a dielectric layer 53 located between adjacent second semiconductor pillars 522 along the third direction or between the second semiconductor pillars 522 and the substrate 10. The dielectric layer 53 is also located between adjacent first semiconductor pillars 521 along the third direction or between the first semiconductor pillars 521 and the substrate 10. The material of the dielectric layer 53 may include, but is not limited to, silicon oxide.

[0072] As an example, see Figure 8 ,At Figure 7 A first hole 11 and a second hole 12 are formed in the three-dimensional structure shown in the figure. The first hole 11 is located in the overlapping area of ​​the first outer support structure 30 and a first semiconductor column 521, and the second hole 12 is located in the overlapping area of ​​the second outer support structure 40 and a first semiconductor column 521. The first hole 11 and the second hole 12 both extend to the substrate 10 along the third direction.

[0073] As an example, see Figure 9a-9b ,exist Figure 8 In the three-dimensional structure shown, ion implantation is performed on the first semiconductor pillars 521 of different layers through the first hole 11 and the second hole 12 to obtain a first ion implantation region 131 circumferentially surrounding the first hole 11 and a second ion implantation region 141 circumferentially surrounding the second hole 12, as shown in FIG. Figure 9a As shown. Further, the first ion implantation region 131 and the second ion implantation region 141 are heat-treated so that the first ion implantation region 131 is thermally diffused to the circumferential surrounding region to obtain the first doping region 13, and the second ion implantation region 141 is thermally diffused to the circumferential surrounding region to obtain the second doping region 14. The portion of the first semiconductor column 521 located between the first doping region 13 and the second doping region 14 is used to form the channel region 15, and an active column 521' including the first doping region 13, the channel region 15 and the second doping region 14 is obtained. The portion of the active column 521' located in the second doping region 14 away from the channel region 15 along the first direction can be used as a capacitor region 16 to form a capacitor in the capacitor region 16. The doping type of the channel region 15 and the active column 521' can be the same, for example, both are P-type doping, and the doping concentration of the channel region 15 can be set to 1E 17 cm -3 -1E 18 cm -3 .

[0074] As an example, see Figure 10 After forming the first doped region 13, the channel region 15, and the second doped region 14, a first inner support structure 111 is formed in the first hole 11, and a second inner support structure 121 is formed in the second hole 12. The first inner support structure 111 and the second inner support structure 121 are used to support the multi-layer active pillars 521' to prevent the active pillars 521' from tilting, warping, and collapse, thereby improving the yield and reliability of the manufactured semiconductor device.

[0075] As an example, see Figure 11 After forming the first inner support structure 111 and the second inner support structure 121, the dielectric material layer 531 located between the first outer support structure 30 and the second outer support structure 40 can be etched to form an isolation trench 212. The dielectric material layer 531 retained on the two outer sidewalls of the active pillar 521' opposite to each other along the second direction is used to form a pseudo word line structure 211.

[0076] As an example, see Figure 12 A deposition process may be used to form a word line isolation structure 20 in the isolation trench 212 . The material of the word line isolation structure 20 may include but is not limited to silicon oxide.

[0077] As an example, see Figure 13The dummy word line structure 211 is removed to form a dual-gate trench 21, which exposes two opposing outer sidewalls of the active pillar 521' along the second direction. The dual-gate trench 21 extends along the third direction to the substrate 10 to form a word line perpendicular to the top surface of the substrate 10. The active pillar 521' and the second semiconductor pillar 522 on the same layer together form a semiconductor layer. The alternating semiconductor layers and dielectric layers 53 form a stacked structure 50.

[0078] As an example, please refer to Figure 13 In the process of removing the dummy word line structure 211 to obtain the dual-gate trench 21, part of the active pillar 521' in the channel region can be removed to obtain a target trench 61' located between the two trenches of the dual-gate trench 21, and the target trench 61' extends to the substrate 10 along the third direction.

[0079] As an example, see Figure 14 A gate dielectric material layer can be formed on the first outer surface 521'a and the second outer surface 521'b of the active pillar 521' in the dual-gate trench 21, and the inner wall and bottom surface of the target trench 61' by using a rapid thermal oxidation process (RTO). Then, a gate conductive material layer is formed in the dual-gate trench 21 and the target trench 61' by using a deposition process. The gate dielectric material layer on the first outer surface 521'a of the active pillar 521' in the dual-gate trench 21 is used to form the gate dielectric layer 221 of the first gate 22, and the gate dielectric material layer on the second outer surface 521'b of the active pillar 521' in the dual-gate trench 21 is used to form the gate dielectric layer 221 of the first gate 22. The gate dielectric material layer is used to form the gate dielectric layer 221' of the second gate 22', the gate conductive material layer located on the first outer surface 521'a of the active pillar 521' is used to form the gate conductive layer 222 of the first gate 22, the gate conductive material layer located on the second outer surface 521'b of the active pillar 521' is used to form the gate conductive layer 222' of the second gate 22', the gate dielectric material layer located within the target trench 61' is used to form the gate dielectric layer 71 of the buried gate structure 70; and the gate conductive material layer located within the target trench 61' is used to form the gate conductive layer 72 of the buried gate structure 70. The gate dielectric material layer can be made of a material selected from silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride, aluminum oxide (Al2O3), aluminum oxynitride (AlON), and combinations thereof. The gate dielectric material layer may also be a high-k dielectric material (a dielectric material having a dielectric constant greater than or equal to 3.9), a low-k dielectric material (a dielectric constant greater than or equal to 2.5 and less than 3.9), an ultra-low-k dielectric material (a dielectric constant less than 2.5), a ferroelectric material, an anti-ferroelectric material, silicon carbide (SiC), or any combination thereof. The gate conductive material layer may be made of a material selected from the group consisting of indium tin oxide, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride, and combinations thereof.

[0080] As an example, see Figure 15-16 A portion of the active pillar 521' in the channel region and a portion of the gate dielectric layer 71 of the buried gate structure 70 are removed, forming an opening (not shown) in the gate dielectric layer 71, thereby obtaining a target recess 60' between the buried gate structure 70 and the second outer support structure 40. A stress structure 60 is formed within the target recess 60', and the gate conductive layer 72 of the buried gate structure 70 is contact-connected to the stress structure 60 via the opening in the gate dielectric layer 71. The stress exerted on the active pillar 521' by the buried gate structure 70 and the stress structure 60 can buffer the stress exerted on the active pillar 521' by the first gate 22 and the second gate 22', thereby preventing damage to the first gate 22 and the second gate 22' due to excessive stress on the active pillar 521', thereby effectively improving the reliability of the memory cell.

[0081] As an example, see Figure 17 The second semiconductor pillar 522 is removed to form a bit line groove (not shown). A bit line 90 is formed in the bit line groove. Bit line 90 extends along the second direction. The material of bit line 90 is selected from copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride, and combinations thereof.

[0082] As an example, see Figure 18 The dielectric material layer 531 on the capacitor region 16 of the active pillar 521 ′ is removed to expose the capacitor region 16 of the active pillar 521 ′, so as to form a capacitor on the exposed capacitor region 16 of the active pillar 521 ′.

[0083] As an example, see Figure 19 A deposition process can be used to form a lower electrode 81 on the outer surface of the capacitor region 16 of the exposed active pillar 521'. The lower electrode 81 covers the end surface 521'c of the active pillar 521' that faces away from the second inner support structure 121 along the first direction and circumferentially surrounds a portion of the side surface of the active pillar 521'. The lower electrodes 81 on different active pillars 521' are insulated from each other by the second inner support structure 121. A dielectric layer (not shown) is then formed. The dielectric layer can cover the outer surface of the lower electrode 81, a portion of the outer surface of the second inner support structure 121, and a portion of the outer surface of the second outer support structure 40. An upper electrode 83 is then formed, covering the outer surface of the dielectric layer. The lower electrode 81, the dielectric layer, and the upper electrode 83 together constitute a capacitor.

[0084] As an example, see Figure 20 , you can also Figure 18A lower electrode 81 is formed on the capacitor region 16 of the three-dimensional structure shown. The lower electrode 81 covers the outer surfaces of the capacitor region 16 of the multiple active pillars 521', the end surfaces 521'c of the active pillars 521' facing away from the second inner support structure 121 in the first direction, a portion of the outer surface of the second inner support structure 121, and a portion of the outer surface of the second outer support structure 40. A dielectric layer is then formed, covering the outer surface of the lower electrode 81. An upper electrode 83 is then formed, covering the outer surface of the dielectric layer. The second inner support structure 121 is then removed, along with portions of the lower electrode 81 located on the outer surfaces of the second inner support structure 121 and the outer surfaces of the second outer support structure 40, to form a third hole (not shown). This insulates the lower electrodes 81 on different active pillars 521' from each other via the third hole. A second inner support structure 121' is then formed within the third hole, insulating the lower electrodes 81 on different active pillars 521' from each other via the second inner support structure 121'. The lower electrode 81 , the dielectric layer and the upper electrode 83 are used to form a capacitor.

[0085] As an example, see Figure 21 The stress structure 60 is an insulating block located between the first gate 22 and the second gate 22', within the channel region 15, and extending through the active pillar 521' along the third direction. The insulating block may be made of, but is not limited to, silicon nitride. The stress exerted by the insulating block on the active pillar 521' offsets the stress exerted by the first gate 22 and the second gate 22' on the active pillar 521'. The stress may be tensile or compressive.

[0086] As an example, see Figure 22 The insulating block 61 is located between the first gate 22 and the second gate 22', within the channel region 15, and extends through the active pillar 521' along the third direction. The insulating block 61 includes a first sub-insulating block 611 and a second sub-insulating block 612 made of different materials. The second sub-insulating block 612 is located between the first sub-insulating block 611 and the capacitor 80. The first sub-insulating block 611 and the second sub-insulating block 612 are used to jointly regulate the stress of the stress structure 60, thereby preventing damage caused by excessive stress in the stress structure 60 and preventing the stress of the stress structure 60 from being too low to offset the stress of the first gate 22 and the second gate 22' on the active pillar 521'. The material of the first sub-insulating block 611 may include silicon oxide, and the material of the second sub-insulating block 612 may include silicon nitride.

[0087] As an example, see Figure 23 The stress structure 60 includes an insulating block 61 and an annular stress layer 62 circumferentially surrounding the insulating block 61. The annular stress layer 62 is located between the insulating block 61 and the active pillar 521'. The insulating block 61 and the annular stress layer 62 are made of different materials, and the annular stress layer 62 may include silicon nitride. The insulating block 61 and the annular stress layer 62 can be used to adjust the stress level of the stress structure 60.

[0088] As an example, see Figure 24 The stress structure 60 is located in the active pillar 521' between the buried gate structure 70 and the capacitor 80. The gate dielectric layer 71 of the buried gate structure 70 has an opening (not shown), and the gate conductive layer 72 of the buried gate structure 70 is contacted and connected to the stress structure 60 via the opening of the gate dielectric layer 71. The buried gate structure 70 can further increase the contact area between the gate conductive layer 72 and the channel region in the buried gate structure 70, thereby further improving the performance of the memory cell. The stress applied to the active pillar 521' by the stress structure 60 and the buried gate structure 70 can buffer the stress of the first gate 22 and the second gate 22' on the active pillar 521', thereby preventing the first gate 22 and the second gate 22' from being damaged due to excessive stress on the active pillar 521', thereby effectively improving the reliability of the memory cell.

[0089] As an example, see Figure 25 The stress structure 60 includes an insulating block 61 and an annular stress layer 62 circumferentially surrounding the insulating block 61. The annular stress layer 62 is located between the insulating block 61 and the active pillar 521' and within the active pillar 521' between the buried gate structure 70 and the capacitor 80. The insulating block 61 and the annular stress layer 62 are made of different materials, and the annular stress layer 62 may include silicon nitride. The insulating block 61 and the annular stress layer 62 can be used to adjust the stress level of the stress structure 60.

[0090] As an example, please refer to Figure 25 The first inner support structure 111 includes a first support layer 1111 and a first support ring 1112. The first support layer 1111 extends through the active pillar 521' along the third direction and is located between the bit line 90 and the stress structure 60. The first support ring 1112 circumferentially surrounds the first support layer 1111 and is located between the first support layer 1111 and the active pillar 521'. The first support layer 1111 and the first support ring 1112 are made of different materials. For example, the first support layer 1111 is made of silicon oxide, while the first support ring 1112 is made of silicon nitride. The stress exerted by the first inner support structure 111 on the active pillar 521' can be adjusted by varying the dimensions of the first support layer 1111 and the first support ring 1112, thereby preventing damage caused by excessive stress and degradation of memory cell performance due to insufficient stress. The first inner support structure 111 is used to support the multi-layer active pillars 521 ′, thereby preventing the active pillars 521 ′ from tilting, warping, and collapsing, thereby improving the yield and reliability of the manufactured semiconductor device.

[0091] As an example, please refer to Figure 25The second inner support structure 121 includes a second support layer 1211 and a second support ring 1212. The second support layer 1211 extends through the active pillar 521' along the third direction and is located between the capacitor 80 and the stress structure 60. The second support ring 1212 circumferentially surrounds the second support layer 1211 and is located between the second support layer 1211 and the active pillar 521'. The second support layer 1211 and the second support ring 1212 are made of different materials. For example, the second support layer 1211 is made of silicon oxide, while the second support ring 1212 is made of silicon nitride. The stress exerted by the second inner support structure 121 on the active pillar 521' can be adjusted by varying the dimensions of the second support layer 1211 and the second support ring 1212, thereby preventing damage caused by excessive stress and degradation of memory cell performance due to insufficient stress. By supporting the multiple layers of active pillars 521', the second inner support structure 121 prevents tilting, warping, and collapse of the active pillars 521', thereby improving the yield and reliability of the manufactured semiconductor device.

[0092] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0093] As an example, please refer to Figure 21-Figure 25 A memory cell includes an active pillar 521', a capacitor 80, a first gate 22, and a second gate 22'. The active pillar 521' has a first end surface and a second end surface that are opposite to each other along a first direction. The first end surface of the active pillar 521' is used to connect to a bit line 90. The active pillar 521' includes a first doped region 13, a channel region 15, and a second doped region 14 arranged in sequence along the first direction. The channel region 15 has a first outer surface and a second outer surface that are opposite to each other along a second direction. The channel region 15 includes a stress structure 60 that penetrates the active pillar 521' along a third direction. The first direction intersects with the second direction and is both perpendicular to the third direction. The capacitor 80 covers the second end surface of the active pillar 521' and circumferentially surrounds a portion of the side surface of the active pillar 521'. The first gate 22 is located on the first outer surface of the channel region 15. The second gate 22' is located on the second outer surface of the channel region 15.

[0094] In the memory cell of the above embodiment, since the first gate 22 and the second gate 22' are formed on two mutually opposing outer surfaces of the channel region 15 on the active pillar 521' along the second direction, and the first gate 22 and the second gate 22' share the same channel region 15, the volume of the memory cell can be reduced while reducing the power consumption of the device. The threshold voltage of the other gate can be modulated by applying a bias voltage to one gate, effectively improving the performance and reliability of the memory cell. One of the first gate 22 and the second gate 22' can serve as a control gate. The stress exerted by the control gate on the channel region 15 can increase the effective carrier mass and reduce gate-induced drain leakage current. The stress exerted on the active pillar 521' by the stress structure 60 buried in the channel region 15 and located between the first gate 22 and the second gate 22' can buffer the stress exerted by the first gate 22 and the second gate 22' on the active pillar 521', thereby preventing damage to the first gate 22 and the second gate 22' due to excessive stress on the active pillar 521', thereby effectively improving the reliability of the memory cell.

[0095] As an example, please refer to Figure 24-25 The memory cell further includes a buried gate structure 70 located in the channel region 15; the buried gate structure 70 is located between the first end surface of the active pillar 521' and the stress structure 60. The stress of the buried gate structure 70 on the active pillar 521' can buffer the stress of the first gate 22 and the second gate 22' on the active pillar 521', and the buried gate structure 70 effectively increases the contact area between the gate and the channel region 15, thereby avoiding the increase in the volume of the memory cell due to the introduction of the buried gate structure 70.

[0096] As an example, please refer to Figure 24-25 The buried gate structure 70 includes a ring-gate structure, which includes a gate conductive layer 72 and a gate dielectric layer 71. The gate conductive layer 72 is located between the bit line 80 and the stress structure 60. The gate dielectric layer 71 is located between the gate conductive layer 72 and the active pillar 521', circumferentially surrounding the gate conductive layer 72 and having an opening. The gate conductive layer 72 is connected to the stress structure 60 through the opening. The ring-gate structure can further increase the contact area between the gate conductive layer 72 and the channel region in the buried gate structure 70, thereby further improving the performance of the memory cell.

[0097] As an example, please refer to Figure 24 The stress structure 60 is an insulating block. The insulating block can be made of silicon nitride. The stress structure 60 and the buried gate structure 70 can buffer the stress of the first gate 22 and the second gate 22' on the active pillar 521' and avoid increasing the volume of the memory cell.

[0098] As an example, please refer to Figure 25The stress structure 60 includes an insulating block 61 and an annular stress layer 62 circumferentially surrounding the insulating block 61. The annular stress layer 62 is located between the insulating block 61 and the active pillar 521', and is located within the active pillar 521' between the buried gate structure 70 and the capacitor 80. The insulating block 61 and the annular stress layer 62 are made of different materials. For example, the insulating block 61 may be made of silicon oxide, and the annular stress layer 62 may be made of silicon nitride. By adjusting the size of the annular stress layer 62 and the size of the insulating block 61, the stress exerted by the stress structure 60 on the active pillar 521' can be adjusted to prevent damage caused by excessive stress and to prevent degradation of memory cell performance due to insufficient stress.

[0099] As an example, please refer to Figure 25 The first inner support structure 111 includes a first support layer 1111 and a first support ring 1112. The first support layer 1111 extends through the active pillar 521' along the third direction and is located between the bit line 90 and the stress structure 60. The first support ring 1112 circumferentially surrounds the first support layer 1111 and is located between the first support layer 1111 and the active pillar 521'. The first support layer 1111 and the first support ring 1112 are made of different materials. For example, the first support layer 1111 is made of silicon oxide, while the first support ring 1112 is made of silicon nitride. The stress exerted by the first inner support structure 111 on the active pillar 521' can be adjusted by adjusting the dimensions of the first support layer 1111 and the first support ring 1112, thereby preventing damage caused by excessive stress and degradation of memory cell performance due to insufficient stress. The first inner support structure 111 supports the multi-layer active pillar 521', preventing tilting, warping, and collapse of the active pillar 521', thereby improving the yield and reliability of the manufactured semiconductor device.

[0100] As an example, please refer to Figure 25 The second inner support structure 121 includes a second support layer 1211 and a second support ring 1212. The second support layer 1211 extends through the active pillar 521' along the third direction and is located between the capacitor 80 and the stress structure 60. The second support ring 1212 circumferentially surrounds the second support layer 1211 and is located between the second support layer 1211 and the active pillar 521'. The second support layer 1211 and the second support ring 1212 are made of different materials. For example, the second support layer 1211 is made of silicon oxide, while the second support ring 1212 is made of silicon nitride. The stress exerted by the second inner support structure 121 on the active pillar 521' can be adjusted by varying the dimensions of the second support layer 1211 and the second support ring 1212, thereby preventing damage caused by excessive stress and degradation of memory cell performance due to insufficient stress. By supporting the multiple layers of active pillars 521', the second inner support structure 121 prevents tilting, warping, and collapse of the active pillars 521', thereby improving the yield and reliability of the manufactured semiconductor device.

[0101] As an example, please refer to Figure 25 The first gate 22 includes a gate dielectric layer 221 located on the first outer surface of the channel region 15, and a gate conductive layer 222 located on the gate dielectric layer 221 away from the surface of the channel region 15 along the second direction; the second gate 22' includes a gate dielectric layer 221' located on the second outer surface of the channel region 15, and a gate conductive layer 222' located on the gate dielectric layer 221' away from the surface of the channel region 15 along the second direction.

[0102] In some embodiments, please refer to Figure 20 A memory includes a word line isolation structure 20 located on a substrate 10, a first outer support structure 30 and a second outer support structure 40 spaced along a first direction and extending along a second direction, and a plurality of memory cells according to any of the disclosed embodiments stacked along a third direction; an active pillar 521' penetrates the first outer support structure 30 and the second outer support structure 40 along the first direction; a first inner support structure 111 is located inside the first outer support structure 30, and a second inner support structure 121 is located inside the second outer support structure 40; the word line isolation structure 20 is located between the first outer support structure 30 and the second outer support structure 40, and is at least located between word lines of memory cells adjacent to each other along the second direction; memory cells adjacent to each other along the second direction share a bit line extending along the second direction; memory cells adjacent to each other along the third direction share a word line extending along the third direction.

[0103] According to some embodiments, the lower electrodes 81 of capacitors 80 on different active pillars 521 ′ are insulated from each other via the second inner support structure 121 ′; the capacitors 80 on different active pillars 521 ′ share the upper electrode 83 and the dielectric layer between the upper electrode 83 and the corresponding lower electrode 81 .

[0104] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present disclosure.

[0105] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0106] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above embodiments merely illustrate several implementations of the present disclosure, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the disclosed patent. It should be noted that a person of ordinary skill in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the disclosed patent shall be determined by the appended claims.

Claims

1. A storage unit, characterized in that: include: An active pillar having a first end surface and a second end surface facing away from each other along a first direction, the first end surface being used to connect to a bit line; the active pillar including a first doped region, a channel region, and a second doped region sequentially arranged along the first direction; the channel region having a first outer surface and a second outer surface facing away from each other along the second direction; the channel region including a stress structure penetrating the active pillar along a third direction; the first direction intersecting with the second direction and being perpendicular to the third direction; a capacitor, covering the second end surface and circumferentially surrounding a portion of a side surface of the active pillar; a first gate, located on the first outer surface; a second gate, located on the second outer surface; as well as, A buried gate structure is located in the channel region, and the buried gate structure is located between the first end surface and the stress structure and is connected to the stress structure.

2. The storage unit according to claim 1, wherein The buried gate structure includes: a gate conductive layer, located between the first end surface and the stress structure; The gate dielectric layer is located between the gate conductive layer and the active pillar, circumferentially surrounds the gate conductive layer and has an opening, and the gate conductive layer is connected to the stress structure via the opening.

3. The storage unit according to claim 1 or 2, characterized in that The stress structure is an insulating block; or The stress structure includes an insulating block and an annular stress layer circumferentially surrounding the insulating block. The annular stress layer is located between the insulating block and the active pillar.

4. The storage unit according to claim 3, wherein: The insulating block includes a first sub-insulating block and a second sub-insulating block located between the first sub-insulating block and the capacitor. The first sub-insulating block and the second sub-insulating block are made of different materials.

5. The storage unit according to claim 1 or 2, characterized in that The active column also includes: a first inner support structure, penetrating the active pillar along the third direction, and located on a side of the first doped region away from the channel region along the first direction; and / or The second inner support structure penetrates the active pillar along the third direction and is located between the second doped region and the capacitor. The storage unit according to claim 5 , wherein: The first inner support structure comprises: a first supporting layer, penetrating the active pillar along the third direction and located between the first end surface and the channel region; a first supporting ring circumferentially surrounding the first supporting layer and located between the first supporting layer and the active pillar; and / or The second inner support structure comprises: a second supporting layer, penetrating the active pillar along the third direction and located between the second end surface and the channel region; The second supporting ring circumferentially surrounds the second supporting layer and is located between the second supporting layer and the active pillar.

7. The storage unit according to claim 1 or 2, characterized in that The first gate includes: a gate dielectric layer, located on the first outer surface; a gate conductive layer, located on a surface of the gate dielectric layer of the first gate away from the channel region along the second direction; and The second gate includes: a gate dielectric layer, located on the second outer surface; The gate conductive layer is located on a surface of the gate dielectric layer of the second gate away from the channel region along the second direction.

8. A method for preparing a memory, characterized in that: include: providing a substrate; A word line isolation structure, a first outer support structure and a second outer support structure spaced apart along a first direction and extending along a second direction, and a stacked structure are formed on the substrate. The stacked structure includes dielectric layers and semiconductor layers alternately stacked in sequence along a third direction, with one dielectric layer adjacent to the substrate. The semiconductor layer includes a plurality of active pillars extending along the first direction, penetrating the first and second outer support structures, and spaced apart along the second direction. The word line isolation structure is located between the first and second outer support structures and defines a dual-gate trench together with the active pillars adjacent to the second direction. The dual-gate trench exposes portions of the first and second outer surfaces of the active pillars that are mutually opposed along the second direction, as well as portions of the substrate. The active pillars include a target trench extending along the third direction to the substrate and located between the dual-gate trenches. forming a first gate and a second gate on the first outer surface and the second outer surface in the dual-gate trench, respectively; and forming a stress structure at least in the target trench; During the process of forming the first gate and the second gate, a buried gate structure is formed in the target trench, the buried gate structure being located between the first outer support structure and the stress structure and connected to the stress structure.

9. The method for preparing a memory according to claim 8, wherein: Before forming the word line isolation structure, the method further includes: forming a first hole penetrating the active pillar and the first outer support structure along the third direction, and a second hole penetrating the active pillar and the second outer support structure along the third direction; Performing a target doping process on the active pillar through the first hole and the second hole to obtain a first doping region, a channel region, and a second doping region sequentially arranged along the first direction; the target trench penetrates the channel region along the third direction; A first inner support structure is formed in the first hole, and a second inner support structure is formed in the second hole.

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