Semiconductor device and method of manufacturing the same, storage system

Abstract

This application provides a semiconductor device and its manufacturing method, and a memory system, comprising: a first semiconductor structure, including: a stacked structure stacked along a second direction, the stacked structure including a plurality of gate layers spaced apart along the second direction, the plurality of gate layers forming a plurality of step surfaces in a step region; and a plurality of gate contacts located in the step region, penetrating the plurality of step surfaces and respectively connected to the plurality of gate layers, the gate contacts including a first contact end and a second contact end located on opposite sides of the stacked structure in the second direction; a second semiconductor structure located on one side of the first semiconductor structure and close to the first contact end in the second direction, and including a first peripheral circuit connected to the first contact end of the gate contacts; and a third semiconductor structure located on the side of the first semiconductor structure away from the second semiconductor structure in the second direction, and including a second peripheral circuit connected to the second contact end of the gate contacts.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method, and a memory system. Background Technology

[0002] In recent years, the development of memory has been particularly rapid. The main characteristics of memory are that it can retain stored information for a long time without power, and it has the advantages of high integration, fast access speed, and easy erasure and rewriting. Therefore, it has been widely used in many fields such as microcomputers and automatic control.

[0003] As memory wiring becomes increasingly complex, simplifying memory wiring has become an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device and its manufacturing method, as well as a memory system, to simplify the wiring of the semiconductor device.

[0005] In a first aspect, this application provides a semiconductor device, the semiconductor device comprising:

[0006] A first semiconductor structure, comprising a memory region and a step region adjacent along a first direction, the first semiconductor structure comprising:

[0007] A stacked structure stacked along a second direction, the stacked structure including a plurality of gate layers spaced apart along the second direction, the plurality of gate layers respectively forming a plurality of step surfaces in the step region, the second direction intersecting the first direction; and

[0008] Multiple gate contacts are located in the stepped region, penetrate the multiple stepped surfaces and are respectively connected to the multiple gate layers, and the gate contacts include a first contact end and a second contact end located on opposite sides of the stacked structure in the second direction;

[0009] A second semiconductor structure, located on one side of the first semiconductor structure and close to the first contact end in the second direction, includes a first peripheral circuit connected to the first contact end of the gate contact portion; and

[0010] A third semiconductor structure is located on the side of the first semiconductor structure away from the second semiconductor structure in the second direction, and includes a second peripheral circuit connected to the second contact end of the gate contact portion.

[0011] Secondly, this application provides a method for manufacturing a semiconductor device, the method comprising:

[0012] A first semiconductor layer is provided, the first semiconductor layer having a first region and a second region adjacent to each other along a first direction;

[0013] A stacked structure is formed on a first semiconductor layer and stacked along a second direction. The stacked structure includes a plurality of gate layers spaced apart along the second direction. The plurality of gate layers respectively form a plurality of stepped surfaces in the first region. The second direction intersects the first direction.

[0014] A plurality of gate contacts are formed in the first region. The plurality of gate contacts penetrate the plurality of stepped surfaces and are respectively connected to the plurality of gate layers. The gate contact includes a first contact end and a second contact end located on opposite sides of the stacked structure in the second direction. The second contact end of the gate contact extends into the first semiconductor layer.

[0015] A first peripheral circuit is formed on the second semiconductor layer, and the first peripheral circuit is disposed between the second semiconductor layer and the stacked structure in the second direction, and connected to the first contact terminal of the gate contact portion; and

[0016] A second peripheral circuit is formed on the third semiconductor layer. In the second direction, the second peripheral circuit is disposed on the side of the stacked structure away from the second semiconductor layer and connected to the second contact terminal of the gate contact portion.

[0017] Thirdly, this application provides a storage system, the storage system comprising:

[0018] The memory includes the semiconductor devices of any of the embodiments described above; and

[0019] A controller, connected to the memory, is used to control the memory.

[0020] In some embodiments of this application, multiple gate contacts are located in a stepped region, extending through multiple stepped surfaces and respectively connected to multiple gate layers. Each gate contact includes a first contact end and a second contact end located on opposite sides of the stacked structure in a second direction. A first peripheral circuit of a second semiconductor structure is connected to the first contact end of the gate contact, and a second peripheral circuit of a third semiconductor structure is connected to the second contact end of the gate contact. This design achieves bidirectional lead-out of the gate contacts, reduces the wiring density of the wires connecting the gate contacts to the first and second peripheral circuits, and thus simplifies the wiring in the semiconductor device.

[0021] Furthermore, based on the bidirectional lead-out of the gate contact portion, the first peripheral circuit is connected to the first contact end of the gate contact portion, and the second peripheral circuit is connected to the second contact end of the gate contact portion. Through this design, the first peripheral circuit and the second peripheral circuit are respectively connected to opposite sides of the first semiconductor structure, which helps to expand the process window of the first peripheral circuit and the second peripheral circuit, thereby reducing the manufacturing difficulty of the first peripheral circuit and the second peripheral circuit. Attached Figure Description

[0022] Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this application;

[0023] Figures 2 to 11 Schematic diagrams of the structure of semiconductor devices for manufacturing some embodiments of this application;

[0024] Figures 12 to 16 Schematic diagrams of the structure of semiconductor devices for manufacturing some other embodiments of this application;

[0025] Figure 17 This is a block diagram of a storage system according to some embodiments of this application;

[0026] Figure 18 This is a block diagram of a storage system according to other embodiments of this application;

[0027] Figure 19 This is a block diagram of an electronic device according to some embodiments of this application.

[0028] The attached diagram is labeled as follows:

[0029] 100, Semiconductor device; 200, Memory; 300, Controller; 400, Storage system; 500, Electronic device; 600, Mainframe;

[0030] 1, First semiconductor structure; 1', First initial semiconductor structure; 1a, Storage region; 1b, Step region; 1c, Peripheral region;

[0031] 01, First semiconductor layer; 01a, First region; 01b, Second region; 01c, Third region; 01d1, Opening of the first semiconductor layer; 01d2, Opening of the second semiconductor layer;

[0032] 11, stacked structure; 111, gate layer; 111a, step surface; 11a, stacked layer; 112, sacrificial layer; 113, gate dielectric layer; 1111, first gate layer; 1112, second gate layer; 1113, third gate layer; 1114, fourth gate layer;

[0033] 12, gate contact portion; 121, through portion; 122, contact portion; 123, gate contact insulating portion; 12a, first contact end; 12b, second contact end;

[0034] 13. Isolation layer;

[0035] 141, First conductor; 142, Second conductor; 143, Third conductor; 144, Fourth conductor; 145, Fifth conductor;

[0036] 152, third bonding layer; 1521, third bonding contact;

[0037] 16, Channel structure; 16a, First channel connection end; 16b, Second channel connection end; 162, Functional layer; 161, Channel layer;

[0038] 17. Common source pole;

[0039] 181, First through-array contact point; 1811, First conductive connection part; 1812, First insulating part;

[0040] 182, Second through-array contact point; 1821, Second conductive connection part; 1822, Second insulating part;

[0041] 19. Dielectric layer;

[0042] 2, Second semiconductor structure; 02, Second semiconductor layer; 21, First peripheral circuit; 211, First string drive circuit; 212, First page buffer circuit; 22, Fourth bonding layer; 221, Fourth bonding contact;

[0043] 3', Third initial semiconductor structure; 3, Third semiconductor structure; 03, Third semiconductor layer; 31, Second peripheral circuit; 311, Second string drive circuit; 312, Second page buffer circuit; 32, Second bonding layer; 321, Second bonding contact; 33, Connecting contact; 331, First connecting contact; 332, Second connecting contact;

[0044] 4. Pad area; 41. First pad area; 42. Second pad area;

[0045] x, the first direction; z, the second direction. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0047] Please refer to Figure 1 The diagram shown is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this application. The method for manufacturing a semiconductor device includes the following steps:

[0048] S101: A first semiconductor layer is provided, the first semiconductor layer having a first region and a second region adjacent to each other along a first direction;

[0049] S102: A stacked structure is formed on the first semiconductor layer along the second direction. The stacked structure includes a plurality of gate layers spaced apart along the second direction. The plurality of gate layers respectively form a plurality of stepped surfaces in the first region. The second direction intersects with the first direction.

[0050] S103: A plurality of gate contacts are formed in the first region. The plurality of gate contacts penetrate the plurality of stepped surfaces and are respectively connected to the plurality of gate layers. The gate contacts include a first contact end and a second contact end located on opposite sides of the stacked structure in the second direction. The second contact end of the gate contact extends into the first semiconductor layer.

[0051] S104: A first peripheral circuit is formed on the second semiconductor layer, and the first peripheral circuit is disposed between the second semiconductor layer and the stacked structure in a second direction, and the first contact terminal of the first peripheral circuit and the gate contact portion is connected; and

[0052] S105: A second peripheral circuit is formed on the third semiconductor layer, and the second peripheral circuit is disposed on the side of the stacked structure away from the second semiconductor layer in the second direction, and the second contact end of the second peripheral circuit and the gate contact portion are connected.

[0053] In some embodiments of this application, a plurality of gate contacts are formed, penetrating multiple stepped surfaces and respectively connected to multiple gate layers. Each gate contact includes a first contact end and a second contact end located on opposite sides of the stacked structure in a second direction. This method allows the gate contacts to be connected to peripheral circuits via the first and second contact ends, meaning the gate contacts can be bidirectionally led out. This provides conditions for multiple chips, including peripheral circuits, to be disposed on opposite sides of the stacked structure, while simultaneously reducing the wiring density connecting the gate contacts and peripheral circuits, which helps simplify the wiring design of semiconductor devices.

[0054] Furthermore, based on the bidirectional lead-out capability of the gate contact portion, the first contact terminal of the first peripheral circuit is connected to the gate contact portion, and the second contact terminal of the second peripheral circuit is connected to the gate contact portion. This method connects the first and second peripheral circuits to opposite sides of the stacked structure, thereby expanding the process window for the first and second peripheral circuits and reducing their manufacturing complexity.

[0055] Please refer to Figures 2 to 11 This is a schematic diagram of the structure of a semiconductor device used in manufacturing some embodiments of this application. The following is in conjunction with... Figure 1 , Figures 2 to 11 The manufacturing methods of semiconductor devices according to some embodiments of this application are described in detail.

[0056] First, refer to Figure 2 As shown, step S101 is performed: a first semiconductor layer 01 is provided, the first semiconductor layer 01 having a first region 01a and a second region 01b adjacent to each other along the first direction x.

[0057] In some embodiments, the first semiconductor layer 01 has a first region 01a, a second region 01b, and a third region 01c. The first region 01a and the second region 01b are adjacent to each other along a first direction x. The third region 01c is adjacent to the second region 01b along the first direction x. In the first region 01a, the gate contact 12 (hereinafter referred to as the gate contact 12) is connected to the gate layer 111. The second region 01b is used to form a memory array. The third region 01c is located outside the first region 01a and the second region 01b.

[0058] Exemplarily, the first semiconductor layer 01 includes two first regions 01a and two second regions 01b, but is not limited thereto. In the first direction x, the two first regions 01a are arranged adjacent to each other, and the two second regions 01b are located on opposite sides of the two first regions 01a. A third region 01c is disposed around the two second regions 01b.

[0059] Next, refer to Figure 3 As shown, in step S102, a stacked structure 11 stacked along the second direction z is formed on the first semiconductor layer 01. The stacked structure 11 includes a plurality of gate layers 111 spaced along the second direction z. The plurality of gate layers 111 respectively form a plurality of step surfaces 111a in the first region 01a. The second direction z intersects with the first direction x.

[0060] For example, the second direction z is perpendicular to the first direction x, but is not limited thereto.

[0061] In some embodiments, refer to Figure 2 As shown, forming a stacked structure 11 stacked along the second direction z on the first semiconductor layer 01 includes: forming a stacked layer 11a stacked along the second direction z on the first semiconductor layer 01, the stacked layer 11a including a plurality of sacrificial layers 112 and a plurality of gate dielectric layers 113 alternately arranged along the second direction z.

[0062] For example, the materials of the plurality of sacrificial layers 112 include, but are not limited to, silicon nitride. The materials of the plurality of gate dielectric layers 113 include, but are not limited to, silicon oxide.

[0063] In some embodiments, forming a stacked structure 11 stacked along the second direction z on the first semiconductor layer 01 further includes replacing a plurality of sacrificial layers 112 with a plurality of gate layers 111 to obtain the stacked structure 11.

[0064] It should be noted that, by... Figure 2 After replacing the multiple sacrificial layers 112 of the semiconductor structure shown with multiple gate layers 111, the following is obtained: Figure 3 The first initial semiconductor structure 1' is shown.

[0065] In some embodiments, a plurality of gate layers 111 form a plurality of stepped surfaces 111a in the first region 01a.

[0066] For example, the plurality of gate layers 111 includes a first gate layer 1111, a second gate layer 1112, a third gate layer 1113, and a fourth gate layer 1114. The first gate layer 1111 and the second gate layer 1112 are respectively located in two first regions 01a and are disposed on the same layer. The third gate layer 1113 and the fourth gate layer 1114 are respectively located in two first regions 01a and are disposed on the same layer.

[0067] It should be noted that the two elements set on the same layer are coplanar or substantially coplanar in the first direction x.

[0068] For example, the material of the gate layer 111 includes, but is not limited to, metals, including but not limited to tungsten, cobalt, copper, nickel and combinations thereof.

[0069] Next, please refer to Figure 3 As shown, step S103 is performed: a plurality of gate contacts 12 are formed in the first region 01a. The plurality of gate contacts 12 penetrate the plurality of step surfaces 111a and are respectively connected to the plurality of gate layers 111. The gate contacts 12 include a first contact end 12a and a second contact end 12b located on opposite sides of the stacked structure 11 in the second direction z. The second contact end 12b of the gate contact 12 extends into the first semiconductor layer 01.

[0070] In some embodiments, refer to Figure 2 As shown, the formation of a plurality of gate contacts 12 in the first region 01a includes: forming a plurality of gate contacts 12 in the first region 01a that penetrate the stacked layer 11a and extend into the first semiconductor layer 01.

[0071] It should be noted that after replacing the multiple sacrificial layers 112 with multiple gate layers 111, multiple gate contacts 12 penetrate the stacked structure 11 and are respectively connected to the multiple gate layers 111.

[0072] In some embodiments, the gate contact 12 includes a through portion 121 and a contact portion 122, both extending along a second direction z, and the through portion 121 is connected to the contact portion 122. The through portion 121 penetrates the stacked structure 11 and extends into the first semiconductor layer 01, with one end of the through portion 121 away from the contact portion 122 being a second contact end 12b. The end of the contact portion 122 away from the through portion 121 is a first contact end 12a, and the contact portion 122 also contacts the step surface 111a of the gate layer 111, thereby connecting the gate contact 12 to the gate layer 111.

[0073] In some embodiments, the dimension of the through portion 121 along the first direction x is smaller than the dimension of the contact portion 122 along the first direction x, so that the contact portion 122 can contact the stepped surface 111a of the gate layer 111 to realize the connection between the gate contact portion 12 and the gate layer 111.

[0074] In some embodiments, the gate contact portion 12 further includes a gate contact insulating portion 123, which covers the through portion 121 and the sidewall of the contact portion 122 extending along the second direction z, and the gate contact insulating portion 123 also covers the bottom wall of the through portion 121 located in the first semiconductor layer 01.

[0075] For example, the materials of the through portion 121 and the contact portion 122 include metals, including but not limited to tungsten, cobalt, copper, nickel, and combinations thereof. The materials of the gate contact insulating portion 123 include but not limited to silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof.

[0076] In some embodiments, refer to Figure 2 As shown, before replacing the multiple sacrificial layers 112 with multiple gate layers 111, the above method further includes: forming a multiple channel structure 16 in the second region 01b that extends through the stacked layer 11a along the second direction z. The multiple channel structure 16 includes a first channel connection end 16a and a second channel connection end 16b located on opposite sides of the stacked layer 11a in the second direction z. The second channel connection end 16b of the channel structure 16 extends into the first semiconductor layer 01.

[0077] In some embodiments, the channel structure 16 includes a functional layer 162 and a channel layer 161 disposed from the outside to the inside. The functional layer 162 includes a barrier layer, a charge trapping layer, and a tunneling layer disposed sequentially from the outside to the inside. The channel layer 161 extends along a second direction z, and its opposite ends in the second direction z include a first channel connection end 16a and a second channel connection end 16b.

[0078] For example, the barrier layer, charge trapping layer, and tunneling layer may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure. The material of the channel layer 161 includes, but is not limited to, polysilicon.

[0079] It should be noted that after replacing multiple sacrificial layers 112 with multiple gate layers 111, the channel structure 16 penetrates the stacked structure 11 along the second direction z, and the first channel connection terminal 16a and the second channel connection terminal 16b of the channel structure 16 are located on opposite sides of the stacked structure 11.

[0080] In some embodiments of this application, the channel structure 16 and the gate contact portion 12 both penetrate the stacked structure 11, which facilitates the use of a single photomask to prepare the channel hole filling the channel structure 16 and the gate contact hole filling the gate contact portion 12, thereby reducing the number of photomasks required to manufacture semiconductor devices and reducing the cost required to manufacture semiconductor devices.

[0081] In some embodiments, refer to Figure 2 As shown, before replacing the multiple sacrificial layers 112 with multiple gate layers 111, the above method further includes: forming a dielectric layer 19 in the third region 01c and the first region 01a, the dielectric layer 19 covering the stacked layer 11a of the first region 01a and filling the third region 01c.

[0082] Exemplarily, the material of the dielectric layer 19 includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof. Specifically, the material of the dielectric layer 19 includes silicon oxide.

[0083] In some embodiments, refer to Figure 2 As shown, the above method further includes: forming a first through-array connection contact point 181 on the first semiconductor layer 01 of the third region 01c, the first through-array connection contact point 181 extending into the first semiconductor layer 01 along the second direction z.

[0084] In some embodiments of this application, at least one of the first peripheral circuit and the second peripheral circuit is connected to an external circuit through a first through-array contact point 181.

[0085] In some embodiments, the first through-array contact point 181 penetrates the dielectric layer 19 of the third region 01c and extends into the first semiconductor layer 01.

[0086] In some embodiments, the first through-array contact point 181 includes a first conductive connection portion 1811 and a first insulating portion 1812. The first conductive connection portion 1811 extends along a second direction z, and the first insulating portion 1812 covers the sidewall of the first conductive connection portion 1811 extending along the second direction z. The first insulating portion 1812 also covers the bottom wall of the first conductive connection portion 1811 located in the first semiconductor layer 01.

[0087] In some embodiments, refer to Figure 2As shown, the above method further includes: forming a second through-array contact point 182 extending along the second direction z on the first semiconductor layer 01, the second through-array contact point 182 extending into the first semiconductor layer 01.

[0088] In some embodiments of this application, the second through-array connection contact 182 is connected between the first peripheral circuit and the second peripheral circuit; in other words, the second through-array connection contact 182 is used to connect the first peripheral circuit and the second peripheral circuit.

[0089] In some embodiments, forming a second through-array connection contact 182 extending along the second direction z on the first semiconductor layer 01 includes forming the second through-array connection contact 182 in one of the third region 01c and the first region 01a.

[0090] For example, refer to Figure 2 As shown, a second through-array connection contact 182 is formed in the third region 01c. The second through-array connection contact 182 penetrates the dielectric layer 19 and extends into the first semiconductor layer 01. The second through-array connection contact 182 and the first through-array connection contact 181 are spaced apart.

[0091] In some embodiments, the second through-array contact point 182 includes a second conductive connection portion 1821 and a second insulating portion 1822. The second insulating portion 1822 covers the sidewall of the second conductive connection portion 1821 extending along the second direction z, and the second insulating portion 1822 also covers the bottom wall of the second conductive connection portion 1821 located in the first semiconductor layer 01.

[0092] For example, the materials of the second conductive connection portion 1821 and the first conductive connection portion 1811 both include metals, including but not limited to tungsten, cobalt, copper, nickel, and combinations thereof. The materials of the first insulating portion 1812 and the second insulating portion 1822 include but are not limited to silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof.

[0093] In some embodiments, refer to Figure 2 As shown, the method further includes: forming a third conductive line 143 on the side of the gate contact portion 12 away from the first semiconductor layer 01; the third conductive line 143 being connected to the first contact ends 12a of at least two gate contacts 12; and the at least two gate contacts 12 connected to the third conductive line 143 being respectively connected to at least two gate layers 111 located in two first regions 01a and disposed in the same layer. With this design, when a signal is applied to one third conductive line 143, at least two gate layers 111 located in the same layer can be driven simultaneously.

[0094] For example, the first contact ends 12a of the two gate contact portions 12 that are respectively connected to the first gate layer 1111 and the second gate layer 1112 are both connected to the third wire 143.

[0095] In some embodiments, refer to Figure 2 As shown, the above method further includes: forming a third bonding contact 1521, which is located on the side of the third wire 143 away from the first semiconductor layer 01 in the second direction z.

[0096] In some embodiments, a third bonding layer 152 is formed on the side of the third conductor 143 away from the first semiconductor layer 01, and the third bonding layer 152 includes a plurality of third bonding contacts 1521.

[0097] In some embodiments, a plurality of third bonding contacts 1521 are respectively connected to the third wire 143, the first channel connection end 16a of the channel structure 16, the first through-array connection contact 181, and the second through-array connection contact 182. Wherein, since the third bonding contacts 1521 are connected to the third wire 143, the third bonding contacts 1521 are also connected to the first contact end 12a of the gate contact portion 12.

[0098] Through the above steps S101, S102, S103 and other steps, we obtain Figure 3 The first initial semiconductor structure 1' is shown.

[0099] Next, refer to Figures 4 to 5 As shown, in step S104, a first peripheral circuit 21 is formed on the second semiconductor layer 02. The first peripheral circuit 21 is disposed between the second semiconductor layer 02 and the stacked structure 11 in the second direction z, and the first peripheral circuit 21 is connected to the first contact terminal 12a of the gate contact portion 12.

[0100] In some embodiments, refer to Figure 4 As shown, the first peripheral circuit 21 includes a first drive circuit 211, which is connected to the first contact terminal 12a of the gate contact portion 12 to drive the gate layer 111 connected to the gate contact portion 12. The first drive circuit 211 includes at least one high-voltage transistor.

[0101] In some embodiments, the first peripheral circuit 21 further includes a first page buffer circuit 212, which is connected to a first channel connection terminal 16a of the channel structure 16 to drive the channel structure 16. The first page buffer circuit 212 includes at least one of a high-voltage transistor and a low-voltage transistor.

[0102] For example, the first page buffer circuit 212 includes a high-voltage transistor and a low-voltage transistor.

[0103] In some embodiments, refer to Figure 4 As shown, the above method further includes: forming a fourth bonding contact 221 on the side of the first peripheral circuit 21 away from the second semiconductor layer 02, and the fourth bonding contact 221 is connected to the first peripheral circuit 21.

[0104] For example, multiple fourth bonding contacts 221 are respectively connected to the first page buffer circuit 212 and the first string drive circuit 211.

[0105] In some embodiments, forming a fourth bonding contact 221 on the side of the first peripheral circuit 21 away from the second semiconductor layer 02 includes forming a fourth bonding layer 22 on the side of the first peripheral circuit 21 away from the second semiconductor layer 02, the fourth bonding layer 22 including the fourth bonding contact 221.

[0106] In some embodiments of this application, by forming a first peripheral circuit 21 and a fourth bonding layer 22, etc., on the second semiconductor layer 02, the following structure is obtained: Figure 4 The second semiconductor structure 2 is shown.

[0107] In some embodiments, refer to Figure 5 As shown, disposing the first peripheral circuit 21 between the second semiconductor layer 02 and the stacked structure 11 in the second direction z includes: Figure 3 The first initial semiconductor structure 1' shown is flipped and placed in... Figure 4 On the second semiconductor structure 2 shown, the first semiconductor layer 01 of the first initial semiconductor structure 1' is located on the side of the stacked structure 11 away from the second semiconductor structure 2.

[0108] In some embodiments, after placing the first initial semiconductor structure 1' on the second semiconductor structure 2, the method further includes bonding the third bonding contact 1521 and the fourth bonding contact 221.

[0109] In some embodiments of this application, the first peripheral circuit 21 is connected to the third wire 143, the first channel connection end 16a of the channel structure 16, the first through array connection contact 181 and the second through array connection contact 182 by bonding the third bonding contact 1521 and the fourth bonding contact 221.

[0110] The first page buffer circuit 212 is connected to the second through array contact point 182 and the first channel connection terminal 16a of the channel structure 16. The first string drive circuit 211 is connected to the first contact terminal 12a of at least two gate contacts 12 via the third wire 143.

[0111] In some embodiments, the first contact terminal 12a connecting the first peripheral circuit 21 and the gate contact 12 includes: in two adjacent gate contacts 12, the first contact terminal 12a of one gate contact 12 is connected to the first peripheral circuit 21, while the other gate contact 12 is connected to the second peripheral circuit (hereinafter referred to as the second peripheral circuit) via a second contact terminal 12b. In this way, two adjacent gate contacts 12 are led out from different contact terminals, reducing the concentration and complexity of the wiring connecting the first contact terminal 12a of the gate contact 12 to the first peripheral circuit 21.

[0112] For example, in a first region 01a, two gate contacts 12 connected to the first gate layer 1111 and the third gate layer 1113 are adjacent in the first direction x. The first contact end 12a of the gate contact 12 connected to the first gate layer 1111 is connected to the first peripheral circuit 21, while the first contact end 12a of the gate contact 12 connected to the third gate layer 1113 is not connected to the first peripheral circuit 21.

[0113] In some embodiments, the first contact terminal 12a connecting the first peripheral circuit 21 and the gate contact portion 12 further includes: the first contact terminal 12a of at least two gate contacts 12 respectively connected to at least two gate layers 111 disposed in the same layer is connected to the first peripheral circuit 21. In this way, a single third wire 143 can be used to connect the first contact terminals 12a of at least two gate contacts 12 to drive the at least two gate layers 111 disposed in the same layer, and the number of wires connected to the first contact terminals 12a of the gate contacts 12 is reduced.

[0114] For example, in the first direction x, the first gate layer 1111 and the second gate layer 1112 are disposed on the same layer, such that the first contact end 12a of the two gate contact portions 12 connected to the first gate layer 1111 and the second gate layer 1112 are connected to the first peripheral circuit 21 through the third wire 143.

[0115] Please refer to Figure 6 As shown, after connecting the first initial semiconductor structure 1' and the second semiconductor structure 2, the above method further includes: removing the first semiconductor layer 01 of the first region 01a to form a first semiconductor layer opening 01d1 and exposing the second contact ends 12b of the plurality of gate contact portions 12.

[0116] In some embodiments, while removing the first semiconductor layer 01 of the first region 01a, the first semiconductor layer 01 of the third region 01c is also removed to form a first semiconductor layer opening 01d1 and expose the second conductive connection portion 1821 of the second through-array connection contact 182 and the first conductive connection portion 1811 of the first through-array connection contact 181.

[0117] For example, an etching process is used to remove the first semiconductor layer 01 of the first region 01a and the third region 01c, then an etching process is used to remove the gate contact insulating portion 123 covering the second contact end 12b of the gate contact portion 12, and an etching process is used to remove the first insulating portion 1812 covering the bottom wall of the first conductive connection portion 1811 and the second insulating portion 1822 covering the bottom wall of the second conductive connection portion 1821.

[0118] Please refer to Figure 7 As shown, the above method further includes: forming an isolation layer 13 in the opening 01d1 of the first semiconductor layer, wherein the second contact ends 12b of the plurality of gate contacts 12 all extend into the isolation layer 13.

[0119] In some embodiments, the isolation layer 13 also covers the second through-array contact point 182 and the first through-array contact point 181.

[0120] For example, the material of the isolation layer 13 includes, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof.

[0121] In some embodiments, please refer to Figure 8 As shown, after forming the isolation layer 13, the above method further includes: removing the first semiconductor layer 01 of the second region 01b to form a second semiconductor layer opening 01d2 and exposing the second channel connection ends 16b of the plurality of channel structures 16.

[0122] For example, an etching process is used to remove the first semiconductor layer 01 of the second region 01b, and an etching process is used to remove the functional layer 162 outside the second channel connection terminal 16b.

[0123] In some embodiments, please refer to Figure 9 As shown, a common source electrode 17 is formed in the opening 01d2 of the second semiconductor layer, and the second channel connection terminals 16b of the plurality of channel structures 16 extend into the common source electrode 17 and contact the common source electrode 17.

[0124] In some embodiments, the material of the common source 17 includes, but is not limited to, metal or polysilicon. For example, the material of the common source 17 includes polysilicon.

[0125] In other embodiments, after removing the first semiconductor layer 01 of the first region 01a, the second region 01b, and the third region 01c, an isolation layer 13 may be formed at the location where the first semiconductor layer 01 was removed. An isolation layer opening may be formed on the isolation layer 13, and a common source electrode 17 may be formed in the isolation layer opening. The common source electrode 17 may be connected to the second channel connection terminal 16b of the plurality of channel structures 16.

[0126] In some embodiments, please continue to refer to Figure 9As shown, after forming the common source 17, the above method further includes: forming a first wire 141 on the side of the isolation layer 13 away from the stacked structure 11 in the second direction z, and connecting the first wire 141 to the second contact end 12b of the gate contact portion 12.

[0127] In some embodiments, the second contact ends 12b of at least two gate contact portions 12 respectively connected to at least two gate layers 111 disposed in the same layer are connected to the first wire 141 to reduce the number of wires connected to the second contact ends 12b of the gate contact portions 12.

[0128] For example, the second contact end 12b of the two gate contact portions 12 connected to the third gate layer 1113 and the fourth gate layer 1114 disposed in the same layer is connected to the first wire 141.

[0129] In some embodiments, the method further includes forming a second wire 142 on the side of the common source 17 away from the stacked structure 11 in the second direction z, and the second wire 142 is connected to the common source 17.

[0130] For example, the second conductor 142 is connected to at least two common source poles 17 to reduce the number of wires connected to the common source poles 17.

[0131] In some embodiments, the method further includes: forming a fourth wire 144 and a fifth wire 145 on the side of the isolation layer 13 away from the stacked structure 11 in the second direction z, and connecting the fourth wire 144 to the first conductive connection portion 1811 of the first through-array connection contact point 181, and connecting the fifth wire 145 to the second conductive connection portion 1821 of the second through-array connection contact point 182.

[0132] In some embodiments, the first wire 141, the second wire 142, the fourth wire 144, and the fifth wire 145 are obtained by patterning a conductive layer, and therefore, the first wire 141, the second wire 142, the fourth wire 144, and the fifth wire 145 are located in the same layer.

[0133] In other embodiments, the first conductor 141, the second conductor 142, the fourth conductor 144, and the fifth conductor 145 may also be located in different layers.

[0134] In some embodiments, please continue to refer to Figure 9 As shown, the above method further includes: forming a first bonding contact 1511 on the side of the first wire 141 away from the stacked structure 11 in the second direction z, and the first bonding contact 1511 is connected to the first wire 141.

[0135] In some embodiments, a first bonding layer 151 is formed on the side of the first wire 141 away from the stacked structure 11 in the second direction z. The first bonding layer 151 includes a plurality of first bonding contacts 1511, which are respectively connected to the first wire 141, the second wire 142, the fourth wire 144 and the fifth wire 145.

[0136] In some embodiments of this application, since multiple first bonding contacts 1511 are respectively connected to the first wire 141, the second wire 142, the fourth wire 144 and the fifth wire 145, the multiple first bonding contacts 1511 are respectively connected to the first through-array connection contact 181, the second through-array connection contact 182, the second channel connection end 16b of the channel structure 16 and the second contact end 12b of the gate contact portion 12.

[0137] In some embodiments of this application, the above steps are used to form Figure 9 The first semiconductor structure 1 shown includes a memory region 1a, a step region 1b, and a peripheral region 1c. A stacked structure 11 is located in the memory region 1a and the step region 1b, with the step surface 111a of the gate layer 111 located in the step region 1b. A first through-array connection contact 181 and a second through-array connection contact 182 are located in the peripheral region 1c.

[0138] It should be noted that storage area 1a corresponds to the second area 01b, step area 1b corresponds to the first area 01a, and outer area 1c corresponds to the third area 01c.

[0139] Finally, refer to Figure 10 and Figure 11 As shown, by performing step S105, a second peripheral circuit 31 is formed on the third semiconductor layer 03. The second peripheral circuit 31 is disposed on the side of the stacked structure 11 away from the second semiconductor layer 02 in the second direction x, and the second peripheral circuit 31 and the second contact terminal 12b of the gate contact portion 12 are connected.

[0140] In some embodiments, refer to Figure 10 As shown, the second peripheral circuit 31 includes a second drive circuit 311, which is connected to the second contact terminal 12b of the gate contact portion 12 to drive the gate layer 111. The second drive circuit 311 includes at least one high-voltage transistor.

[0141] In some embodiments, the second peripheral circuit 31 further includes a second page buffer circuit 312, which is connected to the second channel connection terminal 16b of the channel structure 16 to drive the channel structure 16. The second page buffer circuit 312 includes at least one of a high-voltage transistor and a low-voltage transistor.

[0142] In related technologies, multiple wires are connected to the same end of the gate contact, resulting in dense wiring and significant wiring difficulties. However, in some embodiments of this application, because the first drive circuit 211 is connected to the first contact end 12a of the gate contact 12 and the second drive circuit 311 is connected to the second contact end 12b of the gate contact 12, bidirectional lead-out of the gate contact 12 is achieved. This reduces the density of wires connecting the gate contact 12 to the peripheral circuit, which is beneficial for improving the wiring design of semiconductor devices and enhancing their performance.

[0143] In some embodiments of this application, since the first page buffer circuit 212 is used to connect to the first channel connection terminal 16a of the channel structure 16 and the second page buffer circuit 312 is used to connect to the second channel connection terminal 16b of the channel structure 16, bidirectional lead-out of the channel structure 16 is also realized, reducing the density of the wires connecting the channel structure 16 and the peripheral circuit, which is beneficial to improving the wiring design of the semiconductor device and improving the performance of the semiconductor device.

[0144] In some embodiments, refer to Figure 10 As shown, the above method further includes: forming a connection contact 33 on the third semiconductor layer 03, the connection contact 33 extending into the third semiconductor layer 03 along the second direction z, and the connection contact 33 being spaced apart from the second peripheral circuit 31.

[0145] In some embodiments, the connection contact 33 includes a first connection contact 331 and a second connection contact 332. The first connection contact 331 is connected to the second peripheral circuit 31. The second connection contact 332 is used to connect to the first through-array connection contact 181.

[0146] In some embodiments, the materials of the first contact point 331 and the second contact point 332 include metals, including but not limited to tungsten, cobalt, copper, nickel, and combinations thereof.

[0147] In some embodiments, refer to Figure 10 As shown, the above method further includes: forming a second bonding contact 321 connected to the second peripheral circuit 31 on the side of the second peripheral circuit 31 away from the third semiconductor layer 03 in the second direction z.

[0148] In some embodiments, a second bonding layer 32 is formed on the side of the second peripheral circuit 31 away from the third semiconductor layer 03 in the second direction z. The second bonding layer 32 includes a plurality of second bonding contacts 321, which are respectively connected to the first connection contact 331, the second connection contact 332 and the second peripheral circuit 31.

[0149] In some embodiments of this application, the above method is used to prepare... Figure 10The third initial semiconductor structure 3' is shown.

[0150] In some embodiments, refer to Figure 11 As shown, placing the second peripheral circuit 31 on the side of the stacked structure 11 away from the second semiconductor layer 02 in the second direction x includes: flipping the third initial semiconductor structure 3' and then placing it on... Figure 9 The first semiconductor structure 1 is located on the side away from the second semiconductor structure 2, and the third semiconductor layer 03 is located on the side of the first semiconductor structure 1 away from the second semiconductor structure 2.

[0151] In some embodiments, after placing the third initial semiconductor structure 3' on the first semiconductor structure 1, the above method includes: bonding the second bonding contact 321 to the first bonding contact 1511 to connect the second peripheral circuit 31 and the second contact end 12b of the gate contact portion 12.

[0152] In some embodiments, the second contact end 12b connecting the second peripheral circuit 31 and the gate contact portion 12 includes: in two adjacent gate contacts 12, the second contact end 12b of the other gate contact portion 12 is connected to the second peripheral circuit 31.

[0153] For example, when the first contact end 12a of the gate contact portion 12 connected to the first gate layer 1111 is connected to the first peripheral circuit 21 via the third wire 143, the second contact end 12b of the gate contact portion 12 connected to the third gate layer 1113 is connected to the second peripheral circuit 31 via the first wire 141.

[0154] In some embodiments, the second contact end 12b connecting the second peripheral circuit 31 and the gate contact portion 12 further includes: connecting the second contact end 12b of at least two gate contacts 12 respectively connected to at least two gate layers 111 disposed in the same layer to the second peripheral circuit 31.

[0155] For example, the second contact ends 12b of the two gate contact portions 12 of the third gate layer 1113 and the fourth gate layer 1114 disposed in the same layer are connected to the second peripheral circuit 31 through the first wire 141.

[0156] In some embodiments of this application, since the second bonding contact 321 is bonded to the first bonding contact 1511, the second peripheral circuit 31 and the first peripheral circuit 21 are connected through the second through-array connection contact 182 and the fifth wire 145, etc., and the second connection contact 332 and the first peripheral circuit 21 are connected through the first through-array connection contact 181 and the fourth wire 144, etc. Moreover, the second page buffer circuit 312 is connected to the second channel connection terminal 16b of the channel structure 16 through the second wire 142 and the common source 17, etc., and the second string drive circuit 311 is connected to the second contact terminal 12b of the gate contact portion 12 through the first wire 141, etc.

[0157] In some embodiments, after connecting the third initial semiconductor structure 3' and the first semiconductor structure 1, the method further includes: forming a pad portion 4 on the side of the third semiconductor layer 03 away from the second peripheral circuit 31, so that the first through array connection contact point 181 connects the pad portion 4 and the first peripheral circuit 21.

[0158] In some embodiments, before forming the pad portion 4 on the side of the third semiconductor layer 03 away from the second peripheral circuit 31, the surface of the third semiconductor layer 03 away from the second peripheral circuit 31 is thinned to expose the connection contact 33.

[0159] In some embodiments, forming a pad portion 4 on the side of the third semiconductor layer 03 away from the second peripheral circuit 31 includes: forming a pad portion 4 on the side of the thinned third semiconductor layer 03 away from the second peripheral circuit 31, and the pad portion 4 being connected to the connection contact point 33.

[0160] In some embodiments, the pad portion 4 includes a first pad portion 41 and a second pad portion 42. The first pad portion 41 is connected to a first connection contact 331, thereby connecting the first pad portion 41 to the second peripheral circuit 31, facilitating signal transmission between the second peripheral circuit 31 and external circuits through the first pad portion 41. The second pad portion 42 is connected to a second connection contact 332, thereby connecting the second pad portion 42 to the first peripheral circuit 21 through the second connection contact 332 and the first through-array connection contact 181, facilitating signal transmission between the first peripheral circuit 21 and external circuits through the second pad portion 42.

[0161] In other embodiments, the method further includes forming a pad portion 4 on the side of the second semiconductor layer 02 away from the first peripheral circuit 21, and connecting the first through array contact point 181 to the pad portion 4 and the second peripheral circuit 31.

[0162] In some embodiments of this application, the third initial semiconductor structure 3' is processed using the method described above to obtain... Figure 11 The third semiconductor structure 3 is shown.

[0163] In some embodiments of this application, the gate contact portion 12 in the first initial semiconductor structure 1' extends through the stacked structure 11. The gate contact portion 12 has opposing first contact ends 12a and second contact ends 12b, and the gate contact portion 12 can be bidirectionally led out. Based on the bidirectional lead-out of the gate contact portion 12, the first initial semiconductor structure 1' is connected to the second semiconductor structure 2, and the second semiconductor structure 2 is connected to some of the first contact ends 12a of the gate contact portions 12. Next, the first initial semiconductor structure 1' is processed to obtain the first semiconductor structure 1. A third initial semiconductor structure 3' is connected to the side of the first semiconductor structure 1 away from the second semiconductor structure 2, and the third initial semiconductor structure 3' is connected to some of the second contact ends 12b of the other gate contact portions 12. The third initial semiconductor structure 3' is processed to obtain... Figure 11 Semiconductor device 100 shown.

[0164] In other embodiments, reference is made to Figure 12 As shown, after step S101 and before step S102, the method further includes: pre-burying a common source layer 17a in the first semiconductor layer 01.

[0165] In other embodiments, the material of the common source layer 17a is different from the material of the first semiconductor layer 01. The material of the common source layer 17a includes, but is not limited to, metal or polysilicon. Specifically, the material of the common source layer 17a includes polysilicon.

[0166] In other embodiments, reference is made to Figure 12 As shown, in step S103 above, forming a plurality of gate contact portions 12 in the first region 01a includes: forming a plurality of gate contact portions 12 extending into the common source layer 17a, and the second contact ends 12b of the plurality of gate contact portions 12 extending into the common source layer 17a.

[0167] In other embodiments, reference is made to Figure 12 and Figure 13 As shown, before replacing the multiple sacrificial layers 112 with multiple gate layers 111, the above method further includes: forming a multiple channel structure 16 in the second region 01b that penetrates the stacked layer 11a along the second direction z. The multiple channel structure 16 includes a first channel connection terminal 16a and a second channel connection terminal 16b located on opposite sides of the stacked layer 11a in the second direction z. The second channel connection terminal 16b of the channel structure 16 extends into the common source layer 17a and contacts the common source layer 17a.

[0168] It should be noted that, Figure 12 The semiconductor structure shown is Figure 2 The semiconductor structures shown are basically similar, except that... Figure 12A common source layer 17a is pre-embedded in the first semiconductor layer 01 shown, and the common source layer 17a is located in the first region 01a, the second region 01b, and the third region 01c. Additionally, Figure 12 After replacing the sacrificial layer 112 of the semiconductor structure shown with the gate layer 111, the following is obtained: Figure 13 The first initial semiconductor structure 1' is shown.

[0169] In other embodiments, reference is made to Figure 14 As shown, the connection Figure 13 The first initial semiconductor structure 1' shown is Figure 4 The second semiconductor structure 2 is shown.

[0170] In other embodiments, reference is made to Figure 15 As shown, the connection Figure 13 The first initial semiconductor structure 1' shown is Figure 4 Following the second semiconductor structure 2 shown, the method further includes thinning the surface of the first semiconductor layer 01 away from the stacked structure 11 to expose the common source layer 17a.

[0171] In other embodiments, reference is made to Figure 16 As shown, the above method further includes: removing the common source layer 17a of the first region 01a to form a common source layer opening and exposing the second contact ends 12b of the plurality of gate contact portions 12; and

[0172] An isolation layer 13 is formed in the common source layer opening, and the second contact ends 12b of the plurality of gate contacts 12 all extend into the isolation layer 13.

[0173] In other embodiments, reference is made to Figure 16 As shown, the above method further includes: removing the common source layer 17a of the first region 01a while removing the common source layer 17a of the third region 01c, exposing the first conductive connection portion 1811 of the first through-array connection contact point 181, and exposing the second conductive connection portion 1821 of the second through-array connection contact point 182.

[0174] In other embodiments, reference is made to Figure 16 As shown, the above method further includes: removing the common source electrode layer 17a of the first region while retaining the common source electrode layer 17a of the second region 01b to form a common source electrode 17, and the second channel connection end 16b of the channel structure 16 extends into the common source electrode 17 and contacts the common source electrode 17.

[0175] In some other embodiments of this application, by pre-burying a common source layer 17a in the first semiconductor layer 01, removing a portion of the common source layer 17a to form a common source 17, and extending the second channel connection terminal 16b of the channel structure 16 into the common source 17 and contacting the common source 17, the problem of damage to the channel structure 16 caused by etching to remove the functional layer other than the second channel connection terminal 16b and then forming the common source 17 is improved.

[0176] The following combination Figure 11 Semiconductor devices 100 according to some embodiments of this application are described.

[0177] The semiconductor device 100 includes a first semiconductor structure 1, a second semiconductor structure 2, and a third semiconductor structure 3. In the second direction z, the second semiconductor structure 2 is located on one side of the first semiconductor structure 1, and the third semiconductor structure 3 is located on the side of the first semiconductor structure 1 away from the second semiconductor structure 2. The first semiconductor structure 1 is connected to both the third semiconductor structure 3 and the second semiconductor structure 2.

[0178] The first semiconductor structure 1 includes a memory region 1a and a step region 1b adjacent to each other along a first direction x. The first semiconductor structure 1 also includes a peripheral region 1c disposed at a distance from the step region 1b along the first direction x, and the peripheral region 1c is disposed around the memory region 1a.

[0179] The first semiconductor structure 1 includes a stacked structure 11 stacked along a second direction z. The stacked structure 11 includes a plurality of gate layers 111 and a plurality of gate dielectric layers 113 alternately arranged along the second direction z. The plurality of gate layers 111 are spaced apart in the second direction z, and a plurality of step surfaces 111a are formed in the step region 1b, respectively. The second direction z intersects with the first direction x.

[0180] For example, the second direction z is perpendicular to the first direction x, but is not limited thereto.

[0181] The first semiconductor structure 1 also includes a plurality of gate contacts 12 located in the step region 1b. The plurality of gate contacts 12 penetrate the plurality of step surfaces 111a and are respectively connected to the plurality of gate layers 111. The gate contacts 12 include a first contact end 12a and a second contact end 12b located on opposite sides of the stacked structure 11 in the second direction z. In other words, the gate contacts 12 penetrate the stacked structure 11 in the step region 1b.

[0182] In related technologies, the gate contact portion only contacts the step surface, making it difficult to achieve bidirectional lead-out. However, in some embodiments of this application, the gate contact portion 12 penetrates the stacked structure 11 of the step region 1b, and the peripheral circuit can be connected to the first contact end 12a and the second contact end 12b of the gate contact portion 12, that is, the gate contact portion 12 can be bidirectionally led out.

[0183] In some embodiments, the gate contact 12 includes a through portion 121 and a contact portion 122, both extending along a second direction z, and the through portion 121 is connected to the contact portion 122. The through portion 121 penetrates the stacked structure 11 of the step region 1b, and the end of the through portion 121 away from the contact portion 122 is a second contact end 12b. The end of the contact portion 122 away from the through portion 121 is a first contact end 12a, and the end of the contact portion 122 near the through portion 121 also contacts the step surface 111a of the gate layer 111, thereby connecting the gate contact 12 to the gate layer 111.

[0184] In some embodiments, the dimension of the through portion 121 along the first direction x is smaller than the dimension of the contact portion 122 along the first direction x, so that the contact portion 122 can contact the stepped surface 111a of the gate layer 111 to realize the connection between the gate contact portion 12 and the gate layer 111.

[0185] In some embodiments, the gate contact portion 12 further includes a gate contact insulating portion 123, which covers the through portion 121 and the sidewall of the contact portion 122 extending along the second direction z. With this design, on the one hand, an insulating layer is provided between the through portion 121 and the gate layer 111 it penetrates; on the other hand, one end of the contact portion 122 connected to the through portion 121 can contact the corresponding gate layer 111, thereby realizing the connection between the gate contact portion 12 and the corresponding gate layer 111.

[0186] The second semiconductor structure 2 is disposed near the first contact terminal 12a and includes a first peripheral circuit 21, which is connected to the first contact terminal 12a of the gate contact portion 12. The third semiconductor structure 3 includes a second peripheral circuit 31, which is connected to the second contact terminal 12b of the gate contact portion 12. This design enables bidirectional routing of the gate contact portion 12, reducing the wiring density of the wires connecting the gate contact portion 12 to the first peripheral circuit 21 and the second peripheral circuit 31, thereby simplifying the wiring in the semiconductor device 100. Furthermore, connecting the first peripheral circuit 21 and the second peripheral circuit 31 to opposite sides of the first semiconductor structure 1 respectively helps to expand the process window of the first peripheral circuit 21 and the second peripheral circuit 31, thereby reducing the manufacturing difficulty of the first peripheral circuit 21 and the second peripheral circuit 31.

[0187] In some embodiments, in two adjacent gate contacts 12, the first contact end 12a of one gate contact 12 is connected to the first peripheral circuit 21, and the second contact end 12b of the other gate contact 12 is connected to the second peripheral circuit 31. With this design, the two adjacent gate contacts 12 are led out from different contact ends, the wiring connecting the first contact end 12a of the gate contact 12 to the first peripheral circuit 21 has a low concentration, and the wiring connecting the second contact end 12b of the gate contact 12 to the second peripheral circuit 31 also has a low concentration, further simplifying the wiring of the semiconductor device 100.

[0188] In some embodiments, the first contact ends 12a of at least two gate contacts 12 respectively connected to at least two gate layers 111 disposed in the same layer are connected to the first peripheral circuit 21, and / or the second contact ends 12b of at least two gate contacts 12 respectively connected to at least two gate layers 111 disposed in the same layer are connected to the second peripheral circuit 31. This design helps to reduce the number of wires connecting the first contact ends 12a of the gate contacts 12 to the first peripheral circuit 21, and also reduces the number of wires connecting the second contact ends 12b of the gate contacts 12 to the second peripheral circuit 31, further simplifying the wiring of the semiconductor device 100.

[0189] Specifically, the first contact end 12a of at least two gate contact portions 12 respectively connected to at least two gate layers 111 disposed in the same layer is connected to the first peripheral circuit 21, and the second contact end 12b of at least two gate contact portions 12 respectively connected to at least two gate layers 111 disposed in the same layer is connected to the second peripheral circuit 31.

[0190] In some embodiments, the first semiconductor structure 1 further includes an isolation layer 13 located in the step region 1b and the peripheral region 1c. The isolation layer 13 is located between the stacked structure 11 and the third semiconductor structure 3. The second contact ends 12b of the plurality of gate contacts 12 all extend into the isolation layer 13, such that the plurality of gate contacts 12 are mutually insulated.

[0191] In some embodiments, the first semiconductor structure 1 further includes a first wire 141, which is located on the side of the isolation layer 13 away from the stacked structure 11 and is connected to the second contact end 12b of the gate contact portion 12.

[0192] In some embodiments, a first wire 141 is connected to the second contact end 12b of at least two gate contacts 12 to reduce the number of required first wires 141 and further simplify the wiring of the semiconductor device 100.

[0193] In some embodiments, the first semiconductor structure 1 further includes a third wire 143, which is located on the side of the stacked structure 11 near the second semiconductor structure 2 and is connected to the first contact end 12a of the gate contact portion 12.

[0194] In some embodiments, a third wire 143 is connected to the first contact end 12a of at least two gate contacts 12 to reduce the number of required third wires 143 and further simplify the wiring of the semiconductor device 100.

[0195] In some embodiments of this application, the first contact end 12a and the second contact end 12b of the plurality of gate contacts 12 are respectively connected to the third wire 143 and the first wire 141 to realize bidirectional lead-out of the plurality of gate contacts 12.

[0196] The first semiconductor structure 1 also includes a plurality of channel structures 16 located in the memory region 1a. The plurality of channel structures 16 extend through the stacked structure 11 along the second direction z, and the channel structures 16 include a first channel connection terminal 16a and a second channel connection terminal 16b located on opposite sides of the stacked structure 11 in the second direction z. The first channel connection terminal 16a is disposed close to the second semiconductor structure 2 and connected to the first peripheral circuit 21, and the second channel connection terminal 16b is disposed close to the third semiconductor structure 3 and connected to the second peripheral circuit 31.

[0197] In some embodiments of this application, a plurality of channel structures 16 extend through the stacked structure 11 along the second direction z. The channel structures 16 include a first channel connection terminal 16a and a second channel connection terminal 16b located on opposite sides of the stacked structure 11 in the second direction z. With this design, the channel structures 16 can also be led out from the first channel connection terminal 16a and the second channel connection terminal 16b respectively to connect with peripheral circuits, further simplifying the wiring of the semiconductor device 100.

[0198] In some embodiments, the channel structure 16 includes a functional layer 162 and a channel layer 161 disposed from the outside to the inside. The functional layer 162 includes a barrier layer, a charge trapping layer, and a tunneling layer disposed sequentially from the outside to the inside. The channel layer 161 extends along a second direction z, and its opposite ends in the second direction z include a first channel connection end 16a and a second channel connection end 16b.

[0199] In some embodiments, the first semiconductor structure 1 further includes a common source 17 located in the memory region 1a. In the second direction z, the common source 17 is located on the side of the stacked structure 11 away from the second semiconductor structure 2, and the second channel connection ends 16b of the plurality of channel structures 16 extend into the common source 17 and contact the common source 17.

[0200] In some embodiments, the first semiconductor structure 1 further includes a second wire 142, which is located on the side of the common source 17 away from the stacked structure 11 and is connected to the common source 17 and the second peripheral circuit 31.

[0201] In some embodiments, a second conductor 142 connects at least two common sources 17 to reduce the number of required second conductors 142 and further simplify the wiring of the semiconductor device 100.

[0202] In some embodiments, the third semiconductor structure 3 further includes a first connection contact 331 and a first pad portion 41 connected to each other. The first connection contact 331 extends along the second direction z into the third semiconductor layer 03 and is connected to the second peripheral circuit 31. In the second direction z, the first pad portion 41 is located on the side of the third semiconductor layer 03 away from the second peripheral circuit 31, so as to facilitate the transmission of signals between the second peripheral circuit 31 and the external circuit through the first pad portion 41.

[0203] In other embodiments, the second semiconductor structure 2 may also include a first connection contact 331 and a first pad portion 41 connected to each other. The first connection contact 331 extends into the second semiconductor layer 02 along the second direction z and is connected to the first peripheral circuit 21. In the second direction z, the first pad portion 41 is located on the side of the second semiconductor layer 02 away from the first peripheral circuit 21, so as to facilitate the transmission of signals between the first peripheral circuit 21 and the external circuit through the first pad portion 41.

[0204] In some embodiments, the first semiconductor structure 1 further includes a first through-array connection contact 181 located in the peripheral region 1c and extending along the second direction z, the first through-array connection contact 181 extending into the isolation layer 13. The third semiconductor structure 3 further includes a second connection contact 332 and a second pad portion 42 interconnected. The second connection contact 332 extends along the second direction z into the third semiconductor layer 03 and is spaced apart from the second peripheral circuit 31. In the second direction z, the second pad portion 42 is located on the side of the third semiconductor layer 03 away from the second peripheral circuit 31, and the first pad portion 41 is disposed adjacent to it. The first through-array connection contact 181 is connected to the second connection contact 332 and the first peripheral circuit 21, such that the first through-array connection contact 181 connects the second pad portion 42 and the first peripheral circuit 21, facilitating signal transmission between the first peripheral circuit 21 and external circuits through the second pad portion 42.

[0205] In other embodiments, the second semiconductor structure 2 may also include interconnected second connection contacts 332 and second pad portions 42. The second connection contacts 332 extend along a second direction z into the second semiconductor layer 02 and are spaced apart from the first peripheral circuit 21. In the second direction z, the second pad portions 42 are located on the side of the second semiconductor layer 02 away from the first peripheral circuit 21 and are adjacent to the first pad portions 41. A first through-array connection contact 181 is connected to the second connection contacts 332 and the second peripheral circuit 31, such that the first through-array connection contact 181 connects the second pad portions 42 and the second peripheral circuit 31, facilitating signal transmission between the second peripheral circuit 31 and external circuits via the second pad portions 42.

[0206] In some embodiments, the first semiconductor structure 1 further includes a fourth wire 144, which is connected between the first through-array connection contact 181 and the second connection contact 332, and the fourth wire 144 is located on the side of the isolation layer 13 away from the stacked structure 11 in the second direction z.

[0207] In some embodiments, the first semiconductor structure 1 further includes a second through-array connection contact 182, which extends along the second direction z into the isolation layer 13 and connects the first peripheral circuit 21 and the second peripheral circuit 31.

[0208] In some embodiments, the second through-array contact point 182 is located in at least one of the peripheral region 1c and the stepped region 1b. Specifically, the second through-array contact point 182 is located in the peripheral region 1c, and the first through-array contact points 181 are spaced apart.

[0209] In some embodiments, the first semiconductor structure 1 further includes a fifth wire 145 located on the side of the isolation layer 13 away from the stacked structure 11 in the second direction z, and the fifth wire 145 is connected between the second through array contact point 182 and the second peripheral circuit 31.

[0210] In some embodiments, the first semiconductor structure 1 further includes a first bonding layer 151, located between the first conductive line 141 and the third semiconductor structure 3. The first bonding layer 151 includes a plurality of first bonding contacts 1511, which are respectively connected to the first conductive line 141, the second conductive line 142, the fifth conductive line 145, and the fourth conductive line 144. The third semiconductor structure 3 further includes a second bonding layer 32, located on the side of the second peripheral circuit 31 away from the third semiconductor layer 03. The second bonding layer 32 includes a plurality of second bonding contacts 321, which are respectively connected to the second peripheral circuit 31 and the second connection contact 332. The plurality of second bonding contacts 321 are bonded to the plurality of first bonding contacts 1511 to form a first bonding surface.

[0211] Since multiple second bonding contacts 321 are bonded to multiple first bonding contacts 1511, the fourth wire 144 is connected to the second connecting contact 332, the second connecting contact 332 is connected to the first through array connecting contact 181, and the second peripheral circuit 31 is connected to the first wire 141, the second wire 142 and the fifth wire 145.

[0212] In some embodiments, the first semiconductor structure 1 further includes a third bonding layer 152 located between the stacked structure 11 and the second semiconductor structure 2 in the second direction z. The third bonding layer 152 includes a plurality of third bonding contacts 1521, which are respectively connected to the third wire 143, the first channel connection terminal 16a of the channel structure 16, the first through-array connection contact 181, and the second through-array connection contact 182. The second semiconductor structure 2 further includes a fourth bonding layer 22 located on the side of the first peripheral circuit 21 away from the second semiconductor layer 02. The fourth bonding layer 22 includes a plurality of fourth bonding contacts 221 connected to the first peripheral circuit 21. The plurality of fourth bonding contacts 221 are bonded to the plurality of third bonding contacts 1521 to form a second bonding surface.

[0213] Because multiple fourth bonding contacts 221 are bonded to multiple third bonding contacts 1521 respectively. The third wire 143, the first channel connection end 16a of the channel structure 16, the first through array connection contact 181 and the second through array connection contact 182 are all connected to the first peripheral circuit 21.

[0214] Please refer to Figure 17 and Figure 18 This application also provides a storage system 400, which includes a memory 200 and a controller 300. The memory 200 includes semiconductor devices 100 as described in any of the above embodiments. The controller 300 is connected to the memory 200 and is used to control the memory 200.

[0215] The storage system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein.

[0216] In some embodiments, refer to Figure 17As shown, the storage system 400 includes a memory 200 and a controller 300. The storage system 400 can be integrated into a 3D memory card.

[0217] Among them, 3D memory cards include any one of the following: PC card (PCMCIA, the International Association for Personal Computer 3D Memory Cards), Compact Flash (CF) card, Smart Media (SM) card, 3D memory, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0218] In other embodiments, reference is made to Figure 18 As shown, the storage system 400 includes multiple memory units 200 and a controller 300. The storage system 400 is integrated into a solid-state drive (SSD).

[0219] In some embodiments, in the storage system 400, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0220] In other embodiments, in storage system 400, controller 300 is configured to operate in high duty cycle environments in SSDs or eMMCs used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0221] In some embodiments, the controller 300 may be configured to manage data stored in the memory 200 and to communicate with external devices (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions relating to data stored or to be stored in the memory 200, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes relating to data read from or written to the memory 200.

[0222] Of course, controller 300 can also perform any other suitable functions, such as formatting memory 200; for example, controller 300 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0223] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0224] Please refer to Figure 19 Some embodiments of this application also provide an electronic device 500. The electronic device 500 can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0225] Electronic device 500 may include the aforementioned storage system 400 and host 600, wherein host 600 includes at least one of a central processing unit (CPU) and a cache.

[0226] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A first semiconductor structure, comprising a memory region and a step region adjacent along a first direction, the first semiconductor structure comprising: A stacked structure stacked along a second direction, the stacked structure including a plurality of gate layers spaced apart along the second direction, the plurality of gate layers forming a plurality of step surfaces in the step region, the second direction intersecting the first direction; A plurality of gate contacts are located in the stepped region, penetrating the plurality of stepped surfaces and respectively connected to the plurality of gate layers. Each gate contact includes a first contact end and a second contact end located on opposite sides of the stacked structure in the second direction. One gate contact includes a through portion and a contact portion, both extending along the second direction, and the through portion is connected to the contact portion. The through portion penetrates the stacked structure of the stepped region, with the end of the through portion away from the contact portion being the second contact end. The end of the contact portion away from the through portion is the first contact end, and the end face of the contact portion near the through portion and extending along the first direction also contacts the gate layer. Multiple channel structures are located in the storage area and extend through the stacking structure along the second direction. One of the channel structures includes a first channel connection end and a second channel connection end located on opposite sides of the stacking structure in the second direction. A second semiconductor structure, located on one side of the first semiconductor structure and near the first contact end in the second direction, includes a first peripheral circuit connected to the first contact end of the gate contact portion, and a first channel connection end located near the second semiconductor structure and connected to the first peripheral circuit; and A third semiconductor structure is located on the side of the first semiconductor structure away from the second semiconductor structure in the second direction, and includes a second peripheral circuit. The second peripheral circuit is connected to the second contact end of the gate contact portion, and the second channel connection end is disposed close to the third semiconductor structure and connected to the second peripheral circuit.

2. The semiconductor device according to claim 1, characterized in that, In two adjacent gate contacts, the first contact end of one gate contact is connected to the first peripheral circuit, and the second contact end of the other gate contact is connected to the second peripheral circuit.

3. The semiconductor device according to claim 1, characterized in that, The first contact end of at least two gate contacts that are respectively connected to at least two gate layers disposed in the same layer is connected to the first peripheral circuit; And / or, The second contact end of at least two gate contacts that are respectively connected to at least two gate layers disposed in the same layer is connected to the second peripheral circuit.

4. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: An isolation layer is located between the stacked structure and the third semiconductor structure, and the second contact ends of the plurality of gate contacts all extend into the isolation layer.

5. The semiconductor device according to claim 4, characterized in that, The first semiconductor structure further includes: A first conductive line is located on the side of the isolation layer away from the stacked structure and is connected to the second contact end of the gate contact portion.

6. The semiconductor device according to claim 5, characterized in that, The first semiconductor structure further includes: A first bonding contact is located between the first wire and the third semiconductor structure, and is connected to the first wire; The third semiconductor structure further includes a second bonding contact connected to the second peripheral circuit, the second bonding contact being bonded to the first bonding contact.

7. The semiconductor device according to claim 1, characterized in that, The dimension of the through portion along the first direction is smaller than the dimension of the contact portion along the first direction.

8. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: A common source electrode is located in the memory region, on the side of the stacked structure away from the second semiconductor structure in the second direction, and the second channel connection ends of the plurality of channel structures extend into the common source electrode and contact the common source electrode.

9. The semiconductor device according to claim 8, characterized in that, The first semiconductor structure further includes: The second wire is located on the side of the common source electrode away from the stacked structure and is connected to the common source electrode and the second peripheral circuit.

10. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes a peripheral region spaced apart from the stepped region in the first direction and a first through-array contact point located in the peripheral region and extending along the second direction; The third semiconductor structure further includes a pad portion, and the first through-array connection point connects the pad portion and the first peripheral circuit; or... The second semiconductor structure also includes a pad portion, and the first through-array connection point connects the pad portion and the second peripheral circuit.

11. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: The second through-array connection point extends along the second direction and connects the first peripheral circuit and the second peripheral circuit.

12. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: The third bonding contact is located between the stacked structure and the second semiconductor structure in the second direction; The second semiconductor structure further includes a fourth bonding contact connected to the first peripheral circuit, the fourth bonding contact being bonded to the third bonding contact.

13. A method for manufacturing a semiconductor device, characterized in that, The method includes: A first semiconductor layer is provided, the first semiconductor layer having a first region and a second region adjacent to each other along a first direction; A stacked layer is formed on the first semiconductor layer along a second direction, the stacked layer including multiple sacrificial layers and multiple gate dielectric layers alternately arranged along the second direction, the second direction intersecting the first direction; A plurality of channel structures are formed in the second region, extending through the stacked layer in the second direction. The plurality of channel structures include a first channel connection end and a second channel connection end located on opposite sides of the stacked layer in the second direction. The multiple sacrificial layers are replaced with multiple gate layers to obtain a stacked structure; the multiple gate layers form multiple stepped surfaces in the first region; A plurality of gate contacts are formed in the first region, the plurality of gate contacts penetrating the plurality of stepped surfaces and respectively connecting to the plurality of gate layers. Each gate contact includes a first contact end and a second contact end located on opposite sides of the stacked structure in the second direction, the second contact end of the gate contact extending into the first semiconductor layer; wherein, one gate contact includes a through portion and a contact portion, both the through portion and the contact portion extending along the second direction, and the through portion connecting to the contact portion; the through portion penetrates the stacked structure of the first region, the end of the through portion away from the contact portion being the second contact end; the end of the contact portion away from the through portion being the first contact end, and the end face of the contact portion near the through portion and extending along the first direction also contacting the gate layer; A first peripheral circuit is formed on the second semiconductor layer. The first peripheral circuit is disposed between the second semiconductor layer and the stacked structure in the second direction, and connects the first peripheral circuit to the first contact terminal of the gate contact portion and the first channel connection terminal of the channel structure. A second peripheral circuit is formed on the third semiconductor layer. In the second direction, the second peripheral circuit is disposed on the side of the stacked structure away from the second semiconductor layer, and the second peripheral circuit is connected to the second contact terminal of the gate contact portion and the second channel connection terminal of the channel structure.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The first contact terminal connecting the first peripheral circuit and the gate contact portion includes: In two adjacent gate contacts, the first contact end of one of the gate contacts is connected to the first peripheral circuit; The second contact terminal connecting the second peripheral circuit and the gate contact portion includes: In one of two adjacent gate contacts, the second contact end of the other gate contact is connected to the second peripheral circuit.

15. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The first contact terminal connecting the first peripheral circuit and the gate contact portion includes: The first contact ends of at least two gate contacts that are respectively connected to at least two gate layers disposed in the same layer are connected to the first peripheral circuit; and / or, The second contact terminal connecting the second peripheral circuit and the gate contact portion includes: The second contact end of at least two gate contacts that are respectively connected to at least two gate layers disposed in the same layer is connected to the second peripheral circuit.

16. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The method further includes: Remove the first semiconductor layer in the first region to form a first semiconductor layer opening and expose the second contact ends of the plurality of gate contacts; and An isolation layer is formed in the opening of the first semiconductor layer, and the second contact ends of the plurality of gate contacts all extend into the isolation layer.

17. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The method further includes: A common source layer is pre-embedded in the first semiconductor layer; The formation of a plurality of gate contacts in the first region includes: forming a plurality of gate contacts extending into the common source layer, wherein the second contact ends of the plurality of gate contacts extend into the common source layer.

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that, The method further includes: The surface of the first semiconductor layer away from the stacked structure is thinned to expose the common source layer; Remove the common source layer in the first region to form a common source layer opening and expose the second contact ends of the plurality of gate contacts; and An isolation layer is formed in the common source layer opening, and the second contact ends of the plurality of gate contacts all extend into the isolation layer.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The second channel connection end of the channel structure extends into the common source electrode layer; The method further includes: removing the common source electrode layer in the first region while retaining the common source electrode layer in the second region, the remaining common source electrode layer constituting a common source electrode, and the second channel connection end of the channel structure extending into the common source electrode and contacting the common source electrode.

20. The method for manufacturing a semiconductor device according to claim 16 or 18, characterized in that, The method further includes: A first conductor is formed on the side of the isolation layer away from the stacked structure in the second direction, and the first conductor is connected to the second contact end of the gate contact.

21. The method for manufacturing a semiconductor device according to claim 20, characterized in that, The method further includes: A first bonding contact is formed on the side of the first wire away from the stacked structure in the second direction, and the first bonding contact is connected to the first wire; A second bonding contact connected to the second peripheral circuit is formed on the side of the second peripheral circuit away from the third semiconductor layer in the second direction; and The second bonding contact is bonded to the first bonding contact.

22. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The second channel connection end of the channel structure extends into the first semiconductor layer.

23. The method for manufacturing a semiconductor device according to claim 22, characterized in that, The method further includes: The first semiconductor layer in the second region is removed to form a second semiconductor layer opening and expose the second channel connection ends of the plurality of channel structures; A common source electrode is formed in the opening of the second semiconductor layer, and the second channel connection ends of the plurality of channel structures extend into the common source electrode and contact the common source electrode.

24. The method for manufacturing a semiconductor device according to claim 19 or 23, characterized in that, The method further includes: A second conductor is formed on the side of the common source electrode away from the stacked structure in the second direction, and the second conductor is connected to the common source electrode.

25. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The first semiconductor layer further includes a third region located outside the second region and the first region; the method further includes: A first through-array connection contact point is formed on the first semiconductor layer in the third region, and the first through-array connection contact point extends into the first semiconductor layer along the second direction; A pad portion is formed on the side of the third semiconductor layer away from the second peripheral circuit, such that the first through-array connection contact connects the pad portion and the first peripheral circuit; or, A pad portion is formed on the side of the second semiconductor layer away from the first peripheral circuit, and the first through-array connection contact point connects the pad portion and the second peripheral circuit.

26. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The method further includes: A second through-array connection contact point extending along the second direction is formed on the first semiconductor layer; and The second through-array connection point connects the first peripheral circuit and the second peripheral circuit.

27. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The method further includes: A third bonding contact is formed, wherein the third bonding contact is located on the side of the stacked structure away from the first semiconductor layer in the second direction, and the third bonding contact is connected to the first contact end of the gate contact portion; A fourth bonding contact is formed on the side of the first peripheral circuit away from the second semiconductor layer, and the fourth bonding contact is connected to the first peripheral circuit; and The third bonding contact and the fourth bonding contact are bonded.

28. A storage system, characterized in that, The storage system includes: Memory, including the semiconductor device as described in any one of claims 1-12; and A controller, connected to the memory, is used to control the memory.

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