Three-dimensional memory and preparation method thereof
By optimizing the traditional two-dimensional memory into a three-dimensional structure and using the left and right electrode layers to form longitudinal memory cells, the problems of degradation in storage performance and high production costs caused by miniaturization of semiconductor processes are solved, and more efficient storage performance and cost reduction are achieved.
Patent Information
- Application Number
- CN202411441551.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-01-10
AI Technical Summary
As the semiconductor process shrinks, the area of the storage unit of the traditional two-dimensional memory becomes smaller, resulting in a decrease in the effective area of the storage layer and the electrode layer, affecting the storage performance, and the photocoat process is complex, increasing production costs.
Using a three-dimensional memory structure, by optimizing the upper and lower electrode layers into left and right electrode layers, a longitudinal memory cell is formed, the effective area of the memory cell is increased, the optical mask process steps are reduced, and the production cost is reduced.
It improves storage performance, saves the area of storage units, improves the operating efficiency and reliability of devices, and effectively reduces production costs.
Smart Images
Figure CN119300363A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a three-dimensional memory and a preparation method thereof. Background Art
[0002] New memory devices such as phase change memory (PRAM) or ferroelectric memory (FeRAM) are devices that integrate memory cells in the back-end of the line (BEOL). The storage performance of a memory cell is proportional to the effective area of the storage layer and electrode layer in the memory cell.
[0003] The storage unit of the traditional two-dimensional (2D) memory is composed of an upper and lower electrode layer and a storage layer in the middle. The upper and lower electrode layers and the storage layer are deposited and grown layer by layer by atomic layer deposition (ALD). The storage layer is formed by phase change material or ferroelectric material. However, with the miniaturization of semiconductor process, the storage unit area of the traditional two-dimensional memory becomes smaller, which further leads to a reduction in the effective area of the storage layer and the electrode layer, thereby affecting the storage performance of the memory; and the preparation of the connection structure connecting the upper and lower electrode layers of the storage unit requires multiple mask processes, resulting in an increase in production costs. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a three-dimensional memory and a preparation method thereof, which can save the occupied area of the storage unit and increase the effective area of the device, thereby improving the storage performance, and can save the mask process and reduce the production cost.
[0005] In order to solve the above problems, the present invention provides a three-dimensional memory, comprising: a substrate; a first dielectric layer, covering the surface of the substrate; a first main connection structure, penetrating the first dielectric layer; a first electrode layer, formed on the surface of the first dielectric layer and in one-to-one contact with the first main connection structure; a storage layer, covering a side wall of the first electrode layer and having an extension extending to the surface of the first dielectric layer; a second dielectric layer, covering the first dielectric layer, all the first electrode layers and all the storage layers; and a second main connection structure, penetrating the second dielectric layer and in contact with a side of the storage layer away from the first electrode layer and the extension; wherein the second main connection structure also serves as a second electrode layer, and the first electrode layer, the storage layer and the second electrode layer constitute a storage unit of the three-dimensional memory.
[0006] In some embodiments, the second main connection structure is made of the same material as the first main connection structure and is different from the first electrode layer.
[0007] In some embodiments, the three-dimensional memory further comprises: a metal structure formed on the surface of the second dielectric layer and in one-to-one contact with the second main connection structure. Specifically, the metal structure is made of the same material as the first electrode layer and different from the second main connection structure.
[0008] In order to solve the above problems, the present invention also provides a method for preparing a three-dimensional memory, the method comprising the following steps: forming a semiconductor substrate, the semiconductor substrate comprising a substrate, a first dielectric layer covering the surface of the substrate, a first main connection structure penetrating the first dielectric layer, and a first electrode layer formed on the surface of the first dielectric layer and in one-to-one contact with the first main connection structure; forming a storage layer, the storage layer covering a side wall of the first electrode layer and having an extension extending to the surface of the first dielectric layer; forming a second dielectric layer, the second dielectric layer covering the first dielectric layer, all the first electrode layers and all the storage layers; and forming a second main connection structure, the second main connection structure penetrating the second dielectric layer and in contact with a side of the storage layer away from the first electrode layer and the extension; wherein the second main connection structure also serves as a second electrode layer, and the first electrode layer, the storage layer, and the second electrode layer constitute a storage unit of the three-dimensional memory. The above technical solution optimizes the traditional horizontal storage unit into a vertical storage unit by optimizing the upper and lower electrode layers into left and right electrode layers, and the effective area of a single storage unit is increased, so that the area of a single storage unit can be smaller, so as to save the occupied area of the storage unit; the increase in the effective area of the device can improve the storage performance, optimize and improve the operation efficiency and reliability of the device. Moreover, the arrangement of the vertical storage unit makes it possible that when the first main connection structure is formed, even if the first main connection structure in contact with the first electrode layer has a protrusion, it will not affect the deposition and phase change performance of the storage layer, thereby avoiding affecting the performance of the storage unit; and when the second main connection structure as the second electrode layer is formed, there is no problem of etching through the storage layer, thereby further avoiding affecting the performance of the storage unit. Moreover, the second main connection structure is used as the second electrode layer and the second main connection structure at the same time, saving a contact hole mask process, which can effectively reduce the production cost. The present invention solves the problem in the prior art that as the semiconductor process is miniaturized, the area of the storage layer and the electrode layer of the storage unit becomes smaller, resulting in a reduction in the effective area of the storage layer and the electrode layer, thereby affecting the storage performance of the memory, and saves the mask process, which can effectively reduce the production cost.
[0009] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0011] Figure 1 It is a schematic diagram of the device structure of a memory in the prior art;
[0012] Figure 2 A schematic diagram of the steps of a method for preparing a three-dimensional memory according to an embodiment of the present invention;
[0013] Figure 3A to Figure 3D A schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention;
[0014] Figure 4A to Figure 4C A schematic diagram of a device structure for forming a storage layer according to an embodiment of the present invention;
[0015] Figure 5 A schematic diagram of a device structure for forming a second dielectric layer according to an embodiment of the present invention;
[0016] Figure 6A to Figure 6B A schematic diagram of a device structure for forming a second main connection structure according to an embodiment of the present invention;
[0017] Figure 7 FIG. 1 is a schematic diagram of a device structure for forming a metal structure according to an embodiment of the present invention. DETAILED DESCRIPTION
[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0019] See also Figure 1 , which is a schematic diagram of the device structure of a memory in the prior art. Figure 1As shown, the existing memory includes: a substrate 10, a first dielectric layer 111 formed on the substrate 10, a first connection structure 121 formed in the first dielectric layer 111, a second dielectric layer 112 formed on the first dielectric layer 111, a first metal structure 131 formed in the second dielectric layer 112 and in contact with the first connection structure 121, a second connection structure 122 formed in the second dielectric layer 112 and in contact with the first metal structure 131, a storage unit 14 formed on the second dielectric layer 112 and in contact with the second connection structure 122, a third dielectric layer 113 covering the second dielectric layer 112 and the storage unit 14, a third connection structure 123 formed in the third dielectric layer 113 and in contact with the storage unit 14, and a second metal structure 132 formed on the surface of the third dielectric layer 113 and in contact with the third connection structure 123. The storage unit 14 is composed of a lower electrode layer 141, a middle storage layer 142, and an upper electrode layer 143.
[0020] The storage performance of the memory cell 14 is proportional to the effective area of the memory layer and the electrode layer. However, as the semiconductor process is miniaturized, the area of the memory layer and the electrode layer is reduced, resulting in a reduction in the effective area of the memory layer and the electrode layer, thereby affecting the storage performance of the memory. At the same time, when preparing the existing memory, the preparation of the first connection structure 121, the second connection structure 122, and the third connection structure 123 requires three photomask processes, resulting in an increase in production costs.
[0021] In order to solve the problem in the prior art that as the semiconductor process is miniaturized, the area of the storage layer and the electrode layer of the storage unit becomes smaller, resulting in a reduction in the effective area of the storage layer and the electrode layer, thereby affecting the storage performance of the memory, the present invention provides a three-dimensional (3D) structured three-dimensional memory and a preparation method thereof, which can save the occupied area of the storage unit and increase the effective area of the device, thereby improving the storage performance, optimizing and improving the operating efficiency and reliability of the device, and can save mask processes and reduce production costs.
[0022] An embodiment of the present invention provides a method for preparing a three-dimensional memory.
[0023] Please also read Figure 2 to Figure 7 ,in, Figure 2 A schematic diagram of the steps of a method for preparing a three-dimensional memory according to an embodiment of the present invention; Figure 3A to Figure 3D A schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention; Figure 4A to Figure 4C A schematic diagram of a device structure for forming a storage layer according to an embodiment of the present invention; Figure 5 A schematic diagram of a device structure for forming a second dielectric layer according to an embodiment of the present invention; Figure 6A to Figure 6BA schematic diagram of a device structure for forming a second main connection structure according to an embodiment of the present invention; Figure 7 FIG. 1 is a schematic diagram of a device structure for forming a metal structure according to an embodiment of the present invention.
[0024] like Figure 2 As shown, the preparation method of the three-dimensional memory described in this embodiment includes the following steps: S21, forming a semiconductor substrate, the semiconductor substrate includes a substrate, a first dielectric layer covering the surface of the substrate, a first main connection structure penetrating the first dielectric layer, and a first electrode layer formed on the surface of the first dielectric layer and in one-to-one contact with the first main connection structure; S22, forming a storage layer, the storage layer covers a side wall of the first electrode layer and has an extension extending to the surface of the first dielectric layer; S23, forming a second dielectric layer, the second dielectric layer covers the first dielectric layer, all the first electrode layers and all the storage layers; and S24, forming a second main connection structure, the second main connection structure penetrates the second dielectric layer and is in contact with a side of the storage layer away from the first electrode layer and the extension; wherein the second main connection structure also serves as a second electrode layer, and the first electrode layer, the storage layer, and the second electrode layer constitute a storage unit of the three-dimensional memory.
[0025] Please refer to step S21 and Figure 3D , forming a semiconductor substrate, the semiconductor substrate includes a substrate 30, a first dielectric layer 31 covering the surface of the substrate 30, a first main connection structure 321 penetrating the first dielectric layer 31, and a first electrode layer 33 formed on the surface of the first dielectric layer 31 and in one-to-one contact with the first main connection structure 321.
[0026] In this embodiment, the first main connection structures 321 penetrate the first dielectric layer 31 along the second direction D2 and are arranged at intervals along the first direction D1 , wherein the first direction D1 is parallel to the surface of the substrate 30 , and the second direction D2 is perpendicular to the surface of the substrate 30 .
[0027] In this embodiment, the material of the first electrode layer 33 is different from the material of the first main connection structure 321 .
[0028] In this embodiment, the step of forming a semiconductor substrate specifically includes: (1) providing a substrate 30, wherein the first dielectric layer 31 is formed on the surface of the substrate 30, and a first contact hole 320 penetrating the first dielectric layer 31 is formed in the first dielectric layer 31, such as Figure 3A (2) Filling the first contact hole 320 with a first metal material to form the first main connection structure 321, as shown in FIG. Figure 3B(3) Depositing and patterning a second metal material to form the first electrode layer 33 on the surface of the first dielectric layer 31 and in one-to-one contact with the first main connection structure 321, as shown in FIG. Figure 3D Specifically, the second metal material is different from the first metal material.
[0029] In this embodiment, the step of depositing and patterning the second metal material specifically includes: (31) depositing a second metal material layer 330 on the surface of the first dielectric layer 31, and forming a patterned first protective layer 38 on the surface of the second metal material layer 330, such as Figure 3C As shown; (32) using the patterned first protective layer 38 as a mask and the first dielectric layer 31 as an etching stop layer, etching the second metal material layer 330 to form the first electrode layer 33 in one-to-one contact with the first main connection structure 321, and the first protective layer 38 is retained and covers the surface of the first electrode layer 33, as shown Figure 3D The second metal material layer 330 can be deposited and grown by atomic layer deposition (Atomic Layer Deposition, ALD for short).
[0030] In this embodiment, the material of the first dielectric layer 31 may be an oxide (OX) material, such as silicon oxide (SiO). The material of the first main connection structure 321 may be metal tungsten; the material of the first electrode layer 33 is selected from one of aluminum, copper, or aluminum-copper alloy, preferably aluminum-copper alloy. Among them, aluminum-copper alloy is relatively hard, generally composed of 97% aluminum and 3% copper. Aluminum-copper alloy has similar chemical properties to metal aluminum, is light and has high tensile strength, and can replace expensive copper wire. The material of the first protective layer 38 may be nitride oxide, such as silicon oxynitride (SiON).
[0031] In this embodiment, a gate structure 39 is further formed on the surface of the substrate 30, the first dielectric layer 31 further covers the gate structure 39, and the first main connection structure 321 is arranged on both sides of the gate structure 39 along the first direction D1. The gate structure 39 includes a polysilicon gate 391, a gate oxide layer 392 located below the polysilicon gate 391, and a spacer 393 located on the sidewall of the polysilicon gate 391. Figure 3A shown.
[0032] In this embodiment, the top surface of the first main connection structure 321 is flush with the top surface of the first dielectric layer 31 .
[0033] In this embodiment, the first electrode layer 33 is in one-to-one contact with the first main connection structure 321 , and a plurality of first electrode layers 33 are disposed on the surface of the first dielectric layer 31 at intervals.
[0034] Please refer to step S22 and Figure 4C , forming a storage layer 34 , the storage layer 34 covers a side wall of the first electrode layer 33 and has an extension portion 341 extending to the surface of the first dielectric layer 31 .
[0035] In this embodiment, the step S22 specifically includes: (1) depositing a storage material to form a storage material layer 340 covering the first dielectric layer 31 and all of the first electrode layer 33, such as Figure 4A (2) depositing an anti-reflection material on the surface of the storage material layer 340 and flattening it to form a first anti-reflection layer 41, and forming a first photoresist structure 42 on the surface of the first anti-reflection layer 41, wherein the first photoresist structure 42 has a shielding portion 420 that shields a side wall of the first electrode layer 33 and a portion of the first dielectric layer 31 adjacent to the side wall corresponding to the area, as shown in FIG. Figure 4B (3) Using the first photoresist structure 42 as a mask, etching is performed to etch the remaining storage material layer 340 to form the storage layer 34, as shown in FIG. Figure 4C shown.
[0036] In this embodiment, the storage layer 34 also covers a portion of the top surface of the first protection layer 38 located on the top surface of the first electrode layer 33 .
[0037] In some embodiments, the storage material layer 340 can be deposited and grown by maskless atomic layer deposition (ALD). The material of the storage layer 34 is a ferroelectric material or a phase change material. The first anti-reflective layer 41 can be a bottom anti-reflective coating (BARC), which is a layer of organic or inorganic anti-reflective material deposited before photolithography coating to achieve the purpose of increasing the photolithography process window and improving the photolithography strip width control. The process of forming the first anti-reflective layer 41 can also include a planarization process so that the formed first anti-reflective layer 41 has a relatively flat surface. The planarization can be achieved by a chemical mechanical polishing (CMP) process. The shielding portion 420 of the first photoresist structure 42 is projected on the first dielectric layer 31 to cover a side wall of the first electrode layer 33 and a portion of the first dielectric layer 31 corresponding to the side wall.
[0038] Please refer to step S23 and Figure 5, forming a second dielectric layer 35 , wherein the second dielectric layer 35 covers the first dielectric layer 31 , all the first electrode layers 33 and all the storage layers 34 .
[0039] The material of the second dielectric layer 35 may be the same as that of the first dielectric layer 31 , both of which are oxide (OX) materials, such as silicon oxide (SiO).
[0040] Please refer to step S24 and Figure 6B , forming a second main connection structure 361, the second main connection structure 361 penetrates the second dielectric layer 35, and contacts the side of the storage layer 34 away from the first electrode layer 33 and the extension portion 341; wherein the second main connection structure 361 also serves as a second electrode layer, and the first electrode layer, the storage layer, and the second electrode layer constitute a storage unit of the three-dimensional memory.
[0041] In this embodiment, the material of the second main connection structure 361 can be the same as that of the first main connection structure 321 , for example, both are made of metal tungsten. And the material of the second main connection structure 361 is different from that of the first electrode layer 33 .
[0042] In this embodiment, in the second direction D2, the height of the second main connection structure 361 is greater than the height of the first electrode layer 33, so that the effective area of the electrode plate of the formed memory cell can be increased.
[0043] In this embodiment, the second main connection structure 361 and the first electrode layer 33 are arranged in pairs, and together with the intermediate storage layer 34, form a vertical storage unit (along the D2 direction shown in the figure), which can save the occupied area of the storage unit and increase the effective area of the device. The arrangement of the vertical storage unit in this embodiment makes it possible to avoid the problem of etching through the storage layer when forming the second main connection structure 361 as the second electrode layer (upper contact hole process), thereby further avoiding affecting the performance of the storage unit. And the second main connection structure 361 is used as the second electrode layer and the second main connection structure at the same time. Compared with Figure 1 In the conventional method, there are three dielectric layers and three contact hole (VIA) mask processes. This embodiment only requires two dielectric layers and two contact hole (VIA) mask processes, thus saving one contact hole mask process and effectively reducing production costs.
[0044] In this embodiment, a plurality of storage units are formed and distributed at intervals, and adjacent storage units are separated by a second dielectric layer 35 .
[0045] In this embodiment, before the step of forming the second dielectric layer 35, the step further includes: forming an etching stop layer 50, wherein the etching stop layer 50 covers the first dielectric layer 31, all the first electrode layers 33 and all the storage layers 34, and the second dielectric layer 35 covers the etching stop layer 50. Accordingly, the step of forming the second main connection structure 361 specifically includes: (1) using the etching stop layer 50 as an etching stop layer, etching in the second dielectric layer 35 to form a second contact hole 350 exposing the side of the storage layer 34 away from the first electrode layer 33 and the extension portion 341, such as Fig. 6A (2) depositing a first metal material and planarizing it to form the second main connection structure 361 in the second contact hole 350, as shown in FIG. Figure 6B The material of the etching stop layer 50 can be silicon nitride (SiN).
[0046] In this embodiment, the top surface of the second main connection structure 361 is flush with the top surface of the second dielectric layer 35 .
[0047] like Figure 7 As shown, in this embodiment, after the step of forming the second main connection structure 361, the step further includes: depositing a second metal material and patterning it to form a metal structure 37 in one-to-one contact with the second main connection structure 361 on the surface of the second dielectric layer 35. The metal structure 37 is made of the same material as the first electrode layer 33 and is different from the material of the second main connection structure 361. The metal structure 37 serves as a lead-out structure or a pad.
[0048] In this embodiment, a first auxiliary connection structure 322 is formed while forming the first main connection structure 321. The first auxiliary connection structure 322 penetrates the first dielectric layer 31 and is spaced apart from the first main connection structure 321. A second auxiliary connection structure 362 is formed while forming the second main connection structure 361. The second auxiliary connection structure 362 penetrates the second dielectric layer 35 and contacts the first auxiliary connection structure 322. One of the metal structures 37 is also in contact with the adjacent second auxiliary connection structure 362. Figure 7 shown.
[0049] The memory cell of the three-dimensional memory prepared in this embodiment optimizes the upper and lower electrode layers into left and right electrode layers to realize the transformation of the traditional lateral memory cell (Cell) (such as Figure 1The storage unit 14 shown in the figure is optimized as a longitudinal storage unit (along the direction D2 shown in the figure). The effective area of a single storage unit is increased, and a smaller area (Footprint) of a single storage unit can be achieved to save the occupied area of the storage unit; the increase in the effective area of the device can improve the storage performance, optimize and improve the operating efficiency and reliability of the device. In addition, the arrangement of the longitudinal storage unit in this embodiment makes it possible to form a first main connection structure 321 (lower contact hole process) when forming the first main connection structure 321 (lower contact hole process). Even if the lower contact hole process causes a protrusion in the first main connection structure 321 in contact with the first electrode layer 33 (left electrode layer shown in the figure), it will not affect the deposition and phase change performance of the storage layer 34, thereby avoiding affecting the performance of the storage unit; and when forming the second main connection structure 361 (upper contact hole process) as the second electrode layer, there is no problem of etching through the storage layer 34, thereby further avoiding affecting the performance of the storage unit. In addition, the second main connection structure 361 serves as both the second electrode layer and the second main connection structure. Compared with Figure 1 In the conventional method, there are three dielectric layers and three contact holes (VIA) mask processes. This embodiment only requires two dielectric layers and two contact holes (VIA) mask processes, saving one contact hole mask process, which can effectively reduce production costs. This embodiment solves the problem in the prior art that as the semiconductor process shrinks, the area of the storage layer and the electrode layer of the storage unit becomes smaller, resulting in a reduction in the effective area of the storage layer and the electrode layer, thereby affecting the storage performance of the memory, and saves the mask process, which can effectively reduce production costs.
[0050] Based on the same inventive concept, the present invention also provides a three-dimensional memory prepared by the above method of the present invention.
[0051] See also Figure 3A to Figure 7 The three-dimensional memory described in this embodiment includes: a substrate 30, a first dielectric layer 31, a first main connection structure 321, a first electrode layer 33, a storage layer 34, a second dielectric layer 35 and a second main connection structure 361. The second main connection structure 361 serves as both a second electrode layer and a second main connection structure, and the first electrode layer, the storage layer and the second electrode layer constitute a storage unit of the three-dimensional memory.
[0052] In this embodiment, the second main connection structure 361 is made of the same material as the first main connection structure 321 , and is different from the material of the first electrode layer 33 .
[0053] Specifically, the first dielectric layer 31 covers the surface of the substrate 30. The material of the first dielectric layer 31 may be an oxide (OX) material, such as silicon oxide (SiO).
[0054] Specifically, the first main connection structure 321 penetrates the first dielectric layer 31 . The material of the first main connection structure 321 is metal tungsten. The top surface of the first main connection structure 321 is flush with the top surface of the first dielectric layer 31 .
[0055] Specifically, the first electrode layer 33 is formed on the surface of the first dielectric layer 31 and is in one-to-one contact with the first main connection structure 321. A plurality of first electrode layers 33 are arranged at intervals on the surface of the first dielectric layer 31. The material of the first electrode layer 33 is selected from one of aluminum, copper, or aluminum-copper alloy, preferably aluminum-copper alloy.
[0056] Specifically, the storage layer 34 covers a side wall of the first electrode layer 33 and has an extension portion 341 extending to the surface of the first dielectric layer 31. The material of the storage layer 34 is a ferroelectric material or a phase change material.
[0057] Specifically, the second dielectric layer 35 covers the first dielectric layer 31, all the first electrode layers 33 and all the storage layers 34. The material of the second dielectric layer 35 can be the same as that of the first dielectric layer 31, both are oxide (OX) materials, such as silicon oxide (SiO).
[0058] Specifically, the second main connection structure 361 penetrates the second dielectric layer 35 and contacts the side of the storage layer 34 away from the first electrode layer 33 and the extension portion 341. The material of the second main connection structure 361 can be metal tungsten. In the second direction D2, the height of the second main connection structure 361, which also serves as the second electrode layer, is greater than the height of the first electrode layer 33, so that the effective area of the electrode plate of the formed storage unit can be increased. The second main connection structure 361 and the first electrode layer 33 are arranged in pairs, and form a longitudinal (along the D2 direction shown in the figure) storage unit with the middle storage layer 34, which can save the occupied area of the storage unit and increase the effective area of the device.
[0059] In this embodiment, the material of the storage layer 34 is a ferroelectric material or a phase change material; the materials of the first dielectric layer 31 and the second dielectric layer 35 are both oxide materials; the material of the first main connection structure 321 is metal tungsten; the material of the first electrode layer 33 and the second main connection structure 361 is the same, and both are selected from one of aluminum, copper, or aluminum-copper alloy, preferably aluminum-copper alloy.
[0060] In this embodiment, a gate structure 39 is further formed on the surface of the substrate 30, the first dielectric layer 31 further covers the gate structure 39, and the first main connection structure 321 is disposed along the first direction D1 on both sides of the gate structure 39. The gate structure 39 includes a polysilicon gate 391, a gate oxide layer 392 located below the polysilicon gate 391, and a spacer 393 located on the sidewall of the polysilicon gate 391.
[0061] In this embodiment, the three-dimensional memory further includes: a first protective layer 38 covering the surface of the first electrode layer 33. The material of the first protective layer 38 may be nitride oxide, such as silicon oxynitride (SiON).
[0062] In this embodiment, the three-dimensional memory further includes: a metal structure 37; the metal structure 37 is formed on the surface of the second dielectric layer 35 and is in one-to-one contact with the second main connection structure 361. The metal structure 37 serves as a lead-out structure or a pad. The metal structure 37 is made of the same material as the first electrode layer 33, and is different from the material of the second main connection structure 361.
[0063] In this embodiment, the three-dimensional memory further includes: a first auxiliary connection structure 322, the first auxiliary connection structure 322 and the first main connection structure 321 are formed by the same process, the first auxiliary connection structure 322 penetrates the first dielectric layer 31 and is spaced apart from the first main connection structure 321. A second auxiliary connection structure 362, the second auxiliary connection structure 362 and the second main connection structure 361 are formed by the same process, the second auxiliary connection structure 362 penetrates the second dielectric layer 35 and contacts the first auxiliary connection structure 322. One of the metal structures 37 is also in contact with the adjacent second auxiliary connection structure 362, such as Figure 7 shown.
[0064] In the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.
[0065] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only include those elements, but also include other elements not clearly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, there is a sentence "also includes a ..." The elements limited do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.
[0066] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. It should be noted that a person skilled in the art may make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications shall also be regarded as the protection scope of the present invention.
Claims
1. A three-dimensional memory, characterized in that: include: substrate; A first dielectric layer, covering the surface of the substrate; A first main connection structure, penetrating the first dielectric layer; A first electrode layer, formed on a surface of the first dielectric layer and in one-to-one contact with the first main connection structure; a storage layer, covering a side wall of the first electrode layer and having an extension portion extending to a surface of the first dielectric layer; a second dielectric layer, covering the first dielectric layer, all the first electrode layers and all the storage layers; as well as a second main connection structure, penetrating the second dielectric layer and contacting a side of the storage layer away from the first electrode layer and the extension portion; The second main connection structure also serves as a second electrode layer, and the first electrode layer, the storage layer, and the second electrode layer constitute a storage unit of the three-dimensional memory.
2. The three-dimensional memory according to claim 1, characterized in that: The second main connection structure is made of the same material as the first main connection structure and is different from the first electrode layer.
3. The three-dimensional memory according to claim 1, characterized in that: The material of the storage layer is ferroelectric material or phase change material, the materials of the first dielectric layer and the second dielectric layer are both oxide materials, the materials of the first main connection structure and the second main connection structure are both metal tungsten, and the material of the first electrode layer is selected from aluminum, copper, or aluminum-copper alloy.
4. The three-dimensional memory according to claim 1, characterized in that: Also includes: The metal structure is formed on the surface of the second dielectric layer and is in one-to-one contact with the second main connection structure.
5. The three-dimensional memory according to claim 4, characterized in that: The metal structure is made of the same material as the first electrode layer, and is different from the second main connection structure.
6. The three-dimensional memory according to claim 4, characterized in that: Also includes: a first auxiliary connection structure, formed by the same process as the first main connection structure, the first auxiliary connection structure passing through the first dielectric layer and spaced apart from the first main connection structure; a second auxiliary connection structure, formed by the same process as the second main connection structure, the second auxiliary connection structure passing through the second dielectric layer and contacting the first auxiliary connection structure; One of the metal structures is also in contact with the adjacent second auxiliary connection structure.
7. A method for preparing a three-dimensional memory, characterized in that: The method comprises the following steps: Forming a semiconductor substrate, the semiconductor substrate comprising a substrate, a first dielectric layer covering a surface of the substrate, a first main connection structure penetrating the first dielectric layer, and a first electrode layer formed on a surface of the first dielectric layer and in one-to-one contact with the first main connection structure; forming a storage layer, wherein the storage layer covers a side wall of the first electrode layer and has an extension portion extending to a surface of the first dielectric layer; forming a second dielectric layer, wherein the second dielectric layer covers the first dielectric layer, all the first electrode layers and all the storage layers; as well as forming a second main connection structure, wherein the second main connection structure penetrates the second dielectric layer and contacts a side of the storage layer away from the first electrode layer and the extension portion; The second main connection structure also serves as a second electrode layer, and the first electrode layer, the storage layer, and the second electrode layer constitute a storage unit of the three-dimensional memory.
8. The method according to claim 7, characterized in that The second main connection structure is made of the same material as the first main connection structure and is different from the first electrode layer.
9. The method according to claim 7, characterized in that: The steps of forming a semiconductor substrate specifically include: Providing a substrate, wherein the first dielectric layer is formed on the surface of the substrate, and a first contact hole penetrating through the first dielectric layer is formed in the first dielectric layer; Filling the first contact hole with a first metal material to form the first main connection structure; A second metal material is deposited and patterned to form the first electrode layer on the surface of the first dielectric layer, which is in one-to-one contact with the first main connection structure.
10. The method according to claim 9, characterized in that The step of depositing and patterning the second metal material specifically includes: Depositing a second metal material layer on the surface of the first dielectric layer, and forming a patterned first protective layer on the surface of the second metal material layer; The second metal material layer is etched using the patterned first protective layer as a mask and the first dielectric layer as an etching stop layer to form the first electrode layer in one-to-one contact with the first main connection structure, and the first protective layer is retained and covers the surface of the first electrode layer.
11. The method according to claim 7, characterized in that The step of forming the storage layer specifically includes: Depositing a storage material to form a storage material layer covering the first dielectric layer and all of the first electrode layers; An anti-reflection material is deposited on the surface of the storage material layer and planarized to form a first anti-reflection layer, and a first photoresist structure is formed on the surface of the first anti-reflection layer, wherein the first photoresist structure has a side wall for shielding the first electrode layer and a shielding portion of the first dielectric layer adjacent to the side wall; etching is performed using the first photoresist structure as a mask to etch the remaining storage material layer to form the storage layer.
12. The method according to claim 7, characterized in that Before the step of forming the second dielectric layer, the method further comprises: forming an etch stop layer, wherein the etch stop layer covers the first dielectric layer, all the first electrode layers and all the storage layers, and the second dielectric layer covers the etch stop layer; The step of forming the second main connection structure specifically includes: Using the etching barrier layer as an etching stop layer, etching in the second dielectric layer to form a second contact hole exposing a side of the storage layer away from the first electrode layer and the extension portion; A first metal material is deposited and planarized to form the second main connection structure in the second contact hole, wherein the top surface of the second main connection structure is flush with the top surface of the second dielectric layer.
13. The method according to claim 7, characterized in that After the step of forming the second main connection structure, the method further comprises: A second metal material is deposited and patterned to form a metal structure on the surface of the second dielectric layer that is in one-to-one contact with the second main connection structure.
14. The method according to claim 13, characterized in that A first auxiliary connection structure is formed while the first main connection structure is formed, wherein the first auxiliary connection structure penetrates the first dielectric layer and is spaced apart from the first main connection structure; A second auxiliary connection structure is formed while forming the second main connection structure, wherein the second auxiliary connection structure penetrates the second dielectric layer and contacts the first auxiliary connection structure; One of the metal structures is also in contact with the adjacent second auxiliary connection structure.