Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention discloses a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device comprises a base body; a drift layer of the first conductivity type; a base layer of a second conductivity type; a trench; a first collector layer of a second conductivity type, wherein a side surface of the first collector layer away from the drift layer in a first direction at least partially constitutes a part of a second main surface; the surface of one side, far away from the drift layer in the first direction, of the second collector layer at least partially forms a part of the second main surface, the first collector layer is arranged on the outer side of the second collector layer in a surrounding mode, and the ion doping concentration of the second collector layer is larger than that of the first collector layer. Therefore, the self-regulation of the injection efficiency of the collector can be realized, so that the semiconductor device has better turn-off dv / dt consistency under different current working conditions, the turn-off loss is reduced, and the compromise between the forward conduction voltage drop and the turn-off loss is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] As a mainstream device in power electronics technology, IGBT (insulated gate bipolar transistor) has the advantages of low on-state voltage, fast switching speed, good thermal stability, simple driving circuit, etc. It is widely used in power electronics control fields such as energy, home appliances, industry, communications, aerospace, etc. Among them, the application of IGBT in PFC (power factor correction) circuit is a very common application scenario for IGBT, which improves energy efficiency, reduces line losses and reduces harmonic interference for power systems.

[0003] In the related art, when PFC is working, the semiconductor device IGBT has different current switching conditions, and has an obvious problem of poor turn-off dv / dt consistency. A small turn-off dv / dt will increase the turn-off loss, which will significantly increase the loss of the PFC application and increase the temperature rise, which is a severe test for the reliability of the device. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a semiconductor device that can achieve self-regulation of collector injection efficiency and has lower turn-off loss.

[0005] Another object of the present invention is to provide a method for manufacturing a semiconductor device.

[0006] According to an embodiment of the present invention, a semiconductor device comprises: a substrate, the substrate having a first main surface and a second main surface opposite to the first main surface, the first main surface and the second main surface being spaced apart in a first direction; a drift layer of a first conductive type, the drift layer being arranged on the substrate and located between the first main surface and the second main surface; a base layer of a second conductive type, the base layer being arranged on a side of the drift layer facing the first main surface, a surface of the base layer on a side away from the drift layer in a first direction constituting a part of the first main surface, the thickness of the base layer extending from the first main surface along the first direction toward the second main surface; a groove, the base layer penetrating from the first main surface in the direction of the groove thickness to reach the drift layer, the length direction of the groove extending in the second direction of the semiconductor device, the groove being multiple, and the multiple grooves being arranged in the first direction of the semiconductor device. The first collector layer is arranged at intervals in three directions, wherein the first direction, the second direction and the third direction are perpendicular to each other; a first collector layer of the second conductivity type, the first collector layer is arranged on the side of the drift layer facing the second main surface, and a surface of the first collector layer on the side away from the drift layer in the first direction at least partially constitutes a part of the second main surface, and a thickness of the first collector layer extends from the second main surface along the first direction toward the first main surface; a second collector layer of the second conductivity type, the second collector layer is arranged on the side of the drift layer facing the second main surface, and a surface of the second collector layer on the side away from the drift layer in the first direction at least partially constitutes a part of the second main surface, the first collector layer is arranged around the outside of the second collector layer, and the ion doping concentration of the second collector layer is greater than the ion doping concentration of the first collector layer.

[0007] Therefore, by arranging the first collector layer and the second collector layer, the surfaces of the first collector layer and the second collector layer on one side away from the drift layer both constitute a part of the second main surface, and the ion doping concentration of the second collector layer is greater than the ion doping concentration of the first collector layer. In this way, self-regulation of the collector injection efficiency can be achieved, so that the semiconductor device has better turn-off dv / dt consistency under different current conditions, reduces turn-off loss, and improves the compromise between forward conduction voltage drop and turn-off loss.

[0008] In some examples of the present invention, the ion doping concentration of the first collector layer is A, and A satisfies the relationship: 1×10 11 cm -3 <A<1×10 13 cm -3 , the ion doping concentration of the second collector layer is B, and B satisfies the relationship: 1×10 13 cm -3 <B<1×10 15 cm-3 .

[0009] In some examples of the present invention, a side of the second collector layer facing the drift layer is spaced apart from the drift layer.

[0010] In some examples of the present invention, there are a plurality of the second collector layers, and the plurality of the second collector layers are spaced apart in the third direction.

[0011] In some examples of the present invention, the distances between any two adjacent second collector layers in the plurality of second collector layers are equal.

[0012] In some examples of the present invention, the semiconductor device also includes: a collector metal layer, the collector metal layer is arranged on the second main surface, the total contact area between the multiple first collector layers and the collector metal layer is S1, the contact area between the second collector layer and the collector metal layer is S2, and S1 and S2 satisfy the relationship: S1>S2.

[0013] A method for manufacturing a semiconductor device according to an embodiment of the present invention is used to manufacture the semiconductor device described above, and the method for manufacturing a semiconductor device comprises the following steps: preparing a substrate, and injecting into the substrate a collector layer of a second conductivity type, a field stop layer of a first conductivity type, a drift layer of a first conductivity type, a carrier storage layer of a first conductivity type, and a base layer of a second conductivity type; etching a groove in the substrate; growing an oxide layer on the surface of the groove and the substrate; depositing polysilicon of a first conductivity type on the oxide layer, and etching the polysilicon; injecting a first conductivity type dopant on both sides of the base layer corresponding to the groove to form an emitter layer; depositing a dielectric layer on the surface of the oxide layer and the polysilicon, and etching contact holes on the dielectric layer; and injecting a second conductivity type dopant into the collector layer so that the collector layer includes a first collector layer and a second collector layer.

[0014] In some examples of the present invention, after the step of injecting a second conductive type dopant into the collector layer so that the collector layer includes a first collector layer and a second collector layer, the method for manufacturing the semiconductor device may further include: depositing an emitter metal layer on the first main surface and etching the emitter metal layer; depositing a passivation layer on the emitter metal layer and etching the passivation layer.

[0015] In some examples of the present invention, after the steps of depositing a passivation layer on the emitter metal layer and etching the passivation layer, the method for manufacturing a semiconductor device may further include: depositing a collector metal layer on the second main surface.

[0016] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 2 is a partial schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0020] Figure 3 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0021] Figure 4 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0022] Figure 5 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0023] Figure 6 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0024] Figure 7 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0025] Figure 8 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0026] Fig. 9 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0027] Fig.10 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0028] Fig.11 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0029] Fig.12 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention;

[0030] Fig.13 is a state diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

[0031] Reference numerals:

[0032] 100. semiconductor device; 110. insulated gate bipolar transistor region; 120. fast recovery diode region;

[0033] 10. substrate; 101. first main surface; 102. second main surface;

[0034] 11. drift layer; 12. base layer; 13. carrier storage layer; 14. field stop layer; 15. collector layer; 151. first collector layer; 152. second collector layer; 16. cathode layer; 17. emitter layer; 18. contact region;

[0035] 20. oxide layer; 30. polysilicon;

[0036] 40. dielectric layer; 41. contact hole;

[0037] 50. emitter metal layer; 60. collector metal layer;

[0038] 70. Groove. DETAILED DESCRIPTION

[0039] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0040] Reference below Figure 1-Figure 13 The semiconductor device according to the embodiment of the present invention is described, and the semiconductor device 100 may adopt a method for manufacturing the semiconductor device 100. The semiconductor device 100 includes but is not limited to an IGBT (Insulated Gate Bipolar Transistor), an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor), and the like.

[0041] In the following description, N and P represent the conductivity type of the semiconductor, and in the present invention, the first conductivity type is set to N type and the second conductivity type is set to P type. Also, the first direction, the second direction and the third direction are perpendicular to each other.

[0042] Combination Figure 1 and Figure 2 As shown, the semiconductor device 100 according to the present invention may mainly include: a substrate 10, a drift layer 11 of a first conductivity type, a base layer 12 of a second conductivity type, a trench 70, a first collector layer 151 of a second conductivity type, and a second collector layer 152 of a second conductivity type.

[0043] Specifically, the substrate 10 has a first main surface 101 and a second main surface 102 on the opposite side of the first main surface 101, and the first main surface 101 and the second main surface 102 are arranged at intervals in the first direction. The drift layer 11 is arranged on the substrate 10 and is located between the first main surface 101 and the second main surface 102, and the base layer 12 is arranged on the side of the drift layer 11 facing the first main surface 101, and the upper surface of the base layer 12 constitutes a part of the first main surface 101, and the thickness of the base layer 12 extends from the first main surface 101 toward the second main surface 102 along the first direction.

[0044] Furthermore, a groove 70 is provided in the substrate 10, and the groove 70 penetrates the base layer 12 from the first main surface 101 in the thickness direction to reach the drift layer 11, and the length direction of the groove 70 extends in the second direction of the semiconductor device 100. There are multiple grooves 70, and the multiple grooves 70 are arranged at intervals in the third direction of the semiconductor device 100. Among them, an oxide insulating layer and polysilicon 30 can be sequentially arranged in the groove 70, so that a gate can be formed at the groove 70, which is convenient for electrical connection with the gate pad.

[0045] The collector layer 15 is arranged on the side of the drift layer 11 facing the second main surface 102 . The surface of the collector layer 15 on the side away from the drift layer 11 in the first direction constitutes a part of the second main surface 102 . The thickness of the collector layer 15 extends from the second main surface 102 along the first direction toward the first main surface 101 .

[0046] Furthermore, the dielectric layer 40 is disposed on the first main surface 101, and the dielectric layer 40 can protect the first main surface 101. The emitter metal layer 50 is disposed on the side of the dielectric layer 40 away from the first main surface 101, and the emitter metal layer 50 at least partially passes through the dielectric layer 40 to contact the base layer 12, and the emitter metal layer 50 can serve as an emitter lead-out terminal. In addition, the second main surface 102 of the substrate 10 is also provided with a collector metal layer 60, and the collector metal layer 60 can serve as a collector lead-out terminal.

[0047] In this way, the basic structure of the semiconductor device 100 can be formed. The semiconductor device 100 has advantages such as low on-state voltage, high switching speed, good thermal stability, and a simple driving circuit.

[0048] The semiconductor device 100 can be applied to a PFC (power factor correction) circuit to improve energy efficiency, reduce line losses, and reduce harmonic interference for the power system. For PFC, a boost converter Boost topology is usually used to minimize the harmonics of the input current and keep the phase of the voltage and current consistent. The basic idea is to remove the filter capacitor after the 220V rectifier bridge stack, and then use a chopper circuit to convert the pulse current into a high frequency. Therefore, its waveform characteristics are that the current waveform is intermittent, and its envelope is the same as the voltage waveform, and the envelope and voltage waveform have the same phase. Among them, within a sinusoidal half-cycle waveform, the semiconductor device 100 has switching conditions with different current sizes.

[0049] In the prior art, under low current conditions, the semiconductor device has a small turn-off dv / dt, and under high current conditions, the semiconductor device has a large turn-off dv / dt. That is, the semiconductor device has an obvious problem of poor turn-off dv / dt consistency. A small turn-off dv / dt will increase the turn-off loss, and further significantly increase the loss of the PFC application as a whole, and aggravate the temperature rise, reducing reliability.

[0050] In this application, combined Figure 1 and Figure 2 As shown, the collector layer 15 may include: a first collector layer 151 and a second collector layer 152 .

[0051] The first collector layer 151 is disposed on the side of the drift layer 11 facing the second main surface 102, and the side surface of the first collector layer 151 in the first direction away from the drift layer 11 at least partially constitutes a part of the second main surface 102. The thickness of the first collector layer 151 extends from the second main surface 102 along the first direction toward the first main surface 101. In addition, the second collector layer 152 is disposed on the side of the drift layer 11 facing the second main surface 102, and the side surface of the second collector layer 152 in the first direction away from the drift layer 11 at least partially constitutes a part of the second main surface 102. In addition, the first collector layer 151 is disposed around the outside of the second collector layer 152, and the ion doping concentration of the second collector layer 152 is greater than the ion doping concentration of the first collector layer 151.

[0052] It can be understood that the first collector layer 151 and the second collector layer 152 together constitute the collector layer 15 of the semiconductor device 100, and since the side surface of the first collector layer 151 away from the drift layer 11 in the first direction at least partially constitutes a part of the second main surface 102, and the side surface of the second collector layer 152 away from the drift layer 11 in the first direction at least partially constitutes a part of the second main surface 102, the first collector layer 151 and the second collector layer 152 are both in contact with the collector metal layer 60.

[0053] By making the first collector layer 151 surround the outside of the second collector layer 152, and making the ion doping concentration of the second collector layer 152 greater than the ion doping concentration of the first collector layer 151, in the off state, on the one hand, under the condition of small current, the injection path is from the first collector layer 151 to the drift layer 11, and the number of minority carriers injected is determined by the doping concentration of the first collector layer 151, and its injection efficiency is low. On the other hand, under the condition of large current, the injection path is from the second collector layer 152 to the first collector layer 151 and then to the drift layer 11, and the number of minority carriers injected is determined by the doping concentration of the second collector layer 152, and its injection efficiency is high.

[0054] In this way, the collector injection efficiency can be self-regulated. The semiconductor device 100 has a lower minority carrier injection efficiency under low current conditions, because in the off state, the size of dv / dt is negatively correlated with the number of minority carriers in the drift layer 11, that is, the more minority carriers there are in the drift layer 11, the smaller the off dv / dt, thereby improving the off dv / dt under low current conditions, making the semiconductor device 100 have better off dv / dt consistency under different current conditions, reducing the off loss, and improving the compromise between the forward conduction voltage drop and the off loss, thereby reducing the overall loss of the PFC application and improving the overall temperature rise.

[0055] Therefore, by setting the first collector layer 151 and the second collector layer 152, the side surfaces of the first collector layer 151 and the second collector layer 152 away from the drift layer 11 both constitute a part of the second main surface 102, and the ion doping concentration of the second collector layer 152 is greater than the ion doping concentration of the first collector layer 151, so that self-regulation of the collector injection efficiency can be achieved, so that the semiconductor device 100 has better turn-off dv / dt consistency under different current conditions, reduces turn-off loss, and improves the compromise between forward conduction voltage drop and turn-off loss.

[0056] In some embodiments of the present invention, the ion doping concentration of the first collector layer 151 is A, and A satisfies the relationship: 1×10 11 cm -3 <A<1×10 13 cm -3 , the ion doping concentration of the second collector layer 152 is B, and B satisfies the relationship: 1×10 13 cm -3 <B<1×10 15 cm -3 .

[0057] In this way, the ion doping concentration of the first collector layer 151 and the ion doping concentration of the second collector layer 152 can be set within a reasonable range, respectively, which can not only ensure the normal operation of the first collector layer 151 and the second collector layer 152, that is, ensure the normal operation of the collector layer 15 as a whole and the basic function of the semiconductor device 100, but also avoid the ion doping concentration of the second collector layer 152 being too high, resulting in avalanche breakdown failure and the like, which may affect the working performance of the semiconductor device 100.

[0058] Combination Figure 1 and Figure 2 As shown, the side of the second collector layer 152 away from the drift layer 11 constitutes a part of the second main surface 102 , and the side of the second collector layer 152 facing the drift layer 11 is spaced apart from the drift layer 11 .

[0059] Specifically, the side of the second collector layer 152 away from the drift layer 11 constitutes a part of the second main surface 102, and the side of the second collector layer 152 facing the drift layer 11 is spaced apart from the drift layer 11, that is, the second collector layer 152 extends from the second main surface 102 toward the first main surface 101, and the thickness of the second collector layer 152 is less than the thickness of the first collector layer 151. In this way, in the first direction, at least part of the first collector layer 151 can exist between the second collector layer 152 and the drift layer 11, which can prevent the second collector layer 152 from extending to directly contact the drift layer 11, and prevent the second collector layer 152 from directly separating the first collector layer 151 in the third direction, resulting in the first collector layer 151 and the second collector layer 152 being staggered in the third direction.

[0060] Specifically, if the second collector layer 152 directly separates the first collector layer 151 in the third direction, so that the first collector layer 151 and the second collector layer 152 are staggered in the third direction, and the second collector layer 152 also extends to directly contact the drift layer 11, then when the semiconductor device 100 is turned off, under the influence of the on-state voltage drop, whether it is a large current operating condition or a small current operating condition, the injection path is from the second collector layer 152 to the drift layer 11, and self-regulation of the collector injection efficiency cannot be achieved.

[0061] By spacing the second collector layer 152 on the side facing the drift layer 11 away from the drift layer 11 , it is possible to ensure that the injection paths from the collector layer 15 to the drift layer 11 are different under different current conditions, thereby ensuring different injection efficiencies and achieving self-regulation of the collector injection efficiency.

[0062] It should be noted that in some embodiments, in the first direction, a field stop layer 14 is further provided between the drift layer 11 and the collector layer 15. In this case, it is necessary to control the second collector layer 152 to be spaced apart from the field stop layer 14 on the side facing the drift layer 11, which will not be elaborated here.

[0063] Combination Figure 1 and Figure 2 As shown, there are multiple second collector layers 152, and the multiple second collector layers 152 are arranged at intervals in the third direction. Specifically, different from setting a continuous large-sized second collector layer, the present application sets multiple second collector layers 152, and the multiple second collector layers 152 are arranged at intervals in the third direction, so that the structure of the collector layer 15 can be more evenly distributed in the third direction, and on the premise of realizing self-regulation of the collector injection efficiency, the current uniformity of the semiconductor device 100 is improved, and the electric field distribution in the semiconductor device 100 is optimized, thereby improving the working performance of the semiconductor device 100.

[0064] Furthermore, combined with Figure 1 and Figure 2 As shown, the spacing between any two adjacent second collector layers 152 in the plurality of second collector layers 152 is equal. Specifically, by setting the spacing between any two adjacent second collector layers 152 in the plurality of second collector layers 152 to be equal, the distribution of the plurality of second collector layers 152 can be made more uniform and reasonable, thereby improving the consistency and symmetry of the collector layer 15, further improving the current balancing of the semiconductor device 100, and further optimizing the electric field distribution in the semiconductor device 100, thereby improving the working performance of the semiconductor device 100.

[0065] Combination Figure 1 and Figure 2 As shown, the total contact area between the plurality of first collector layers 151 and the collector metal layer 60 is S1, the contact area between the second collector layer 152 and the collector metal layer 60 is S2, and S1 and S2 satisfy the relationship: S1>S2.

[0066] Specifically, the collector layer 15 injects holes into the drift layer 11, and an electron current is required to flow from the first main surface 101 through the drift layer 11 to the collector layer 15 to generate a voltage drop to turn on the PN junction. The PN junction formed by the first collector layer 151 and the drift layer 11 is defined as the first junction, and the PN junction formed by the second collector layer 152 and the drift layer 11 is defined as the second junction. Due to the difference in ion doping concentration, the built-in potential of the first junction is different from the built-in potential of the second junction, and the built-in potential of the second junction is larger.

[0067] Since the contact area between the collector layer 15 and the drift layer 11 will affect the turn-on voltage drop of the PN junction between the collector layer 15 and the drift layer 11, by setting the total contact area of ​​the multiple second collector layers 152 and the collector metal layer 60 to be smaller than the contact area between the first collector layer 151 and the collector metal layer 60, electrons can be more inclined to flow to the first collector layer 151, thereby ensuring that only the first junction is turned on under low current conditions, that is, it can ensure that the injection path under low current conditions is from the first collector layer 151 to the drift layer 11, so that the semiconductor device 100 has a lower minority carrier injection efficiency under low current conditions.

[0068] In addition, the contact area between the first collector layer 151 and the second collector layer 152 is defined as the third junction. Since the third junction is short-circuited on the second main surface 102, the second junction will only be opened when the voltage at the second junction exceeds the voltage at the first junction, that is, the voltage drop caused by the electron current flowing along the drift layer 11 to the second collector layer 152 when flowing through the first collector layer 151 is greater than the thermal voltage. This ensures that the second collector layer 152 can effectively inject holes into the drift layer 11 only under high current conditions, thereby achieving high injection efficiency.

[0069] In this way, the self-regulation of the collector injection efficiency can be ensured, so that the semiconductor device 100 has better turn-off dv / dt consistency under different current conditions, reduces turn-off loss, and improves the trade-off between forward conduction voltage drop and turn-off loss.

[0070] In some embodiments of the present invention, Figure 1 As shown, the semiconductor device 100 is an IGBT, and the first collector layer 151 and the second collector layer 152 both correspond to the active region of the semiconductor device 100 , which will not be described in detail herein.

[0071] In other embodiments of the present invention, Figure 2 As shown, the semiconductor device 100 is an RC-IGBT, and the semiconductor device 100 has a fast recovery diode region 120 and an insulated gate bipolar transistor region 110. Specifically, the semiconductor device 100 may further include a cathode layer 16 of the first conductivity type, the first collector layer 151 and the second collector layer 152 both correspond to the insulated gate bipolar transistor region 110, the cathode layer 16 is arranged on the side of the drift layer 11 facing the second main surface 102 and corresponds to the fast recovery diode region 120, the surface of the cathode layer 16 on one side away from the drift layer 11 in the first direction constitutes a part of the second main surface 102, and the thickness of the cathode layer 16 extends from the second main surface 102 along the first direction toward the first main surface 101.

[0072] In this way, the IGBT region 110 can realize forward conduction of the semiconductor device 100 , and the fast recovery diode region 120 can realize reverse conduction of the semiconductor device 100 , so that the semiconductor device 100 has both forward conduction and reverse conduction characteristics.

[0073] Furthermore, by making the second collector layer 152 correspond to the insulated gate bipolar transistor region 110 instead of the fast recovery diode region 120, self-regulation of the collector injection efficiency of the insulated gate bipolar transistor region 110 can be achieved without affecting the normal operation of the fast recovery diode region 120, thereby further improving the operating performance of the semiconductor device 100.

[0074] Combination Figure 3-Figure 13 As shown, the method for manufacturing the semiconductor device 100 according to the present invention can be applied to the manufacturing of the semiconductor device 100 described above.

[0075] Combination Figure 3-Figure 12 As shown, the manufacturing method of the semiconductor device 100 may mainly include the following steps: preparing a substrate 10, implanting a collector layer 15 of a second conductivity type, a field stop layer 14 of a first conductivity type, a drift layer 11 of a first conductivity type, a carrier storage layer 13 of a first conductivity type, and a base layer 12 of a second conductivity type into the substrate 10; etching a groove 70 in the substrate 10; growing an oxide layer 20 on the surface of the groove 70 and the substrate 10; depositing polysilicon 30 of a first conductivity type on the oxide layer 20, and etching the polysilicon 30; implanting a first conductivity type dopant on both sides of the base layer 12 corresponding to the groove 70 to form an emitter layer 17; depositing a dielectric layer 40 on the surface of the oxide layer 20 and the polysilicon 30, and etching a contact hole 41 in the dielectric layer 40; implanting a second conductivity type dopant into the collector layer 15, so that the collector layer 15 includes a first collector layer 151 and a second collector layer 152.

[0076] Specifically, when manufacturing the semiconductor device 100, a substrate 10 can be provided first, and the substrate 10 has a first main surface 101 and a second main surface 102. Different concentrations of dopants of the first conductive type and different concentrations of dopants of the second conductive type are sequentially injected into the substrate 10 to form a collector layer 15 of the second conductive type, a field stop layer 14 of the first conductive type, a drift layer 11 of the first conductive type, a carrier storage layer 13 of the first conductive type, and a base layer 12 of the second conductive type, which are arranged in sequence.

[0077] Then, a groove 70 is etched in the substrate 10, so that the thickness direction of the groove 70 penetrates the base layer 12 from the first main surface 101 along the first direction to reach the drift layer 11, and the length direction of the groove 70 extends in the second direction of the semiconductor device 100, and the rounding process is completed, and the oxide layer 20 is grown on the surface of the substrate 10 and the groove 70. Then, the polysilicon 30 is deposited and etched so that the polysilicon 30 is only located in the groove 70.

[0078] Then, the first conductive type dopant is implanted on both sides of the base layer 12 corresponding to the trench 70 to form an emitter layer 17 . The emitter layer 17 is used to be electrically connected to the emitter metal layer 50 later.

[0079] Then, a dielectric layer 40 is deposited on the surface of the oxide layer 20 and the polysilicon 30. The dielectric layer 40 can protect the oxide layer 20 and the polysilicon 30, thereby protecting the first main surface 101 of the substrate 10 and reducing the risk of damage to the semiconductor device 100. A contact hole 41 is etched on the dielectric layer 40. In addition, a second conductive type dopant can be implanted into the base layer 12 at a position below the contact hole 41 to form a contact region 18.

[0080] Furthermore, on the side of the collector layer 15 away from the first main surface 101 , a second conductive type dopant is implanted with a smaller implantation energy so that the collector layer 15 includes a first collector layer 151 and a second collector layer 152 , and the ion doping concentration of the second collector layer 152 is higher than the ion doping concentration of the first collector layer 151 .

[0081] Combination Figure 3 and Fig.13 As shown, after the step of injecting a second conductive type dopant into the collector layer 15 so that the collector layer 15 includes a first collector layer 151 and a second collector layer 152, the manufacturing method of the semiconductor device 100 may further include the following steps: depositing an emitter metal layer 50 on the first main surface 101 and etching the emitter metal layer 50; depositing a passivation layer on the emitter metal layer 50 and etching the passivation layer.

[0082] Specifically, after the step of injecting the second conductive type dopant into the collector layer 15 so that the collector layer 15 includes the first collector layer 151 and the second collector layer 152, the emitter metal layer 50 can be provided on the upper surface of the dielectric layer 40 and at the contact hole 41, so that the emitter metal layer 50 can be conveniently contacted with the source layer through the contact hole 41 to ensure the normal operation of the semiconductor device 100. It should be noted that, considering the small size of the contact hole 41, the tungsten plug and Ti / TiN can be injected into the contact hole 41, and then the metal is deposited on the dielectric layer 40 to form the emitter metal layer 50.

[0083] Then, a passivation layer is deposited on the emitter metal layer 50 and etched. The passivation layer can protect the emitter metal layer 50 , thereby completing the relevant manufacturing processes of the semiconductor device 100 on the first main surface.

[0084] Combination Figure 3 and Fig.13 As shown, after a passivation layer is deposited on the emitter metal layer 50 and the passivation layer is etched, a collector metal layer 60 is deposited on the second main surface 102 . Then, the collector metal layer 60 is deposited on the second main surface 102 .

[0085] In this way, the manufacturing of the semiconductor device 100 can be completed. It can be understood that the manufacturing of the semiconductor device 100 can also be compatible with the existing process, and only one step is added. The manufacturing method of the semiconductor device 100 is simple and convenient.

[0086] It should be noted that other structures and operations of the semiconductor device according to the embodiment of the present invention are known to those skilled in the art and will not be described in detail here.

[0087] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0088] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0089] Although embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A substrate having a first main surface and a second main surface opposite to the first main surface, wherein the first main surface and the second main surface are spaced apart in a first direction; A drift layer of a first conductivity type, the drift layer being disposed on the substrate and located between the first main surface and the second main surface; A base layer of a second conductivity type, the base layer being arranged on a side of the drift layer facing the first main surface, a surface of the base layer on a side away from the drift layer in a first direction constituting a part of the first main surface, and the base layer extending from the first main surface along a first direction toward the second main surface; A groove, wherein the groove penetrates the base layer from the first main surface to the drift layer in a thickness direction, and the length direction of the groove extends in a second direction of the semiconductor device. There are a plurality of grooves, and the plurality of grooves are arranged at intervals in a third direction of the semiconductor device, wherein the first direction, the second direction and the third direction are perpendicular to each other; a first collector layer of a second conductivity type, the first collector layer being arranged on a side of the drift layer facing the second main surface, a surface of the first collector layer on a side away from the drift layer in a first direction at least partially constituting a part of the second main surface, and a thickness of the first collector layer extending from the second main surface along the first direction toward the first main surface; A second collector layer of a second conductivity type, wherein the second collector layer is arranged on a side of the drift layer facing the second main surface, a surface of the second collector layer in a first direction away from the drift layer at least partially constitutes a part of the second main surface, the first collector layer is arranged around the outside of the second collector layer, and the ion doping concentration of the second collector layer is greater than the ion doping concentration of the first collector layer.

2. The semiconductor device according to claim 1, wherein: The ion doping concentration of the first collector layer is A, and A satisfies the relationship: 1×10 11 cm -3 <A<1×10 13 cm -3 , the ion doping concentration of the second collector layer is B, and B satisfies the relationship: 1×10 13 cm -3 <B<1×10 15 cm -3 .

3. The semiconductor device according to claim 1, wherein: The second collector layer is spaced apart from the drift layer at a side facing the drift layer.

4. The semiconductor device according to claim 1, wherein: There are a plurality of the second collector layers, and the plurality of the second collector layers are spaced apart in the third direction.

5. The semiconductor device according to claim 4, wherein: The distances between any two adjacent second collector layers in the plurality of second collector layers are equal.

6. The semiconductor device according to claim 4, wherein: Also includes: The collector metal layer is arranged on the second main surface, the total contact area between the first collector layers and the collector metal layer is S1, the contact area between the second collector layer and the collector metal layer is S2, and S1 and S2 satisfy the relationship: S1>S2.

7. The semiconductor device according to claim 1, wherein: Also includes: A cathode layer of a first conductive type, the semiconductor device has a fast recovery diode region and an insulated gate bipolar transistor region, the first collector layer and the second collector layer both correspond to the insulated gate bipolar transistor region, the cathode layer is arranged on a side of the drift layer facing the second main surface and corresponds to the fast recovery diode region, a surface of the cathode layer on one side away from the drift layer in a first direction constitutes a part of the second main surface, and the thickness of the cathode layer extends from the second main surface along the first direction toward the first main surface.

8. A method for manufacturing a semiconductor device, applicable to the semiconductor device according to any one of claims 1 to 7, characterized in that: The following steps are involved: Prepare a substrate, and implant into the substrate a collector layer of the second conductivity type, a field stop layer of the first conductivity type, a drift layer of the first conductivity type, a carrier storage layer of the first conductivity type, and a base layer of the second conductivity type; etching a groove in the substrate; growing an oxide layer on the surface of the groove and the substrate; Depositing polysilicon of a first conductivity type on the oxide layer, and etching the polysilicon; Implanting a first conductive type dopant on both sides of the base layer corresponding to the trench to form an emission layer; Depositing a dielectric layer on the surfaces of the oxide layer and the polysilicon, and etching contact holes on the dielectric layer; A second conductive type dopant is implanted into the collector layer, so that the collector layer includes a first collector layer and a second collector layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: After the step of injecting the second conductive type dopant into the collector layer so that the collector layer includes the first collector layer and the second collector layer, the method may further include: Depositing an emitter metal layer on the first main surface, and etching the emitter metal layer; A passivation layer is deposited on the emitter metal layer, and the passivation layer is etched.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: After the step of depositing a passivation layer on the emitter metal layer and etching the passivation layer, the method may further include: A collector metal layer is deposited on the second major surface.

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