Transistor preparation method and electronic equipment
During the preparation process of the vertical gate fully surround transistor, the silicon layer is protected by masks and isolation materials to avoid metal contamination, solve the problem of source/drain and gate short circuits, and ensure the normal preparation of the transistor.
Patent Information
- Application Number
- CN202310827223.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-06
- Publication Date
- 2025-01-10
AI Technical Summary
During the deposition of the vertical gate fully surrounds the metal gate of the transistor, the source/drain is prone to metal contamination, resulting in possible short circuit problems.
By stacking the first silicon layer, the silicon germanium layer and the second silicon layer in sequence on the silicon substrate, and forming a plurality of rows of first masks in the first direction, covering the first isolation material after etching, protecting the second silicon layer, Avoid metal contamination and fill the metal material in the plurality of first grooves, annealing to form a plurality of first silicon columns in the first direction, and then forming a plurality of rows of second columns in the second direction on the plurality of first silicon columns The gate material is etched and deposited to form a plurality of second silicon columns.
It effectively prevents the source/drain from being contaminated by metal, avoids short circuits between the source/drain and gate, and ensures the normal preparation process of the transistor.
Smart Images
Figure CN119300382A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for manufacturing a transistor and an electronic device. Background Art
[0002] The vertical gate-all-around (VGAA) transistor is a new type of semiconductor device. Compared with the planar GAA transistor, the vertical GAA transistor (VGAA) has a small projected area and an unlimited channel length.
[0003] In the related art, during the process of depositing the metal gate of the VGAA transistor, the exposed source / drain is easily contaminated with metal and is difficult to remove, which may cause a short circuit between the source / drain and the metal gate. Summary of the invention
[0004] The embodiment of the present application provides a method for manufacturing a transistor and an electronic device, which effectively prevents the source / drain of the transistor from being contaminated by metal during the manufacturing process. The technical solution is as follows:
[0005] In one aspect, a method for preparing a transistor is provided, the method comprising:
[0006] A first silicon layer (301), a silicon germanium layer (302) and a second silicon layer (303) are sequentially stacked on a silicon substrate (300), wherein the first silicon layer (301) is in contact with the silicon substrate (300); a plurality of columns of first masks (304) are formed on the second silicon layer (303) along a first direction; the second silicon layer (303) is etched according to the plurality of columns of first masks (304), and a first isolation material (305) is covered on the surfaces of the etched second silicon layer (303) and the plurality of columns of first masks (304);
[0007] Etching the silicon substrate (300), the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to the multiple columns of first masks (304) to form a plurality of first grooves (306); filling the plurality of first grooves (306) with metal material and annealing to form a plurality of first silicon pillars (307) along the first direction;
[0008] Forming a plurality of columns of second masks (308) along a second direction on the plurality of first silicon pillars (307); etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to the plurality of columns of second masks (308); continuing to etch the silicon germanium layer (302) based on the grooves obtained by etching; epitaxially growing silicon in a partially etched area of the silicon germanium layer (302), and depositing a gate material in a remaining etched area of the silicon germanium layer (302) to form a plurality of second silicon pillars (309), wherein the plurality of second silicon pillars (309) are distributed in an array along the first direction and the second direction;
[0009] The first isolation material (305) covered by the plurality of second silicon pillars (309) is etched.
[0010] In one aspect, an electronic device is provided, wherein the electronic device includes a logic device, wherein the logic device includes a transistor manufactured according to any of the above-mentioned methods for manufacturing a transistor.
[0011] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:
[0012] By covering the surface of the second silicon layer after etching according to the first mask with the first isolation material, the second silicon layer is protected, and possible metal contamination of the second silicon layer during the subsequent deposition of gate material is avoided, thereby avoiding a short circuit between the source / drain and the gate. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0014] Figure 1 is a schematic diagram of a VGAA transistor provided by one or more exemplary embodiments of the present application;
[0015] Figure 2 is a flow chart of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0016] Figure 3 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0017] Figure 4 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0018] Figure 5is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0019] Figure 6 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0020] Figure 7 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0021] Figure 8 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0022] Fig. 9 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0023] Fig.10 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0024] Fig.11 is a flow chart of a method for preparing a transistor provided by one or more exemplary embodiments of the present application;
[0025] Fig.12 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0026] Fig.13 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0027] Fig.14 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0028] Fig.15 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0029] Fig.16 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0030] Fig.17 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0031] Fig.18 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0032] Fig.19is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0033] Fig. 20 is a schematic diagram of relevant steps in a preparation process provided by one or more exemplary embodiments of the present application;
[0034] Fig.21 is a three-dimensional diagram of a VGAA transistor provided by one or more exemplary embodiments of the present application;
[0035] Fig. 22 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0036] Fig.23 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0037] Fig.24 is a schematic diagram of a process for forming a stacked structure provided by one or more exemplary embodiments of the present application;
[0038] Fig.25 is a schematic diagram of a formation process of a stacking structure provided by another one or more exemplary embodiments of the present application;
[0039] Fig.26 is a schematic diagram of a formation process of a stacking structure provided by another one or more exemplary embodiments of the present application;
[0040] Fig. 27 It is a schematic diagram of a formation process of a stacking structure provided by one or more other exemplary embodiments of the present application. DETAILED DESCRIPTION
[0041] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0042] In an embodiment of the present application, a method for preparing a transistor is provided. Optionally, the method for preparing the transistor is mainly applied in a process for preparing a VGAA transistor.
[0043] First, the structure of the VGAA transistor is introduced. Figure 1 As shown, the transistor array 100 includes a plurality of transistor cells 110. Each transistor cell 110 includes a bit line (BL) 111, a word line (WL) 112, a source / drain 113, and a gate 114.
[0044] Among them, multiple transistor units 110 in the same column of the transistor array 100 are connected by coupling with the extended bit line 111; multiple transistor units 110 in the same row of the transistor array 100 are connected by coupling with the extended word line 112.
[0045] The word line 112 is connected to the gate 114 and serves as a gate line to turn on the transistor unit 110 . The bit line 111 is connected to the source / drain 113 and serves as a data signal writing line. The word line 112 surrounds the gate 114 .
[0046] Combined with the above introduction to VGAA transistors, Figure 2 is a flow chart of a method for preparing a VGAA transistor provided by an exemplary embodiment of the present application, such as Figure 2 As shown, the method includes the following steps.
[0047] Step 201, stacking a first silicon layer, a silicon germanium layer, and a second silicon layer in sequence on a silicon substrate;
[0048] Combined with reference Figure 3 , Figure 3 The diagram shows a first silicon layer 301 , a silicon germanium layer 302 , and a second silicon layer 303 stacked in sequence on a silicon substrate 300 . The first silicon layer 301 is in contact with the silicon substrate 300 .
[0049] Step 202, forming a plurality of columns of first masks along a first direction on the second silicon layer;
[0050] A plurality of columns of first masks are formed along a first direction on the second silicon layer 303. The first direction is a bit line direction. Optionally, the mask material is also called a photoresist material, a photoresist, and the like.
[0051] Step 203, etching the second silicon layer according to the multiple columns of first masks, and covering the surfaces of the etched second silicon layer and the multiple first masks with a first isolation material;
[0052] Combined with reference Figure 4 , Figure 4 A schematic diagram of a three-dimensional structure obtained by etching the second silicon layer 303 according to multiple columns of first masks 304 is shown. Figure 4 It is shown that the areas in the second silicon layer 303 not covered by the multiple columns of first masks 304 will be removed by etching. Figure 4 Part (A) shows a three-dimensional schematic diagram of the three-dimensional structure obtained after etching. Figure 4Part (B) shows a two-dimensional plane view of the three-dimensional structure observed along the first direction. In one embodiment, the second silicon layer 303 is etched using a SADP (Self-Aligned Double Patterning) process.
[0053] Combined with reference Figure 5 , Figure 5 A schematic diagram of a three-dimensional structure obtained by covering the surfaces of the second silicon layer 303 and the plurality of first masks 304 with the first isolation material 305 after etching is shown. Figure 5 Part (A) shows a three-dimensional schematic diagram of the stereostructure. Figure 5 Part (B) shows a two-dimensional plane view obtained by observing the three-dimensional structure along the first direction. In one embodiment, the first isolation material 305 is nitride. Optionally, the first isolation material 305 is silicon nitride.
[0054] In one embodiment, the first isolation material 305 is covered on the surfaces of the etched second silicon layer 303 and the plurality of first masks 304 by an ALD (Atomic Layer Deposition) process.
[0055] Step 204, etching the silicon substrate, the first silicon layer, the silicon germanium layer and the second silicon layer according to the first masks in multiple columns to form a plurality of first grooves;
[0056] Combined with reference Figure 6 , Figure 6 It shows a plurality of first grooves 306 formed after etching the silicon substrate 300 , the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 according to a plurality of columns of first masks 304 .
[0057] Step 205, filling a plurality of first grooves with metal material and annealing to form a plurality of first silicon pillars along a first direction;
[0058] Combined with reference Figure 7 , Figure 7 A plurality of first silicon pillars 307 along a first direction are shown. After the metal material is filled in the plurality of first grooves 306 and annealed, the metal material will diffuse to the silicon substrate portion included in the plurality of first silicon pillars 307. Figure 7 Part (A) shows a three-dimensional diagram of the three-dimensional structure of the plurality of first silicon pillars 307 . Figure 7 Part (B) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the first direction.
[0059] Step 206, forming a plurality of columns of second masks along a second direction on the plurality of first silicon pillars; etching the first silicon layer, the silicon germanium layer, and the second silicon layer according to the plurality of columns of second masks;
[0060] Optionally, the second direction is a word line direction. Figure 8 , Figure 8 A plurality of columns of second masks 308 deposited along a second direction on the plurality of first silicon pillars 307 are shown. Figure 8 Part (A) shows a three-dimensional image of a three-dimensional structure obtained by depositing multiple rows of second masks 308 . Figure 8 Part (B) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the first direction. Figure 8 Part (C) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
[0061] Step 207, based on the grooves obtained by etching, continue etching the silicon germanium layer;
[0062] In one embodiment, based on the etching operation performed in step 206 , an etched groove is obtained, and the silicon germanium layer 302 is further etched based on the groove.
[0063] Step 208, epitaxially growing silicon in the partially etched regions of the silicon germanium layer, and depositing gate material in the remaining etched regions of the silicon germanium layer to form a plurality of second silicon pillars;
[0064] In one embodiment, silicon is epitaxially grown in the partially etched area of the silicon germanium layer 302, and gate material is deposited in the remaining unetched area to form a plurality of second silicon pillars. The plurality of second silicon pillars are arrayed along the first direction and the second direction. Optionally, the gate material includes a gate oxide layer material, a high-K material, and a gate metal layer material. Optionally, the gate material is deposited in the gaps in the middle and upper parts of the plurality of second silicon pillars by an ALD process.
[0065] Combined with reference Fig. 9 , Fig. 9 A plurality of second silicon pillars 309 resulting from epitaxial silicon and metal gate material deposition operations are shown. Fig. 9 Part (A) shows a perspective view of a plurality of second silicon pillars 309 . Fig. 9 Part (B) shows a two-dimensional image of the corresponding three-dimensional structure observed along the first direction. Fig. 9 Part (C) shows a two-dimensional image of the corresponding three-dimensional structure observed along the second direction.
[0066] Step 209 , etching the first isolation material covered by the plurality of second silicon pillars.
[0067] Combined with reference Fig.10 , Fig.10 A plurality of second silicon pillars 309 are shown after etching of the first isolation material 305 is performed. Fig.10 Part (A) of FIG. 1 shows a perspective view of the plurality of second silicon pillars 309 after etching the first isolation material. Fig.10Part (B) of FIG. 1 shows a two-dimensional image of the plurality of second silicon pillars 309 observed along the first direction. Fig.10 Part (C) of FIG. 1 shows a two-dimensional image of a plurality of second silicon pillars 309 observed along the second direction. Fig. 9 and Fig.10 , it can be found that the first isolation material 305 has been removed.
[0068] In summary, by covering the surface of the second silicon layer 303 etched according to the first mask 304 with the first isolation material 305, the second silicon layer 303 is protected, and possible metal contamination of the second silicon layer 303 during the subsequent metal deposition process is avoided, thereby avoiding a short circuit between the source / drain and the gate.
[0069] Fig.11 A flowchart of a method for preparing a transistor provided by an exemplary embodiment of the present application is shown, the method comprising:
[0070] Step 1101, stacking a first silicon layer, a silicon germanium layer, and a second silicon layer in sequence on a silicon substrate;
[0071] Combined with reference Fig.12 , Fig.12 Part (A) shows a three-dimensional structure in which a first silicon layer 301, a silicon germanium layer 302 and a second silicon layer 303 are sequentially stacked on a silicon substrate 300. The first silicon layer 301 is in contact with the silicon substrate 300.
[0072] Step 1102, forming a plurality of columns of first masks along a first direction on the second silicon layer;
[0073] Combined with reference Fig.12 , Fig.12 Part (B1) shows a plurality of columns of first masks 304 deposited along a first direction on the second silicon layer 303. Optionally, the first direction is a bit line direction. Fig.12 Part (B2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the first direction.
[0074] Step 1103, etching the second silicon layer according to the multiple columns of first masks, and covering the surfaces of the etched second silicon layer and the multiple first masks with a first isolation material;
[0075] Fig.12 Part (B1) also shows a three-dimensional diagram of a three-dimensional structure obtained by performing an etching operation on the second silicon layer 303 according to multiple columns of first masks 304. Fig.12 Part (B2) also shows a two-dimensional image of the three-dimensional structure obtained by etching the second silicon layer 303 observed along the first direction.
[0076] Fig.12Part (C1) shows that the first isolation material 305 covers the surface of the etched second silicon layer 303 and the plurality of first masks 304. In one embodiment, the first isolation material 305 is nitride. Alternatively, the first isolation material 305 is silicon nitride. Fig.12 Part (C2) also shows a two-dimensional image of the corresponding three-dimensional structure observed along the first direction.
[0077] In one embodiment, the first isolation material 305 is covered on the surfaces of the etched second silicon layer 303 and the plurality of first masks 304 by an ALD (Atomic Layer Deposition) process.
[0078] Step 1104, etching the first silicon layer, the silicon germanium layer, and the second silicon layer according to the first mask in multiple columns;
[0079] Fig.13 Part (A1) of FIG. 1 shows a three-dimensional schematic diagram after etching the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 using multiple columns of first masks 304 . Fig.13 Part (A2) of FIG. 3 shows a two-dimensional plan view after etching the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 as viewed along the first direction.
[0080] It can be understood that after the etching operation in step 1104 is performed, the bit line pattern of the VGAA transistor can be observed along the first direction.
[0081] Step 1105, covering the surfaces of the etched first silicon layer, silicon germanium layer and second silicon layer with a second isolation material;
[0082] Combined with reference Fig.13 , Fig.13 Part (B1) of FIG. 3 shows a perspective schematic diagram of the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303 after etching, and the surfaces are covered with the second isolation material 310. In one embodiment, the second isolation material is nitride. Optionally, the second isolation material is silicon nitride. Fig.13 Part (B2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the first direction.
[0083] In one embodiment, the surfaces of the etched first silicon layer 301 , silicon germanium layer 302 , and second silicon layer 303 are covered with the second isolation material 310 by an ALD (Atomic Layer Deposition) process.
[0084] Step 1106, continue etching the silicon substrate to form a plurality of first grooves;
[0085] Combined with reference Fig.13 , Fig.13 The portion (C1) of FIG. 3 shows a plurality of first grooves 306 . In one embodiment, the silicon substrate 300 is etched continuously along the vertical direction of the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 , and then lateral etching is performed to form a plurality of first grooves 306 . Fig.13 Part (C2) shows a plurality of first grooves 306 observed along the first direction.
[0086] In one embodiment, the silicon substrate 300 is continuously etched in the plurality of first recesses 306 by a wet process to form the plurality of first recesses 306 .
[0087] Step 1107, filling a plurality of first grooves with metal material and etching;
[0088] Combined with reference Fig.13 and Fig.14 , Fig.14 Part (A1) shows a perspective view of a plurality of first grooves 306 filled with metal material. Fig.14 Part (A2) shows a two-dimensional plane view of the corresponding three-dimensional structure observed along the first direction. In one embodiment, the metal material is tungsten.
[0089] Combined with reference Fig.14 , Fig.14 Part (B1) shows the three-dimensional structure after the metal material in the plurality of first grooves 306 is etched. Fig.14 Part (B2) of FIG. 3 shows a two-dimensional plan view of the metal material in the plurality of first grooves 306 after being etched, as observed along the first direction. It can be found that the upper surface of the etched metal material is higher than the lower surface of the second isolation material 310. The second isolation material 310 protects the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 from being contaminated by the filled metal, thereby preventing a short circuit.
[0090] Step 1108, performing an annealing operation on the metal material in the plurality of first grooves;
[0091] Combined with reference Fig.14 , Fig.14 Part (C1) shows the three-dimensional structure after the annealing operation is performed on the metal material in the plurality of first grooves 306 . Fig.14 Part (C2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the first direction. The purpose of the annealing operation is to diffuse the metal material into the silicon substrate at the bottom of the first silicon column to cover the bottom of the first silicon column with silicide, which is used to form the bit line of the metal gate transistor.
[0092] Step 1109, continue etching the silicon substrate in the plurality of first grooves to form a plurality of first silicon pillars;
[0093] Combined with reference Fig.15 , Fig.15 Part (A1) shows the three-dimensional structure of multiple first silicon pillars 307. Fig.15 Part (A2) of FIG. 3 shows a two-dimensional plan view of the plurality of first silicon pillars 307 observed along the first direction. In one embodiment, the silicon substrate is further etched through the plurality of first grooves 306 to separate the plurality of first silicon pillars 307, thereby preventing the existence of connected silicides between two first silicon pillars 307, and further preventing the bit lines between the plurality of first silicon pillars 307 from being short-circuited.
[0094] Step 1110, filling the gaps between the plurality of first silicon pillars with oxide and grinding the gaps;
[0095] Combined with reference Fig.15 , Fig.15 Part (B1) shows the three-dimensional structure after the gaps between the plurality of first silicon pillars are filled with oxide and polished. Fig.15 Part (B2) shows a two-dimensional plan view of the three-dimensional structure after the oxide is filled and polished along the first direction. In one embodiment, the polishing operation is performed by CMP (Chemical Mechanical Polishing). In one embodiment, the oxide is silicon dioxide.
[0096] Step 1111, forming a plurality of columns of second masks along a second direction on the plurality of first silicon pillars;
[0097] Optionally, the second direction is a word line direction. Fig.15 , Fig.15 Part (C1) shows a three-dimensional structure obtained by depositing multiple columns of second masks 308 on multiple first silicon pillars 307. Fig.15 Part (C2) shows a two-dimensional plan view of the three-dimensional structure after depositing multiple columns of second masks 308 as viewed along the first direction. Fig.15 Part (C3) shows a two-dimensional plan view of the three-dimensional structure observed along the second direction after depositing multiple rows of second masks 308. In one embodiment, the second mask 308 is a three-layer structure consisting of a spacer, a mandrel and a spacer.
[0098] Step 1112, etching the first silicon layer, the silicon germanium layer, and the second silicon layer according to a plurality of columns of second masks to form a plurality of second grooves;
[0099] In one embodiment, the areas of the first silicon layer 301, the silicon germanium layer 302, and the second silicon layer 303 that are not covered by the plurality of columns of the second mask 308 will be removed by etching. Fig.16 , Fig.16Part (A1) shows a three-dimensional structure of a plurality of second grooves 311 formed by etching the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 using a plurality of columns of second masks 308 . Fig.16 Part (A2) shows the corresponding two-dimensional plan view observed along the second direction.
[0100] In one embodiment, the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 are etched according to the plurality of columns of the second mask 308 by a dry process.
[0101] Step 1113, performing a first lateral etching on the silicon germanium layer;
[0102] The first lateral etching is performed on the silicon germanium layer 302. In one embodiment, the lateral etching is performed on both sides of the silicon germanium layer 302. The etching depth corresponding to each side is about 1 / 2 of the thickness of the sidewall. In one embodiment, the lateral etching is performed by an ALE (Atomic Layer Etch) process.
[0103] Step 1114, filling the generated etched grooves with oxide and grinding them flat;
[0104] Fig.16 Part (B1) shows a three-dimensional schematic diagram of a three-dimensional structure obtained by filling the etched grooves produced by the first lateral etching with oxide and then grinding them flat. Fig.16 Part (B2) shows a two-dimensional schematic diagram of a three-dimensional structure obtained by filling the etched grooves produced by the first lateral etching with oxide and then grinding them flat.
[0105] Step 1115, performing a first lateral epitaxial silicon growth on the first silicon layer, the silicon germanium layer, and the second silicon layer to form a first lateral groove;
[0106] Fig.16 Part (C1) of FIG. 3 is a perspective view showing a first lateral groove 312 formed by performing a first lateral epitaxial silicon growth on the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 . Fig.16 Part (C2) shows a two-dimensional plan view of a first lateral groove 312 formed by performing a first lateral epitaxial silicon growth on the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 .
[0107] Step 1116, filling the first lateral groove with oxide and grinding it flat, and removing the epitaxial silicon at the bottom of the second groove; filling the second groove with nitride and grinding it flat;
[0108] Combined with reference Fig.17 , Fig.17Part (A1) shows a three-dimensional schematic diagram of the three-dimensional structure after the first lateral groove 312 is filled with oxide and polished, and the epitaxial silicon at the bottom of the second groove 311 is removed. Fig.17 Part (A2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
[0109] Fig.17 Part (B1) shows a three-dimensional schematic diagram of the three-dimensional structure after the second groove 311 is filled with nitride and polished. Fig.17 Part (B2) shows a two-dimensional schematic diagram of the three-dimensional structure after the second groove 311 is filled with nitride and polished. In one embodiment, the second mask 308 is a three-layer structure consisting of a sidewall, a mandrel 313 and a sidewall.
[0110] In one embodiment, the first lateral recess 312 is filled with oxide by an ALD process.
[0111] In one embodiment, the oxide is silicon dioxide. In one embodiment, the nitride is silicon nitride.
[0112] Step 1117, etching the first silicon layer, the silicon germanium layer, and the second silicon layer according to the plurality of mandrels in the plurality of second masks to form a plurality of third grooves;
[0113] Fig.17 Part (C1) shows a three-dimensional structure obtained by etching the first silicon layer 301 , the silicon germanium layer 302 , and the second silicon layer 303 according to the plurality of mandrels 313 in the plurality of second masks 308 . Fig.17 Part (C2) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction. Fig.17 Part (C2) shows that the area covered by the mandrel 313 has been etched. Fig.17 Part (C2) shows the third groove 314 obtained by etching.
[0114] Step 1118, performing a second lateral etching on the silicon germanium layer;
[0115] A second lateral etching is performed on the silicon germanium layer 302. In one embodiment, the second lateral etching is performed to completely etch away the silicon germanium material of the silicon germanium layer 302 in combination with the first lateral etching.
[0116] Step 1119, filling the generated etched grooves with oxide and grinding them flat;
[0117] Combined with reference Fig.18 , Fig.18 Part (A1) shows a three-dimensional schematic diagram of the three-dimensional structure after the etched grooves produced by the second lateral etching are filled with oxide and polished. Fig.18Part (A2) shows a two-dimensional schematic diagram of the three-dimensional structure observed along the second direction.
[0118] Step 1120, performing a second lateral epitaxial silicon growth on the first silicon layer, the silicon germanium layer, and the second silicon layer to form a second lateral groove;
[0119] Fig.18 Part (B1) shows that a second lateral groove 315 is formed by performing a second lateral epitaxial silicon growth on the first silicon layer 301 , the silicon germanium layer 302 and the second silicon layer 303 . Fig.18 Part (B2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
[0120] Step 1121, filling the second lateral groove with oxide and grinding it flat, and removing the epitaxial silicon at the bottom of the third groove; filling the third groove with nitride and grinding it flat;
[0121] Fig.18 Part (C1) shows a three-dimensional schematic diagram of a three-dimensional structure obtained by filling the second lateral groove 315 with oxide and grinding it flat, and removing the silicon obtained by epitaxy at the bottom of the third groove 314. Fig.18 Part (C2) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction.
[0122] Combined with reference Fig.19 , Fig.19 Part (A1) shows a three-dimensional schematic diagram of a three-dimensional structure obtained by filling the third groove 314 with nitride and then grinding it flat. Fig.19 Part (A2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction.
[0123] In one embodiment, the second lateral recess 315 is filled with oxide by an ALD process.
[0124] In one embodiment, the oxide is silicon dioxide. In one embodiment, the nitride is silicon nitride.
[0125] Step 1122, etching oxide in the first lateral groove and the second lateral groove;
[0126] Combined with reference Fig.19 , Fig.19 Part (B1) and part (B2) of FIG. 3 show that the oxide filled in the first lateral groove 312 and the second lateral groove 315 is etched, and at this time, the first lateral groove 312 and the second lateral groove 315 are filled with air. Fig.19 Part (B1) is a three-dimensional schematic diagram. Fig.19 Part (B2) is a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction.
[0127] Step 1123, depositing a gate material in the gaps in the middle and upper parts of the plurality of second silicon pillars;
[0128] The upper middle portion includes a gate layer and a second silicon layer. Fig.19 , Fig.19 Part (C1) shows a three-dimensional schematic diagram of a three-dimensional structure in which gate materials are deposited in the gaps in the middle and upper parts of the plurality of second silicon pillars 309 . Fig.19 Part (C2) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the first direction. Fig.19 Part (C3) shows a two-dimensional plan view of the corresponding three-dimensional structure observed along the second direction. Optionally, the gate material includes a gate oxide layer material, a high-K material and a gate metal layer material. Optionally, the gate material is deposited in the gaps in the middle and upper parts of the plurality of second silicon pillars by an ALD process.
[0129] Step 1124, etching the gate material in the second silicon layer region on the plurality of second silicon pillars;
[0130] Combined with reference Fig.19 and Fig. 20 , Fig. 20 Part (A1) shows a three-dimensional schematic diagram of the three-dimensional structure after the gate material in the second silicon layer 303 region on the plurality of second silicon pillars 309 is etched. Fig. 20 Part (A2) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the first direction. Fig. 20 Part (A3) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction.
[0131] Step 1125, etching the nitride in the middle and upper portions of the plurality of second silicon pillars to form air gaps;
[0132] Fig. 20 Part (B1) shows a three-dimensional schematic diagram of a three-dimensional structure formed after the nitride in the middle and upper parts of the plurality of second silicon pillars is etched. Fig. 20 Part (B2) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the first direction. Fig. 20 Part (B3) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction.
[0133] Step 1126 , etching the first isolation material covered by the plurality of second silicon pillars.
[0134] Fig. 20 Part (B1) also shows a three-dimensional schematic diagram of a three-dimensional structure formed after the first isolation material 305 covered by the plurality of second silicon pillars 309 is etched. Fig. 20Part (B2) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the first direction. Fig. 20 Part (B3) shows a two-dimensional schematic diagram of the corresponding three-dimensional structure observed along the second direction.
[0135] Combined with reference Fig.21 , Fig.21 The resulting vertical gate-all-around transistor is shown.
[0136] based on Figure 2 and Fig.11 In the method embodiment shown, when executing step 201 and step 1101 , well isolation is also formed in the stack structure.
[0137] In one embodiment, in conjunction with reference Fig. 22 , Fig. 22 Part (A1) shows the stack structure after well isolation is formed. Fig. 22 Part (A2) shows a two-dimensional plan view of the stacked structure. Considering the stacked structure after well isolation, it includes a silicon substrate 300, a first silicon layer 301, a silicon germanium layer 302 and a second silicon layer 303. Further, the silicon substrate 300 includes an upper silicon substrate 300-1 and a lower silicon substrate 300-2. Optionally, the lower silicon substrate 300-2 is doped to N type, the upper silicon substrate 300-1 is doped to P type, and the first silicon layer 301 is doped to P type. Optionally, the lower silicon substrate 300-2 is doped to P type, the upper silicon substrate 300-1 is doped to N type, and the first silicon layer 301 is doped to N type.
[0138] It can be noted that Fig. 22 Part (B1) shows the three-dimensional structure of the plurality of first silicon pillars 307 obtained after taking well isolation into consideration. Fig. 22 At this time, the longitudinal etching depth of the first silicon pillar 307 only reaches the upper part of the silicon substrate 300-1, and the plurality of first silicon pillars 307 (i.e., bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 307.
[0139] In one embodiment, in conjunction with reference Fig.23 , Fig.23 Part (A1) shows the stack structure after well isolation is formed. Fig.23 Part (A2) shows a two-dimensional plan view of the stacked structure. Considering the stacked structure after well isolation, it includes a silicon substrate 300, a first silicon layer 301, a silicon germanium layer 302, a second silicon layer 303, and a third silicon layer 304 located between the silicon substrate 300 and the first silicon layer. Optionally, the silicon substrate 300 is doped to P type, and the first silicon layer 301 and the third silicon layer 304 are doped to N type.
[0140] It can be noted that Fig.23 Part (B1) shows the three-dimensional structure of the plurality of first silicon pillars 307 obtained after taking well isolation into consideration. Fig.23 At this time, the longitudinal etching depth of the first silicon pillars 307 only reaches the third silicon layer 304, and the plurality of first silicon pillars 307 (ie, bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 307.
[0141] Illustratively, the following four possible implementations of step 201 and step 1101 are provided.
[0142] A first possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into N-type and dope the upper part of the silicon substrate into P-type; sequentially stack a first silicon layer, a silicon germanium layer and a second silicon layer on the silicon substrate; dope the first silicon layer into P-type. Optionally, after doping the silicon substrate, annealing is performed to restore the silicon substrate lattice.
[0143] Combined with reference Fig.24 , Fig.24 Part (A) shows a silicon substrate 300; Fig.24 Part (B) of FIG. 1 shows a lower portion of the silicon substrate 300 - 1 doped with N type and an upper portion of the silicon substrate 300 - 2 doped with P type. Fig.24 Part (C) shows the stacked first silicon layer 301 , silicon germanium layer 302 , and second silicon layer 303 , wherein the first silicon layer 301 is doped to a P type.
[0144] A second possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into P type, and dope the upper part of the silicon substrate into N type; sequentially stack a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and dope the first silicon layer into N type. Optionally, after doping the silicon substrate, an annealing operation is performed to restore the silicon substrate lattice.
[0145] Combined with reference Fig.25 , Fig.25 Part (A) shows a silicon substrate 300; Fig.25 Part (B) of FIG. 1 shows a lower portion of the silicon substrate 300 - 1 doped with a P type and an upper portion of the silicon substrate 300 - 2 doped with an N type. Fig.25 Part (C) shows the stacked first silicon layer 301 , silicon germanium layer 302 , and second silicon layer 303 , wherein the first silicon layer 301 is doped to N type.
[0146] A third possible implementation method is to obtain a silicon substrate; dope the silicon substrate into N-type; sequentially stack a third silicon layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and dope the third silicon layer and the first silicon layer into P-type.
[0147] Combined with reference Fig.26 , Fig.26 Part (A) shows a silicon substrate 300; Fig.26 Part (B) of FIG. 1 shows a silicon substrate 300 doped to an N-type. Fig.26 Part (C) shows the stacked third silicon layer 304, the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303. The third silicon layer 304 is doped to P type, and the first silicon layer 301 is doped to P type.
[0148] A fourth possible implementation method is to obtain a silicon substrate; dope the silicon substrate into P type; sequentially stack a third silicon layer, a first silicon layer, a silicon germanium layer, and a second silicon layer on the silicon substrate; and dope the third silicon layer and the first silicon layer into N type.
[0149] Combined with reference Fig. 27 , Fig. 27 Part (A) shows a silicon substrate 300; Fig.26 Part (B) of FIG. 1 shows a silicon substrate 300 doped to a P type. Fig. 27 Part (C) shows the stacked third silicon layer 304, the first silicon layer 301, the silicon germanium layer 302 and the second silicon layer 303. The third silicon layer 304 is doped to N type, and the first silicon layer 301 is doped to N type.
[0150] The embodiment of the present application provides an electronic device, wherein the electronic device includes a logic device, wherein the logic device includes a transistor as provided in the above embodiment. The logic device can be applied to a logic operator and a memory, etc.
[0151] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
[0152] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise clearly defined.
[0153] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0154] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing a transistor, characterized in that: The method comprises: A first silicon layer (301), a silicon germanium layer (302) and a second silicon layer (303) are sequentially stacked on a silicon substrate (300), wherein the first silicon layer (301) is in contact with the silicon substrate (300); a plurality of columns of first masks (304) are formed on the second silicon layer (303) along a first direction; the second silicon layer (303) is etched according to the plurality of columns of first masks (304), and a first isolation material (305) is covered on the surfaces of the etched second silicon layer (303) and the plurality of columns of first masks (304); Etching the silicon substrate (300), the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to the multiple columns of first masks (304) to form a plurality of first grooves (306); filling the plurality of first grooves (306) with metal material and annealing to form a plurality of first silicon pillars (307) along the first direction; Forming a plurality of columns of second masks (308) along a second direction on the plurality of first silicon pillars (307); etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to the plurality of columns of second masks (308); continuing to etch the silicon germanium layer (302) based on the grooves obtained by etching; epitaxially growing silicon in a partially etched area of the silicon germanium layer (302), and depositing a gate material in a remaining etched area of the silicon germanium layer (302) to form a plurality of second silicon pillars (309), wherein the plurality of second silicon pillars (309) are distributed in an array along the first direction and the second direction; The first isolation material (305) covered by the plurality of second silicon pillars (309) is etched.
2. The method according to claim 1, characterized in that The step of filling the plurality of first grooves (306) with metal material and annealing the metal material to form a plurality of first silicon pillars (307) along the first direction comprises: Filling the plurality of first grooves (306) with metal material and annealing the metal material; The silicon substrate (300) is further etched in the plurality of first grooves (306) to form the plurality of first silicon pillars (307).
3. The method according to claim 2, characterized in that The etching of the silicon substrate (300), the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to the plurality of columns of first masks (304) to form a plurality of first grooves (306) comprises: Etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to the multiple columns of first masks (304); covering the surfaces of the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) after etching with a second isolation material (310); The silicon substrate (300) is continuously etched to form the plurality of first grooves (306).
4. The method according to claim 3, characterized in that The step of filling the plurality of first grooves (306) with metal material and annealing the metal material comprises: Filling the plurality of first grooves (306) with metal material and etching the metal material, wherein the upper surface of the etched metal material is higher than the lower surface of the second isolation material (310); An annealing operation is performed on the metal material within the plurality of first grooves (306).
5. The method according to any one of claims 1 to 4, characterized in that: The first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) are etched according to the plurality of second masks (308); the silicon germanium layer (302) is further etched based on the grooves obtained by etching; silicon is epitaxially grown in a partially etched area of the silicon germanium layer (302), and a gate material is deposited in a remaining etched area of the silicon germanium layer (302) to form a plurality of second silicon pillars (309), comprising: Etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to the plurality of columns of second masks (308) to form a plurality of second grooves (311); performing a first lateral etching on the silicon germanium layer (302), and then performing a first lateral epitaxial silicon growth on the first silicon layer, the silicon germanium layer and the second silicon layer to form a first lateral groove (312); The first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) are etched according to the plurality of mandrels (313) in the plurality of second masks (308) to form a plurality of third grooves (314); the silicon germanium layer (302) is subjected to a second lateral etching, and then the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) are subjected to a second lateral epitaxial silicon growth to form second lateral grooves (315), wherein the two lateral etchings completely remove the silicon germanium material of the silicon germanium layer (302); A gate material is deposited in the first lateral groove (312) and the second lateral groove (315) to form the plurality of second silicon pillars (309).
6. The method according to claim 5, characterized in that After performing the first lateral etching on the silicon germanium layer (302), the method further comprises: filling the generated etched groove with oxide and grinding it flat; after forming the first lateral groove (312), the method further comprises: filling the first lateral groove (312) with oxide and grinding it flat, and removing the epitaxial silicon at the bottom of the second groove (311); and filling the second groove (311) with nitride and grinding it flat; After performing the second lateral etching on the silicon germanium layer (302), the method further includes: filling the generated etched groove with oxide and grinding it flat; after forming the second lateral groove (315), the method further includes: filling the second lateral groove (315) with oxide and grinding it flat, and removing the epitaxial silicon at the bottom of the third groove (314); and filling the third groove (314) with nitride and grinding it flat; The step of depositing a gate material in the first lateral groove (312) and the second lateral groove (315) comprises: The oxide in the first lateral groove (312) and the second lateral groove (315) is etched; a gate material is deposited in the gap in the middle and upper parts of the plurality of second silicon pillars (309), wherein the middle and upper parts include a gate layer and the second silicon layer (303); and the gate material in the second silicon layer (303) region on the plurality of second silicon pillars (309) is etched.
7. The method according to claim 6, characterized in that After etching the gate material in the second silicon layer (303) region on the plurality of second silicon pillars (309), the method further includes: The nitride in the middle and upper portions of the plurality of second silicon pillars (309) is etched to form an air gap.
8. The method according to any one of claims 1 to 4, characterized in that: Before depositing a plurality of columns of second masks (308) on the plurality of first silicon pillars (307) along the second direction, the method further comprises: The gaps between the plurality of first silicon pillars (307) are filled with oxide and then polished.
9. An electronic device, characterized in that: The electronic device comprises a logic device, and the logic device comprises a transistor manufactured according to the method for manufacturing a transistor as claimed in any one of claims 1 to 8.
10. The electronic device according to claim 9, characterized in that: The electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.