Method of manufacturing semiconductor device including ion implantation process

Abstract

The invention relates to a method of manufacturing a semiconductor device including an ion implantation process. The method includes forming a doped region in a semiconductor body. Forming the doped region includes introducing a first dopant through a first surface of the semiconductor body at a first vertical reference level by a first ion implantation process. Thereafter, forming the doped region includes applying a first thermal treatment to the semiconductor body. Thereafter, forming the doped region includes introducing a second dopant through the first surface of the semiconductor body at a first vertical reference level by a second ion implantation process. The atomic number of the first dopant is equal to the atomic number of the second dopant. The difference between the ion implantation energy of the second ion implantation process and the ion implantation energy of the first ion implantation process is less than 20%. The difference between the ion implantation dose of the second ion implantation process and the ion implantation dose of the first ion implantation process is less than 20%.

Description

Technical Field

[0001] The present disclosure relates to a method of manufacturing a semiconductor device, and more particularly to a method including forming a doped region in a semiconductor body by an ion implantation process. Background Art

[0002] The technical development of new generation power semiconductor devices (e.g., insulated gate field effect transistors (IGFETs) such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs) or junction field effect transistors (JFETs) or freewheeling diodes) aims to improve electrical device characteristics, such as area-to-on state resistance. By modifying the characteristics of the doped semiconductor regions (e.g., peak, slope, extension), the electrical device parameters can be adapted to the specific needs of the semiconductor device.

[0003] There is a steady need for improved flexibility in forming doped semiconductor regions. Summary of the invention

[0004] An example of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes: forming a doped region in a semiconductor body. Forming the doped region includes: introducing a first dopant through a first surface of the semiconductor body at a first vertical reference level through a first ion implantation process. Thereafter, a first heat treatment is applied to the semiconductor body. Thereafter, a second dopant is introduced through the first surface of the semiconductor body at a first vertical reference level through a second ion implantation process. The atomic number of the first dopant is equal to the atomic number of the second dopant. The ion implantation energy of the second ion implantation process differs by less than 20% from the ion implantation energy of the first ion implantation process. The ion implantation dose of the second ion implantation process differs by less than 20% from the ion implantation dose of the first ion implantation process.

[0005] Another example of the present disclosure relates to another method for manufacturing a semiconductor device. The method includes: forming a doped region in a semiconductor body. Forming the doped region includes: introducing a first dopant through a first surface of the semiconductor body at a first vertical reference level by a first ion implantation process. The first dopant is implanted along a beam axis that deviates by up to 1.5° relative to a main crystal axis of the semiconductor body along which channeling occurs. Thereafter, a first heat treatment is applied to the semiconductor body. Thereafter, a second dopant is introduced through the first surface of the semiconductor body at a first vertical reference level by a second ion implantation process. The second dopant is implanted along a beam axis that deviates by up to 1.5° relative to a main crystal axis of the semiconductor body along which channeling occurs.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate examples of semiconductor device processing features and together with the description serve to explain the principles of the examples. Additional examples are described in the following detailed description and claims.

[0008] Figures 1A to 1C is a schematic cross-sectional view for illustrating process features of a method for manufacturing a semiconductor device, the method including forming a doped region.

[0009] Figure 2 is a schematic cross-sectional view used to illustrate features of a process for electrically activating dopants in a doped region.

[0010] Figures 3A to 3C is a schematic cross-sectional view for illustrating further process features of a method for fabricating a semiconductor device, the method including forming a doped region.

[0011] Figure 4 and 5 is a schematic cross-sectional view for illustrating a configuration example of a semiconductor device including Figures 1A to 1C Describes the process characteristics for forming the doped regions.

[0012] Figure 6 is a schematic illustration of the simulated channeling profile. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which specific examples of processable semiconductor substrates are shown as illustrations. It should be understood that other examples may be used and structural or logical changes may be implemented without departing from the scope of the present disclosure. For example, features illustrated or described for one example can be used on other examples or used in conjunction with other examples to produce another example. It is intended that the present disclosure includes such modifications and variations. Examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The accompanying drawings are not drawn to scale and are for illustrative purposes only. If not otherwise indicated, corresponding elements are designated by the same reference numerals in different drawings.

[0014] The terms "having", "containing", "including", "comprising" and the like are open ended and indicate the presence of stated structures, elements or features but do not exclude the presence of additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0015] The term "electrically connected" describes a permanent low resistance connection between electrically connected elements, such as direct contact between the elements involved or a low resistance connection via metal and / or heavily doped semiconductor materials. The term "electrically coupled" includes that one or more intervening elements suitable for signal and / or power transfer may be connected between the electrically coupled elements, such as elements that can be controlled to temporarily provide a low resistance connection in a first state and a high resistance electrical decoupling in a second state.

[0016] If two elements A and B are combined using "or", if not explicitly or implicitly defined otherwise, this should be understood to disclose all possible combinations, i.e. only A, only B and A and B. Alternative wordings for the same combination are "at least one of A and B" or "A and / or B". The same applies to combinations of more than two elements, if appropriately modified.

[0017] Ranges given for physical dimensions include the boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value (e.g., "at most" and "at least").

[0018] The main components of a layer or structure of a chemical compound or alloy are such elements whose atoms form said chemical compound or alloy.For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0019] The term “on” should not be interpreted as meaning only “directly on.” On the contrary, if an element is disposed “on another element” (for example, a layer is “on another layer” or “on a substrate”), another component (for example, another layer) may be disposed between the two elements (for example, if a layer is “on a substrate,” another layer may be disposed between the layer and the substrate).

[0020] An example of a method for manufacturing a semiconductor device includes forming a doped region in a semiconductor body. Forming the doped region may include introducing a first dopant through a first surface of the semiconductor body at a first vertical reference level through a first ion implantation process. Thereafter, a first thermal treatment may be applied to the semiconductor body. Thereafter, a second dopant may be introduced through the first surface of the semiconductor body at a first vertical reference level through a second ion implantation process. The atomic number of the first dopant may be equal to the atomic number of the second dopant. The ion implantation energy of the second ion implantation process may differ from the ion implantation energy of the first ion implantation process by less than 20%, or by less than 10%, or even by less than 5%. The ion implantation dose of the second ion implantation process may differ from the ion implantation dose of the first ion implantation process by less than 20%, or by less than 10%, or even by less than 5%.

[0021] The semiconductor body may have a crystal lattice suitable for channeling ions. Typically, in some crystal directions of a single crystal material, the open space extends directly into the crystal. The open space forms a channel through which the ions travel with fewer interactions with the atoms of the crystal lattice than outside the channel. The channel controls the movement of the ions, wherein ions entering such a channel show a deceleration pattern different from the deceleration pattern of ions entering the semiconductor body outside the channel. In other words, in some crystal directions of a single crystal material, the atoms are aligned in such a way that they form a so-called channel in which the incoming ion flux is constrained. The channel direction coincides with the main crystal direction.

[0022] For example, the first dopant and the second dopant may be implanted into the semiconductor body via ions of the corresponding element or element compound. For example, between the ion implantation of the first dopant and the ion implantation of the second dopant, no other ion implantation may be performed. In addition to the first and second ion implantation processes, additional ion implantation processes may be performed to form doped regions. For example, before the first ion implantation process or after the second ion implantation process, each ion implantation process in the additional ion implantation process other than the first and second ion implantation processes may be performed. After each additional ion implantation process or some additional ion implantation processes in the additional ion implantation process, another heat treatment may be performed. A series of n ion implantations followed by crystal damage annealing may be performed to form doped regions, where n is an integer equal to or greater than 2, such as 3, 4, 5, 6, 7, 8, 9, 10 or even greater. For example, between the ion implantation processes, a semiconductor layer may be formed on the surface of the semiconductor body, and dopants enter the semiconductor body from the surface through the ion implantation process. This may allow the vertical extent of the doped region to be expanded. Parameters of the additional ion implantation process, such as ion implantation energy and / or ion implantation dose and / or ion implantation tilt angle with respect to a vertical axis on the first surface, may be similar to the first and / or second ion implantation process.

[0023] The first vertical reference level is measured relative to a fixed vertical position inside the semiconductor body and may define an outer surface of the semiconductor body. When a semiconductor layer is deposited on a first surface at the first reference level by a semiconductor layer deposition process followed by a subsequent ion implantation process into the deposited semiconductor layer, the subsequent ion implantation process will introduce dopants through a surface of the deposited semiconductor layer at a second vertical reference level different from the first vertical reference level. The first vertical reference level may define an outer surface of the semiconductor layer prior to the layer deposition process, and the second vertical reference level may define an outer surface of the semiconductor body plus the deposited semiconductor layer.

[0024] A first thermal treatment may be performed to anneal the semiconductor body. The first thermal treatment may be performed by a furnace process or by a rapid thermal processing RTP. In addition, or as an alternative, annealing may be performed by a melting or non-melting laser thermal annealing LTA. By a suitable annealing budget, this may allow the crystal damage in the irradiation band to be reduced or minimized. Thus, the channeling performance degradation or de-channeling effect of the subsequent ion implantation of dopants (e.g., a second ion implantation process) due to the crystal damage caused by the first ion implantation process may be reduced or minimized. For example, this may allow an improvement in the tuning of the vertical dopant concentration profile.

[0025] For example, the semiconductor device may be an integrated circuit or a discrete semiconductor device or a semiconductor module. The semiconductor device may be or include a power semiconductor device, such as a vertical power semiconductor device having a load current flowing between a first surface and a second surface. The semiconductor device may be or include a power semiconductor IGFET, such as a power semiconductor MOSFET or a power semiconductor IGBT. The power semiconductor device may be configured to conduct a current exceeding 1A or exceeding 10A or even exceeding 30A, and may also be configured to block a voltage between load electrodes (e.g., between the emitter and collector of an IGBT or between the drain and source of a MOSFET) in a range of hundreds or up to several thousand volts, such as 400V, 650V, 1.2kV, 1.7kV, 3.3kV, 4.5kV, 5.5kV, 6kV, 6.5kV. For example, the blocking voltage may correspond to a voltage level specified in a data sheet of the power semiconductor device.

[0026] For example, the semiconductor body may be or may include a crystalline SiC semiconductor substrate. For example, the crystalline SiC semiconductor substrate may have a hexagonal polymorph, such as 4H or 6H. The semiconductor body may be uniformly doped, or may include SiC layer portions that are doped in different ways, such as with a doping concentration of at least 2×10 17 cm -3 and up to 1x10 19 cm -3 , for example at least 5x10 17 cm -3 and up to 1x10 19 cm -3 , or may be nominally undoped (e.g., doping concentration is at most 1x10 17 cm -3 or up to 1x10 15 cm -3; so-called "unintentionally doped silicon carbide"). For example, the semiconductor body may include a substantially uniformly doped SiC semiconductor substrate and an epitaxial buffer layer on the SiC semiconductor substrate, for example as part of a SiC layer doped in a different manner. For example, the semiconductor body may include one or more layers from another material having a melting point close to or higher than that of crystalline silicon carbide. For example, a layer from another material may be embedded in a crystalline SiC semiconductor substrate. The crystalline SiC semiconductor substrate may have two essentially parallel main surfaces of the same shape and size and side surface areas connecting the edges of the two main surfaces. For example, the silicon carbide semiconductor substrate may be: a rectangular prism with or without rounded edges; or a right circular cylinder or a slightly inclined circular cylinder (for example, where the side faces are inclined at an angle of at most 8° or at most 5° or at most 3°), with or without one or more flats or notches along the periphery. As an alternative to SiC, a wide bandgap semiconductor wafer may be processed, for example including a wide bandgap semiconductor material different from silicon carbide. The wide bandgap semiconductor wafer may have a bandgap larger than the bandgap of silicon (1.1 eV). For example, the wide bandgap semiconductor wafer may be a gallium arsenide (GaAs) wafer or a gallium nitride (GaN) wafer. As an alternative to SiC and wide bandgap materials, a silicon semiconductor body may also be used. For example, the semiconductor body may have a diamond cubic crystal lattice like silicon (Si). In the case of a diamond cubic crystal lattice, the surface of the semiconductor body may coincide with the (100) crystal plane, may be tilted up to ±2 degrees relative to the {100} crystal plane, or may be any other face suitable for the channeling effect. Thus, as one of the several principal crystal directions along which the channeling effect occurs, the surface of the semiconductor body may be aligned with the (100) crystal plane, may be tilted up to ±2 degrees relative to the {100} crystal plane, or may be any other face suitable for the channeling effect. <100> The crystal direction or any other suitable direction extends perpendicular to the process surface.

[0027] By dividing the ion implantation dose of an ion implantation process into multiple ion implantations with lower doses (with intermediate heat treatments for annealing crystal damage caused by previous implantations), the resulting ion implantation profile of the multiple ion implantations can allow greater flexibility in profile shaping compared to a single ion implantation process or fewer ion implantation processes with the same total dose as the multiple ion implantations. The intermediate heat treatment for annealing crystal damage of the previous ion implantation process improves the channeling ion implantation of the subsequent ion implantation by reducing the effects of dechanneling or channeling degradation. More particularly, by applying the intermediate heat treatment, the concentration of the implanted ions in the channeling tail region can be increased as a result of the reduced crystal damage.

[0028] For example, the first and / or second dopant may be implanted along a beam axis that deviates by at most 1.5°, or by at most 1.0°, or by at most 0.5°, or by at most 0.3°, or by at most 0.1° relative to a main crystal axis of the semiconductor body along which channeling occurs. For example, a maximum tilt angle between the main beam direction and the main crystal direction along which channeling of the ions occurs and an implant beam incidence angle variability of at most ±0.5 degrees may be effective for at least 80% of the surface of the semiconductor body.

[0029] The details for the above process features are equally applicable to another example of a method for manufacturing a semiconductor device. The method includes: forming a doped region in a semiconductor body. Forming the doped region may include: introducing a first dopant through a first surface of the semiconductor body at a first vertical reference level by a first ion implantation process. The first dopant may be implanted along a beam axis that deviates by up to 1.5° relative to a main crystal axis of the semiconductor body along which channeling occurs. Thereafter, a first heat treatment may be applied to the semiconductor body. Thereafter, a second dopant may be introduced through the first surface of the semiconductor body at a first vertical reference level by a second ion implantation process. The second dopant may be implanted along a beam axis that deviates by up to 1.5° relative to a main crystal axis of the semiconductor body along which channeling occurs. For example, the semiconductor body may be a SiC semiconductor body, and the main crystal axis is a c-axis. For example, the atomic number of the first dopant may be different from the atomic number of the second dopant. In addition, or as an alternative, the ion implantation energy of the second ion implantation process may differ from the ion implantation energy of the first ion implantation process by less than 20%, or by less than 10%, or even by less than 5%. Additionally or alternatively, the ion implantation dose of the second ion implantation process may differ from the ion implantation dose of the first ion implantation process by less than 20%.

[0030] For example, the second ion implantation energy may be less than the first ion implantation energy.

[0031] For example, the second ion implantation dose may be smaller than the first ion implantation dose.

[0032] For example, an ion implantation mask of a first ion implantation process may be reused for a second ion implantation process.

[0033] For example, the method may further include: applying an activation heat treatment to the semiconductor body after the second ion implantation process. The activation heat treatment may be configured to electrically activate the first dopant and the second dopant. The maximum temperature of the activation heat treatment may be greater than the maximum temperature of the first heat treatment.

[0034] The maximum temperature of the activation heat treatment may be greater than the maximum temperature of the first heat treatment by more than 400 K, or more than 500 K, or even more than 600 K. For example, the temperature value of the first heat treatment may be in the range from 600° C. to 1000° C., and the temperature value of the activation heat treatment may be in the range from 1600° C. to 1900° C.

[0035] For example, the maximum temperature of the first thermal treatment may be configured to anneal crystal damage caused by the first ion implantation process.

[0036] For example, the semiconductor body may be a SiC semiconductor body.For example, the maximum temperature of the first thermal treatment may have a value from 600°C to 1200°C or from 600°C to 1000°C or from 700°C to 900°C.

[0037] For example, the method may further include an ion implantation process other than the first and second ion implantation processes. Each of the ion implantation processes other than the first and second ion implantation processes may be performed before the first ion implantation process or after the second ion implantation process. Between subsequent ion implantation processes including at least one of the additional ion implantation processes, a heat treatment for annealing crystal damage may be performed. For example, the atomic number of the dopant for the additional ion implantation processed for forming the doped region may be equal to or different from the atomic number of the first / second dopant.

[0038] For example, the doped region may be a p-doped region or an n-doped region of a superjunction structure, the superjunction structure comprising a p-doped region laterally adjoining an n-doped region.

[0039] For example, forming a super junction structure may further include: forming a semiconductor layer on the first surface of the semiconductor body. Forming a super junction structure may further include: introducing a third dopant through the surface of the semiconductor layer at a second vertical reference level through a third ion implantation process. Thereafter, a second thermal treatment may be applied to the semiconductor body and the semiconductor layer. Thereafter, through a fourth ion implantation process, through the surface of the semiconductor layer at a second vertical reference level, a fourth dopant may be implanted. The atomic number of the third dopant may be equal to the atomic number of the fourth dopant. The ion implantation energy of the fourth ion implantation process may differ from the ion implantation energy of the third ion implantation process by less than 20%, or by less than 10%, or even by less than 5%. The ion implantation dose of the fourth ion implantation process may differ from the ion implantation dose of the third ion implantation process by less than 20%, or by less than 10%, or even by less than 5%.

[0040] For example, forming a super junction structure may further include: forming a semiconductor layer on the first surface of the semiconductor body. Forming a super junction structure may further include: introducing a third dopant through the surface of the semiconductor layer at a second vertical reference level through a third ion implantation process; and introducing a fourth dopant through the surface of the semiconductor layer at a second vertical reference level through a fourth ion implantation process. The introduction of both the first dopant and the third dopant may be performed before the first thermal treatment, and the introduction of both the second dopant and the fourth dopant may be performed after the first thermal treatment. For example, the atomic number of the third dopant is equal to the atomic number of the fourth dopant, and / or the ion implantation energy of the fourth ion implantation process differs from the ion implantation energy of the third ion implantation process by less than 20%, and / or the ion implantation dose of the fourth ion implantation process differs from the ion implantation dose of the third ion implantation process by less than 20%.

[0041] For example, the first dopant and the second dopant both form an n-doped region or column of the superjunction structure, and the third dopant and the fourth dopant both form a p-doped region or column of the superjunction structure. In other words, along each channeling axis, in at least two implantation steps, an n-doped region and a p-doped region of the superjunction structure can be formed. Between the implantation steps, a corresponding heat treatment can be performed to repair the crystal lattice so as to improve the channeling effect in the subsequent implantation step.

[0042] For example, the doped region may be an n-doped current extension region of a power semiconductor device including a gate trench. The current extension region may be adjacent to the bottom side of the gate trench. The current extension region may also be adjacent to a channel end, the channel end being opposite to another channel end, the other channel end being adjacent to the source region.

[0043] For example, each of the ion implantation energy of the first ion implantation process and the ion implantation energy of the second ion implantation process may be greater than 1000 keV.

[0044] For example, the temperature of the semiconductor body during the introduction of the first dopant is less than the temperature of the semiconductor body during the introduction of the second dopant. For example, the second dopant is injected at a higher temperature of the semiconductor body than the first dopant. For example, the temperature of the semiconductor body differs by at least 10 K, or even by at least 30 K. Prior to the introduction of the first dopant, the semiconductor body may be cooled, and / or prior to the introduction of the second dopant, the semiconductor body may be heated. This may reduce the influence of phonons and / or the amorphization limit of the semiconductor material of the semiconductor body.

[0045] For example, the semiconductor device may include a doped region formed by a method of any one of the examples disclosed herein. For example, the semiconductor device may be a vertical power semiconductor device, which may be part of an integrated circuit, a discrete semiconductor device, or a semiconductor module or may be at least one of an integrated circuit, a discrete semiconductor device, or a semiconductor module. The semiconductor device may be used in applications related to power transmission and distribution, automotive and transportation, renewable energy, consumer electronics, and other industrial applications. For example, the vertical power semiconductor device may be or may include an insulated gate field effect transistor (IGFET) such as a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a junction field effect transistor (JFET). For example, for semiconductor devices based on substrate materials (e.g., SiC) that only allow low diffusion of dopants, the examples described herein may allow greater flexibility in shaping the doping concentration profile. For example, higher concentrations and box-shaped profiles in large depths may be achieved in such substrate materials. For example, doped regions that require greater depths to meet their intended purposes may benefit from the examples disclosed herein. For example, the doped region may be an n-doped current extension region of an n-channel MOSFET. For example, the doped region may also be part of a superjunction SJ structure of a superjunction MOSFET, for example as a pillar-shaped n-doped or p-doped portion.

[0046] Further details and aspects are mentioned in connection with the examples described above or below.Processing a semiconductor body may include one or more optional further features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0047] Aspects and features mentioned and described in conjunction with one or more of the previously described examples and figures may also be combined with one or more of the other examples in order to replace similar features of the other examples, or in order to otherwise introduce the features into the other examples.

[0048] It will be understood that although the method is described above and below as a series of steps or events, the ordering of such steps or events described should not be interpreted in a limiting sense. On the contrary, in addition to the order described above and below, some steps may occur in a different order and / or occur simultaneously with other steps or events.

[0049] The functional and structural details described with respect to the above examples should apply equally to the examples illustrated in the drawings and described further below.

[0050] Reference Figures 1A to 1C Schematic cross-sectional views of exemplary process features for fabricating a semiconductor device are illustrated.

[0051] The illustrated process features of the method illustrate exemplary process features for forming the doped region 102 in the semiconductor body 104 .

[0052] Reference Figure 1A , by a first ion implantation process I2-1, at a first vertical reference level L1, through a first surface 106 of a semiconductor body 104, a first dopant 1081 is introduced. The first vertical reference level L1 refers to a predetermined vertical position inside the semiconductor body 104. The first dopant 1081 is implanted along a beam axis 1101 having an angle α1 with respect to a vertical axis on the first surface 106. For example, the angle α1 may deviate by up to 1.5° relative to a main crystal axis of the semiconductor body 104 along which a channeling effect occurs (e.g., a c-axis in a SiC semiconductor body). The first ion implantation process I2-1 is based on an ion implantation energy E1 and an ion implantation dose D1.

[0053] Reference Figure 1B , a first thermal treatment T1 is applied to the semiconductor body 104. For example, the first thermal treatment T1 may include annealing the semiconductor body 104 by a furnace process or a rapid thermal process RTP. Additionally or alternatively, annealing may be performed by melting or non-melting laser thermal annealing LTA. By suitable annealing, this may allow reducing or minimizing crystal damage in the irradiated zone.

[0054] Reference Figure 1C , after the first thermal treatment T1, a second dopant 1082 is introduced through the first surface 106 of the semiconductor body 104 at a first vertical reference level L1 by a second ion implantation process I2-2. The second dopant 1082 is implanted along a beam axis 1102 having an angle α2 with respect to a vertical axis on the first surface 106. For example, the angle α2 may deviate by up to 1.5° relative to a main crystal axis of the semiconductor body 104 along which a channeling effect occurs (e.g., a c-axis in a SiC semiconductor body). The second ion implantation process I2-2 is based on an ion implantation energy E2 and an ion implantation dose D2. The atomic number of the first dopant 1081 is equal to the atomic number of the second dopant 1082. For example, the first dopant and the second dopant may be Al for p-type doping, for example, in a semiconductor body made of SiC or Si. For example, the first dopant and the second dopant may be P for n-type doping, for example, in a semiconductor body made of SiC or Si. The ion implantation energy E2 of the second ion implantation process I2-2 differs from the ion implantation energy E1 of the first ion implantation process I2-1 by less than 20%, or by less than 10%, or by less than 5%. The ion implantation dose D2 of the second ion implantation process I2-2 differs from the ion implantation dose D1 of the first ion implantation process I2-1 by less than 20%, or by less than 10%, or by less than 5%.

[0055] For example, in the case of Figure 1A , 1B , before, after, or between the process features illustrated in FIG1C , additional process features may be implemented. Examples of additional process features are, among others, deposition processes for forming insulating or semiconductor or conductive layers; etching processes, such as via (one or more) lithographic etching masks, for patterning structures; and doping processes for forming additional doped regions in the semiconductor body 104. Exemplary doped regions include source and drain regions or emitter and collector regions, (one or more) body regions, (one or more) body contact regions, (one or more) current spreading regions, (one or more) shielding regions configured to shield the gate dielectric from high electric fields, (one or more) field stop regions. Exemplary insulating layers include (one or more) gate dielectrics, (one or more) interlayer insulating dielectrics in the wiring area above the semiconductor body 104. Exemplary semiconducting layers include (one or more) gate electrodes, (one or more) field electrodes, (one or more) floating electrodes formed of highly doped semiconductor materials. Exemplary conductive layers include patterned wiring level(s), such as patterned metal wiring layer(s), vias, contact plugs, bonding pad(s).

[0056] exist Figures 1A to 1C In the example illustrated in , the formation of the doped region 102 has been illustrated as being based on two ion implantation processes I2-1, I2-2. The two ion implantation processes I2-1, I2-2 for forming the doped region 102 are merely exemplary and are by no means restrictive. Additional ion implantation processes other than the first and second ion implantation processes I2-1, I2-2 may be implemented to form the doped region 102. For example, before the first ion implantation process I2-1 or after the second ion implantation process I2-2, each ion implantation process in the ion implantation process other than the first and second ion implantation processes I2-1, I2-2 may be implemented. Parameters of the additional ion implantation process, such as ion implantation energy and / or ion implantation dose and / or ion implantation tilt angle for a vertical axis on the first surface 106, may be similar to the first and / or second ion implantation processes I2-1, I2-2.

[0057] Reference Figure 2 , the method for forming the doped region 102 may further include an activation heat treatment Ta applied to the semiconductor body 104 after the second ion implantation process I2-2. The activation heat treatment is configured to activate the first and second dopants 1081, 1082 in an electrically manner.

[0058] The method for forming the doped region 102 may include referring to Figures 3A to 3C For example, the process features may be described in the schematic cross-sectional view of FIG. Figure 1C and / or Figure 2 After or after the process characteristics shown in the figure Figure 1C After the process characteristics and Figure 2 The process characteristics have been implemented before.

[0059] Reference Figure 3A , forming the doped region 102 also includes: forming a semiconductor layer 1041 on the first surface 106 of the semiconductor body 104. Through the third ion implantation process I2-3, at the second vertical reference level L2, through the surface 1061 of the semiconductor layer 1041, a third dopant 1083 is introduced. The third dopant 1083 is implanted along a beam axis 1103 having an angle α3 with respect to a vertical axis on the surface 1061. For example, the angle α3 may deviate by up to 1.5° relative to a main crystal axis of the semiconductor body 104 along which a channeling effect occurs (e.g., a c-axis in a SiC semiconductor body). The third ion implantation process I2-3 is based on an ion implantation energy E3 and an ion implantation dose D3.

[0060] Reference Figure 3B , forming the doped region 102 further includes: applying a second thermal treatment T2 to the semiconductor body 104 and the semiconductor layer 1041 .

[0061] Reference Figure 3C , by a fourth ion implantation process I2-4, at a second vertical reference level L2, through the surface 1061 of the semiconductor layer 1041, a fourth dopant 1084 is introduced. The fourth dopant 1084 is implanted along a beam axis 1104 having an angle α4 with respect to a vertical axis on the surface 1061. For example, the angle α4 may deviate by up to 1.5° relative to a main crystal axis of the semiconductor body 104 along which a channeling effect occurs (e.g., a c-axis in a SiC semiconductor body). The fourth ion implantation process I2-4 is based on an ion implantation energy E4 and an ion implantation dose D4. The atomic number of the third dopant 1083 may be equal to the atomic number of the fourth dopant 1084. The ion implantation energy E4 of the fourth ion implantation process I2-4 differs from the ion implantation energy E3 of the third ion implantation process I2-3 by less than 20%, or by less than 10%, or by less than 5%. The ion implantation dose D4 of the fourth ion implantation process I2 - 4 differs from the ion implantation dose D3 of the third ion implantation process I2 - 3 by less than 20%, or by less than 10%, or by less than 5%.

[0062] In combination Figures 3A to 3C of Figures 1A to 1CIn the example illustrated in , the formation of the doped region 102 has been illustrated as being based on four ion implantation processes I2-1, I2-2, I2-3, and I2-4. The four ion implantation processes for forming the doped region 102 are merely exemplary and are by no means restrictive. In addition to the first to fourth ion implantation processes I2-1, I2-2, I2-3, and I2-4, additional ion implantation processes may be implemented to form the doped region 102. Before the ion implantation processes I2-1, I2-2, I2-3, and I2-4, between two ion implantation processes in the ion implantation processes I2-1, I2-2, I2-3, and I2-4, or after the ion implantation processes I2-1, I2-2, I2-3, and I2-4, (one or more) ion implantation processes in addition to the ion implantation processes I2-1, I2-2, I2-3, and I2-4 may be implemented. For example, one or more semiconductor layers may be formed on the surface 1061 of the semiconductor layer 1041, and two or more additional ion implantation processes may be performed to introduce dopants into each of the one or more semiconductor layers on the semiconductor layer 1041. For example, this allows for flexible design of the vertical doping concentration profile for profile depth and profile shape. For example, the parameters of the additional ion implantation process, such as ion implantation energy and / or ion implantation dose and / or ion implantation tilt angle for the vertical axis, may be similar to the first to fourth ion implantation processes I2-1, I2-2, I2-3, I2-4.

[0063] Figure 4 The schematic cross-sectional view of illustrates an example of a configuration of a semiconductor device 100, which includes a superjunction structure SJ, which includes a p-doped region 1021 that is laterally adjacent to an n-doped region 1022. By the process example for forming the doped region 102 described herein, the p-doped region 1021 and / or the n-doped region 1022 can be formed. The semiconductor device 100 is schematically illustrated as a vertical power semiconductor device, which includes: a first load contact LC1, such as a source or emitter electrode, is electrically coupled to a transistor cell region 114 via a first side 1151 of the semiconductor device 100. The transistor cell region 114 is illustrated in a simplified manner by a dashed box, and it can include any design of a transistor cell, such as a planar or trench gate design. The superjunction structure SJ is arranged between the transistor cell region 114 and the second side 1152 of the semiconductor device 100. A control electrode contact C (eg, a gate pad) is electrically coupled to the transistor cell region via a first side 1051 of the semiconductor device 100. A second load contact LC2 (eg, a drain or collector electrode) is electrically coupled to the semiconductor body 104 via a second side 1152 of the semiconductor device 100.

[0064] Figure 51 illustrates another example of a semiconductor device 100 configured as an n-channel trench gate MOSFET, which includes an n-doped current extension region 116, which is adjacent to a trench gate structure 118, and the trench gate structure 118 includes a gate dielectric 1181 and a gate electrode 1182. The gate electrode 1182 is electrically connected to the control contactor C. The first load contact LC1 (e.g., source contact) is electrically coupled to the n-channel trench gate MOSFET via the first side 1151 of the semiconductor device 100. + The source region 120 and the p-doped body region 122 are doped. A second load contact LC2 (eg, a drain electrode) is electrically coupled to the semiconductor body 104 via a second side 1152 of the semiconductor device 100 .

[0065] Figure 6 Schematic illustration of simulated channeling profile of aluminum in the c-axis of a SiC semiconductor body at 60keV ion implantation energy. Concentration profile C1 is caused by high dose (1E15 cm-2) implantation and shows a clear channeling peak at a depth of about 90nm. Concentration profile C3 is based on the same simulation parameters as concentration profile C1, but at one-tenth the dose (i.e., 1E14 cm-2). Here, a more terrace-like profile is achieved. Concentration profile C2 is based on concentration profile C3, but multiplied by a factor of 10. Here, it is assumed that ion implantation at a dose of 1E14 cm-2 is repeated 10 times, and between each implantation process, annealing of the crystal is performed to retain the crystal structure and allow constant channeling performance. The dotted area shows how much aluminum concentration still exists at a greater depth, and the grid area shows how much concentration is reduced in a random depth compared to concentration profile C1. The illustrated separation into ten consecutive implantation and annealing steps is for illustrative purposes only. The frequency with which the channeling implant will be divided into individual steps depends, for example, on the needs of the technology itself.

[0066] The description and drawings illustrate only the principles of the present disclosure. In addition, all examples described herein are primarily intended to be used for illustrative purposes only to help readers understand the principles and concepts of the present disclosure contributed by (one or more) inventors to promote the art. All statements describing the principles, aspects and examples of the present disclosure and specific examples of the present disclosure herein are intended to include their equivalents.

[0067] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A doped region (102) is formed in a semiconductor body (104), wherein forming the doped region (102) comprises: introducing a first dopant (1081) through a first surface (106) of the semiconductor body (104) at a first vertical reference level (L1) by a first ion implantation process (I2-1); thereafter applying a first thermal treatment (T1) to the semiconductor body (104); and thereafter A second dopant (1082) is introduced through a second ion implantation process (I2-2) at the first vertical reference level (L1) through the first surface (106) of the semiconductor body (104), wherein the atomic number of the first dopant (1081) is equal to the atomic number of the second dopant (1082), the ion implantation energy (E2) of the second ion implantation process (I2-2) differs from the ion implantation energy (E1) of the first ion implantation process (I2-1) by less than 20%, and the ion implantation dose (D2) of the second ion implantation process (I2-2) differs from the ion implantation dose (D1) of the first ion implantation process (I2-1) by less than 20%.

2. A method as claimed in the preceding claim, wherein the second dopant (1082) is implanted along a beam axis (1102) which deviates by at most 1.5° relative to a main crystal axis of the semiconductor body (104) along which the channeling effect occurs.

3. A method as claimed in any one of the preceding claims, wherein the first dopant (1081) is implanted along a beam axis (1101), which deviates by at most 1.5° relative to a main crystal axis of the semiconductor body (104) along which the channel effect occurs.

4. A method for manufacturing a semiconductor device, the method comprising: A doped region (102) is formed in a semiconductor body (104), wherein forming the doped region (102) comprises: introducing a first dopant (1081) through a first surface (106) of the semiconductor body (104) at a first vertical reference level (L1) by means of a first ion implantation process (I2-1), wherein the first dopant (1081) is implanted along a beam axis (1101) which deviates by at most 1.5° with respect to a main crystal axis of the semiconductor body (104) along which a channeling effect occurs; thereafter applying a first thermal treatment (T1) to the semiconductor body (104); and thereafter A second dopant (1082) is introduced through the first surface (106) of the semiconductor body (104) at the first vertical reference level (L1) by a second ion implantation process (I2-2), wherein the second dopant (1082) is implanted along a beam axis (1102) that deviates by at most 1.5° relative to a main crystal axis of the semiconductor body (104) along which a channel effect occurs.

5. The method as claimed in any one of the preceding claims 2 to 4, wherein the semiconductor body is a SiC semiconductor body and the main crystal axis is the c-axis.

6. A method as claimed in claim 4 or claim 5 as defined by claim 4, wherein The atomic number of the first dopant (1081) is different from the atomic number of the second dopant (1082), and / or The ion implantation energy (E2) of the second ion implantation process (I2-2) differs from the ion implantation energy (E1) of the first ion implantation process (I2-1) by less than 20%, and / or The ion implantation dose (D2) of the second ion implantation process (I2-2) differs from the ion implantation dose (D1) of the first ion implantation process (I2-1) by less than 20%.

7. The method according to any of the preceding claims, wherein the second ion implantation energy (E2) is less than the first ion implantation energy (E1).

8. The method according to any one of the preceding claims, wherein the second ion implantation dose (D2) is less than the first ion implantation dose (D1).

9. The method according to any one of the preceding claims, wherein an ion implantation mask of the first ion implantation process (I2-1) is reused for the second ion implantation process (I2-2).

10. The method according to any one of the preceding claims, further comprising: After the second ion implantation process (I2-2), an activation heat treatment is applied to the semiconductor body (104), wherein the activation heat treatment is configured to electrically activate the first and second dopants (1081, 1082), and wherein a maximum temperature of the activation heat treatment is greater than a maximum temperature of the first heat treatment (T1).

11. The method according to the preceding claim, wherein the maximum temperature of the activation thermal treatment is more than 400 K greater than the maximum temperature of the first thermal treatment.

12. The method according to any of the preceding claims, wherein the maximum temperature of the first thermal treatment is configured to anneal crystal damage caused by the first ion implantation process (I2-1).

13. The method according to any of the preceding claims, wherein the semiconductor body (104) is a SiC semiconductor body and the maximum temperature of the first thermal treatment (T1) has a value from 600°C to 1200°C.

14. The method according to any one of the preceding claims, further comprising: An ion implantation process other than the first ion implantation process and the second ion implantation process (I2-1, I2-2), wherein each of the ion implantation processes other than the first ion implantation process and the second ion implantation process (I2-1, I2-2) is performed before the first ion implantation process (I2-1) or after the second ion implantation process (I2-2).

15. The method according to any one of the preceding claims, wherein the doped region (102) is a p-doped region (1022) or an n-doped region (1021) of a superjunction structure (SJ), the superjunction structure (SJ) comprising the p-doped region (1022) laterally adjacent to the n-doped region (1021).

16. The method according to the preceding claim, wherein forming the super junction structure (SJ) further comprises: forming a semiconductor layer (1041) on the first surface (106) of the semiconductor body (104); and introducing a third dopant (1083) through the surface (1061) of the semiconductor layer (1041) at a second vertical reference level (L2) through a third ion implantation process (I2-3); thereafter applying a second heat treatment (T2) to the semiconductor body (104) and the semiconductor layer (1041); and thereafter Through a fourth ion implantation process (I2-4), a fourth dopant (1084) is introduced through the surface (1061) of the semiconductor layer (1041) at the second vertical reference level (L2), wherein the atomic number of the third dopant (1083) is equal to the atomic number of the fourth dopant (1084), the ion implantation energy (E4) of the fourth ion implantation process (I2-4) differs from the ion implantation energy (E3) of the third ion implantation process (I2-3) by less than 20%, and the ion implantation dose (D4) of the fourth ion implantation process (I2-4) differs from the ion implantation dose (D3) of the third ion implantation process (I2-3) by less than 20%.

17. The method of claim 15, wherein forming the super junction structure (SJ) further comprises: forming a semiconductor layer (1041) on the first surface (106) of the semiconductor body (104); and introducing a third dopant (1083) through the surface (1061) of the semiconductor layer (1041) at a second vertical reference level (L2) by a third ion implantation process (I2-3); and introducing a fourth dopant (1084) through the surface (1061) of the semiconductor layer (1041) at the second vertical reference level (L2) by a fourth ion implantation process (I2-4), Wherein the introduction of both the first dopant (1081) and the third dopant (1083) is performed before the first heat treatment (T1), and wherein the introduction of both the second dopant (1082) and the fourth dopant (1084) is performed after the first heat treatment (T1).

18. A method as claimed in any one of claims 16 or 17, wherein The first dopant (1081) and the second dopant (1082) together form the n-doped region (1022) of the super junction structure (SJ); and The third dopant (1083) and the fourth dopant (1083) together form the p-doped region (1022) of the super junction structure (SJ).

19. The method according to any of the preceding claims, wherein the doped region (102) is an n-doped current extension region (116) of a power semiconductor device comprising a gate trench, the current extension region adjoining a bottom side of the gate trench.

20. The method according to any one of the preceding claims, wherein each of the ion implantation energy (E1) of the first ion implantation process (I2-1) and the ion implantation energy (E2) of the second ion implantation process (I2-2) is greater than 1000 keV.

21. A method as claimed in any of the preceding claims, wherein the temperature of the semiconductor body (104) during the introduction of the first dopant (1081) is less than the temperature of the semiconductor body (104) during the introduction of the second dopant (1082).

22. A semiconductor device (100), comprising: A doped region (102) formed by a method as claimed in any preceding claim.

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