Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. A method according to one embodiment includes forming a plurality of fins protruding from a substrate; forming a first dummy gate stack and a second dummy gate stack over the fin; and depositing a capping structure over the fin. A first portion of the capping structure extends between the first dummy gate stack and the second dummy gate stack. The method also includes etching the fin to form a first trench between the first dummy gate stack and the first portion of the cap structure and a second trench between the second dummy gate stack and the first portion of the cap structure; removing the covering structure; and epitaxially growing a first epitaxial feature from the first trench and epitaxially growing a second epitaxial feature from the second trench. The first epitaxial feature and the second epitaxial feature merge after rising above the top surface of the fin.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as IC technology moves toward smaller nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of a channel region. Fin field effect transistors (FinFETs) and multi-bridge channel (MBC) transistors are examples of multi-gate devices, which have become popular and promising candidate devices for high performance and low leakage applications. FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., a gate wraps around the top and sidewalls of a semiconductor material "fin" extending from a substrate). MBC transistors have a gate structure that can extend partially or completely around a channel region to provide access to a channel region on two or more sides. Because its gate structure surrounds the channel region, MBC transistors can also be referred to as gate-around transistors (SGTs) or gate-all-around (GAA) transistors.

[0004] In order to improve the performance of multi-gate transistors, efforts have been invested in developing epitaxial features in the source / drain regions.While conventional epitaxial features in the source / drain regions are generally adequate for their intended purpose, they are not satisfactory in all respects. Summary of the invention

[0005] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a plurality of fins protruding from a substrate, each of the fins extending longitudinally in a first direction; forming a first dummy gate stack and a second dummy gate stack above the fins, each of the first dummy gate stack and the second dummy gate stack extending longitudinally in a second direction different from the first direction; depositing a capping structure above the fin, wherein in a top view of the semiconductor device, a first portion of the capping structure extends longitudinally in the second direction between the first dummy gate stack and the second dummy gate stack; etching the fin along the first direction in a cross-sectional view of the semiconductor device using the capping structure as an etching mask to form a first trench between the first dummy gate stack and the first portion of the capping structure and a second trench between the second dummy gate stack and the first portion of the capping structure; removing the capping structure; epitaxially growing a first epitaxial component from the first trench and epitaxially growing a second epitaxial component from the second trench, the first epitaxial component and the second epitaxial component merging after rising above a top surface of the fin to form a merged epitaxial component; and replacing the first dummy gate stack and the second dummy gate stack with a first metal gate stack and a second metal gate stack, respectively.

[0006] Other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: patterning a substrate to form a fin, the fin having a first source / drain region, a second source / drain region, and a channel region between the first source / drain region and the second source / drain region; forming a gate stack above the channel region of the fin; in a top view of the semiconductor device, forming a covering structure having a first portion next to the gate stack and a second portion extending parallel to the gate stack and across the first source / drain region; in a cross-sectional view of the semiconductor device cut along the fin, recessing the first source / drain region and the second source / drain region of the fin to form a first trench and a second trench in the first source / drain region, and forming at least a third trench in the second source / drain region; and epitaxially growing a first epitaxial component from the first trench, epitaxially growing a second epitaxial component from the second trench, and epitaxially growing a third epitaxial component from the third trench, wherein the first epitaxial component and the second epitaxial component merge above the top surface of the fin.

[0007] Still other embodiments of the present application provide a semiconductor device comprising: a substrate; a plurality of fins protruding from the substrate, each of the fins extending longitudinally in a first direction; a gate stack disposed above the fins, the gate stack extending longitudinally in a second direction perpendicular to the first direction; a first epitaxial component disposed on a first side of the gate stack; and a second epitaxial component disposed on a second side of the gate stack, wherein: the first epitaxial component extends continuously so that each of the fins is located directly below the first epitaxial component, and in a cross-sectional view of the semiconductor device cut along one of the fins, the first epitaxial component includes a first lower portion extending below a top surface of one of the fins, a second lower portion extending below the top surface of one of the fins, and a connecting portion adjacent to the first lower portion and the second lower portion above the top surface of one of the fins. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A flow chart of a method for forming a semiconductor device according to one or more aspects of an embodiment of the present disclosure is shown.

[0010] Figure 7 , Figure 8 and Fig.15 The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Figure 1 A perspective view of the method during the bonding process.

[0011] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.16 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 , Fig.32 , Fig.33 , Fig.34 , Fig.35 , Fig.36 , Fig.37 , Fig.38 , Fig.39 , Fig.40 , Fig.41A , Fig.41B , Fig.41C , Fig.42A , Fig.42B and Fig.42C The workpieces according to one or more aspects of the embodiments of the present disclosure are respectively shown in FIG. Figure 1 Top view and cross-sectional views during the manufacturing process of the method.

[0012] Fig.17 It is shown that one or more aspects of the embodiments of the present disclosure can be Figure 1 The method is used during the epitaxial growth system of the manufacturing process. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0015] In addition, when "about," "approximately," or the like is used to describe a numerical value or a range of numerical values, as understood by one of ordinary skill in the art, the term is intended to encompass numerical values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the numerical values, the numerical value or range of numerical values ​​encompasses a reasonable range that includes the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer known to one of ordinary skill in the art is + / - 15%. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] The disclosed embodiments generally relate to multi-gate transistors and methods of fabrication, and more particularly to epitaxial features (also referred to as source / drain epitaxial features or source / drain features) developed in source / drain regions of a multi-gate transistor having multiple fins. The source / drain region may refer to a source or a drain, either individually or collectively depending on the context.

[0017] Source / drain features epitaxially grown on multiple fins of a multi-gate transistor can be merged. The merged source / drain features confine subsequently formed source / drain contacts to the merged source / drain features. However, the spacing between multiple fins and other factors may cause the source / drain features to be incompletely merged, so that some of the source / drain features may be merged, while gaps may still exist between some other unmerged source / drain features. The source / drain contacts may penetrate the gaps and reach down to the isolation features between the fins, which may cause device degradation and limitations for device current adjustment. In some embodiments of the present disclosure, the profile of the source / drain region is adjusted before the source / drain features are epitaxially grown to improve the lateral merging of adjacent source / drain features.

[0018] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 1 1 is a flow chart illustrating a method 100 of forming a semiconductor device from a workpiece according to an embodiment of the present disclosure. The method 100 is merely an example and is not intended to limit the disclosed embodiments to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Figures 2 to 42C Describing method 100, Figures 2 to 42C is based on Figure 11 and 2. The workpiece 200 of the embodiment of the method 100 in FIG. 1 is a perspective view, a top view and a cross-sectional view at different manufacturing stages. Because the workpiece 200 will be manufactured into a semiconductor device, the workpiece 200 may be referred to as a semiconductor device 200 in this article as the context requires. For avoidance, Figures 2 to 42C The X, Y and Z directions are perpendicular to each other. Throughout the disclosed embodiments, the same reference numerals represent the same components unless otherwise specified. It should also be understood that although Figures 2 to 42C The formation of FinFETs is shown as examples of multi-gate transistors, but these examples are provided for illustrative purposes only, and one of ordinary skill in the art will appreciate that the presently disclosed embodiments also contemplate the formation of MBC transistors (eg, SGT transistors or GAA transistors).

[0019] refer to Figure 1 and Figure 2 , the method 100 includes a block 102, wherein a mask layer 204 is formed over a substrate 202 in order to fabricate a semiconductor device 200. The mask layer 204 is formed by, for example, thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other suitable method. In some embodiments, the substrate 202 is, for example, a substrate having a thickness of about 1×10 15 cm -3 About 2×10 15 cm -3 In other embodiments, the substrate 202 is a p-type silicon substrate having an impurity concentration in the range of about 1×10 15 cm -3 About 2×10 15 cm -3 . Alternatively, substrate 202 may include: another elemental semiconductor such as germanium; a compound semiconductor including IV-IV compound semiconductors such as SiC and SiGe, III-V compound semiconductors such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or a combination thereof. In one embodiment, substrate 202 is a silicon layer of a SOI (silicon on insulator) substrate. An amorphous substrate such as amorphous Si or amorphous SiC or an insulating material such as silicon oxide may also be used as substrate 202. Substrate 202 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type conductivity).

[0020] In some embodiments, the mask layer 204 includes, for example, a pad oxide (e.g., silicon oxide) layer 206 and a silicon nitride mask layer 208. The pad oxide layer 206 may be formed by using a thermal oxidation or CVD process. The silicon nitride mask layer 208 may be formed by CVD, plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure CVD (LPCVD), high density plasma CVD (HDPCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), such as sputtering methods and / or other processes. In some embodiments, the thickness of the pad oxide layer 206 is in the range of about 2 nm to about 15 nm, and the thickness of the silicon nitride mask layer 208 is in the range of about 2 nm to about 50 nm.

[0021] A mask pattern 210 is further formed over the mask layer 204. The mask pattern 210 is, for example, a resist pattern formed by a photolithography operation. By using the mask pattern 210 as an etching mask, a hard mask pattern of the pad oxide layer 206 and the silicon nitride mask layer 208 is formed. In some embodiments, the width of the hard mask pattern is in the range of about 5 nm to about 40 nm. In certain embodiments, the width of the hard mask pattern is in the range of about 7 nm to about 12 nm.

[0022] refer to Figure 1 and Figure 3 , the method 100 includes a frame 104, in which the substrate 202 is patterned into a plurality of fins 212 by using a hard mask pattern as an etching mask. The patterning of the substrate 202 may include an etching process, such as a dry etching method and / or a wet etching method, to form a groove 214. The height of the fin 212 may be in the range of about 20nm to about 300nm. In some embodiments, the height is in the range of about 30nm to about 60nm. When the height of the fin 212 is not uniform, the height from the substrate can be measured from a plane corresponding to the average height of the fin 212. The width of each of the fins 212 may be in the range of about 7nm to about 15nm.

[0023] In some embodiments, a bulk silicon wafer is used as substrate 202. In some embodiments, other types of substrates may be used as substrate 202. For example, a silicon-on-insulator (SOI) wafer may be used as a starting material, and an insulating layer of the SOI wafer constitutes substrate 202, and a silicon layer of the SOI wafer is used for fins 212.

[0024] Still reference Figure 3, nine fins 212 are disposed above the substrate 202. However, the number of fins is not limited to nine. There may be as few as one fin and more than nine fins. In addition, one or more dummy fins may be disposed adjacent to the side of the fin to improve pattern fidelity in the patterning process. In some embodiments, the width of each fin 212 is in the range of about 5nm to about 40nm, and in other embodiments, in the range of about 7nm to about 15nm. In some embodiments, the width of the groove 214 between adjacent fins is in the range of about 5nm to about 80nm, and in other embodiments, in the range of about 7nm to about 15nm. However, those skilled in the art will appreciate that the dimensions and values ​​cited throughout the specification are merely exemplary and may be changed to accommodate integrated circuits of different sizes.

[0025] refer to Figure 1 and Figure 4 , method 100 includes frame 106, in which isolation features 216 are formed in the trenches 214 between the fins 212 and above the fins 212, so that the fins 212 are buried in the isolation features 216. The isolation features 216 are also called shallow trench isolation (STI) features. The isolation features 216 include one or more insulating material layers, such as silicon oxide, silicon oxynitride, or silicon nitride, formed by LPCVD (low pressure chemical vapor deposition), plasma CVD, or flowable CVD. In flowable CVD, a flowable dielectric material is deposited instead of silicon oxide. Flowable dielectric materials, as the name implies, can "flow" during deposition to fill gaps or spaces with a high aspect ratio. Typically, various chemicals are added to the silicon-containing precursor to allow the deposited film to flow. In some embodiments, hydrogenated nitrogen bonding is added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include silicates, siloxanes, methyl silsesquioxane (MSQ), hydrogen silsesquioxane (HSQ), MSQ / HSQ, perhydrosilazane (TCPS), perhydropolysilazane (PSZ), tetraethyl orthosilicate (TEOS) or silylamines, such as trimethylsilylamine (TSA). These flowable silicon oxide materials are formed in multiple operation processes. After the flowable film is deposited, it is cured and then annealed to remove undesirable elements. When the undesirable elements are removed, the flowable film densifies and shrinks. In some embodiments, multiple annealing processes are implemented. The flowable film is cured and annealed more than once. The flowable film can be doped with boron and / or phosphorus. In some embodiments, the isolation member 216 is formed by one or more layers of SOG, SiO, SiON, SiOCN and / or fluorine-doped silicate glass (FSG).

[0026] refer to Figure 1 and Figure 5The method 100 includes block 108, where a planarization operation is performed to remove a portion of the isolation feature 216. The planarization operation may include a chemical mechanical polishing (CMP) and / or an etch back process. The mask layer 204 may be removed, exposing an upper portion of the fin 212.

[0027] refer to Figure 1 and Figure 6 , method 100 includes frame 110, wherein the planarized isolation feature 216 is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof. After the recessing, the fin 212 rises above the isolation feature 216. In some embodiments, the partial removal of the isolation feature 216 is implemented using a suitable etching process. For example, a wet etching process can be implemented, such as by immersing the substrate in hydrofluoric acid (HF) or phosphoric acid (H3PO4). On the other hand, the partial removal of the isolation feature 216 can be implemented using a dry etching process. For example, a dry etching process can be used, using CHF3 or BF3 as an etching gas. Figure 7 2 depicts a perspective view of the semiconductor device 200 showing the fin 212 rising above the isolation feature 216. The exposed portion of the fin 212 includes a channel region (on which a gate structure will be formed) and a source / drain region (in which an epitaxial feature (also referred to as a source / drain epitaxial feature or a source / drain feature) will be formed). In the disclosed embodiments, source and drain are used interchangeably, and the term source / drain refers to any one of the source and the drain.

[0028] refer to Figure 1 and Figures 8 to 11 The method 100 includes block 112 where a dummy gate stack 230 is formed over a channel region of the fin 212 . Figure 8 shows a perspective view of a semiconductor device 200, Fig. 9 A top view of a semiconductor device 200 is shown, and Fig.10 and Fig.11 Shown respectively through Figure 8 AA and BB lines in FIG. In some embodiments, a gate replacement process (or gate-last process) is employed, wherein the dummy gate stack 230 is used as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are also possible.

[0029] Forming the dummy gate stack 230 may include: depositing layers in the dummy gate stack 230; and patterning the layers. Figures 8 to 11, a dummy dielectric layer 226, a dummy electrode layer 228, and a gate top hard mask layer 232 may be blanket deposited over the semiconductor device 200. In some embodiments, the dummy dielectric layer 226 may be formed on the fin 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable processes. In some instances, the dummy dielectric layer 226 may include silicon oxide. Thereafter, the dummy electrode layer 228 may be deposited over the dummy dielectric layer 226 using a CVD process, an ALD process, or other suitable processes. In some instances, the dummy electrode layer 228 may include polysilicon. For patterning purposes, the gate top hard mask layer 232 may be deposited on the dummy electrode layer 228 using a CVD process, an ALD process, or other suitable processes. The gate top hard mask layer 232, the dummy electrode layer 228, and the dummy dielectric layer 226 may then be patterned to form a dummy gate stack 230. For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 232 may include a silicon oxide layer 234 and a silicon nitride layer 236 above the silicon oxide layer 234.

[0030] Still reference Figure 1 and Figures 8 to 11 , the method 100 includes a frame 114, wherein a gate spacer layer 238 is deposited over the dummy gate stack 230. In some embodiments, the gate spacer layer 238 is conformally deposited over the workpiece 200, including over the top surface and sidewalls of the dummy gate stack 230. The term "conformally" may be used herein to facilitate describing a layer having a substantially uniform thickness over various regions. The gate spacer layer 238 may be a single layer or multiple layers. At least one layer of the gate spacer layer 238 may include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. The gate spacer layer 238 may be deposited over the dummy gate stack 230 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, an ALD process, or other suitable process. In one embodiment, the gate spacer layer 238 includes a first layer and a second layer disposed over the first layer. The first layer may include silicon oxynitride, and the second layer may include silicon nitride.

[0031] Since the dummy gate stack 230 and the gate spacer layer 238 are formed above the fin 212, the fin 212 is divided into a channel region 212C located below the dummy gate stack 230 (and the gate spacer layer 238) and a source / drain region 212SD not located below the dummy gate stack 230. Fig.11 . The channel region 212C is adjacent to the source / drain region 212SD, wherein each channel region 212C is disposed between two source / drain regions 212SD along the X direction. Opposite sidewalls of the gate spacer layer 238 define a trench 240 between adjacent dummy gate stacks 230. The width of the trench 240 along the X direction is denoted as W0. In some embodiments, the width W0 of the trench 240 may be in the range of about 40 nm to about 200 nm. Fig.11 Also shown are a dashed line T216 marking the location of the top surface of isolation feature 216 and a dashed line T202 marking the location of the top surface of substrate 202 .

[0032] refer to Figure 1 and Figure 12 to Figure 13 The method 100 includes block 116 , in which a source / drain capping structure (or simply a capping structure) 244 is formed on the semiconductor device 200 . Fig.12 A top view of a semiconductor device 200 is shown, and Fig.13 Shown through Fig.12 BB line cutting in the cross-sectional view. In some embodiments, the capping structure 244 may be a patterned resist layer or a patterned hard mask. In some embodiments, a bottom anti-reflective coating (BARC) layer 242 is first deposited on the semiconductor device 200, and the BARC layer 242 fills the groove 240 between adjacent pseudo gate stacks 230. Subsequently, a capping structure 244 is formed on the BARC layer 242. In one example, the BARC layer 242 includes an organic BARC material formed by a spin coating technique, and the capping structure 244 is a patterned hard mask formed by a patterned hard mask layer. In the illustrated embodiment, the top surface of the BARC layer 242 is coplanar with the top surface of the pseudo gate stack 230, so that the pseudo gate stack 230 is still exposed. In other embodiments, the BARC layer 242 may cover the semiconductor device 200, wherein the pseudo gate stack 230 is covered below the BARC layer 242.

[0033] refer to Fig.12, the covering structure 244 includes at least one base portion 244a and at least one protruding portion 244b. In the illustrated embodiment, the covering structure 244 includes two base portions 244a sandwiching the dummy gate stack 230 in the Y direction and a protruding portion 244b connecting the two base portions 244a. Each of the base portions 244a extends longitudinally in the same direction as the fin 212 along the X direction, and the protruding portion 244b extends longitudinally in the same direction as the dummy gate stack 230 in the Y direction. One or more base portions 244a provide mechanical support mainly from the gate side to the protruding portion 244b. Therefore, the base portion 244a is also referred to as the gate side portion 244a. The protruding portion 244b protrudes from the base portion 244a and extends across the source / drain region of the fin 212 in the Y direction. Therefore, as the context requires, the protruding portion 244b may be referred to as the source / drain covering portion 244b herein.

[0034] With ever decreasing gate-to-gate spacing and increasing number of fins formed in one active area, the shape of the source / drain capping portion 244b in the top view may resemble a long and thin line, which is susceptible to damage during manufacturing operations and may become easily delaminated if the base portion 244a is not present to improve the mechanical integrity of the capping structure 244. In the illustrated embodiment, there are two base portions 244a connected to both ends of the source / drain capping portion 244b. In other embodiments, there may be a single base portion 244a connected to one end of the source / drain capping portion 244b, which will also be discussed in further detail below.

[0035] refer to Fig.13, the source / drain covering portion 244b has a width denoted as W1, and W1 is less than the spacing W0 between adjacent dummy gate stacks 230. The source / drain covering portion 244b is positioned between adjacent dummy gate stacks 230, leaving a first opening with a width W2 on one side of the source / drain covering portion 244b and a second opening with a width W3 on the other side of the source / drain covering portion 244b. That is, W0 = W1 + W2 + W3. In some embodiments, the source / drain covering portion 244b is positioned at the center of the source / drain region 212SD, where W2 = W3. In some embodiments, the source / drain covering portion 244b is closer to one of the adjacent dummy gate stacks 230, where W2 < W3 or W2 > W3. In various embodiments, each of the widths W2 and W3 can be at least about 10% of the width W0. If W2 and W3 are less than about 10% of the width W0, the openings may become too small for a subsequent etching process to recess the fins 212 in the source / drain region 212SD. In some embodiments, the width W1 can be at least about 10% of the width W0. If W1 is less than about 10% of the width W0, the source / drain covering portion 244b may be too thin and become prone to peeling during manufacturing operations.

[0036] Reference Figure 1 and Fig.14 , method 100 includes block 118, wherein an etching process is implemented through an opening in the source / drain region 212SD not covered by the dummy gate stack 230 (having a gate spacer layer 238) and the source / drain covering portion 244b. The corresponding source / drain regions of the fins 212 are recessed to form source / drain trenches 250. In some embodiments, the source / drain regions of the fins 212 are etched by a dry etching or a suitable etching process to form the source / drain trenches 250. For example, the dry etching process can implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases, and / or a plasma and / or a combination thereof. In the source / drain region 212SD where there is no source / drain covering portion 244b, such as Fig.14 the left and right ones of the source / drain region 212SD in Fig.14In the central source / drain region 212SD, two small source / drain trenches 250b and 250c with a first opening width W2 and a second opening width W3 are formed, respectively. The volume of the source / drain trench 250a is larger than any one of the source / drain trenches 250b and 250c. In addition, the volume of the source / drain trench 250a is larger than the sum of the source / drain trenches 250b and 250c. Further, due to the etchant loading effect associated with the larger opening, the depth of the source / drain trench 250a is greater than the source / drain trenches 250b and 250c. In the illustrated embodiment, each of the source / drain trenches 250a, 250b, 250c extends below the dotted line T216. In some other embodiments, the source / drain trench 250 a extends below the dotted line T216 , while the source / drain trenches 250 b and 250 c remain above the dotted line T216 .

[0037] refer to Figure 1 and Figure 15 to Figure 16 The method 100 includes block 120 , where the BARC layer 242 and the capping structure 244 are removed from the semiconductor device 200 . Fig.15 A perspective view of a semiconductor device 200 is shown, and Fig.16 Shown through Fig.15 The operation in box 120 may include any suitable etching process, including wet etching, dry etching, reactive ion etching, ashing, and / or other suitable techniques. At the end of the operation in box 118, the middle portion of the fin 212 between the source / drain trenches 250b and 250c and the other portion of the fin 212 below the dummy gate stack 230 have a flush top surface.

[0038] refer to Figure 1 and Fig.17 , the method 100 includes block 122, where an epitaxial growth process is performed to form source / drain features in the semiconductor device 200 by the epitaxial growth system 300. The semiconductor device 200 is placed on a mounting platform 321 to position and control the substrate 202 and the fin 212 during the epitaxial growth process. Fig.17 The cross-sectional view of the semiconductor device 200 is taken along Fig.15 The CC line in FIG. 2 cuts through the source / drain region of the fin 212 .

[0039] Epitaxial growth system 300 may be used to receive precursor materials from first precursor delivery system 305, second precursor delivery system 306, third precursor delivery system 308, and fourth precursor delivery system 310, and form material layers (e.g., source / drain features) on fin 212. In an embodiment, first precursor delivery system 305, second precursor delivery system 306, third precursor delivery system 308, and fourth precursor delivery system 310 work in conjunction with one another to supply various different precursor materials to epitaxial growth chamber 303 in which semiconductor device 200 is placed. First precursor delivery system 305, second precursor delivery system 306, third precursor delivery system 308, and fourth precursor delivery system 310 may have similar physical components to one another.

[0040] For example, first precursor delivery system 305, second precursor delivery system 306, third precursor delivery system 308, and fourth precursor delivery system 310 may each include gas system 307 and flow controller 309. In embodiments where the first precursor is stored in a gaseous state, gas system 307 may supply the first precursor to epitaxial growth chamber 303.

[0041] Gas system 307 may be a container, such as a gas tank, located near epitaxial growth chamber 303 or at a location away from epitaxial growth chamber 303. In another embodiment, gas system 307 may be a facility that independently prepares a first precursor and delivers the first precursor to flow controller 309. Any suitable source for the first precursor may be used as gas system 307, and all such sources are fully intended to be included within the scope of the embodiment. Gas system 307 may supply the desired precursor to flow controller 309. Flow controller 309 may be used to control the flow of the precursor to precursor gas controller 313, and ultimately control the flow to epitaxial growth chamber 303, thereby also helping to control the pressure within epitaxial growth chamber 303. Flow controller 309 may be, for example, a proportional valve, a regulating valve, a needle valve, a pressure regulator, a mass flow controller, a combination of these, and the like. Any suitable method for controlling and regulating the flow of the first precursor may be utilized, and all such components and methods are fully intended to be included within the scope of the embodiment.

[0042] In addition, in embodiments where the first precursor is stored in a solid or liquid state, the gas system 307 may also store or receive a carrier gas, and the carrier gas may be introduced into a precursor tank (not shown separately) that stores the first precursor in a solid or liquid state. The carrier gas is then used to propel and transport the first precursor as it evaporates or sublimates to the gas section of the precursor tank before being sent to the precursor gas controller 313. Any suitable method and combination of units may be utilized to provide the first precursor, and all such combinations of units are fully intended to be included within the scope of the embodiments.

[0043] The first precursor delivery system 305, the second precursor delivery system 306, the third precursor delivery system 308, and the fourth precursor delivery system 310 can supply their respective precursor materials into the precursor gas controller 313. The precursor gas controller 313 connects and isolates the first precursor delivery system 305, the second precursor delivery system 306, the third precursor delivery system 308, and the fourth precursor delivery system 310 from the epitaxial growth chamber 303 to deliver the desired precursor materials to the epitaxial growth chamber 303 (discussed further below).

[0044] The precursor gas controller 313 may include devices such as valves, flow meters, sensors, etc. to control the delivery rate of each of the precursors, and may be controlled by instructions received from the control unit. The precursor gas controller 313 (upon receiving instructions from the control unit) may open and close valves to connect one or more of the first precursor delivery system 305, the second precursor delivery system 306, the third precursor delivery system 308, and the fourth precursor delivery system 310 to the epitaxial growth chamber 303, and direct the desired precursor material through the manifold 316, and into the epitaxial growth chamber 303, and to the nozzle 317. The nozzle 317 may be used to disperse one or more of the selected precursor materials into the epitaxial growth chamber 303, and may be designed to uniformly disperse the precursor materials to minimize undesirable process conditions that may be caused by uneven dispersion. In an embodiment, the nozzle 317 may have a circular design with openings evenly distributed around the nozzle 317 to allow the desired precursor material to be dispersed into the epitaxial growth chamber 303.

[0045] As one of ordinary skill in the art will appreciate, the introduction of precursor materials into epitaxial growth chamber 303 through a single showerhead 317 or through a single introduction point as described above is intended to be illustrative only and is not intended to be limiting of the embodiments. Any number of separate and independent showerheads 317 or other openings may be utilized to introduce various precursor materials into epitaxial growth chamber 303. All such combinations of showerheads and other introduction points are fully intended to be included within the scope of the embodiments.

[0046] The epitaxial growth chamber 303 can receive the desired precursor material and expose the precursor material to the fin 212, and the epitaxial growth chamber 303 can be a shape suitable for dispersing the precursor material and contacting the precursor material with the fin 212. In the illustrated embodiment, the epitaxial growth chamber 303 has cylindrical sidewalls and a bottom. The epitaxial growth chamber 303 is not limited to a cylindrical shape, and any other suitable shape, such as a hollow square tube, an octagonal shape, etc., can be utilized. In addition, the epitaxial growth chamber 303 can be surrounded by a shell 319, and the shell 319 is made of a material that is inert to various process materials. Therefore, although the shell 319 can be any suitable material that can withstand the chemicals and pressures involved in the deposition process, in an embodiment, the shell 319 can be steel, stainless steel, nickel, aluminum, alloys of these, combinations of these, etc.

[0047] Within the epitaxial growth chamber 303, the substrate 202 may be placed on a mounting platform 321 to position and control the substrate 202 and the fins 212 during the epitaxial growth process. The mounting platform 321 may include a heating mechanism to heat the substrate 202 during the epitaxial growth process. In addition, the epitaxial growth chamber 303 and the mounting platform 321 may be part of a cluster tool system (not shown). The cluster tool system may be used in conjunction with an automated handling system to position and place the semiconductor device 200 into the epitaxial growth chamber 303 before the epitaxial growth process, position and hold the semiconductor device 200 during the epitaxial growth process, and remove the semiconductor device 200 from the epitaxial growth chamber 303 after the epitaxial growth process.

[0048] Epitaxial growth chamber 303 may also have an exhaust outlet 325 for exhaust gases to leave epitaxial growth chamber 303. A vacuum pump 323 may be connected to the exhaust outlet 325 of epitaxial growth chamber 303 to help exhaust the exhaust gases. Vacuum pump 323 (under the control of control unit 315) may also be used to reduce and control the pressure within epitaxial growth chamber 303 to a desired pressure, and may also be used to exhaust precursor materials from epitaxial growth chamber 303 in preparation for the introduction of the next precursor material.

[0049] In preparation for forming source / drain features, a first precursor material is placed into or formed by a first precursor delivery system 305. For example, in embodiments where a doped semiconductor material such as silicon phosphorus is to be grown, the first precursor material may be a silicon-containing precursor material such as dichlorosilane (DCS), although other suitable precursors such as silane (SiH4) or disilane (Si2H6) may also be utilized. All suitable precursor materials are fully intended to be included within the scope of the embodiments.

[0050] In addition, a second precursor material can be placed into or formed by the second precursor delivery system 306. In this embodiment, the second precursor can be used to provide a dopant material that complements the semiconductor material present in the first precursor material. For example, in an embodiment where a silicon layer doped with phosphorus (SiP) is to be grown as a source / drain component and the first precursor material is dichlorosilane, the second precursor material can be a material that includes a suitable dopant such as phosphorus (P). In a specific embodiment, the second precursor material is PH3. However, any suitable dopant-containing material, such as arsenic (As) or antimony (Sb), can be utilized and placed within the second precursor delivery system 306.

[0051] In addition to the first and second precursor materials used together to grow the epitaxial material (e.g., SiP), an etching precursor may also be utilized during the growth process and may be placed in the third precursor delivery system 308. In embodiments where the material to be grown will be at least partially deposited on materials other than the exposed fins 212 (such as by growing on exposed surfaces of the isolation features 216), the addition of an etching precursor will serve to remove the epitaxially grown material from these undesirable locations and help make the epitaxial growth more selective. In embodiments, the etching precursor is a precursor that will remove undesirable growth of the growing material while still allowing the desired material to grow over the fins 212, and may be an etchant such as hydrochloric acid (HCl). Other suitable etching precursors may be utilized.

[0052] Further, in order to help control the three-dimensional shape of the source / drain features during the epitaxial growth process by helping the etching efficiency of the etching precursor during the cleaning process, a forming precursor can be placed in the fourth precursor delivery system 310. In an embodiment, the forming precursor is a material that, when incorporated into the source / drain region during the cleaning process, will help amorphize and modify the crystal structure of the source / drain region that has been grown before the introduction of the forming precursor. In a specific embodiment where the growth material is silicon phosphorus, the forming precursor is a material that includes a material with a different lattice constant, such as germanium. In a specific embodiment, the forming precursor is GeH4. Other suitable forming precursors can be utilized.

[0053] Once the first precursor material, the second precursor material, the etching precursor, and the forming precursor are prepared in the first precursor delivery system 305, the second precursor delivery system 306, the third precursor delivery system 308, and the fourth precursor delivery system 310, respectively, the formation of the source / drain features can be started by the control unit sending instructions to the precursor gas controller 313 to start the first step and connecting the first precursor delivery system 305, the second precursor delivery system 306, and the third precursor delivery system 308 to the epitaxial growth chamber 303. Once connected, the first precursor delivery system 305, the second precursor delivery system 306, and the third precursor delivery system 308 can deliver the first precursor material (e.g., dichlorosilane), the second precursor material (e.g., PH3), and the etching precursor (e.g., HCl) to the showerhead 317 through the precursor gas controller 313 and the manifold 316. Showerhead 317 may then dispense the first precursor material, the second precursor material, and the etching precursor into epitaxial growth chamber 303 , wherein the first precursor material and the second precursor material may react with the exposed surfaces of fin 212 and begin growing the bulk sections of the source / drain features on the exposed sections of fin 212 .

[0054] In some embodiments, the source / drain components in the n-type transistor region and the p-type transistor region can be formed separately. For example, when epitaxial growth is used for the source / drain components in the n-type transistor region, the p-type transistor region can be covered under the resist layer, and the resist layer prevents epitaxial growth from occurring in the p-type transistor region. After forming the source / drain components in the n-type transistor region, the source / drain components in the p-type transistor region are epitaxially grown, and the n-type transistor region is covered under the resist layer, and the resist layer prevents epitaxial growth from occurring in the n-type transistor region. Optionally, the source / drain components in the p-type transistor region can be epitaxially grown before the source / drain components in the n-type transistor region.

[0055] In the n-type transistor region, the source / drain components may include Si, SiP, SiAs, SiC, SiCP, SiCAs, or other suitable semiconductor materials. The source / drain components may be doped with dopants such as arsenic (As) or phosphorus (P). In one example, the source / drain components are doped with a dopant having a value from about 5×10 20 cm -3 About 4×10 21 cm -3When the source / drain component includes carbon, the carbon atomic percentage may be in the range of about 10% to about 20%. In the p-type transistor region, the source / drain component may include SiGe, SiSn, or other suitable semiconductor materials. The source / drain component may be doped with a dopant such as germanium (Ge) or boron (B). In one example, the source / drain component may be doped with boron (B), and the source / drain component includes a carbon having a carbon content of from about 4×10 20 cm -3 About 2×10 21 cm -3 When the source / drain features include germanium, the germanium atomic percentage may be in the range of about 10 atomic % to about 60 atomic %.

[0056] Figures 18 to 20 Semiconductor device 200 is shown at the end of the epitaxial growth process in block 122 . Fig.18 is the edge of the semiconductor device 200 Fig.15 A cross-sectional view of a cut through one of the fins 212 is shown along line BB in FIG. Fig.19 is the edge of the semiconductor device 200 Fig.18 A cross-sectional view of a cut where line CC in FIG. 2 passes through one of the source / drain regions previously covered by the capping structure 244 . Fig. 20 is the edge of the semiconductor device 200 Fig.18 A cross-sectional view where line DD in FIG. 2 cuts through one of the source / drain regions that was not previously covered by the capping structure 244 .

[0057] From the larger source / drain trench 250a ( Fig.16 ) epitaxially grown source / drain features are shown as source / drain features 260a, and from smaller source / drain trenches 250b and 250c ( Fig.16 ) The epitaxially grown source / drain feature is represented as source / drain feature 260b. In the depicted embodiment, because the sum of the volumes of source / drain trenches 250b and 250c is still less than the volume of source / drain trench 250a, source / drain trenches 250b and 250c will fill up faster than source / drain trench 250a. In other words, source / drain feature 260b has a faster growth rate in the Z direction than source / drain feature 260a. Therefore, source / drain feature 260b rises above source / drain feature 260a, as shown in FIG. Fig.18As shown in . The source / drain feature 260b has two lower portions located in the source / drain trenches 250b and 250c, respectively, and a connection portion adjoining the two lower portions. The connection portion of the source / drain feature 260b is formed by merging the two lower portions in the source / drain trenches 250b and 250c after they rise above the top surface of the fin 212.

[0058] Common Reference Fig.19 and Fig. 20 , for the same amount of the first precursor material and the second precursor material that are deposited in further reaction to the source / drain regions to form epitaxial features 260a and 260b, respectively, because there is less epitaxial material filled in the smaller source / drain trenches 250b and 250c, more epitaxial material can be applied on the top portion of the source / drain feature 260b to promote vertical rise and lateral merging of the source / drain feature 260b above the fin 212. In comparison, there is more epitaxial material filled in the larger source / drain trench 250a, and less epitaxial material can be applied to the top portion of the source / drain feature 260a, so that some of the source / drain features 260a can remain separated with gaps 264 between them. In the illustrated embodiment, merged source / drain feature 260b has a flat top surface and faceted sidewall surfaces with an air gap 262 between merged source / drain feature 260b and isolation feature 216, and in comparison, source / drain feature 260a has a sawtooth top surface interrupted by gaps 264 with an air gap 262 between source / drain feature 260a and isolation feature 216. Poor lateral merging of source / drain feature 260a with gaps 264 therebetween may cause subsequently formed source / drain contacts to cut into isolation feature 216 through gaps 264 and may degrade device performance.

[0059] Fig.21 Another embodiment of the capping structure 244 at the end of the frame 116 is shown. In this embodiment, the capping structure 244 includes two base portions 244a sandwiching the dummy gate stack 230 in the Y direction and a plurality of source / drain capping portions 244b connecting the two base portions 244a and located above each of the source / drain regions between two adjacent dummy gate stacks 230. Due to the source / drain capping portions 244b, at the end of the frame 120, each source / drain region has two small source / drain trenches 250b and 250c spaced apart from each other, as shown in FIG. Fig. 22 As shown in Fig. 22 is the edge of the semiconductor device 200 Fig.21 A cross-sectional view of a cut through one of the fins 212 is shown along line BB in FIG.

[0060] The resulting structure after the epitaxial growth process at the end of block 122 is Figure 23 to Figure 25 Shown in. Fig.23 is the edge of the semiconductor device 200 Fig.21 A cross-sectional view of a cut through one of the fins 212 is shown along line BB in FIG. Fig.24 is the edge of the semiconductor device 200 Fig.23 A cross-sectional view of a cut where line CC in FIG. 2 passes through one of the source / drain regions previously covered by the capping structure 244 . Fig.25 is the edge of the semiconductor device 200 Fig.23 DD line in FIG. 2 is a cross-sectional view cut through one of the source / drain regions previously covered by the capping structure 244. A source / drain component 260b is formed in each of the source / drain regions. Each of the source / drain components 260b includes two lower portions located in the source / drain trenches 250b and 250c, respectively, and a connecting portion adjoining the two lower portions. The connecting portion of the source / drain component 260b is formed by merging the two lower portions in the source / drain trenches 250b and 250c after they rise above the top surface of the fin 212. For the same amount of the first precursor material and the second precursor material deposited to the source / drain region in further reaction to form the epitaxial feature 260b, because there is less epitaxial material to fill in the smaller source / drain trenches 250b and 250c, more epitaxial material can be applied on the top portion of the source / drain feature 260b to promote vertical rise and lateral merging of the source / drain feature 260b above the fin 212. In the illustrated embodiment, the merged source / drain feature 260b has a flat top surface and a sidewall surface with a small plane, with an air gap 262 between the merged source / drain feature 260b and the isolation feature 216.

[0061] refer to Figure 1 and Figure 26 to Figure 27 , the method 100 includes block 124, where further processes are performed. Such further processes may include, for example: depositing a contact etch stop layer (CESL) 270 over the semiconductor device 200; depositing an interlayer dielectric (ILD) layer 272 over the CESL 270; replacing the dummy gate stack 230 with a metal gate stack 274; forming source / drain contacts 280 and gate contacts 284; and forming an interconnect multilayer structure 286. Fig.26 is the edge of the semiconductor device 200 Fig.21 A cross-sectional view of a cut through one of the fins 212 is shown along line BB in FIG. Fig. 27 is the edge of the semiconductor device 200 Fig.26 A cross-sectional view of a cut where line CC in FIG. 2 passes through one of the source / drain regions previously covered by the capping structure 244 .

[0062] CESL 270 is formed before forming ILD layer 272. In some examples, CESL 270 includes silicon nitride, silicon oxynitride, and / or other materials known in the art. CESL 270 can be formed by ALD, plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition process. Then, ILD layer 272 is deposited on CESL 270. In some embodiments, ILD layer 272 includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. ILD layer 272 can be deposited by PECVD process or other suitable deposition techniques. CESL 270 is directly disposed on the top surface of source / drain features 260b (and 260a, if present). After depositing the CESL 270 and the ILD layer 272, the semiconductor device 200 may be planarized by a planarization process to expose the dummy gate stack 230. For example, the planarization process may include a chemical mechanical planarization (CMP) process.

[0063] The exposure of the dummy gate stack 230 allows the dummy gate stack 230 to be removed. In some embodiments, the removal of the dummy gate stack 230 creates a gate trench (not shown) above the channel region. Removing the dummy gate stack 230 may include one or more etching processes that are selective to the material of the dummy gate stack 230. For example, removing the dummy gate stack 230 may be performed using a selective wet etch that is selective to the dummy gate stack 230, a selective dry etch, or a combination thereof.

[0064] Subsequently, a metal gate stack 274 is formed in the gate trench. The metal gate stack 274 includes a gate dielectric layer 276 and a gate electrode layer 278 above the gate dielectric layer 276. In some embodiments, although not explicitly shown in the drawings, the gate dielectric layer 276 includes an interface layer and a high-K gate dielectric layer. High-K dielectric materials (as used and described herein) include dielectric materials with a high dielectric constant, for example, a dielectric constant greater than that of thermal silicon oxide (~3.9). The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-K gate dielectric layer may include hafnium oxide. Alternatively, the high-K gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0065] The gate electrode layer 278 of the metal gate stack 274 may include a single layer or optionally a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the gate electrode layer 278 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer 278 may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes.

[0066] In some embodiments, the source / drain contact 280 and the gate contact 284 may include a conductive barrier layer and a metal filling layer above the conductive barrier layer. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru) or a conductive nitride, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN) or a combination thereof, and may be formed by CVD, PVD, ALD and / or other suitable processes. The metal filling layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu) or other metals, and may be formed by CVD, PVD, ALD, plating or other suitable processes. In some embodiments, the conductive barrier layer is omitted. In order to reduce contact resistance, a silicide component 282 may be formed between the source / drain contact 280 and the source / drain component 260b (and 260a, if present). In some embodiments, the silicide feature 282 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. Fig. 27 As shown in FIG. 2 , the partially recessed source / drain regions facilitate lateral merging of source / drain features 260b above the fins 212. The merged source / drain features 260 prevent the source / drain contacts 280 from penetrating gaps that would otherwise exist between unmerged source / drain features.

[0067] The interconnect multilayer structure 286 includes vias 288 and metal lines 290 embedded in the dielectric layer. The interconnect multilayer structure 286 connects the gate, source, and drain components of each transistor and other circuits in the semiconductor device 200 to form an integrated circuit in part or in whole. The semiconductor device 200 may further include a passivation layer, an adhesion layer, and / or other layers built on the front side of the semiconductor device 200. These layers and one or more interconnect layers are collectively indicated by the reference numeral 286.

[0068] Fig.28Another embodiment of a capping structure 244 at the end of block 116 is shown. In this embodiment, the capping structure 244 includes a single base portion 244a and a plurality of protruding portions 244b disposed on one side of the dummy gate stack 230. A first protruding portion 244b-1 does not extend into the source / drain region and does not cover any fins 212, a second protruding portion 244b-2 extends into the source / drain region and covers several fins 212, and a third protruding portion 244b-3 extends further into the source / drain region and covers even more fins 212.

[0069] The resulting structure after the epitaxial growth process at the end of block 122 is Fig.29 Shown in. Fig.29 is the edge of the semiconductor device 200 Fig.28 BB line in FIG. 2 is a cross-sectional view cut through one of the fins 212. A source / drain feature 260a is formed in a large source / drain trench corresponding to the first protruding portion 244b-1, a source / drain feature 260b-2 is formed in a small source / drain trench corresponding to the second protruding portion 244b-2, and a source / drain feature 260b-3 is formed in a small source / drain trench corresponding to the third protruding portion 244b-3. Each of the source / drain features 260b-2 and 260b-3 has two lower portions located in the source / drain trenches 250b and 250c, respectively, and a connection portion adjoining the two lower portions. Even though no protrusion 244b extends completely through the corresponding source / drain region in the Y direction, the protrusions 244b-2 and 244b-3 still allow relatively less epitaxial material to be filled in the corresponding source / drain trenches, and thus allow more epitaxial material to be deposited on top of the corresponding source / drain features. Therefore, both source / drain features 260b-2 and 260b-3 are taller than source / drain feature 260a, and the source / drain feature 260b-3 corresponding to the longer protrusion 244b-3 is taller than the source / drain feature 260b-2 corresponding to the shorter protrusion 244b-2.

[0070] Fig.30 Another embodiment of a capping structure 244 at the end of frame 116 is shown. In this embodiment, the capping structure 244 includes a single base portion 244a and a plurality of protruding portions 244b disposed on one side of the dummy gate stack 230. The first protruding portion 244b-1 extends into the middle source / drain region and covers several (e.g., four) fins 212, and the second protruding portion 244b-2 extends into the right source / drain region and covers the same number of fins 212. There is no corresponding protruding portion for the source / drain region on the left. The first protruding portion 244b-1 has a larger width measured in the X direction than the second protruding portion 244b-2.

[0071] The resulting structure after the epitaxial growth process at the end of block 122 is Figure 31 to Figure 33 Shown in. Fig.31 is the edge of the semiconductor device 200 Fig.30 A cross-sectional view of the DD line cutting through the source / drain region on the left. Fig.32 is the edge of the semiconductor device 200 Fig.30 A cross-sectional view of the CC line cutting through the middle source / drain region. Fig.33 is the edge of the semiconductor device 200 Fig.30 EE line in FIG. 2 cuts through the right source / drain region. Source / drain feature 260a is formed in a large source / drain trench, source / drain feature 260b-2 is formed in a small source / drain trench corresponding to the thinner protrusion 244b-2, and source / drain feature 260b-1 is formed in an even smaller source / drain trench corresponding to the wider protrusion 244b-2.

[0072] For the same amount of the first precursor material and the second precursor material that are deposited into the source / drain regions in further reaction to form epitaxial features 260a, 260b-1, and 260b-2, respectively, because there is less epitaxial material filled in the smaller source / drain trenches 250b and 250c, more epitaxial material can be applied on the top portions of the source / drain features 260b-1 and 260b-2 to promote vertical rising and lateral merging of the source / drain features above the fin 212, while in comparison, there is more epitaxial material filled in the larger source / drain trench 250a, but less epitaxial material can be applied to the top portions of the source / drain features 260a, so that some of the source / drain features 260a can remain separated with gaps 264 between them. Comparing source / drain features 260b-1 and 260b-2, source / drain features 260b-1 and 260b-2 above uncovered fins (e.g., five fins) also benefit from more epitaxial material deposited on the top portions of source / drain features 260-1 and 260-2. Because source / drain feature 260b-1 has the smallest volume below the top surface of fin 212, it has the largest volume above the top surface of fin 212, and the top surface of the merged source / drain feature 260b-1 is substantially flat. Similarly, source / drain feature 260b-2 has a relatively large volume below the top surface of fin 212, it has a relatively small volume above the top surface of fin 212, and the top surface of the merged source / drain feature 260b-2 has a sawtooth profile. The source / drain features 260 a have the largest volume below the top surface of the fin 212 , and some of the source / drain features 260 a still remain separated.

[0073] Fig.34 Another embodiment of the capping structure 244 at the end of block 116 is shown. In this embodiment, the capping structure 244 includes a single base portion 244a disposed on one side of the dummy gate stack 230 and a plurality of protruding portions 244b. The first protruding portion 244b-1, the second protruding portion 244b-2, and the third protruding portion 244b-3 have the same width W1, but the distances to the respective nearest dummy gate stacks 230 are different. The second protruding portion 244b-2 is positioned at the center of two adjacent dummy gate stacks 230-2 and 230-3, the first protruding portion 244b-1 is positioned closer to the dummy gate stack 230-1 by a distance W2 and farther from the dummy gate stack 230-2 by a distance W3 (W2 < W3), and the third protruding portion 244b-3 is positioned closer to the dummy gate stack 230-4 by a distance W2' and farther from the dummy gate stack 230-3 by a distance W3' (W2' < W3'). There is no corresponding protruding portion in the source / drain region between the dummy gate structures 230-4 and 230-5.

[0074] The resulting structure after the epitaxial growth process at the end of block 122 is shown in Fig.35 FIG. Fig.35 is a cross-sectional view of the semiconductor device 200 cut along line B-B in Fig.34 FIG. through one of the fins 212. The source / drain member 260a is formed in the largest source / drain trench extending between the dummy gate stacks 230-4 and 230-5 because there is no source / drain capping structure portion. The source / drain members 260b-1, 260b-2, 260b-3 are formed in the smaller source / drain trenches corresponding to the first protruding portion 244b-1, the second protruding portion 244b-2, the third protruding portion 244b-3. Each of the source / drain members 260-1, 260b-2, 260b-3 has two lower portions respectively located in the source / drain trenches 250b and 250c ( Fig.16 ), and a connecting portion adjacent to the two lower portions. Even though the protruding portions 244b do not completely extend through the source / drain region in the Y direction, the protruding portions 244b-1, 244b-2, 244b-3 still allow relatively less epitaxial material to fill in the corresponding source / drain trenches, and thus allow more epitaxial material to be deposited on top of the corresponding source / drain members. Therefore, the topmost portions of the source / drain members 260b-1, 260b-2, 260b-3 are all higher than the source / drain member 260a.

[0075] With respect to the source / drain component 260b-2, the two lower portions have the same width and the same depth, and the top surface is substantially flat. With respect to the source / drain component 260b-1, the lower portion of the smaller width W2 is narrower and also shallower than the lower portion of the larger width W3, and the top surface is inclined, wherein the lower edge abuts the dummy gate stack 230-1, and the upper edge abuts the dummy gate stack 230-2. In addition, the lower edge of the source / drain component 260b-1 is located below the top surface of the source / drain component 260b-2, and the upper edge of the source / drain component 260b-1 is located above the top surface of the source / drain component 260b-2. Further, in some embodiments, the lower edge of the source / drain component 260b-1 may be located below the top surface of the source / drain component 260a. In the depicted embodiment, the higher edge being located above the larger of the two immediately adjacent trenches may be due to the fact that once the epitaxial feature grows above the fin top 212, the vertical growth rate associated with the larger opening will catch up with and exceed the vertical growth rate associated with the smaller opening. However, this phenomenon occurs more often in two immediately adjacent trenches between the same opposing gate spacer sidewalls. With respect to the source / drain feature 260b-3, the lower portion of the smaller width W2' is narrower and also shallower than the lower portion of the larger width W3', and the top surface is inclined, with the lower edge abutting the dummy gate stack 230-4 and the higher edge abutting the dummy gate stack 230-3. In addition, the lower edge of the source / drain feature 260b-3 is located below the top surface of the source / drain feature 260b-2, and the higher edge of the source / drain feature 260b-3 is located above the top surface of the source / drain feature 260b-2. Further, in some embodiments, the lower edge of the source / drain feature 260b-3 can be located below the top surface of the source / drain feature 260a. Similarly, in the depicted embodiment, the upper edge is located above the larger of the two closely adjacent trenches, which may be due to the vertical growth rate associated with the larger opening catching up with and exceeding the vertical growth rate associated with the smaller opening once the epitaxial feature grows above the fin top 212. However, this phenomenon occurs more often in two closely adjacent trenches between the same opposing gate spacer sidewalls.

[0076] Fig.36Another embodiment of a capping structure 244 at the end of frame 116 is shown. In this embodiment, the capping structure 244 includes two base portions 244a-1 and 244a-2 sandwiching the dummy gate stack 230 in the Y direction. The base portion 244a-1 includes a first protruding portion 244b-1 that extends partially into the source / drain region between the dummy gate stacks 230-2 and 230-3 and a third protruding portion 244b-3 that extends partially into the source / drain region between the dummy gate stacks 230-4 and 230-5. The base portion 244a-2 includes a second protruding portion 244b-2 that extends partially into the source / drain region between the dummy gate stacks 230-3 and 230-4 and a fourth protruding portion 244b-4 that extends partially into the source / drain region between the dummy gate stacks 230-4 and 230-5.

[0077] The resulting structure after the epitaxial growth process at the end of block 122 is Figures 37 to 40 Shown in. Fig.37 is the edge of the semiconductor device 200 Fig.36 A cross-sectional view of a source / drain region cut through the dummy gate stacks 230 - 1 and 230 - 2 by line DD in FIG. Fig.38 is the edge of the semiconductor device 200 Fig.36 A cross-sectional view of the source / drain region between the dummy gate stacks 230 - 2 and 230 - 3 cut along line CC in FIG. Fig.39 is the edge of the semiconductor device 200 Fig.36 A cross-sectional view where line EE in FIG. 5 cuts through the source / drain region between the dummy gate stacks 230 - 3 and 230 - 4 . Fig.40 is the edge of the semiconductor device 200 Fig.36 A cross-sectional view where the FF line in FIG. 1 cuts through the source / drain region between the dummy gate stacks 230 - 4 and 230 - 5 .

[0078] The source / drain feature 260a is formed in a larger source / drain trench extending between the dummy gate structures 230-1 and 230-2 because there is no source / drain covering structure portion. The source / drain features 260b-1, 260b-2, 260b-3 are formed in smaller source / drain trenches corresponding to the first protruding portion 244b-1, the second protruding portion 244b-2, and the common third protruding portion 244b-3 and the fourth protruding portion 244b-4, respectively.

[0079] For the same amount of the first precursor material and the second precursor material that are deposited in further reaction to the source / drain regions to form epitaxial features 260a, 260b-1, 260b-2, and 260b-3, respectively, there is less epitaxial material to fill the smaller source / drain trenches 250b and 250c ( Fig.16 ), so more epitaxial material can be applied on the top portions of the source / drain features 260b-1, 260b-2, and 260b-3 to promote vertical rise and lateral merging of the source / drain features above the fin 212, although as a comparison, there is more epitaxial material filled in the larger source / drain trench 250a, but less epitaxial material can be applied to the top portions of the source / drain features 260a, so that some of the source / drain features 260a can remain separated with gaps 264 between them. With respect to the source / drain features 260b-1 and 260b-2, the source / drain features 260b-1 and 260b-2 above the six uncovered fins also benefit from more epitaxial material deposited on the top portions of the source / drain features 260-1 and 260-2, where all the epitaxial features above the fin merge with the sawtooth top surface. The central portion of the source / drain feature 260b-3 is located above the side portions of the source / drain feature 260b-3 and also above the other source / drain features 260b-1, 260b-2, and 260a. The source / drain feature 260a is lower than the source / drain features 260b-1, 260b-3, and 260b-3 due to its largest volume below the top surface of the fin 212.

[0080] FIG. 41A to FIG. 41C Various embodiments of the cover structure 244 are shown, and FIG. 42A to FIG. 42C The corresponding FIG. 41A to FIG. 41C 4. A cross-sectional view of a transistor 400 with a capping structure 244 along line BB in FIG. Transistor 400 may be an n-type transistor or a p-type transistor. Transistor 400 includes a channel region joined to a metal gate stack 274. The channel region may be provided by a top portion of a fin in a FinFET transistor or a plurality of vertically stacked channel layers in a GAA transistor. In the case of a FinFET transistor, a metal gate stack 274 is deposited on the top and sidewalls of the fin. In the case of a GAA transistor, a metal gate stack 274 wraps around each of the suspended channel layers. The channel region of transistor 400 is sandwiched between two source / drain components 260 along the X direction.

[0081] Common Reference Fig.41A and Fig.42A , the capping structure 244 includes a base portion 244a, but does not include a protruding portion or a protruding portion extending into the source / drain region, and thus a single source / drain trench 250a is formed in each source / drain region ( Fig.16 ). After the epitaxial growth process, a source / drain feature 260a is formed in the source / drain trench 250a. The two source / drain features 260a of the transistor 400 have substantially the same depth into the fin 212 and a flush top surface.

[0082] Common Reference Fig.41B and Fig.42B , the capping structure 244 includes a base portion 244a having a protruding portion 244b that partially extends to (or completely extends through) one of the source / drain regions in the Y direction, and thus two small source / drain trenches 250b and 250c are formed at portions of the source / drain region located below the protruding portion 244b ( Fig.16 ), and a large source / drain trench 250a is formed in the other source / drain regions ( Fig.16 ). After the epitaxial growth process, a source / drain component 260a is formed in the large source / drain trench 250a, and a source / drain component 260b is formed in the two small source / drain trenches 250b and 250c. The source / drain component 260a has a larger volume below the top surface of the fin 212, but has a lower top surface. The source / drain component 260b has a smaller volume below the top surface of the fin 212, but has a higher top surface.

[0083] Common Reference Fig.41C and Fig.42C , the capping structure 244 includes a base portion 244a having a first protruding portion 244b-1 extending partially to (or completely extending through) the source / drain region between the dummy gate stacks 230-1 and 230-2 along the Y direction and a second protruding portion 244b-2 extending partially to (or completely extending through) the source / drain region between the dummy gate stacks 230-2 and 230-3 along the Y direction. Therefore, two small source / drain trenches 250b and 250c ( Fig.16 ). After the epitaxial growth process, source / drain components 260b are formed in the source / drain trenches 250b and 250c. Each of the source / drain components 260b has two lower portions located in the source / drain trenches 250b and 250c, respectively, and a connecting portion adjacent to the two lower portions. The two source / drain components 260b of the transistor 400 have substantially the same depth into the fin 212 and a flush top surface. Due to the smaller volume below the top surface of the fin 212, more epitaxial growth occurs on the top surface of the source / drain component 260b, so that the epitaxial component 260b merges laterally with an increased thickness above the fin 212.

[0084] Implementing the source / drain capping structure before recessing the source / drain region allows more epitaxial material to be redistributed to the top portion of the source / drain feature during formation of the source / drain feature, which promotes lateral merging of the source / drain feature above the fin. The source / drain capping structure can have different shapes, which allows fine tuning of the profile of the source / drain feature to meet different device performance requirements.

[0085] In one exemplary aspect, the disclosed embodiments relate to a method for manufacturing a semiconductor device. The method includes: forming a plurality of fins protruding from a substrate, each of the fins extending longitudinally in a first direction; forming a first dummy gate stack and a second dummy gate stack above the fin, each of the first dummy gate stack and the second dummy gate stack extending longitudinally in a second direction different from the first direction; depositing a capping structure above the fin, wherein in a top view of the semiconductor device, a first portion of the capping structure extends longitudinally in the second direction between the first dummy gate stack and the second dummy gate stack; etching the fin along the first direction in a cross-sectional view of the semiconductor device using the capping structure as an etching mask to form a first trench between the first dummy gate stack and the first portion of the capping structure and a second trench between the second dummy gate stack and the first portion of the capping structure; removing the capping structure; epitaxially growing a first epitaxial component from the first trench and epitaxially growing a second epitaxial component from the second trench, the first epitaxial component and the second epitaxial component merging after rising above the top surface of the fin to form a merged epitaxial component; and replacing the first dummy gate stack and the second dummy gate stack with a first metal gate stack and a second metal gate stack, respectively. In some embodiments, the merged epitaxial component extends continuously over the fin so that each of the fins is located directly below the merged epitaxial component. In some embodiments, in a top view, the covering structure includes a second portion disposed beside the first dummy gate stack and the second dummy gate stack, and the first portion protrudes from an edge of the second portion. In some embodiments, in a top view, the covering structure includes a third portion disposed beside the first dummy gate stack and the second dummy gate stack, and the second portion and the third portion sandwich the first dummy gate stack and the second dummy gate stack in the second direction. In some embodiments, the first portion connects the second portion and the third portion. In some embodiments, in a top view, the first portion overlaps each of the fins. In some embodiments, in a top view, the first portion does not overlap with a subset of the fins. In some embodiments, the first portion is spaced apart from the first dummy gate stack by a first distance along the first direction, and spaced apart from the second dummy gate stack by a second distance along the second direction, and wherein the first distance is equal to the second distance. In some embodiments, the first portion is spaced apart from the first dummy gate stack by a first distance along the first direction, and spaced apart from the second dummy gate stack by a second distance along the second direction, and wherein the first distance is less than the second distance. In some embodiments, in a cross-sectional view, the first epitaxial feature is shallower than the second epitaxial feature.

[0086] In another exemplary aspect, the disclosed embodiments relate to a method for manufacturing a semiconductor device. The method includes: patterning a substrate to form a fin, the fin having a first source / drain region, a second source / drain region, and a channel region between the first source / drain region and the second source / drain region; forming a gate stack above the channel region of the fin; in a top view of the semiconductor device, forming a capping structure having a first portion next to the gate stack and a second portion extending parallel to the gate stack and across the first source / drain region; in a cross-sectional view of the semiconductor device cut along the fin, recessing the first source / drain region and the second source / drain region of the fin to form a first trench and a second trench in the first source / drain region, and forming at least a third trench in the second source / drain region; and epitaxially growing a first epitaxial component from the first trench, epitaxially growing a second epitaxial component from the second trench, and epitaxially growing a third epitaxial component from the third trench. The first epitaxial component and the second epitaxial component merge above the top surface of the fin. In some embodiments, the method also includes: before epitaxially growing the first epitaxial component, the second epitaxial component, and the third epitaxial component, removing the capping structure. In some embodiments, the first portion extends parallel to the fin. In some embodiments, in a top view, the capping structure does not overlap with the second source / drain region, and each of the first epitaxial component and the second epitaxial component is shallower than the third epitaxial component. In some embodiments, the top surface of the first epitaxial component and the second epitaxial component is located above the top surface of the third epitaxial component. In some embodiments, the capping structure includes a third portion extending parallel to the gate stack and across the second source / drain region, recessed in the second source / drain region to form a fourth trench, epitaxially growing a fourth epitaxial component from the fourth trench, and the third and fourth epitaxial components and the fourth epitaxial component merge above the top surface of the fin.

[0087] In another exemplary aspect, the disclosed embodiments relate to a semiconductor device. The semiconductor device includes: a substrate; a plurality of fins protruding from the substrate, each of the fins extending longitudinally in a first direction; a gate stack disposed above the fins, the gate stack extending longitudinally in a second direction perpendicular to the first direction; a first epitaxial component disposed on a first side of the gate stack; and a second epitaxial component disposed on a second side of the gate stack. The first epitaxial component extends continuously so that each of the fins is located directly below the first epitaxial component. In a cross-sectional view of the semiconductor device cut along one of the fins, the first epitaxial component includes a first lower portion extending below the top surface of one of the fins, a second lower portion extending below the top surface of one of the fins, and a connecting portion adjoining the first lower portion and the second lower portion above the top surface of one of the fins. In some embodiments, the second epitaxial component is divided into a first segment separated from the second segment by at least one gap. In some embodiments, the top surface of the first epitaxial component is substantially flat. In some embodiments, the first lower portion of the first epitaxial component has a first bottom surface, the second lower portion of the second epitaxial component has a second bottom surface, and the first bottom surface is located above the second bottom surface.

[0088] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a plurality of fins protruding from the substrate, each of the fins extending longitudinally in a first direction; forming a first dummy gate stack and a second dummy gate stack over the fin, each of the first dummy gate stack and the second dummy gate stack extending longitudinally in a second direction different from the first direction; depositing a capping structure over the fin, wherein in a top view of the semiconductor device, a first portion of the capping structure extends longitudinally in the second direction between the first dummy gate stack and the second dummy gate stack; etching the fin using the capping structure as an etching mask in a cross-sectional view of the semiconductor device along the first direction to form a first trench between the first dummy gate stack and the first portion of the capping structure and a second trench between the second dummy gate stack and the first portion of the capping structure; removing the covering structure; epitaxially growing a first epitaxial feature from the first trench and epitaxially growing a second epitaxial feature from the second trench, the first epitaxial feature and the second epitaxial feature merging after rising above a top surface of the fin to form a merged epitaxial feature; as well as The first dummy gate stack and the second dummy gate stack are replaced with a first metal gate stack and a second metal gate stack, respectively.

2. The method according to claim 1, wherein: The merged epitaxial feature extends continuously over the fins such that each of the fins is located directly below the merged epitaxial feature.

3. The method according to claim 1, wherein: In the top view, the capping structure includes a second portion disposed beside the first dummy gate stack and the second dummy gate stack, and the first portion protrudes from an edge of the second portion.

4. The method according to claim 3, wherein: In the top view, the capping structure includes a third portion disposed beside the first dummy gate stack and the second dummy gate stack, and the second portion and the third portion sandwich the first dummy gate stack and the second dummy gate stack along the second direction.

5. The method according to claim 4, wherein: The first portion connects the second portion and the third portion.

6. The method according to claim 1, wherein: In the top view, the first portion overlaps each of the fins.

7. The method according to claim 1, wherein: In the top view, the first portion does not overlap with the subset of the fins.

8. The method according to claim 1, wherein: The first portion is spaced apart from the first dummy gate stack by a first distance along the first direction and spaced apart from the second dummy gate stack by a second distance along the second direction, and wherein the first distance is equal to the second distance.

9. A method for manufacturing a semiconductor device, comprising: patterning a substrate to form a fin having a first source / drain region, a second source / drain region, and a channel region between the first source / drain region and the second source / drain region; forming a gate stack over the channel region of the fin; In a top view of the semiconductor device, forming a capping structure having a first portion beside the gate stack and a second portion extending parallel to the gate stack and across the first source / drain region; In a cross-sectional view of the semiconductor device cut along the fin, the first source / drain region and the second source / drain region of the fin are recessed to form a first trench and a second trench in the first source / drain region, and to form at least a third trench in the second source / drain region; as well as A first epitaxial feature is epitaxially grown from the first trench, a second epitaxial feature is epitaxially grown from the second trench, and a third epitaxial feature is epitaxially grown from the third trench, wherein the first epitaxial feature and the second epitaxial feature merge over a top surface of the fin.

10. A semiconductor device comprising: substrate; a plurality of fins protruding from the substrate, each of the fins extending longitudinally in a first direction; a gate stack disposed above the fin, the gate stack extending longitudinally in a second direction perpendicular to the first direction; a first epitaxial component disposed on a first side of the gate stack; as well as a second epitaxial component disposed on a second side of the gate stack, in: The first epitaxial component extends continuously so that each of the fins is located directly below the first epitaxial component, and In a cross-sectional view of the semiconductor device cut along one of the fins, the first epitaxial component includes a first lower portion extending below a top surface of one of the fins, a second lower portion extending below the top surface of one of the fins, and a connecting portion adjoining the first lower portion and the second lower portion above the top surface of one of the fins.

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