Semiconductor device and method for preparing semiconductor device

Abstract

The embodiment of the present invention discloses a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a substrate; a buffer layer disposed on one side of the substrate; a channel layer disposed on the side of the buffer layer away from the substrate; a barrier layer disposed on the side of the channel layer away from the substrate; a cap layer disposed on the side of the barrier layer away from the substrate; and a regulating layer disposed on the side of the cap layer away from the substrate, wherein the orthographic projection of the regulating layer on the substrate at least partially covers the orthographic projection of the cap layer on the substrate, and the regulating layer is used to adjust the uniformity of the electric field of the cap layer. The technical solution provided in this embodiment adjusts the uniformity of the electric field between the cap layer and the gate, thereby improving the voltage resistance of the gate, and further improving the reliability of the semiconductor device.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] With the development of semiconductor technology, people have higher and higher requirements for semiconductor devices. The cap layer of existing semiconductor devices usually adopts Mg doping to provide a higher hole concentration. However, when a higher positive voltage is applied to the gate, the top area of ​​the cap layer has a higher electric field. As the gate voltage gradually increases, most of the increased voltage falls on the Schottky junction, resulting in a high electric field at the Schottky interface. After long-term high gate voltage stress, the Schottky junction of semiconductor devices will degrade, resulting in reduced reliability.

[0003] Existing semiconductor devices have a problem of poor reliability when the gate voltage is high. Summary of the invention

[0004] The embodiments of the present invention provide a semiconductor device and a method for manufacturing the semiconductor device to solve the problem that the existing semiconductor device has poor reliability when the gate voltage is high.

[0005] In order to achieve the above technical problems, the present invention adopts the following technical solutions:

[0006] An embodiment of the present invention provides a semiconductor device, including:

[0007] substrate;

[0008] A buffer layer disposed on one side of the substrate;

[0009] A channel layer disposed on a side of the buffer layer away from the substrate;

[0010] A barrier layer disposed on a side of the channel layer away from the substrate;

[0011] A cap layer disposed on a side of the barrier layer away from the substrate;

[0012] The regulating layer is arranged on the side of the cap layer away from the substrate, and the orthographic projection of the regulating layer on the substrate at least partially covers the orthographic projection of the cap layer on the substrate. The regulating layer is used to adjust the uniformity of the electric field of the cap layer.

[0013] Optionally, the regulating layer includes a first insertion layer and a second insertion layer;

[0014] The first insertion layer is arranged on a side of the barrier layer away from the substrate, and the second insertion layer is arranged on a side of the first insertion layer away from the substrate;

[0015] The first insertion layer is used to reduce the electric field strength of the cap layer;

[0016] The second insertion layer is used to provide a potential barrier, adjust the intensity of the electric field, and cut off the electric field inside the second insertion layer;

[0017] The orthographic projection of the second insertion layer on the substrate completely covers the orthographic projection of the first insertion layer on the substrate.

[0018] Optionally, the material of the first insertion layer includes unintentionally doped gallium nitride;

[0019] The material of the second insertion layer includes at least one of InxGa1-xN, AlyGa1-yN and InxAlyGa1-x-yN, wherein 0 <x<1,0<y<1。

[0020] Optionally, the control layer also includes:

[0021] a third insertion layer, the third insertion layer being arranged on a side of the second insertion layer away from the substrate, and the third insertion layer being used for playing a voltage dividing role;

[0022] The orthographic projection of the third insertion layer on the substrate completely covers the orthographic projection of the second insertion layer on the substrate.

[0023] Optionally, the material of the third insertion layer includes GaN, and its doping includes n-doped, p-doped or np co-doped.

[0024] Optionally, the thickness of the regulation layer is greater than or equal to 4 nm.

[0025] Optionally, the cap layer includes a P-type doped layer, and the P-type doped layer includes a GaN layer doped with Mg;

[0026] The material of the buffer layer includes AlN, GaN or AlGaN; the material of the channel layer includes GaN; the material of the barrier layer includes AlGaN;

[0027] The semiconductor device also includes a gate, which is arranged on a side of the regulating layer away from the substrate, and a material of the gate includes titanium nitride or tungsten nitride.

[0028] According to another aspect of the present invention, this embodiment provides a method for preparing a semiconductor device, comprising:

[0029] providing a substrate;

[0030] forming a buffer layer on one side of the substrate;

[0031] forming a channel layer on a side of the buffer layer away from the substrate;

[0032] forming a barrier layer on a side of the channel layer away from the substrate;

[0033] forming a cap layer on a side of the barrier layer away from the substrate;

[0034] A regulating layer is formed on the side of the cap layer away from the substrate, the orthographic projection of the regulating layer on the substrate at least partially covers the orthographic projection of the cap layer on the substrate, and the regulating layer is used to adjust the uniformity of the electric field of the cap layer.

[0035] Optionally, forming a regulating layer on a side of the cap layer away from the substrate includes:

[0036] forming a first insertion layer on a side of the barrier layer away from the substrate, the first insertion layer being used to reduce the electric field strength of the cap layer;

[0037] A second insertion layer is formed on the side of the first insertion layer away from the substrate; the second insertion layer is used to provide a potential barrier, adjust the intensity of the electric field, and cut off the electric field inside the second insertion layer; the orthographic projection of the second insertion layer on the substrate completely covers the orthographic projection of the first insertion layer on the substrate.

[0038] Optionally, forming a regulating layer on a side of the cap layer away from the substrate further comprises:

[0039] A third insertion layer is formed on a side of the second insertion layer away from the substrate. The third insertion layer is used to play a voltage dividing role. The orthographic projection of the third insertion layer on the substrate completely covers the orthographic projection of the second insertion layer on the substrate.

[0040] The semiconductor device provided by the embodiment of the present invention is provided with a regulating layer on the side of the cap layer away from the substrate, so that a regulating layer is provided between the cap layer and the gate. This arrangement improves the crystal quality of the cap layer surface, adjusts the electric field slope between the cap layer and the gate, reduces the electric field peak, thereby improving the gate electric field distribution, and can also reduce the leakage of the semiconductor device, improve the gate's voltage resistance, and improve the gate reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the contents of the embodiments of the present invention and these drawings without paying any creative work.

[0042] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0043] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0044] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0045] Figure 4is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0046] Figure 5 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention;

[0047] Figure 6 This is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0049] Based on the above technical problems, this embodiment proposes the following solutions:

[0050] Figure 1 is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention. Figure 1 The semiconductor device provided by the embodiment of the present invention includes a substrate 1; a buffer layer 2 arranged on one side of the substrate 1; a channel layer 3 arranged on the side of the buffer layer 2 away from the substrate 1; a barrier layer 4 arranged on the side of the channel layer 3 away from the substrate 1; a cap layer 5 arranged on the side of the barrier layer 4 away from the substrate 1; and a regulating layer 6 arranged on the side of the cap layer 5 away from the substrate 1, wherein the orthographic projection of the regulating layer 6 on the substrate 1 at least partially covers the orthographic projection of the cap layer 5 on the substrate 1, and the regulating layer 6 is used to adjust the uniformity of the electric field of the cap layer 5.

[0051] Specifically, the substrate 1 may include a Si substrate, a SiC substrate or a sapphire substrate. The buffer layer 2 includes a nitride semiconductor layer. The channel layer 3 is used to transmit electrons. The channel layer 3 includes ions of metals such as Al and Ga. The channel layer 3 generates a two-dimensional electron gas (2DEG). The two-dimensional electron gas passes through the channel layer 3 to form a current. The main functions of the barrier layer 4 include controlling the flow of current and achieving voltage regulation. In semiconductor devices, the barrier layer 4 affects the flow of current by controlling the diffusion of electrons and holes. The barrier layer 4 can be regarded as a diffusion barrier layer for electrons and holes, which limits the flow direction and intensity of the current through a potential difference. This structure is particularly obvious in a PN junction, where the PN junction barrier controls the diffusion of electrons and holes through a potential difference, thereby affecting the flow of current. In addition, the barrier layer 4 can also be used to achieve voltage regulation. By adjusting the height and width of the barrier layer 4, the current passing through the semiconductor device can be controlled, thereby achieving the voltage regulation function. The cap layer 5 may include P-GaN doped with Mg.

[0052] The gate of the traditional P-GaN HEMT (High Electron Mobility Transistor) has a high p-type doping concentration on the top of the pGaN due to the memory effect of Mg during the MOCVD (Metal-Organic Chemical Vapor Deposition) growth process. The memory effect refers to the process of GaN growth, in which the Mg source will still accumulate in the chamber after being turned off, and the GaN that continues to grow will be p-type.

[0053] The Schottky junction in HEMT is formed by the interface between the gate and the cap layer 5. The Schottky junction has nonlinear impedance characteristics, similar to a PN junction, and is usually used to control the concentration of the two-dimensional electron gas (2DEG). The working principle of HEMT is to turn on and off the semiconductor device by controlling the concentration of the two-dimensional electron gas through the gate. In HEMT, the Schottky junction is usually used to control the concentration of 2DEG.

[0054] Since the cap layer 5 of the semiconductor device in the prior art is arranged adjacent to the gate, when a relatively high positive voltage is applied to the gate, the top area of ​​the cap layer 5 has a relatively high electric field. As the gate voltage further increases, most of the increased voltage of the gate falls on the Schottky junction. There will be a very high electric field at the interface of the Schottky junction. After long-term high gate voltage stress, the Schottky junction will degenerate, the Schottky barrier will be partially reduced, the leakage will increase, and the reliability of the gate will be reduced.

[0055] By arranging a regulating layer 6 on the side of the cap layer 5 away from the substrate 1, the orthographic projection of the regulating layer 6 on the substrate 1 at least partially covers the orthographic projection of the cap layer 5 on the substrate 1, the electric field distribution and barrier strength on the side of the cap layer 5 away from the substrate 1 can be further improved. The regulating layer 6 can adjust the doping concentration on the side of the cap layer 5 close to the gate, optimize the distribution of the electric field between the cap layer 5 and the gate, reduce the slope of the electric field, reduce the peak of the electric field, and make the electric field distribution between the cap layer 5 and the gate more uniform. The regulating layer 6 can provide a Schottky barrier, reduce the leakage of the semiconductor device, thereby improving the voltage resistance of the gate, and then improve the reliability of the gate.

[0056] In order to improve the gate reliability, the semiconductor device provided in this embodiment is provided with a regulating layer 6 on the side of the cap layer 5 away from the substrate 1, so that the regulating layer 6 is provided between the cap layer 5 and the gate. In this way, the crystal quality of the surface of the cap layer 5 is improved, the electric field slope between the cap layer 5 and the gate is adjusted, and the electric field peak is reduced, thereby improving the gate electric field distribution, reducing the leakage of the semiconductor device, improving the gate's voltage resistance, and improving the gate reliability.

[0057] Optional, Figure 2FIG. 1 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. Figure 2 The regulating layer 6 may include a first insertion layer 61 and a second insertion layer 62; the first insertion layer 61 is arranged on the side of the barrier layer 4 away from the substrate 1, and the second insertion layer 62 is arranged on the side of the first insertion layer 61 away from the substrate 1; the first insertion layer 61 is used to reduce the electric field strength of the cap layer 5; the second insertion layer 62 is used to provide a potential barrier, adjust the strength of the electric field, and cut off the electric field inside the second insertion layer 62; the orthographic projection of the second insertion layer 62 on the substrate 1 completely covers the orthographic projection of the first insertion layer 61 on the substrate 1.

[0058] Specifically, the doping concentration of the first insertion layer 61 is lower than the doping concentration of the cap layer 5. Since the first insertion layer 61 is disposed on the side of the cap layer 5 away from the substrate 1, the first insertion layer with a lower doping concentration can reduce the slope of the electric field, reduce the peak of the electric field, and improve the uniformity of the electric field.

[0059] In addition, the second insertion layer 62 is disposed on the side of the first insertion layer 61 away from the substrate 1. The second insertion layer 62 is used to provide a potential barrier, so that the potential barrier between the first insertion layer 61 and the gate 7 is higher, which plays a better voltage dividing role, improves the voltage resistance of the gate 7, avoids the degradation of the Schottky junction, and reduces the leakage of the semiconductor device.

[0060] Optionally, based on the above embodiments, continue to refer to Figure 2 The material of the first insertion layer 61 may include unintentionally doped gallium nitride; the material of the second insertion layer 62 may include at least one of InxGa1-xN, AlyGa1-yN and InxAlyGa1-x-yN, wherein 0 <x<1,0<y<1。

[0061] Specifically, the first insertion layer 61 is unintentionally doped gallium nitride (u-GaN). Unintentionally doped gallium nitride means that after growing a certain thickness of P-GaN to form a cap layer 5, the intentional doping source is turned off. Unintentionally doped gallium nitride (u-GaN) formed by GaN growth. Unintentionally doped gallium nitride (u-GaN) may present a medium type. Alternatively, due to the presence of impurities such as O, unintentionally doped gallium nitride (u-GaN) may present a weak n-type.

[0062] The second insertion layer 62 can be one of InxGa1-xN, AlyGa1-yN, InxAlyGa1-x-yN, or a combination of any two materials, where 0 < x < 1 and 0 < y < 1. Additionally, the doping of the second insertion layer 62 can be any one of N-doped (n-doped), P-doped (p-doped), or N / P co-doped (n p co-doped). Si can be used as the n-doped doping element. Mg can be used as the p-doped doping element. It is also possible to simultaneously dope both Si and Mg elements to achieve weak n-doped, weak p-doped, or n p co-doped. Exemplarily, through experimental verification, by setting the first insertion layer 61 and the second insertion layer 62, the breakdown voltage of the gate 7 can be increased by more than 2V.

[0063] Optionally, Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. Based on the above embodiments, referring to Figure 3 , the regulation layer 6 can further include: a third insertion layer 63, which is disposed on the side of the second insertion layer 62 away from the substrate 1, and the third insertion layer 63 is used to play a voltage-dividing role; the orthographic projection of the third insertion layer 63 on the substrate 1 completely covers the orthographic projection of the second insertion layer 62 on the substrate 1.

[0064] Specifically, the third insertion layer 63 is disposed on the side of the second insertion layer 62 away from the substrate 1, and the third insertion layer 63 plays a voltage-dividing role for the cap layer 5, which can further optimize the uniformity of the electric field between the cap layer 5 and the gate 7. Exemplarily, the first insertion layer 61, the second insertion layer 62, and the third insertion layer 63 can all be in-situ grown from bottom to top by MOCVD or MBE (Molecular Beam Epitaxy) and subjected to corresponding doping to be formed.

[0065] In addition, the third insertion layer 63 can also play a role in reducing the surface roughness of the second insertion layer 62. The gate 7 includes a metal material, such as TiN. When the gate and the Al-containing GaN are in direct contact, defects of TiAl compounds will be generated, which remain on the surface of the second insertion layer on the side away from the substrate during the process and cannot be effectively removed, affecting the subsequent process and easily causing yield loss. By introducing the third insertion layer 63, the interface is changed back to the metal contact between GaN and the gate 7, which can avoid the direct contact between the second insertion layer 62 and the gate 7, and at the same time improve the planarization between the gate 7 and the third insertion layer 63, thereby improving the electric field distribution of the gate 7 and further enhancing the reliability of the gate 7.

[0066] Optionally, based on the above embodiments, continue to refer to Figure 3The material of the third insertion layer 63 includes GaN, and its doping includes n-doped, p-doped or np co-doped.

[0067] Specifically, since the second insertion layer 62 is a metal layer, the second insertion layer 62 is used to improve the potential barrier. The third insertion layer 63 is arranged between the second insertion layer 62 and the gate 7, which can not only cut off the electric field inside the second insertion layer 62, but also improve the roughness of the interface of the gate 7, and further improve the voltage resistance of the gate 7.

[0068] Optionally, based on the above embodiments, Figures 1 to 3 , the thickness of the regulating layer 6 is greater than or equal to 4 nm.

[0069] Specifically, if the regulating layer 6 is too thin, the ability to balance the electric field will be reduced. Setting the thickness of the regulating layer 6 to be greater than or equal to 4 nm can effectively extend the distance of the electric field between the cap layer 5 and the gate 7, thereby improving the uniformity of the electric field, better avoiding poor degradation of the Schottky junction, and improving the reliability of the semiconductor device.

[0070] Exemplarily, the thickness of the regulating layer 6 can be set to be greater than or equal to 4 nm and less than or equal to 8 nm. This setting can not only improve the voltage resistance of the gate 7 of the semiconductor device and improve the reliability of the semiconductor device, but also facilitate the miniaturization and thinness of the semiconductor device and reduce the manufacturing cost.

[0071] Optionally, based on the above embodiments, Figure 2 and Figure 3 The cap layer 5 includes a P-type doped layer, and the P-type doped layer includes a GaN layer doped with Mg; the material of the buffer layer 2 includes AlN, GaN or AlGaN; the material of the channel layer 3 includes GaN; the material of the barrier layer 4 includes AlGaN; the semiconductor device also includes a gate 7, which is arranged on the side of the regulating layer 6 away from the substrate 1, and the material of the gate 7 includes titanium nitride or tungsten nitride.

[0072] Figure 4 1 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 1 and Figure 4 This embodiment provides a method for preparing a semiconductor device, comprising:

[0073] S101 . Provide a substrate 1 .

[0074] S102 , forming a buffer layer 2 on one side of the substrate 1 .

[0075] S103 , forming a channel layer 3 on a side of the buffer layer 2 away from the substrate 1 .

[0076] S104 , forming a barrier layer 4 on a side of the channel layer 3 away from the substrate 1 .

[0077] S105 , forming a cap layer 5 on a side of the barrier layer 4 away from the substrate 1 .

[0078] S106 , forming a regulating layer 6 on the side of the cap layer 5 away from the substrate 1 , wherein the orthographic projection of the regulating layer 6 on the substrate 1 at least partially covers the orthographic projection of the cap layer 5 on the substrate 1 , and the regulating layer 6 is used to adjust the uniformity of the electric field of the cap layer 5 .

[0079] The method for preparing a semiconductor device provided in this embodiment, by providing a regulating layer 6 on the side of the cap layer 5 away from the substrate 1, improves the crystal quality of the surface of the cap layer 5, effectively adjusts the electric field slope between the cap layer 5 and the gate 7, reduces the peak of the electric field between the cap layer 5 and the gate 7, thereby improving the electric field distribution of the gate 7 and improving the uniformity of the electric field of the gate 7. On the other hand, such a setting can enhance the potential barrier between the gate 7 and the cap layer 5, better improve the problem of Schottky junction degradation under long-term high voltage of the gate 7, reduce the leakage of the semiconductor device, improve the voltage resistance of the gate 7, and thus improve the reliability of the gate 7 of the semiconductor device.

[0080] Optional, Figure 5 FIG. 1 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 2 and Figure 5 This embodiment provides a method for preparing a semiconductor device, comprising:

[0081] S101 . Provide a substrate 1 .

[0082] S102 , forming a buffer layer 2 on one side of the substrate 1 .

[0083] S103 , forming a channel layer 3 on a side of the buffer layer 2 away from the substrate 1 .

[0084] S104 , forming a barrier layer 4 on a side of the channel layer 3 away from the substrate 1 .

[0085] S105 , forming a cap layer 5 on a side of the barrier layer 4 away from the substrate 1 .

[0086] S201 , forming a first insertion layer 61 on a side of the barrier layer 4 away from the substrate 1 , wherein the first insertion layer 61 is used to reduce the electric field intensity of the cap layer 5 .

[0087] S202, forming a second insertion layer 62 on the side of the first insertion layer 61 away from the substrate 1; the second insertion layer 62 is used to provide a potential barrier, adjust the intensity of the electric field, and cut off the electric field inside the second insertion layer 62; the orthographic projection of the second insertion layer 62 on the substrate 1 completely covers the orthographic projection of the first insertion layer 61 on the substrate 1.

[0088] Specifically, the first insertion layer 61 and the second insertion layer 62 may be both grown in-situ from bottom to top by MOCVD or MBE (Molecular Beam Epitaxy) and then be generated by corresponding doping.

[0089] Optional, Figure 6 FIG. 1 is a flow chart of another method for preparing a semiconductor device provided by an embodiment of the present invention. Figure 3 and Figure 6 This embodiment provides a method for preparing a semiconductor device, comprising:

[0090] S101 . Provide a substrate 1 .

[0091] S102 , forming a buffer layer 2 on one side of the substrate 1 .

[0092] S103 , forming a channel layer 3 on a side of the buffer layer 2 away from the substrate 1 .

[0093] S104 , forming a barrier layer 4 on a side of the channel layer 3 away from the substrate 1 .

[0094] S105 , forming a cap layer 5 on a side of the barrier layer 4 away from the substrate 1 .

[0095] S201 , forming a first insertion layer 61 on a side of the barrier layer 4 away from the substrate 1 , wherein the first insertion layer 61 is used to reduce the electric field intensity of the cap layer 5 .

[0096] S202, forming a second insertion layer 62 on the side of the first insertion layer 61 away from the substrate 1; the second insertion layer 62 is used to provide a potential barrier, adjust the intensity of the electric field, and cut off the electric field inside the second insertion layer 62; the orthographic projection of the second insertion layer 62 on the substrate 1 completely covers the orthographic projection of the first insertion layer 61 on the substrate 1.

[0097] S301 , forming a third insertion layer 63 on a side of the second insertion layer 62 away from the substrate 1 , the third insertion layer 63 is used to divide the voltage, and the orthographic projection of the third insertion layer 63 on the substrate 1 completely covers the orthographic projection of the second insertion layer 62 on the substrate 1 .

[0098] Specifically, the first insertion layer 61, the second insertion layer 62 and the third insertion layer 63 can all be grown in situ from bottom to top by MOCVD or MBE (Molecular Beam Epitaxy) and correspondingly doped. By introducing the third insertion layer 63 and making the GaN of the third insertion layer 63 contact the metal of the gate 7, the direct contact between the second insertion layer 62 and the gate 7 can be avoided, and the planarization between the gate 7 and the third insertion layer 63 can be improved, thereby improving the electric field distribution of the gate 7 and further improving the reliability of the gate 7.

[0099] An optional implementation method, based on the above embodiments, continues to combine Figure 2 and Figure 3 After forming the regulating layer 6 on the side of the cap layer 5 away from the substrate 1, the method may further include: forming a gate 7 on the side of the regulating layer 6 away from the substrate 1. The material of the gate 7 may include titanium nitride or tungsten nitride.

[0100] The method for preparing a semiconductor device provided in this embodiment, by arranging a first insertion layer 61 on the side of the cap layer 5 away from the substrate 1, improves the crystal quality of the surface of the cap layer 5, effectively adjusts the electric field slope between the cap layer 5 and the gate 7, reduces the peak of the electric field between the cap layer 5 and the gate 7, thereby improving the electric field distribution of the gate 7 and improving the uniformity of the electric field of the gate 7. On the other hand, arranging a second insertion layer 62 on the side of the first insertion layer 61 away from the substrate 1 can enhance the barrier between the gate 7 and the cap layer 5, better improve the problem of Schottky junction degradation under long-term high voltage of the gate 7, reduce the leakage of the semiconductor device, improve the voltage resistance of the gate 7, and thus improve the reliability of the gate 7 of the semiconductor device. In addition, arranging a third insertion layer 63 on the side of the second insertion layer 62 away from the substrate 1 can further adjust the interface uniformity between the gate and the second insertion layer 62, thereby improving the voltage division of the third insertion layer 63, thereby further improving the reliability of the gate 7 of the semiconductor device.

[0101] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A buffer layer disposed on one side of the substrate; A channel layer disposed on a side of the buffer layer away from the substrate; A barrier layer disposed on a side of the channel layer away from the substrate; A cap layer disposed on a side of the barrier layer away from the substrate; A regulating layer is arranged on a side of the cap layer away from the substrate, the orthographic projection of the regulating layer on the substrate at least partially covers the orthographic projection of the cap layer on the substrate, and the regulating layer is used to adjust the uniformity of the electric field of the cap layer; The regulating layer comprises a first insertion layer and a second insertion layer; the first insertion layer is arranged on a side of the barrier layer away from the substrate, and the second insertion layer is arranged on a side of the first insertion layer away from the substrate; the first insertion layer is used to reduce the electric field strength of the cap layer; The second insertion layer is used to provide a potential barrier, adjust the intensity of the electric field, and cut off the electric field inside the second insertion layer; The orthographic projection of the second insertion layer on the substrate completely covers the orthographic projection of the first insertion layer on the substrate; a third insertion layer, the third insertion layer being arranged on a side of the second insertion layer away from the substrate, the third insertion layer being used for voltage division; the orthographic projection of the third insertion layer on the substrate completely covering the orthographic projection of the second insertion layer on the substrate; The material of the first insertion layer includes unintentionally doped gallium nitride; The doping of the second insertion layer includes P-doping (p-doped) or N / P co-doping (np co-doped); The material of the third insertion layer includes GaN, and the doping thereof includes p-doped or np co-doped.

2. The semiconductor device according to claim 1, characterized in that: The material of the second insertion layer includes In x Ga 1-x N、Al y Ga 1-y N and In x Al y Ga 1-x-y At least one of N, where 0 <x<1,0<y<1。 3. The semiconductor device according to claim 1, characterized in that: The thickness of the regulating layer is greater than or equal to 4 nm.

4. The semiconductor device according to claim 1, characterized in that: The cap layer includes a P-type doped layer, and the P-type doped layer includes a GaN layer doped with Mg; The material of the buffer layer includes AlN, GaN or AlGaN; the material of the channel layer includes GaN; the material of the barrier layer includes AlGaN; The semiconductor device further comprises a gate, which is arranged on a side of the regulating layer away from the substrate, and a material of the gate comprises titanium nitride or tungsten nitride.

5. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a buffer layer on one side of the substrate; forming a channel layer on a side of the buffer layer away from the substrate; forming a barrier layer on a side of the channel layer away from the substrate; forming a cap layer on a side of the barrier layer away from the substrate; forming a regulating layer on a side of the cap layer away from the substrate, wherein the orthographic projection of the regulating layer on the substrate at least partially covers the orthographic projection of the cap layer on the substrate, and the regulating layer is used to adjust the uniformity of the electric field of the cap layer; The forming of a regulating layer on a side of the cap layer away from the substrate comprises: forming a first insertion layer on a side of the barrier layer away from the substrate, wherein the first insertion layer is used to reduce the electric field strength of the cap layer; A second insertion layer is formed on a side of the first insertion layer away from the substrate; the second insertion layer is used to provide a potential barrier, adjust the intensity of the electric field, and terminate the electric field inside the second insertion layer; the orthographic projection of the second insertion layer on the substrate completely covers the orthographic projection of the first insertion layer on the substrate; The step of forming a regulating layer on a side of the cap layer away from the substrate further comprises: A third insertion layer is formed on a side of the second insertion layer away from the substrate, the third insertion layer is used to play a voltage dividing role, and the orthographic projection of the third insertion layer on the substrate completely covers the orthographic projection of the second insertion layer on the substrate; The material of the first insertion layer includes unintentionally doped gallium nitride; the doping of the second insertion layer includes P-doping (p-doped) or N / P co-doping (np co-doped); the material of the third insertion layer includes GaN, and its doping includes p-doped or np co-doped.

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