Semiconductor device

Abstract

A semiconductor device is provided with: a diode section; a plurality of trench portions provided on the front surface of the semiconductor substrate; a drift region of a first conductivity type provided on the semiconductor substrate; an anode region of a second conductivity type provided above the drift region in the diode section; a first plug region of a second conductivity type provided above the drift region in the diode portion and having a doping concentration higher than that of the anode region; a front surface-side electrode that is provided above the semiconductor substrate; and an interlayer insulating film provided above a mesa portion, the mesa portion being provided between the plurality of trench portions, and the anode region being connected to the front surface-side electrode on a side surface of the plurality of trench portions.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Patent Document 1 describes a semiconductor device having a structure in which “the barrier metal 5 is in ohmic contact with the diode trench electrode 21 a and the p-type contact layer 24 , and is electrically connected to the diode trench electrode and the p-type contact layer 24 ”.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-056498

[0006] Patent Document 2: Japanese Patent Application Publication No. 2022-059487 Summary of the invention

[0007] Technical issues

[0008] In a semiconductor device, it is desirable to increase the forward voltage Vf of a diode portion and reduce the reverse recovery loss Err.

[0009] Technical Solution

[0010] In a first embodiment of the present invention, a semiconductor device is provided, which comprises: a diode portion; a plurality of groove portions, which are arranged on the front side of a semiconductor substrate; a drift region of a first conductivity type, which is arranged on the semiconductor substrate; an anode region of a second conductivity type, which is arranged above the drift region in the diode portion; a first plug region of a second conductivity type, which is arranged above the drift region in the diode portion and has a doping concentration higher than that of the anode region; a front side electrode, which is arranged above the semiconductor substrate; and an interlayer insulating film, which is arranged above a mesa portion, the mesa portion is arranged between the plurality of groove portions, and the anode region is connected to the front side electrode on the side of the plurality of groove portions.

[0011] The semiconductor device may further include a first contact portion extending above the mesa portion in a trench extending direction of the plurality of trench portions and connected to the anode region and the first plug region.

[0012] Any of the above-mentioned semiconductor devices may include a second contact portion, which extends from the side wall of one of the multiple groove portions along the groove arrangement direction of the multiple groove portions on the front side of the semiconductor substrate to the side wall of another groove portion and is connected to the mesa portion.

[0013] In any of the above-mentioned semiconductor devices, the second contact portion may extend beyond at least one of the plurality of trench portions in the trench arrangement direction of the plurality of trench portions and be connected to the at least one trench portion.

[0014] In any of the above semiconductor devices, a width of the first contact portion in the trench arrangement direction may be greater than a width of the second contact portion in the trench extension direction.

[0015] In any of the above semiconductor devices, the second contact portion may be provided above the anode region and the plurality of trench portions alternately provided in the trench arrangement direction.

[0016] In any of the above semiconductor devices, a plurality of the second contact portions may be provided above the anode regions and the plurality of trench portions alternately provided in the trench arrangement direction.

[0017] In any of the above semiconductor devices, the interlayer insulating film may include a first interlayer insulating portion provided between the first plug region and the plurality of trench portions in the trench arrangement direction in a plan view.

[0018] In any of the above semiconductor devices, the interlayer insulating film may include a second interlayer insulating portion provided between the anode region and the plurality of trench portions in the trench arrangement direction in a plan view.

[0019] In any of the above semiconductor devices, a width of the first interlayer insulating portion in a direction in which the trench extends may be greater than a width of the second interlayer insulating portion in the direction in which the trench extends.

[0020] In any of the above-mentioned semiconductor devices, the first interlayer insulating portion can be sandwiched by multiple first contact portions extending along the trench extension direction in the trench arrangement direction, and the first interlayer insulating portion can be sandwiched by multiple second contact portions extending along the trench arrangement direction in the trench extension direction.

[0021] In any of the above-mentioned semiconductor devices, the second interlayer insulating portion can be sandwiched by multiple first contact portions extending along the trench extension direction in the trench arrangement direction, and the second interlayer insulating portion can be sandwiched by multiple second contact portions extending along the trench extension direction in the trench arrangement direction.

[0022] In any of the above-described semiconductor devices, the front-side electrode may include a barrier metal layer provided inside the first contact portion and the second contact portion.

[0023] Any of the above semiconductor devices may include a transistor portion having a base region of the second conductivity type provided above the drift region, and a doping concentration of the anode region may be lower than a doping concentration of the base region.

[0024] In any of the above-mentioned semiconductor devices, the transistor portion may include a contact region of the second conductivity type, the contact region of the second conductivity type is provided above the drift region, and the doping concentration of the first plug region may be higher than the doping concentration of the contact region.

[0025] In any of the above semiconductor devices, the transistor portion may include a second plug region of the second conductivity type, the second plug region being provided above the drift region and having a doping concentration higher than a doping concentration of the base region.

[0026] In any of the above semiconductor devices, the doping concentration of the anode region may be 4E16cm -3 Above and 1E17cm -3 the following.

[0027] In any of the above semiconductor devices, the doping concentration of the first plug region may be 2E19 cm -3 Above and 2E20cm -3 the following.

[0028] In any of the above-mentioned semiconductor devices, the first plug region can be arranged separately from the groove sidewalls of the multiple groove portions in the groove arrangement direction of the multiple groove portions, the anode region can be extended from one groove sidewall of the multiple groove portions to another groove sidewall in the groove arrangement direction, and the first plug region and the anode region can be alternately arranged in the mesa portion in the groove extension direction of the multiple groove portions.

[0029] In any of the above semiconductor devices, in the mesa portion, an area of ​​the anode region on the front surface of the semiconductor substrate may be larger than an area of ​​the first plug region on the front surface of the semiconductor substrate.

[0030] In any of the above-mentioned semiconductor devices, the front-side electrode may include a plug layer made of tungsten.

[0031] In any of the semiconductor devices described above, the diode portion may include a cathode region of the first conductivity type disposed on the back surface of the semiconductor substrate, and the doping concentration of the cathode region may be 5E19cm -3 Above and 2E20cm -3 the following.

[0032] It should be noted that the above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 1 is a diagram showing an example of the upper surface of the semiconductor device 100 of this example.

[0034] Figure 2A 1 is a diagram showing an example of the upper surface of the semiconductor device 100 of this example.

[0035] Figure 2B 1 is a diagram showing an example of aa′ cross section of the semiconductor device 100 of this example.

[0036] Figure 2C 1 is a diagram showing an example of a cross section taken along the line bb′ of the semiconductor device 100 of this example.

[0037] Figure 2D 1 is a diagram showing an example of a CC' cross section of the semiconductor device 100 of this example.

[0038] Figure 2E 1 is a diagram showing an example of a dd' cross section of the semiconductor device 100 of this example.

[0039] Figure 2F 1 is a diagram showing an example of a cross section taken along line ee′ of the semiconductor device 100 of this example.

[0040] Figure 3 This is a diagram showing an example of an enlarged view of the upper surface of the semiconductor device 100 of this example.

[0041] Figure 4 This is a diagram showing a modified example of an enlarged view of the upper surface of the semiconductor device 100 of this example.

[0042] Figure 5 FIG. 5 is a diagram showing an example of the upper surface of a semiconductor device 500 according to a comparative example.

[0043] Fig. 6A 1 is a diagram showing a modified example of the upper surface of the semiconductor device 100 of this example.

[0044] Figure 6B 1 is a diagram showing an example of a cross section taken along the line ff' of the semiconductor device 100 of this example.

[0045] Figure 6C 1 is a diagram showing an example of a gg′ cross section of the semiconductor device 100 of this example.

[0046] Fig.6D 1 is a diagram showing an example of a cross section taken along the line hh′ of the semiconductor device 100 of this example.

[0047] Fig. 7A FIG. 1 is a diagram showing a modification of the top view of the semiconductor device 100 of this example.

[0048] Figure 7B FIG. 1 is a diagram showing a modification of the top view of the semiconductor device 100 of this example.

[0049] Figure 8 2 is a diagram showing the relationship between the forward voltage Vf and the reverse recovery loss Err of the semiconductor device 100 of this example.

[0050] Explanation of symbols

[0051] 10…semiconductor substrate, 12…emitter region, 14…base region, 15…contact region, 16…accumulation region, 17…well region, 18…drift region, 19…anode region, 20…buffer region, 21…front surface, 22…collector region, 23…back surface, 24…back surface side electrode, 25…connection portion, 30…dummy groove portion, 31…extension portion, 32…dummy insulating film, 33…connection portion, 34…dummy conductive portion, 38…interlayer insulating film, 40…gate groove portion, 41…extension portion, 42…gate insulating film, 43…connection portion, 44…gate conductive portion, 50…gate metal layer, 51…extension portion, 52…gate insulating film, 53…connection portion, 54…gate conductive portion, 55…gate metal layer, 56…gate metal layer, 57…gate metal layer, 58…gate metal layer, 59…gate metal layer, 60…gate metal layer, 61…extension portion, 62…gate insulating film, 63…connection portion, 64…gate conductive portion, 65…gate metal layer, 66…gate metal layer, 67…gate metal layer, 68…gate metal layer, 69…gate metal layer, 70…gate metal layer, 71…extension portion, 72…gate insulating film, 73…connection portion, 74…gate conductive portion, 75…gate metal layer, 76…gate metal layer, 77…gate metal layer, 78…gate metal layer, 79…gate metal layer, 80…gate metal layer, 81…gate metal layer, 82…gate metal layer, 83…gate metal layer, 84…gate metal layer, 85…gate metal layer, 86…gate metal layer, 87…gate metal layer, 2…front-side electrode, 54…contact portion, 55…contact hole, 56…contact hole, 61…barrier metal layer, 62…plug layer, 70…transistor portion, 71…mesa portion, 73…second plug region, 80…diode portion, 81…mesa portion, 82…cathode region, 83…first plug region, 100…semiconductor device, 154…first contact portion, 254…second contact portion, 181…first cathode portion, 182…second cathode portion, 381…first interlayer insulating portion, 382…second interlayer insulating portion, 383…third interlayer insulating portion, 500…semiconductor device, 554…contact portion DETAILED DESCRIPTION

[0052] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0053] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper", "lower", "front", and "back" are not limited to the direction of gravity or the mounting direction to a substrate when a semiconductor device is actually mounted.

[0054] In this specification, orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis are sometimes used to explain technical matters. Orthogonal coordinate axes are only used to determine the relative positions of components and do not limit specific directions. For example, the Z-axis is not limited to indicating the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the positive and negative are not recorded but the Z-axis direction is recorded, it means a direction parallel to the +Z-axis and the -Z-axis.

[0055] In this specification, the plane parallel to the upper surface of the semiconductor substrate is referred to as the XY plane, and the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X axis and the Y axis. In addition, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z axis. The depth direction of the semiconductor substrate is sometimes referred to as the Z axis. It should be noted that in this specification, the situation of observing the semiconductor substrate along the Z axis direction is referred to as a top view. In addition, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X axis and the Y axis, is sometimes referred to as a horizontal direction.

[0056] In each embodiment, an example is shown in which the first conductivity type is set to N type and the second conductivity type is set to P type, but the first conductivity type may be set to P type and the second conductivity type may be set to N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment become opposite polarities.

[0057] In this specification, when it is said that they are "same" or "equal", it may include the case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0058] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. In this specification, impurities sometimes specifically refer to any one of N-type donors and P-type acceptors, and are sometimes described as dopants. In this specification, doping refers to introducing donors or acceptors into a semiconductor substrate and making a semiconductor showing N-type conductivity or a semiconductor showing P-type conductivity.

[0059] In this specification, the doping concentration refers to the concentration of donors or the concentration of acceptors in a thermal equilibrium state.

[0060] In this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type. In addition, in this specification, when it is described as P++ type or N++ type, it means that the doping concentration is higher than the doping concentration of P+ type or N+ type.

[0061] Figure 1FIG. 1 shows an example of the upper surface of the semiconductor device 100 of this example. The semiconductor device 100 may include a diode portion 80 having an anode region 19 and a first plug region 83 on a front surface 21 of the semiconductor substrate 10 described later. The semiconductor device 100 includes an interlayer insulating film 38, a first contact portion 154, and a second contact portion 254 above the front surface 21 of the semiconductor substrate 10, but Figure 1 The interlayer insulating film 38 , the first contact portion 154 , and the second contact portion 254 will be described later. In addition, the semiconductor device 100 of this example includes a front surface electrode 52 provided above the front surface 21 of the semiconductor substrate 10 .

[0062] A plurality of groove portions extending in a predetermined direction (in this example, the Y-axis direction) and arranged in a predetermined direction (in this example, the X-axis direction) are provided on the front surface 21 of the semiconductor substrate 10. The plurality of groove portions include a dummy groove portion 30 to which a floating potential or an anode potential is applied. The diode portion 80 of this example includes the dummy groove portion 30. In the case where the semiconductor device 100 includes a transistor portion, the diode portion 80 may include a gate groove portion to which a gate potential is applied.

[0063] The diode portion 80 is a region obtained by projecting a cathode region 82 provided on the back surface of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. As an example, the cathode region 82 in this example is an N+ type. The details of the cathode region 82 will be described later.

[0064] exist Figure 1 In the figure, the area around the chip end as the edge (end) side of the semiconductor device 100 is shown, and other areas are omitted. For example, an edge terminal structure portion can be provided in the area on the negative side in the Y-axis direction of the semiconductor device 100 in this example. The edge terminal structure portion alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge terminal structure portion has, for example, a guard ring, a field plate, a structure for reducing the surface electric field, and a combination thereof. It should be noted that in this example, for convenience, the edge on the negative side in the Y-axis direction is described, but the same is true for other edges of the semiconductor device 100. The edge terminal structure portion can be provided in a manner that surrounds an active area in which a main current flows when the semiconductor device 100 is in operation.

[0065] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0066] The front side electrode 52 is provided above the dummy groove portion 30, the well region 17, and the anode region 19. The front side electrode 52 is formed of a material containing a metal. At least a portion of the front side electrode 52 may be formed of a metal such as aluminum (Al) or an alloy containing aluminum, such as an aluminum-silicon alloy (Al-Si), an aluminum-silicon-copper alloy (Al-Si-Cu), or the like.

[0067] The front-side electrode 52 may include a barrier metal layer 61 formed of titanium, a titanium compound, etc., in the lower layer of the region formed of aluminum or an alloy containing aluminum, etc. That is, the front-side electrode may include a barrier metal layer 61 provided inside the first contact portion 154 and the second contact portion 254 described later. The barrier metal layer 61 will be described later.

[0068] The front-side electrode 52 is provided above the semiconductor substrate 10 via the interlayer insulating film 38. Figure 1 The interlayer insulating film 38 is omitted in FIG. A contact hole 56 is provided through the interlayer insulating film 38 .

[0069] The contact hole 56 connects the front electrode 52 to the dummy conductive portion in the dummy groove portion 30. A plug layer 62 made of tungsten or the like may be formed inside the contact hole 56 via the barrier metal layer 61. That is, the front electrode 52 may include the plug layer 62 made of tungsten. The plug layer 62 will be described later.

[0070] The connection portion 25 electrically connects the front side electrode 52 to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the front side electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. The connection portion 25 of this example is polysilicon doped with N-type impurities (N+). The connection portion 25 is provided above the front side 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0071] The dummy groove portion 30 is a groove portion electrically connected to the front side electrode 52. The dummy groove portion 30 is arranged at a predetermined interval along a predetermined arrangement direction (in this example, the X-axis direction). The dummy groove portion 30 of this example may have two extension portions 31 extending along an extension direction (in this example, the Y-axis direction) parallel to the front side 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 33 connecting the two extension portions 31.

[0072] At least a portion of the connection portion 33 may be formed in a curved shape. By connecting the ends of the two extension portions 31 of the dummy groove portion 30, the electric field concentration at the ends of the extension portion 31 can be alleviated. At the connection portion 33 of the dummy groove portion 30, the front side electrode 52 may be connected to the dummy conductive portion.

[0073] The mesa portion 81 is provided in the region sandwiched between the adjacent dummy groove portions 30 in the diode portion 80. The mesa portion may be a portion of the semiconductor substrate 10 sandwiched between two adjacent groove portions, and is a portion extending from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each groove portion. The extension portion of each groove portion may be regarded as one groove portion. That is, the region sandwiched between the two extension portions may be regarded as the mesa portion.

[0074] The mesa portion 81 has the anode region 19 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has the anode region 19 and the well region 17 on the negative side in the Y-axis direction.

[0075] The well region 17 is a region of the second conductivity type provided on the surface on the front surface 21 side of the semiconductor substrate 10. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. As an example, the well region 17 is of P+ type.

[0076] The well region 17 is formed in a predetermined range from the end of the active region on the side where the front-side electrode 52 is provided. The well region 17 may be provided in a predetermined range from the active region on the side close to the edge terminal structure portion to the edge terminal structure portion. The diffusion depth of the well region 17 may be deeper than the depth of the dummy groove portion 30. A part of the dummy groove portion 30 is formed in the well region 17. The bottom of the end of the dummy groove portion 30 in the extension direction may be covered by the well region 17.

[0077] The anode region 19 is a region of the second conductivity type disposed above the drift region 18. The drift region 18 will be described later. As an example, the anode region 19 of this example is of P-type. The doping concentration of the anode region 19 may be 4E16 cm -3 Above, it can be 1E17cm -3 It should be noted that E refers to a power of 10, for example 1E18cm -3 It means 1×10 18 cm -3 .

[0078] The anode region 19 of this example is provided on the front surface 21 of the mesa portion 81. The anode region 19 can be provided along the X-axis direction from one of the two dummy groove portions 30 sandwiching the mesa portion 81 to the other dummy groove portion 30. That is, the anode region 19 can be extended from one groove side wall of the plurality of groove portions to the other groove side wall in the groove arrangement direction of the plurality of groove portions. The anode region 19 is electrically connected to the front side electrode 52 on the side surface of the plurality of groove portions.

[0079] The first plug region 83 is a region of the second conductivity type with a doping concentration higher than that of the anode region 19. As an example, the first plug region 83 of this example is of P++ type. The doping concentration of the first plug region 83 can be 2E19cm -3 Above and 2E20cm -3 the following.

[0080] The first plug region 83 of this example is provided separately from the trench sidewalls of the plurality of trench portions in the trench arrangement direction of the plurality of trench portions. The anode region 19 may be provided between the first plug region 83 and the trench sidewalls on the front surface 21 of the semiconductor substrate 10. Thus, the amount of dopants injected into the first plug region 83 can be reduced, and the forward voltage Vf of the diode portion 80 can be increased.

[0081] In the mesa portion 81, the first plug region 83 and the anode region 19 may be alternately arranged in the trench extension direction of the plurality of trench portions. In the mesa portion 81, the area of ​​the anode region 19 on the front surface 21 of the semiconductor substrate 10 may be larger than the area of ​​the first plug region 83 on the front surface 21 of the semiconductor substrate 10. By adjusting the amount of the second conductive type dopant in the diode portion 80, the forward voltage Vf and the reverse recovery loss Err of the diode portion 80 can be adjusted.

[0082] Figure 2A FIG. 1 is a diagram showing an example of the upper surface of the semiconductor device 100 of this example. Figure 2A In the Figure 1 The interlayer insulating film 38, the first contact portion 154 and the second contact portion 254 are omitted.

[0083] The first contact portion 154 and the second contact portion 254 are provided inside a contact hole provided to extend from the upper surface of the interlayer insulating film 38 in the depth direction of the semiconductor substrate 10. The first contact portion 154 and the second contact portion 254 are provided to extend in directions different from each other. The first contact portion 154 and the second contact portion 254 may be provided to cross each other. The first contact portion 154 and the second contact portion 254 may be formed integrally.

[0084] The first contact portion 154 and the second contact portion 254 are examples of the front-side electrode 52 . The first contact portion 154 and the second contact portion 254 include a barrier metal layer 61 and a plug layer 62 inside the interlayer insulating film 38 .

[0085] The first contact portion 154 may be provided above the mesa portion 81 to extend along the groove extension direction of the plurality of groove portions. The first contact portion 154 may be connected to the anode region 19, the first plug region 83, or both.

[0086] A plurality of first contact portions 154 may be provided in the semiconductor device 100. The first contact portions 154 of this example are arranged in a stripe shape along the dummy trench portion 30. By injecting a dopant through a contact hole for providing the first contact portion 154, a first plug region 83 is formed, thereby adjusting the amount of the second conductivity type dopant in the diode portion 80, and adjusting the forward voltage Vf and the reverse recovery loss Err of the diode portion 80.

[0087] The second contact portion 254 may be provided on the front surface 21 of the semiconductor substrate 10 in a manner extending from one groove sidewall to another groove sidewall in the groove arrangement direction of the plurality of groove portions, and connected to the mesa portion 81. The second contact portion 254 may extend over at least one of the plurality of groove portions in the groove arrangement direction of the plurality of groove portions, and connected to at least one groove portion. The second contact portion 254 of this example is provided to extend along the groove arrangement direction of the plurality of groove portions, and connected to the plurality of groove portions and the mesa portion 81.

[0088] The second contact portion 254 may be disposed above the anode region 19 and the plurality of groove portions alternately disposed in the groove arrangement direction. The second contact portion 254 may be disposed in common on the plurality of mesa portions 81 in the groove arrangement direction of the plurality of groove portions, or may be disposed on a single mesa portion 81 .

[0089] By providing the second contact portion 254, the area of ​​the connection portion between the front-side electrode 52 in the anode region 19 and the semiconductor substrate 10 can be increased compared to the case where the second contact portion 254 is not provided. Thus, the holes injected from the first plug region 83 are extracted through the second contact portion 254, thereby increasing the forward voltage Vf of the diode portion.

[0090] A plurality of second contact portions 254 may be provided in the semiconductor device 100. The plurality of second contact portions 254 may be provided above the anode region 19 and the plurality of groove portions alternately provided in the groove arrangement direction. The second contact portions 254 of this example are arranged in a stripe shape along a direction orthogonal to the dummy groove portion 30. By providing the second contact portions 254, it is possible to prevent the plug layer 62 formed of tungsten or the like from being peeled off.

[0091] The interlayer insulating film 38 is provided above the mesa portion 81 provided between the plurality of groove portions. The interlayer insulating film 38 may be provided above the plurality of groove portions.

[0092] The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a BPSG (Boro-phosphoSilicate Glass) film, a BSG (borosilicate glass) film, or a PSG (Phosphosilicate glass) film. The interlayer insulating film 38 may also include a high temperature oxide (HTO) silicon film.

[0093] The interlayer insulating film 38 of this example includes a first interlayer insulating portion 381 and a second interlayer insulating portion 382. The first interlayer insulating portion 381 and the second interlayer insulating portion 382 may be made of the same material or different materials.

[0094] The first interlayer insulating portion 381 is provided between the first plug region 83 and the plurality of trench portions in the trench arrangement direction in a plan view. By providing the first interlayer insulating portion 381, the amount of dopant implanted when forming the first plug region 83 can be adjusted.

[0095] The first interlayer insulating portion 381 is provided in a manner sandwiched by a plurality of first contact portions 154 extending in the trench extending direction in the trench arrangement direction. The first interlayer insulating portion 381 is provided in a manner sandwiched by a plurality of second contact portions 254 extending in the trench arrangement direction in the trench extending direction. That is, the first interlayer insulating portion 381 is provided in an island shape above the upper surface of the semiconductor substrate 10. Thus, the area of ​​the plug layer 62 of the front side electrode 52 is reduced, and film peeling of the plug layer 62 is suppressed.

[0096] The second interlayer insulating portion 382 is provided between the anode region 19 and the plurality of trenches in the trench arrangement direction in a plan view. The second interlayer insulating portion 382 can adjust the area of ​​the portion where the second contact portion 254 is connected to the anode region 19 and adjust the characteristics of the semiconductor device 100.

[0097] The second interlayer insulating portion 382 is provided in a manner sandwiched by a plurality of first contact portions 154 extending in the trench extending direction in the trench arrangement direction. The second interlayer insulating portion 382 is provided in a manner sandwiched by a plurality of second contact portions 254 extending in the trench arrangement direction in the trench extending direction. That is, the second interlayer insulating portion 382 is provided in an island shape above the upper surface of the semiconductor substrate 10. Thus, the area of ​​the plug layer 62 of the front-side electrode 52 is reduced, and film peeling of the plug layer 62 is suppressed.

[0098] Figure 2B It is shown Figure 2A1 is a diagram of an example of an a-a' cross section in FIG. The a-a' cross section is an XZ cross section passing through the second contact portion 254. The semiconductor device 100 of this example has a semiconductor substrate 10, a front side electrode 52 and a back side electrode 24 in the a-a' cross section, and the semiconductor substrate 10 is provided with a drift region 18, an anode region 19, a cathode region 82 and a buffer region 20.

[0099] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. As an example, the drift region 18 of this example is of N-type. The drift region 18 may be a region remaining without forming other doping regions in the semiconductor substrate 10. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0100] A buffer region 20 of the first conductivity type may be provided below the drift region 18. The buffer region 20 in this example is of N type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface side of the anode region 19 from reaching the cathode region 82.

[0101] The back electrode 24 is formed on the back side 23 of the semiconductor substrate 10. The back electrode 24 is formed of a conductive material such as a metal. The material of the back electrode 24 can be the same as or different from the material of the front electrode 52. In addition, the back electrode 24 can be a stack of multiple metal layers composed of different materials. As an example, the back electrode 24 is a cathode electrode.

[0102] One or more dummy groove portions 30 are provided on the front surface 21. Each groove portion is provided from the front surface 21 to the drift region 18. In the region where the anode region 19 is provided, each groove portion penetrates the anode region 19 and reaches the drift region 18. The groove portion penetrating the doped region is not limited to the case where the groove portion is formed after the doped region is formed. The case where the doped region is formed between the groove portions after the groove portion is formed is also included in the case where the groove portion penetrates the doped region.

[0103] The dummy groove portion 30 includes a dummy groove formed on the front surface 21 side, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed so as to cover the inner wall of the dummy groove. The dummy conductive portion 34 is formed inside the dummy groove and is formed at a position further inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10.

[0104] The cathode region 82 is provided on the back surface 23 of the semiconductor substrate 10 in the diode portion 80. The cathode region 82 is a region of the first conductivity type having a doping concentration higher than that of the drift region 18. The doping concentration of the cathode region may be 5E19cm -3 Above, it can be 2E20cm -3the following.

[0105] exist Figure 2B In the cross section shown, the interlayer insulating film 38 is not provided on the front surface 21. Therefore, compared with the case where the interlayer insulating film 38 is provided, holes are easily extracted from the anode region 19, and the forward voltage Vf of the diode portion can be increased.

[0106] A barrier metal layer 61 made of titanium, a titanium compound or the like may be provided between the front surface 21 and the front surface-side electrode 52. In addition, a plug layer 62 made of tungsten or the like may be provided on the upper surface of the barrier metal layer 61.

[0107] Figure 2C It is shown Figure 2A FIG. 1 is a diagram showing an example of a bb' cross section in FIG. The bb' cross section is an XZ cross section that passes through the second interlayer insulating portion 382 but not through the first plug region 83. Figure 2C , for Figure 2B Different points are explained.

[0108] The front electrode 52 has a first contact portion 154. The first contact portion 154 is provided so as to be sandwiched between the second interlayer insulating portion 382 in the trench arrangement direction of the plurality of trench portions. That is, the first contact portion 154 is provided so as to be buried inside a contact hole provided in the interlayer insulating film 38.

[0109] The first contact portion 154 may have a barrier metal layer 61 formed of titanium, a titanium compound, etc. inside. A plug layer 62 formed of tungsten, etc. may be formed inside the barrier metal layer 61. The semiconductor substrate 10 is connected to the front-side electrode 52 via the first contact portion 154. It should be noted that the barrier metal layer 61 may also be provided on the upper surface of the second interlayer insulating portion 382.

[0110] exist Figure 2C In the embodiment, a second interlayer insulating portion 382 is provided on the front surface 21 of the semiconductor substrate 10. The second interlayer insulating portion 382 may be provided in a manner sandwiched by two first contact portions 154 in the trench arrangement direction of the plurality of trench portions. In addition, the dummy trench portion 30 is covered by the second interlayer insulating portion 382 on the front surface 21.

[0111] Figure 2D It is shown Figure 2A FIG. 1 is a diagram showing an example of a c-c' cross section in FIG. The c-c' cross section is an XZ cross section passing through the first interlayer insulating portion 381 and the first plug region 83. Figure 2D , for Figure 2B and Figure 2C Different points are explained.

[0112] The first contact portion 154 is provided so as to be sandwiched between the first interlayer insulating portion 381 in the trench arrangement direction of the plurality of trench portions. That is, the first contact portion 154 is provided so as to be buried inside a contact hole provided in the interlayer insulating film 38 .

[0113] The first contact portion 154 may have a barrier metal layer 61 formed of titanium, a titanium compound, etc. inside. A plug layer 62 formed of tungsten, etc. may be formed inside the barrier metal layer 61. The semiconductor substrate 10 is connected to the front-side electrode 52 via the first contact portion 154. It should be noted that the barrier metal layer 61 may also be provided on the upper surface of the first interlayer insulating portion 381.

[0114] The first plug region 83 is provided below the first contact portion 154. The first plug region 83 may be formed by implanting a dopant through a contact hole for providing the first contact portion 154. By providing the first plug region 83, the semiconductor substrate 10 and the front-side electrode 52 can be in ohmic contact.

[0115] exist Figure 2D In the embodiment, a first interlayer insulating portion 381 is provided on the front surface 21 of the semiconductor substrate 10. The first interlayer insulating portion 381 may be provided in a manner of being sandwiched by two first contact portions 154 in the trench arrangement direction of the plurality of trench portions. In addition, the dummy trench portion 30 is covered by the first interlayer insulating portion 381 on the front surface 21. By providing the first interlayer insulating portion 381, the amount of dopant injected when forming the first plug region 83 can be adjusted.

[0116] Figure 2E It is shown Figure 2A The dd′ cross section is a YZ cross section passing through the first interlayer insulating portion 381 , the second interlayer insulating portion 382 , the second contact portion 254 , and the dummy trench portion 30 .

[0117] like Figure 2E As shown in FIG. 1 , above the dummy groove portion 30, in a region where the first interlayer insulating portion 381 and the second interlayer insulating portion 382 are not provided, the front-side electrode 52 is connected to the dummy conductive portion 34. Even if the dummy conductive portion 34 is connected to the front-side electrode 52, it does not affect the value of the forward voltage Vf of the diode portion 80, so by designing in this way, the characteristics of the semiconductor device 100 can be adjusted without additional manufacturing costs.

[0118] The second contact portion 254 is provided between the first interlayer insulating portion 381 and the second interlayer insulating portion 382 in the trench extending direction of the plurality of trench portions. That is, the second contact portion 254 is provided in the contact hole formed in the interlayer insulating film 38 along the trench arrangement direction of the plurality of trench portions.

[0119] The second contact portion 254 may also have a barrier metal layer 61 formed of titanium, a titanium compound, etc. inside, similarly to the first contact portion 154. In addition, a plug layer 62 formed of tungsten, etc. may be provided inside the barrier metal layer 61. The semiconductor substrate 10 is connected to the front-side electrode 52 via the second contact portion 254. It should be noted that the barrier metal layer 61 may also be provided on the upper surfaces of the first interlayer insulating portion 381 and the second interlayer insulating portion 382.

[0120] The first interlayer insulating portion 381 may be provided in a manner sandwiched by two second contact portions 254 in the groove extension direction of the plurality of groove portions. The second interlayer insulating portion 382 may be provided in a manner sandwiched by two second contact portions 254 in the groove extension direction of the plurality of groove portions. In this way, by configuring the first interlayer insulating portion 381 and the second interlayer insulating portion 382 in an island shape, the area of ​​the front-side electrode 52 can be reduced, and film peeling of the front-side electrode 52 can be suppressed.

[0121] Figure 2F It is shown Figure 2A The ee′ cross section is a YZ cross section passing through the first contact portion 154 , the anode region 19 , and the first plug region 83 .

[0122] The first contact portion 154 is provided so as to extend along the groove extension direction of the plurality of groove portions, and is connected to the semiconductor substrate 10. The first contact portion 154 is connected to the anode region 19 and the first plug region 83. A portion of the holes injected from the first plug region 83 is extracted from the first contact portion 154 via the anode region 19, thereby increasing the forward voltage of the diode portion 80 and reducing the reverse recovery loss Err.

[0123] Figure 3 FIG. 1 is a diagram showing an example of an enlarged view of the upper surface of the semiconductor device 100 of this example. Figure 3 , an enlarged view of a mesa portion 81 disposed between two dummy groove portions 30 is shown. Figure 3 In FIG. 1 , the first contact portion 154 and the second contact portion 254 are indicated by hatching from the upper right to the lower left, and the position of the first plug region 83 provided below these contact portions is indicated by hatching from the upper left to the lower right.

[0124] The shaded portion may include a barrier metal layer 61 (not shown) formed of titanium, a titanium compound, etc. In addition, a plug layer 62 (not shown) formed of tungsten, etc. may be provided inside the barrier metal layer 61. Furthermore, the barrier metal layer 61 may also be provided on the upper surface (not shown) of the interlayer insulating film 38 (the first interlayer insulating portion 381 and the second interlayer insulating portion 382).

[0125] The first contact portion 154 has a predetermined width W154 in the groove arrangement direction of the plurality of groove portions. The width W154 of the first contact portion 154 in the groove arrangement direction may be greater than the width W254 of the second contact portion 254 in the groove extension direction. In one example, W154 may be greater than 0.1 μm and less than 1.0 μm.

[0126] The second contact portion 254 has a predetermined width W254 in the groove extension direction of the plurality of groove portions. The width W254 of the second contact portion 254 in the groove extension direction may be smaller than the width W154 of the first contact portion 154 in the groove arrangement direction. In one example, W254 may be greater than 0.1 μm and less than 1.0 μm.

[0127] The first interlayer insulating portion 381 has a predetermined width W381 in the trench extension direction of the plurality of trench portions. The width W381 of the first interlayer insulating portion 381 in the trench extension direction is greater than the width W382 of the second interlayer insulating portion 382 in the trench extension direction. Thus, the amount of dopant in the diode portion 80 can be increased, and the withstand voltage of the semiconductor device 100 can be improved. In one example, W381 can be greater than 0.1 μm and can be less than 1.0 μm.

[0128] The second interlayer insulating portion 382 has a predetermined width W382 in the trench extension direction of the plurality of trench portions. The width W382 of the second interlayer insulating portion 382 in the trench extension direction is smaller than the width W381 of the first interlayer insulating portion 381 in the trench extension direction. In one example, W382 may be greater than or equal to 0 μm and less than or equal to 0.8 μm.

[0129] Figure 4 FIG. 1 is a diagram showing a modified example of an enlarged view of the upper surface of the semiconductor device 100 of this example. Figure 4 , for Figure 3 Different points are explained.

[0130] The interlayer insulating film 38 includes a third interlayer insulating portion 383 disposed above the dummy trench portion 30. The third interlayer insulating portion 383 may be disposed between the first interlayer insulating portion 381 and the second interlayer insulating portion 382 in the trench extension direction of the plurality of trench portions. The third interlayer insulating portion 383 may extend from above the dummy trench portion 30 in the trench arrangement direction of the plurality of trench portions and be disposed above the anode region 19.

[0131] The material of the third interlayer insulating portion 383 may be the same as or different from that of the first interlayer insulating portion 381 and the second interlayer insulating portion 382. When the materials of the first interlayer insulating portion 381, the second interlayer insulating portion 382, ​​and the third interlayer insulating portion 383 are all the same, the three interlayer insulating portions may not be distinguished.

[0132] That is, the interlayer insulating film 38 may be provided in a manner extending along the groove extension direction of the plurality of groove portions and covering the upper surface of the dummy groove portion 30. In addition, the interlayer insulating film 38 may extend along the groove arrangement direction of the plurality of groove portions at predetermined intervals W254 from above the dummy groove portion 30 in a manner having predetermined widths W381 and W382. In this case, the interlayer insulating film 38 may be formed in a comb-teeth shape.

[0133] The shaded portion may include a barrier metal layer 61 (not shown) formed of titanium, a titanium compound, etc. In addition, a plug layer 62 (not shown) formed of tungsten, etc. may be provided inside the barrier metal layer 61. Furthermore, the barrier metal layer 61 may also be provided on the upper surface (not shown) of the interlayer insulating film 38 (the first interlayer insulating portion 381, the second interlayer insulating portion 382, ​​and the third interlayer insulating portion 383).

[0134] The second contact portion 254 is provided so as to extend from an end of one third interlayer insulating portion 383 along the trench arrangement direction of the plurality of trench portions to an end of another third interlayer insulating portion 383 in a plan view, and is connected to the mesa portion 81. Thus, holes injected from the first plug region 83 can be extracted from the second contact portion 254 via the anode region 19, and the forward voltage Vf of the diode portion 80 can be increased.

[0135] Figure 5 1 is a diagram showing an example of the upper surface of a semiconductor device 500 according to a comparative example. Figure 5 , and an example of the upper surface of the semiconductor device 100 of this example is shown Figure 2A Different points are explained.

[0136] In the semiconductor device 500 of the comparative example, the second contact portion 254 is not provided, but only the contact portion 554 is provided. The contact portion 554 may have the same configuration as the first contact portion 154 in the semiconductor device 100 of this example. That is, the contact portion 554 may be provided inside a contact hole formed in the interlayer insulating film.

[0137] In the semiconductor device 500 of the comparative example, since the second contact portion 254 is not provided, the amount of holes extracted from the front electrode 52 is smaller than that of the semiconductor device 100 of the present example. Therefore, the semiconductor device 500 of the comparative example has a smaller forward voltage Vf and an increased reverse recovery loss Err than the semiconductor device 100 of the present example.

[0138] Fig. 6A 1 is a diagram showing a modified example of the upper surface of the semiconductor device 100 of this example. The semiconductor device 100 may be a semiconductor chip further including a transistor unit 70. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor unit 70 may include a boundary region in a portion adjacent to the diode unit 80. The transistor unit 70 of this example does not include a boundary region.

[0139] The transistor section 70 is a region obtained by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 has the second conductivity type. As an example, the collector region 22 in this example is a P+ type. The transistor section 70 includes a transistor such as an IGBT.

[0140] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, a well region 17, and an anode region 19 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example includes a second plug region 73 provided in a mesa portion 71 of a transistor portion 70 and a first plug region 83 provided in a mesa portion 81 of a diode portion 80. In addition, the semiconductor device 100 of this example includes a front-side electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0141] The interlayer insulating film 38 of this example includes a first interlayer insulating portion 381 and a second interlayer insulating portion 382. The first interlayer insulating portion 381 and the second interlayer insulating portion 382 may be made of the same material or different materials. The second interlayer insulating portion 382 is provided in a manner that is sandwiched by a plurality of first contact portions 154 extending in the trench extension direction in the trench arrangement direction. The second interlayer insulating portion 382 is provided in a manner that is sandwiched by a plurality of second contact portions 254 extending in the trench arrangement direction in the trench extension direction. That is, the second interlayer insulating portion 382 is provided in an island shape above the upper surface of the semiconductor substrate 10. Thus, the area of ​​the plug layer 62 of the front side electrode 52 is reduced, and film peeling of the plug layer 62 is suppressed.

[0142] The gate metal layer 50 is formed of a material containing a metal. At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al) or an alloy containing aluminum, such as an aluminum-silicon alloy (Al-Si), an aluminum-silicon-copper alloy (Al-Si-Cu), or the like. The gate metal layer 50 is provided separately from the front side electrode 52.

[0143] The front electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 via the interlayer insulating film 38. The interlayer insulating film 38 is formed on the semiconductor substrate 10. Fig. 6A A contact hole 55 is provided through the interlayer insulating film 38 .

[0144] The contact hole 55 connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70. Inside the contact hole 55, a plug made of tungsten or the like may be formed via a barrier metal.

[0145] exist Fig. 6A In the illustrated variation, a contact portion 54 is provided in the transistor portion 70. The contact portion 54 is formed on the upper surface of each region of the emitter region 12 and the contact region 15. The width of the contact portion 54 in the groove arrangement direction of the plurality of groove portions may be the same as the width of the first contact portion 154 in the groove arrangement direction, or may be the same configuration as the first contact portion 154. The width of the contact portion 54 in the groove arrangement direction may also be different from the width of the first contact portion 154 in the groove arrangement direction.

[0146] The gate groove portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate groove portions 40 of this example may include two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0147] At least a portion of the connection portion 43 may be formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate groove portion 40, the electric field concentration at the ends of the extension portion 41 can be alleviated. At the connection portion 43 of the gate groove portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0148] The transistor portion 70 of this example has a structure in which one gate trench portion 40 and one dummy trench portion 30 are repeatedly arranged. That is, the transistor portion 70 of this example has the gate trench portion 40 and the dummy trench portion 30 at a ratio of 1:1. For example, the transistor portion 70 has one extension portion 31 between two extension portions 41. In addition, the transistor portion 70 has one extension portion 41 between two extension portions 31.

[0149] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 2:3 or 2:4. In addition, the transistor portion 70 may have all trench portions as gate trench portions 40 without having dummy trench portions 30.

[0150] The mesa portion 71 is a mesa portion provided adjacent to the groove portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion 71 is provided adjacent to at least one of the dummy groove portion 30 and the gate groove portion 40 in the transistor portion 70. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are alternately provided on the front surface 21 of the semiconductor substrate 10 in the extending direction of the groove portion (in this example, the Y-axis direction).

[0151] The base region 14 is a region of the second conductivity type disposed above the drift region 18. The doping concentration of the base region 14 may be higher than the doping concentration of the anode region 19. That is, in this example, the doping concentration of the anode region 19 is lower than the doping concentration of the base region 14. As an example, the base region 14 is of P type. The base region 14 may be disposed at both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Fig. 6A In FIG. 1 , only one end portion of the base region 14 in the Y-axis direction is shown.

[0152] The emitter region 12 is a region of the first conductivity type disposed above the base region 14 and having a doping concentration higher than that of the drift region 18. As an example, the emitter region 12 of this example is of N+ type. An example of a dopant of the emitter region 12 is arsenic (As). The emitter region 12 is disposed on the front surface 21 of the mesa portion 71 in contact with the gate groove portion 40. The emitter region 12 can be disposed to extend from one of the two groove portions sandwiching the mesa portion 71 to the other groove portion along the X-axis direction.

[0153] In addition, the emitter region 12 may or may not be in contact with the dummy groove portion 30. In this example, the emitter region 12 is in contact with the dummy groove portion 30.

[0154] The contact region 15 is a region of the second conductivity type having a higher doping concentration than the doping concentration of the base region 14. As an example, the contact region 15 of this example is of P+ type. The contact region 15 of this example is provided on the front surface 21 of the mesa portion 71. The contact region 15 can be provided along the X-axis direction from one of the two groove portions sandwiching the mesa portion 71 to the other groove portion. The contact region 15 may or may not be in contact with the gate groove portion 40 or the dummy groove portion 30. The contact region 15 of this example is in contact with the dummy groove portion 30 and the gate groove portion 40.

[0155] The doping concentration of the contact region 15 is lower than the doping concentration of the first plug region 83 provided in the diode portion 80. That is, the doping concentration of the first plug region 83 is higher than the doping concentration of the contact region 15. The doping concentration of the contact region 15 may be 2E19 cm -3 Above, it can be 2E20cm -3 the following.

[0156] The second plug region 73 is a region of the second conductivity type having a doping concentration higher than that of the base region 14. As an example, the second plug region 73 of this example is of P++ type. The doping concentration of the second plug region 73 may be the same as or different from the doping concentration of the first plug region 83. The second plug region 73 may be formed by implanting a dopant through a contact hole for providing the contact portion 54.

[0157] The second plug region 73 may be provided in the contact region 15 instead of the emitter region 12. The second plug region 73 of this example is provided at the same position as the first plug region 83 in the trench arrangement direction of the plurality of trench portions. Thus, the first plug region 83 and the second plug region 73 can be formed in the same ion implantation process, and the manufacturing cost can be reduced.

[0158] Figure 6B It is shown Fig. 6A FIG. 1 is a diagram of an example of the f-f' cross section in FIG. The f-f' cross section is an XZ cross section passing through the second contact portion 254. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, a front side electrode 52 and a back side electrode 24 in the f-f' cross section, and the semiconductor substrate 10 is provided with an emitter region 12, a base region 14, an accumulation region 16, a drift region 18, a buffer region 20, a first plug region 83 and a second plug region 73. In addition, the cathode region 82 of this example can include a first cathode portion 181 and a second cathode portion 182 in the trench extension direction (Y-axis direction). The first cathode portion 181 and the second cathode portion 182 will be described later.

[0159] The accumulation region 16 is a region of the first conductivity type which is provided at a position lower than the base region 14 in the depth direction of the semiconductor substrate 10 and has a doping concentration higher than the doping concentration of the drift region 18. As an example, the accumulation region 16 of this example is of N+ type. The accumulation region 16 is provided in the transistor portion 70, but not in the diode portion 80. By providing the first accumulation region 16, the carrier injection enhancement effect (IE effect) can be increased, and the on-voltage of the transistor portion 70 can be reduced.

[0160] One or more gate groove portions 40 are provided on the front surface 21. Each groove portion is provided from the front surface 21 to the drift region 18. In the region where at least any one of the emitter region 12, the base region 14, and the storage region 16 is provided, each groove portion also penetrates these regions and reaches the drift region 18. The groove portion penetrating the doped region is not limited to the case where the groove portion is formed after the doped region is formed. The case where the doped region is formed between the groove portions after the groove portions are formed is also included in the case where the groove portion penetrates the doped region.

[0161] The gate groove portion 40 has a gate groove formed on the front side 21, a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is formed in a manner covering the inner wall of the gate groove. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate groove. The gate conductive portion 44 is formed inside the gate groove at a position closer to the inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate groove portion 40 is covered by an interlayer insulating film 38 on the front side 21.

[0162] The gate conductive portion 44 includes a region opposite to the base region 14 adjacent to the mesa portion 71 via the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed in the surface layer of the interface in contact with the gate trench in the base region 14.

[0163] Figure 6C It is shown Fig. 6A The g-g' cross section is an example of a cross section of FIG. The g-g' cross section is an XZ cross section passing through the first plug region 83 and the second plug region 73. Figure 6C , for Figure 6B Different points are explained.

[0164] exist Figure 6C In the g-g' cross section shown, the contact region 15 and the second plug region 73 are provided in the transistor portion 70. The lower end of the second plug region 73 in the depth direction of the semiconductor substrate 10 may be positioned deeper than the lower end of the contact region 15. Thus, the extraction of holes through the second plug region 73 is improved, and the latch-up tolerance of the semiconductor device 100 can be improved.

[0165] Fig.6D It is shown Fig. 6A1 is a diagram of an example of an h-h' cross section in FIG. The h-h' cross section is a YZ cross section passing through the first interlayer insulating portion 381, the second interlayer insulating portion 382, ​​the second contact portion 254, and the dummy trench portion 30. The cathode region 82 may include a first cathode portion 181 and a second cathode portion 182. The first cathode portion 181 is a region of the first conductivity type having a higher doping concentration than the doping concentration of the drift region 18. In one example, the first cathode portion 181 is an N+ type.

[0166] The second cathode portion 182 is a region of the second conductivity type disposed adjacent to the first cathode portion 181 on the back side 23 of the semiconductor substrate 10. That is, the second cathode portion 182 can be directly in contact with the first cathode portion 181. In one example, the second cathode portion 182 is of P+ type. The first cathode portion 181 and the second cathode portion 182 can be alternately arranged in the groove extension direction (Y-axis direction). In addition, the width of the first cathode portion 181 and the second cathode portion 182 in the groove extension direction (Y-axis direction) is not limited by the structure of the front side 21 of the semiconductor substrate 10 and can be set arbitrarily.

[0167] The first cathode portion 181 may be formed by ion-implanting an N-type dopant after ion-implanting a P-type dopant through the ion implantation process for forming the second cathode portion 182. Conversely, the second cathode portion 182 may be formed by ion-implanting a P-type dopant after ion-implanting an N-type dopant through the ion implantation process for forming the first cathode portion 181.

[0168] The first cathode portion 181 and the second cathode portion 182 may be alternately arranged in any direction. The first cathode portion 181 and the second cathode portion 182 of this example are alternately arranged in the groove extension direction (e.g., Y-axis direction), but may also be alternately arranged in the groove arrangement direction (e.g., X-axis direction). The first cathode portion 181 and the second cathode portion 182 may be arranged in a stripe shape when viewed from above. One of the first cathode portion 181 and the second cathode portion 182 may also be formed in a dot shape.

[0169] The cathode region 82 in the diode portion 80 of this example may be provided with a second cathode portion 182. The cathode region 82 in the diode portion 80 of this example may be provided with a first cathode portion 181 and a second cathode portion 182 alternately. In the cathode region 82 in the diode portion 80 of this example, the first cathode portion 181 and the second cathode portion 182 may be provided in a contacting manner. Thus, the concentration of the first conductive type dopant in the cathode region 82 is reduced, and the forward voltage Vf of the diode portion 80 can be increased.

[0170] Fig. 7A 1 is a diagram showing a modified example of the upper surface of the semiconductor device 100 of this example. Fig. 7A , for Figure 2A Different points are explained.

[0171] exist Fig. 7A In the modified example shown in FIG. 1 , the second interlayer insulating portion 382 is not provided. In this example, the second interlayer insulating portion 382 is not provided in the region between two first interlayer insulating portions 381 adjacent to each other in the trench extending direction, but a second contact portion 254 is provided. Figure 2A The same effect is achieved, and the extraction of holes from the anode region 19 is increased, so that the forward voltage Vf of the diode portion can be increased.

[0172] Figure 7B 1 is a diagram showing a modified example of the upper surface of the semiconductor device 100 of this example. The semiconductor device 100 may be a semiconductor chip further including a transistor unit 70. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor unit 70 may include a boundary region at a portion adjacent to the diode unit 80. The transistor unit 70 of this example does not include a boundary region. Figure 7B , for Fig. 6A Different points are explained.

[0173] exist Figure 7B In the modified example shown in FIG. 1 , the second interlayer insulating portion 382 is not provided. In this example, the second interlayer insulating portion 382 is not provided in the region between two first interlayer insulating portions 381 adjacent to each other in the trench extending direction, but a second contact portion 254 is provided. Fig. 6A The same effect is achieved, and the extraction of holes from the anode region 19 is increased, so that the forward voltage Vf of the diode portion can be increased.

[0174] Figure 8 Graph showing the relationship between the forward voltage Vf and the reverse recovery loss Err of the diode unit 80 in the semiconductor device 500 of the comparative example and the semiconductor device 100 of the present example. Figure 8 In FIG. 1 , the forward voltage Vf of the diode unit 80 is plotted on the horizontal axis and the reverse recovery loss Err is plotted on the vertical axis. In the figure, the case indicated by the black circle corresponds to the semiconductor device 500 of the comparative example, and the case indicated by the white circle corresponds to the semiconductor device 100 of the embodiment.

[0175] In the semiconductor device 100 of this example, by providing the second contact portion 254, the hole current flowing through the front electrode 52 is larger than the hole current of the semiconductor device 500 of the comparative example. As a result, the forward voltage Vf of the semiconductor device 100 can be made higher than the forward voltage Vf of the semiconductor device 500 of the comparative example. In addition, since the forward voltage Vf is increased, the reverse recovery loss Err of the semiconductor device 100 can be made lower than the reverse recovery loss Err of the semiconductor device 500 of the comparative example.

[0176] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

[0177] It should be noted that the execution order of each process such as actions, sequences, steps and stages in the devices, systems, programs and methods shown in the claims, specifications and drawings can be implemented in any order unless it is specifically stated that "before" or "earlier than", etc., and the previous processing results are not used in the subsequent processing. Even if the action flow in the claims, specifications and drawings is described using "first" or "next" for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: have: Diode Department; A plurality of groove portions are disposed on the front surface of the semiconductor substrate; A drift region of a first conductivity type, which is disposed on the semiconductor substrate; an anode region of a second conductivity type, which is disposed above the drift region in the diode portion; A first plug region of a second conductivity type, which is disposed above the drift region in the diode portion and has a doping concentration higher than that of the anode region; A front-side electrode disposed above the semiconductor substrate; as well as an interlayer insulating film disposed above a mesa portion disposed between the plurality of groove portions, The anode region is connected to the front-side electrode at the side surfaces of the plurality of groove portions.

2. The semiconductor device according to claim 1, wherein: The semiconductor device includes a first contact portion extending above the mesa portion in a trench extending direction of the plurality of trench portions and connected to the anode region and the first plug region.

3. The semiconductor device according to claim 2, wherein: The semiconductor device includes a second contact portion extending from a side wall of one of the plurality of grooves along a groove arrangement direction of the plurality of grooves on the front surface of the semiconductor substrate to a side wall of another groove and connected to the mesa portion.

4. The semiconductor device according to claim 3, wherein: The second contact portion extends across at least one of the plurality of groove portions in the groove arrangement direction of the plurality of groove portions and is connected to the at least one groove portion.

5. The semiconductor device according to claim 4, wherein: The width of the first contact portion in the trench arrangement direction is greater than the width of the second contact portion in the trench extension direction.

6. The semiconductor device according to claim 4, wherein: The second contact portion is disposed above the anode region and the plurality of trench portions that are alternately disposed in the trench arrangement direction.

7. The semiconductor device according to claim 4, wherein: A plurality of second contact portions are disposed above the anode regions and the plurality of trench portions that are alternately disposed in the trench arrangement direction.

8. The semiconductor device according to claim 4, wherein: The interlayer insulating film includes a first interlayer insulating portion provided between the first plug region and the plurality of trench portions in the trench arrangement direction in a plan view.

9. The semiconductor device according to claim 8, wherein: The interlayer insulating film includes a second interlayer insulating portion provided between the anode region and the plurality of trench portions in the trench arrangement direction in a plan view.

10. The semiconductor device according to claim 9, wherein: A width of the first interlayer insulating portion in a direction in which the trench extends is greater than a width of the second interlayer insulating portion in the direction in which the trench extends.

11. The semiconductor device according to claim 8, wherein: The first interlayer insulating portion is sandwiched in the trench arrangement direction by a plurality of first contact portions extending along the trench extension direction. The first interlayer insulating portion is sandwiched in the trench extending direction by a plurality of second contact portions extending along the trench arrangement direction.

12. The semiconductor device according to claim 9, wherein: The second interlayer insulating portion is sandwiched by a plurality of first contact portions extending along the trench extending direction in the trench arrangement direction. The second interlayer insulating portion is sandwiched in the trench extending direction by a plurality of second contact portions extending along the trench arrangement direction.

13. The semiconductor device according to claim 4, wherein: The front-side electrode includes a barrier metal layer provided inside the first contact portion and the second contact portion.

14. The semiconductor device according to claim 1, wherein: The semiconductor device includes a transistor portion having a second conductivity type base region provided above the drift region. The doping concentration of the anode region is lower than the doping concentration of the base region.

15. The semiconductor device according to claim 14, wherein: The transistor portion includes a contact region of a second conductivity type, the contact region of the second conductivity type being provided above the drift region, The doping concentration of the first plug region is higher than the doping concentration of the contact region.

16. The semiconductor device according to claim 14, wherein: The transistor portion includes a second plug region of a second conductivity type, the second plug region is provided above the drift region, and has a doping concentration higher than that of the base region.

17. The semiconductor device according to any one of claims 1 to 16, characterized in that The doping concentration of the anode region is 4E16cm -3 Above and 1E17cm -3 the following.

18. The semiconductor device according to any one of claims 1 to 16, characterized in that The doping concentration of the first plug region is 2E19cm -3 Above and 2E20cm -3 the following.

19. The semiconductor device according to any one of claims 1 to 16, characterized in that The first plug region is disposed separately from the groove sidewalls of the plurality of groove portions in the groove arrangement direction of the plurality of groove portions, The anode region is extended from one trench sidewall of the plurality of trench portions to another trench sidewall in the trench arrangement direction. The first plug region and the anode region are alternately arranged in the mesa portion in a trench extending direction of the plurality of trench portions.

20. The semiconductor device according to any one of claims 1 to 16, characterized in that In the mesa portion, an area of ​​the anode region on the front surface of the semiconductor substrate is larger than an area of ​​the first plug region on the front surface of the semiconductor substrate.

21. The semiconductor device according to any one of claims 1 to 16, characterized in that The front-side electrode has a plug layer made of tungsten.

22. The semiconductor device according to any one of claims 1 to 16, characterized in that The diode unit includes a cathode region of the first conductivity type provided on the back surface of the semiconductor substrate. The doping concentration of the cathode region is 5E19cm -3 Above and 2E20cm -3 the following.

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