Semi-SGT MOSFET devices

Abstract

The present invention discloses a semi-SGT MOSFET device, in which first and second epitaxial layers are formed on a semiconductor substrate. The terminal structure in the terminal region includes: two or more first annular terminal trenches surrounding the active region. A terminal source conductive material layer is formed in each first annular terminal trench. The outermost unit cell trench and each first annular terminal trench both longitudinally penetrate the second epitaxial layer; a first injection region is formed in the first epitaxial layer at the bottom of the outermost unit cell trench and the bottom of each first annular terminal trench, and no first injection region is formed in the first epitaxial layer inside the outermost unit cell trench. A first width is defined between the inner side surface of the innermost first annular terminal trench and the outer side surface of the outermost first annular terminal trench. The first width ensures that the depletion region size of the terminal region meets the withstand voltage requirements of the semi-SGT MOSFET device. The present invention can expand the size of the depletion region of the terminal region, thereby increasing the breakdown voltage of the device.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit, in particular to a semi-shielded gate trench (Shield Gate Trench, SGT) MOSFET device. Background Art

[0002] Compared to conventional MOSFETs, SGT MOSFETs feature a longitudinal source field plate inserted into the drift region. The source field plate is typically composed of source polysilicon, also known as shielding polysilicon. By utilizing the source field plate and lateral depletion of the drift region, the doping concentration in the drift region can be significantly increased without reducing the breakdown voltage, thereby reducing the specific on-resistance. At the same time, because the source field plate shields the gate, its gate-to-drain capacitance (Cgd) is also significantly reduced, significantly improving the switching speed of the device.

[0003] Increasing the breakdown voltage of an SGT MOSFET requires increasing the depth of the trench containing the source field plate and the thickness of the shielding dielectric material, such as SiO2, used to isolate the source field plate from the drain region (i.e., the drift region). Because shielding dielectric materials are typically grown at high temperatures, typically 1100°C under thermal oxygen growth conditions, and because of differences in thermal expansion coefficients between different materials, deep trenches and thick isolation materials impose significant stress on the silicon wafer, which can affect photolithography alignment. In severe cases, the stress can cause the wafer to warp excessively, preventing it from entering the photolithography tool, and preventing normal tapeout.

[0004] Based on this, for high voltage SGT MOSFETs such as those with a breakdown voltage greater than 200V, semi-SGT MOSFETs are usually used.

[0005] like Figure 1 The figure shows a schematic diagram of the structure of a device unit of an existing semi-SGTMOSFET device; taking an N-type device as an example, Figure 1 The device unit of the half-SGTMOSFET device shown includes:

[0006] The heavily doped N-type semiconductor substrate 1 , such as a silicon substrate, serves as a drain region and is connected to a drain electrode formed by a back metal layer.

[0007] In order to reduce back-diffusion of the semiconductor substrate 1 , an arsenic-doped semiconductor substrate 1 is usually selected.

[0008] N-doped epitaxial layer 2, as a component of the drift region, has a low doping concentration, similar to a VDMOS. As the breakdown voltage increases, the epitaxial layer 2 will continue to be depleted and widened in the vertical direction due to the source field plate.

[0009] The N-doped epitaxial layer 3 is also a component of the drift region and is the N-type drift region of the SGT. That is, a source field plate 5, i.e., source polysilicon, is provided in the region of the epitaxial layer 3. The doping concentration of the epitaxial layer 3 is greater than the doping concentration of the epitaxial layer 2. Because the epitaxial layer 3 is laterally depleted by the source field plate 5, its doping concentration can be greatly increased.

[0010] The biggest difference between the SGT MOSFET and the conventional trench gate MOSFET is that a longitudinal source field plate 5 is inserted laterally in the drift region. Figure 1 In the embodiment, the source field plate 5 is formed in the gate trench, and a shielding dielectric layer 4 is separated between the source field plate 5 and the inner surface of the gate trench. The shielding dielectric layer 4 is usually SiO2.

[0011] A polysilicon gate 6 and a gate dielectric layer 7 are also formed in the gate trench. The gate dielectric layer 7 is usually a gate oxide layer. Figure 1 The gate structure shown is a left-right structure, where the polysilicon gate 6 is formed on the left and right sides of the top region of the source field plate 5 , and the top surface of the source field plate 5 extends to the top surface of the gate trench.

[0012] The withstand voltage of a semi-SGT MOSFET device is provided by the depletion region formed by depletion of epitaxial layer 2 in a VDMOS-like manner, and by the lateral depletion of epitaxial layer 3 by the source field plate 5, which utilizes SGT. A P-type doped channel region 8 is formed on the surface of epitaxial layer 3, and a heavily N-type doped source region 9 is formed on the surface of channel region 8.

[0013] A contact hole 10 (CT), also known as a through hole, is formed at the top of the source region 9 and is connected to the source electrode patterned by the front metal layer 11. The bottom of the contact hole 10 at the top of the source region 9 also passes through the source region 9 and contacts the channel region 8. The contact hole 10 is usually located in the middle of the terrace region (Mesa) between the gate trenches.

[0014] The top of the source field plate 5 is connected to the source.

[0015] The contact hole 10 passes through the interlayer film 12 (ILD).

[0016] When a positive voltage is applied to the gate, an inversion layer is formed on the surface of the channel region 8 and a conductive channel is formed by the inversion layer, so that current flows from the source to the drain.

[0017] In the primary cell region, ie, the active region, the epitaxial layer 3 can be well depleted, but in the terminal region, the depletion of the epitaxial layer 3 becomes extremely difficult.

[0018] like Figure 2 , which is a schematic structural diagram of another device unit of an existing semi-SGT MOSFET device; and Figure 1 The difference between the device units shown is that Figure 2 The gate structure of the device unit of the conventional half-SGT MOSFET device shown is a top-bottom structure, that is, the polysilicon gate 6 is located on top of the source field plate 5 .

[0019] like Figure 3 As shown in FIG, it is a schematic diagram of the top view structure of the existing semi-SGT MOSFET device; Figure 4 Shown is along Figure 3 Schematic diagram of the cross-sectional structure along the center line AA; the terminal structure of the existing semi-SGT MOSFET device is similar to the terminal structure of the existing SGT MOSFET, and is described as follows:

[0020] like Figure 3 As shown, the trenches in the cell region, namely the cell trenches 101, are arranged in parallel in a stripe structure. The periphery of the arrangement area of ​​the cell trenches 101 is surrounded by a ring-shaped source trench 101b. Since the terminal structure mainly plays a role in the depletion of the drift region due to the source field plate, Figure 4 In order to highlight the role of the source field plate, the gate structure of the device unit in the original cell area, including the polysilicon gate and the gate dielectric layer, is omitted.

[0021] like Figure 4 As shown, the left side of line BB is the primary cell region, namely the active region 102 a , and the right side of line BB is the terminal region 102 b .

[0022] An epitaxial layer 103 and an epitaxial layer 104 serving as a drift region are sequentially formed on a semiconductor substrate 102 serving as a drain region. The doping concentration of the epitaxial layer 103 is lower than that of the epitaxial layer 104 .

[0023] Both the unit cell trench 101 and the ring-shaped source trench 101b pass through the epitaxial layer 104. The outermost unit cell trench is individually marked with a reference numeral 101a.

[0024] A P-type doped channel region 105 is formed on the surface of the epitaxial layer 104 of the active region 102a, and an N+ doped source region (not shown) is formed on the surface of the channel region 105. The tops of the source region and the channel region 105 are connected to the source electrode formed by the front metal layer 107 through contact holes 106.

[0025] A unit cell source conductive material layer, namely a unit cell source field plate 108 a , is formed in the unit cell structure 101 , and a terminal source conductive material layer, namely a terminal source field plate 108 b , is formed in the annular source trench 101 b .

[0026] The source field plate 108 a of the primary cell and the terminal source field plate 108 b are both connected to the source. When reverse biased, the source field plate 108 a of the primary cell and the terminal source field plate 108 b will deplete the epitaxial layer 104 .

[0027] In the active region 102a, the periodic arrangement of the source field plates 108a of the unit cells enables effective depletion of the epitaxial layer 104. However, in the terminal region, the terminal source field plates 108b have difficulty depleting the epitaxial layer 104. Consequently, the depletion region of the epitaxial layer 103 at the bottom of the epitaxial layer 104 in the terminal region is reduced, with the boundary of the depletion region shown by the dotted line 109. Consequently, the depletion region in the terminal region is limited in width, resulting in a low breakdown voltage. Summary of the Invention

[0028] The technical problem to be solved by the present invention is to provide a semi-SGT MOSFET device, which can expand the size of the depletion region of the terminal region, thereby increasing the breakdown voltage of the device.

[0029] To solve the above technical problems, in the semi-SGT MOSFET device provided by the present invention, a first epitaxial layer doped with a first conductivity type is formed on a semiconductor substrate, and a second epitaxial layer doped with the first conductivity type is formed on the surface of the first epitaxial layer; the doping concentration of the first epitaxial layer is less than the doping concentration of the second epitaxial layer.

[0030] The semi-SGT MOSFET device is divided into an active region and a termination region, and the termination region surrounds the circumference of the active region.

[0031] In the active area, a channel region doped with the second conductive type is formed on the surface of the second epitaxial layer, and a source region heavily doped with the first conductive type is formed on the surface of the channel region.

[0032] An outermost unit cell groove is also included outside the channel region, an inner surface of the outermost unit cell groove contacts an outer surface of the channel region, and an outer surface of the outermost unit cell groove enters into the terminal region.

[0033] A unit cell source conductive material layer is formed in the outermost unit cell trench, and a unit cell source dielectric layer is interposed between the unit cell source conductive material layer and the inner surface of the outermost unit cell trench.

[0034] A terminal structure is provided in the terminal area, and the terminal structure includes:

[0035] Two or more first annular terminal grooves are formed around the active area and have successively increasing radii.

[0036] A terminal source conductive material layer is formed in each of the first annular terminal grooves, and a terminal source dielectric layer is spaced between the terminal source conductive material layer and the inner surface of the first annular terminal groove.

[0037] The outermost unit cell trench and each of the first ring-shaped terminal trenches both penetrate the second epitaxial layer longitudinally; a first injection region doped with a second conductive type is formed in the first epitaxial layer at the bottom of the outermost unit cell trench and the bottom of each of the first ring-shaped terminal trenches, and the first injection region is not formed in the first epitaxial layer inside the outermost unit cell trench.

[0038] The source region, the channel region, the primary cell source conductive material layer and the terminal source conductive material layer are all connected to the source electrode composed of the front metal layer through corresponding contact holes on the top.

[0039] A first width is defined between an inner side surface of the innermost first annular terminal groove and an outer side surface of the outermost first annular terminal groove.

[0040] Each of the terminal source conductive material layers is used to laterally deplete the second epitaxial layer in the terminal region and laterally widen the depletion region of the second epitaxial layer when reverse biased, and the first injection region is used to increase the longitudinal depletion of the first epitaxial layer in the terminal region and widen the depletion region of the first epitaxial layer at the bottom of the depletion region of the second epitaxial layer when reverse biased; when reverse biased, the first width ensures that the size of the depletion region of the terminal region meets the voltage withstand requirements of the half-SGTMOSFET device.

[0041] A further improvement is that the first epitaxial layer has a first thickness, and the second epitaxial layer has a second thickness.

[0042] Under reverse bias, the maximum longitudinal dimension of the depletion region of the active region is the sum of the first thickness and the second thickness, and the sum of the first thickness and the second thickness meets the withstand voltage requirement of the semi-SGT MOSFET device.

[0043] A further improvement is that the first width is greater than twice the first thickness.

[0044] A further improvement is that the first width is greater than or equal to three times the first thickness.

[0045] A further improvement is that the implantation dose of the first implantation region is 1e12 cm -2 ~6e12cm -2 , the injection energy is 40keV~120keV.

[0046] A further improvement is that, in a direction from the active area to the terminal area from the inside to the outside, the spacing between the first annular terminal grooves remains unchanged or increases sequentially.

[0047] A further improvement is that a plurality of parallel device units are formed in the active area.

[0048] Each of the device units includes a gate structure and a source field plate structure.

[0049] The gate structure is a trench gate, comprising: a gate conductive material layer formed in a cell trench and a gate dielectric layer isolated between the gate conductive material layer and the inner surface of the cell trench.

[0050] The source field plate structure includes a source conductive material layer and a source dielectric layer.

[0051] In the same device unit, the cell source conductive material layer and the gate conductive material layer are formed in the same cell trench, and the cell source conductive material layer and the inner surface of the cell trench are separated by the cell source dielectric layer; the cell source conductive material layer and the gate conductive material layer are separated by an inter-gate dielectric layer.

[0052] Alternatively, in the same device unit, the cell trench is divided into a cell gate trench and a cell source trench, the gate conductive material layer is formed in the cell gate trench, and the gate conductive material layer and the inner surface of the cell gate trench are separated by the gate dielectric layer; the cell source conductive material layer is formed in the cell source trench, and the cell source conductive material layer and the inner surface of the cell source trench are separated by the cell source dielectric layer.

[0053] A further improvement is that a plurality of parallel device units are formed in the active area.

[0054] Each of the device units includes a gate structure and a source field plate structure.

[0055] The gate structure is a planar gate, comprising: a gate dielectric layer and a gate conductive material layer formed on the surface of the gate dielectric layer; the gate dielectric layer covers the surface of the channel region and extends to the surface of the second epitaxial layer outside the channel region.

[0056] The source field plate structure includes a source cell conductive material layer and a source cell dielectric layer; the source cell conductive material layer is formed in the source cell trench, and the source cell dielectric layer is separated from the inner surface of the source cell trench by the source cell conductive material layer.

[0057] A further improvement is that the minimum spacing between the first annular terminal grooves is a first spacing, and the unit cell grooves where the unit cell source conductive material layer is located in the active area have a second spacing.

[0058] The first spacing is smaller than the second spacing.

[0059] A further improvement is that the first spacing is 50% to 90% of the second spacing.

[0060] A further improvement is that when the primitive cell source conductive material layer and the gate conductive material layer are formed in the same primitive cell trench, the gate structure is an upper and lower structure, and the gate conductive material layer is located on the top of the primitive cell source conductive material layer; or, the gate structure is a left and right structure, and the gate conductive material layer is located on the left and right sides of the top area of ​​the primitive cell source conductive material layer.

[0061] A further improvement is that the unit cell grooves and the outermost unit cell grooves are both strip-shaped and arranged in parallel.

[0062] A further improvement is that the terminal structure further includes:

[0063] One or more second annular terminal grooves surround the outermost side of the first annular terminal groove and have successively increasing surrounding radii.

[0064] A second terminal conductive material layer is formed in each of the second annular terminal grooves, and a second terminal dielectric layer is spaced between the second terminal conductive material layer and the inner surface of the second annular terminal groove.

[0065] The second terminal conductive material layer is a floating structure not connected to the electrode.

[0066] Each of the second annular terminal trenches passes through the second epitaxial layer longitudinally; and a first implantation region is also formed in the first epitaxial layer at the bottom of each of the second annular terminal trenches.

[0067] A further improvement is that, in the direction from the active area to the terminal area from the inside to the outside, the spacing between the second annular terminal grooves remains unchanged or increases successively.

[0068] A further improvement is that the terminal structure further includes:

[0069] A third annular terminal groove surrounds the outermost circumference of the second annular terminal groove.

[0070] A third terminal conductive material layer is formed in each of the third annular terminal grooves, and a third terminal dielectric layer is spaced between the third terminal conductive material layer and the inner surface of the third annular terminal groove.

[0071] The top of the third terminal conductive material layer and the top of the second epitaxial layer outside the third annular terminal groove are connected to a first connection layer composed of a front metal layer through contact holes, and the first connection layer is connected to the drain.

[0072] Each of the third annular terminal trenches passes through the second epitaxial layer longitudinally; and the first implantation region is also formed in the first epitaxial layer at the bottom of each of the third annular terminal trenches.

[0073] A further improvement is that the outermost unit cell groove, the first annular terminal groove, the second annular terminal groove and the third annular terminal groove are formed simultaneously using the same process;

[0074] The materials of the original cell source conductive material layer, the terminal source conductive material layer, the second terminal conductive material layer and the third terminal conductive material layer are all made of polysilicon and are formed simultaneously using the same process;

[0075] The original cell source dielectric layer, the terminal source dielectric layer, the second terminal dielectric layer and the third terminal dielectric layer are all formed using oxide layers and are formed simultaneously using the same process.

[0076] The present invention sets a plurality of first annular terminal grooves in the terminal structure and forms a terminal source conductive material layer in the first annular terminal groove, forms the first injection region doped with the second conductive type in the outermost unit cell groove and the first epitaxial layer at the bottom of the first annular terminal groove, and does not form the first injection region in the first epitaxial layer inside the outermost unit cell groove. The plurality of terminal source conductive material layers can realize the lateral widening of the depletion region of the second epitaxial layer with a higher doping concentration in the terminal region, and the first injection region can increase the longitudinal depletion of the first epitaxial layer at the bottom on the basis of the depletion region formed by the laterally widened second epitaxial layer, so that the terminal region The depletion region of the first epitaxial layer can also be widened laterally and vertically. Therefore, the terminal source conductive material layer formed in the first annular terminal groove and the setting of the first injection region of the present invention can realize the expansion of the depletion region of the terminal region under reverse bias. After the depletion region of the terminal region is expanded, the breakdown voltage of the device can be increased, that is, the withstand voltage of the device can be increased. The present invention also meets the withstand voltage requirements of the device by setting the first width between the inner side surface of the innermost first annular terminal groove and the outer side surface of the outermost first annular terminal groove. Therefore, the present invention can expand the size of the depletion region of the terminal region, thereby increasing the breakdown voltage of the device and making the withstand voltage of the device meet the requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0078] Figure 1 It is a structural diagram of a device unit of an existing semi-SGTMOSFET device;

[0079] Figure 2 It is a structural schematic diagram of another device unit of the existing semi-SGT MOSFET device;

[0080] Figure 3 Schematic diagram of the top view structure of an existing semi-SGT MOSFET device;

[0081] Figure 4 It is along Figure 3 Schematic diagram of the cross-section structure along the midline AA;

[0082] Figure 5 1 is a schematic top view of a semi-SGT MOSFET device according to a first embodiment of the present invention;

[0083] Figure 6 FIG1 is a schematic cross-sectional structural diagram of a semi-SGT MOSFET device according to a first embodiment of the present invention;

[0084] Figure 7 FIG2 is a schematic cross-sectional structural diagram of a semi-SGT MOSFET device according to a second embodiment of the present invention;

[0085] Figure 8 FIG. 4 is a schematic cross-sectional structural diagram of a semi-SGT MOSFET device according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0086] like Figure 5 FIG. 1 is a schematic diagram of a top view of a half-SGT MOSFET device according to a first embodiment of the present invention; FIG. Figure 6 FIG. 2 is a schematic cross-sectional view of a half-SGT MOSFET device according to a first embodiment of the present invention; Figure 6 It is along Figure 5 A cross-sectional view of the center line AA; In the first embodiment of the present invention, the half SGT MOSFET device, such as Figure 6 As shown, a first epitaxial layer 203 doped with a first conductive type is formed on a semiconductor substrate 202 , and a second epitaxial layer 204 doped with a first conductive type is formed on the surface of the first epitaxial layer 203 ; the doping concentration of the first epitaxial layer 203 is less than the doping concentration of the second epitaxial layer 204 .

[0087] The semi-SGT MOSFET device is divided into an active region 202a and a termination region 202b. The termination region 202b surrounds the active region 202a. Figure 6 In FIG. 2 , the termination region 202 b is located on the right side of line BB, and the active region 202 a is located on the left side of line BB. Figure 5 In the top view shown, line BB is located at Figure 5 The boundary between the active area 202a and the termination area 202b on the top side. Figure 5 The boundaries of the active region 202a and the terminal region 202b on each side form a circle.

[0088] In the active region 202 a , a channel region 205 doped with the second conductivity type is formed on the surface of the second epitaxial layer 204 , and a source region (not shown) heavily doped with the first conductivity type is formed on the surface of the channel region 205 .

[0089] The second epitaxial layer 204 and the first epitaxial layer 203 at the bottom of the channel region 205 both serve as drift regions. The second epitaxial layer 204 has a higher doping concentration, which is beneficial to reducing the on-resistance. The first epitaxial layer 203 serves as a voltage-resistant layer alone, so a thinner doping concentration is required.

[0090] The outermost unit cell trench 201a is also included outside the channel region 205. The inner surface of the outermost unit cell trench 201a contacts the outer surface of the channel region 205, and the outer surface of the outermost unit cell trench 201a enters the terminal region 202b. Figure 5 As shown, the outermost unit cell groove 201a belongs to the unit cell groove 201, but in order to distinguish the two, the label 201a is used separately to represent the outermost unit cell groove.

[0091] A unit cell source conductive material layer 208 a is formed in the outermost unit cell trench 201 a , and a unit cell source dielectric layer 209 a is interposed between the unit cell source conductive material layer 208 a and the inner surface of the outermost unit cell trench 201 a .

[0092] A terminal structure is provided in the terminal area 202b, and the terminal structure includes:

[0093] Two or more first annular terminal trenches 201b surround the active area 202a and have successively increasing radius. Figure 6 4 first annular terminal grooves 201b are shown in FIG. In other embodiments, the number of the first annular terminal grooves 201b can be adjusted according to the size of the subsequent first width w1.

[0094] A terminal source conductive material layer 208b is formed in each first annular terminal groove 201b, and a terminal source dielectric layer 209b is spaced between the terminal source conductive material layer 208b and the inner surface of the first annular terminal groove 201b.

[0095] The outermost unit cell trench 201a and each first ring-shaped terminal trench 201b both vertically pass through the second epitaxial layer 204; a first injection region 210 doped with the second conductive type is formed in the first epitaxial layer 203 at the bottom of the outermost unit cell trench 201a and the bottom of each first ring-shaped terminal trench 201b, and no first injection region 210 is formed in the first epitaxial layer 203 inside the outermost unit cell trench 201a.

[0096] The first implant region 210 is the trench bottom implant region. In some embodiments, the first implant region 210 is implanted into the trench bottom after trench etching is complete, while the hard mask remains. Alternatively, the first implant region 210 can be implanted after trench etching is complete, the hard mask is stripped, and then implanted. The area implanted into the mesa can serve as part of the subsequent trench.

[0097] The source region, the channel region 205 , the primary cell source conductive material layer 208 a and the terminal source conductive material layer 208 b are all connected to the source electrode composed of the front metal layer 207 through corresponding contact holes 206 at the top.

[0098] The drain region is formed by heavily doping the thinned semiconductor substrate 202 with the first conductivity type, or by heavily doping the first conductivity type with the back side of the thinned semiconductor substrate 202. A drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0099] A first width w1 is defined between an inner side surface of the innermost first annular terminal groove 201 b and an outer side surface of the outermost first annular terminal groove 201 b.

[0100] Each terminal source conductive material layer 208b is used to laterally deplete the second epitaxial layer 204 in the terminal region 202b and laterally widen the depletion region of the second epitaxial layer 204 when reverse biased. The first injection region 210 is used to increase the longitudinal depletion of the first epitaxial layer 203 in the terminal region 202b and widen the depletion region of the first epitaxial layer 203 at the bottom of the depletion region of the second epitaxial layer 204 when reverse biased. When reverse biased, the first width w1 ensures that the size of the depletion region in the terminal region 202b meets the withstand voltage requirement of a half-SGT MOSFET device.

[0101] In the first embodiment of the present invention, the first epitaxial layer 203 has a first thickness t1 , and the second epitaxial layer 204 has a second thickness.

[0102] Under reverse bias, the maximum longitudinal dimension of the depletion region of the active region 202a is the sum of the first thickness t1 and the second thickness. The sum of the first thickness t1 and the second thickness meets the withstand voltage requirement of a half-SGT MOSFET device.

[0103] In the first embodiment of the present invention, the first width w1 is greater than twice the first thickness t1. Preferably, the first width w1 is greater than or equal to three times the first thickness t1. In some examples, taking a typical 200V SGT MOSFET as an example, the first thickness t1 is generally 5 to 8 μm, and the corresponding resistivity of the first epitaxial layer 203 is between 1Ω*cm and 2Ω*cm; therefore, when the first thickness t1 is 5 μm, the first width w1 must be at least greater than 10 μm; when the first thickness t1 is 8 μm, the first width w1 must be at least greater than 16 μm. The resistivity of the second epitaxial layer 204 is generally between 0.5Ω*cm and 0.2Ω*cm; in order to improve the terminal's withstand voltage, the first width w1 can be selected to be more than three times the first thickness t1.

[0104] In the first embodiment of the present invention, the implantation dose of the first implantation region 210 is 1e12 cm -2 ~6e12cm -2 The implantation energy is 40keV to 120keV. Taking an N-type device as an example, the implanted impurities in the first implantation region 210 include boron.

[0105] In the direction from the inside to the outside of the active area 202a to the terminal area 202b, the intervals between the first annular terminal grooves 201b remain unchanged or increase sequentially. Figure 6 In the example, the spacing between the three shared first annular termination trenches 201b is defined by d1, d2, and d3, respectively, with the relationship between the spacings being: d1 ≤ d2 ≤ d3. This arrangement of d1, d2, and d3 facilitates uniform electric field distribution in the depletion region of the second epitaxial layer 204 in the termination region 202b, further promoting widening of the depletion region.

[0106] In the first embodiment of the present invention, a plurality of parallel device units are formed in the active region 202 a .

[0107] Each device cell includes a gate structure (not shown) and a source field plate structure.

[0108] The gate structure is a trench gate, comprising: a gate conductive material layer formed in the unit cell trench 201 and a gate dielectric layer isolated between the gate conductive material layer and the inner surface of the unit cell trench 201 .

[0109] The source field plate structure includes a source conductive material layer 208 a and a source dielectric layer 209 a .

[0110] In the first embodiment of the present invention, in the same device unit, the primary cell source conductive material layer 208a and the gate conductive material layer are formed in the same primary cell trench 201. A primary cell source dielectric layer 209a is separated between the primary cell source conductive material layer 208a and the inner surface of the primary cell trench 201; an inter-gate dielectric layer is separated between the primary cell source conductive material layer 208a and the gate conductive material layer. In this case, Figure 6 A gate conductive material layer, a gate dielectric layer, and an inter-gate dielectric layer are also formed in the cell trench 201 and the outermost cell trench 201a. In some embodiments, the gate structure is a top-bottom structure, and the gate conductive material layer is located on top of the cell source conductive material layer 208a. For device units with a top-bottom gate structure, please refer to Figure 2 The existing device unit structure shown is not described in detail here. In some embodiments, the gate structure is a left-right structure, and the gate conductive material layer is located on the left and right sides of the top area of ​​the original cell source conductive material layer 208a; For device units with a left-right gate structure, please refer to Figure 1 The conventional device unit structure shown is not described in detail here.

[0111] In some embodiments, in the same device unit, the primary cell trench 201 is divided into a primary cell gate trench (not shown) and a primary cell source trench. Figure 6 The unit cell trench 201 and the outermost unit cell trench 201a shown in the figure are both unit cell source trenches. A gate conductive material layer is formed in the unit cell gate trench, with a gate dielectric layer separating the gate conductive material layer and the inner surface of the unit cell gate trench. Unit cell source conductive material layer 208a is formed in the unit cell source trench, with a unit cell source dielectric layer 209a separating the unit cell source conductive material layer 208a and the inner surface of the unit cell source trench. After the unit cell gate trench and the unit cell source trench are separated, the unit cell source conductive material layer 208a can still laterally deplete the second epitaxial layer 204 between the unit cell source trenches.

[0112] In some embodiments, the gate structure can also be a planar gate, including: a gate dielectric layer and a gate conductive material layer formed on the surface of the gate dielectric layer; the gate dielectric layer covers the surface of the channel region 205 and extends to the surface of the second epitaxial layer 204 outside the channel region 205.

[0113] The source field plate structure includes a unit-cell source conductive material layer 208a and a unit-cell source dielectric layer 209a. The unit-cell source conductive material layer 208a is formed in the unit-cell trench 201, and the unit-cell source dielectric layer 209a separates the unit-cell source conductive material layer 208a from the inner surface of the unit-cell trench 201. Since the gate structure is a planar gate, there is no unit-cell gate trench in this embodiment, and the unit-cell trench 201 is entirely a unit-cell source trench.

[0114] In the first embodiment of the present invention, the minimum spacing between the first annular terminal trenches 201b is a first spacing d1, and the unit cell trenches 201 within the active region 202a where the unit cell source conductive material layer 208a is located have a second spacing. The first spacing d1 is smaller than the second spacing. In some embodiments, the first spacing d1 is 50% to 90% of the second spacing. The first spacing d1 being smaller than the second spacing facilitates enhanced depletion of the second epitaxial layer 202b in the terminal region 202b near the active region 202a under reverse bias, thereby facilitating widening of the depletion region of the second epitaxial layer 202b in the terminal region 202b. In one example, the second spacing is 1.2 μm; d1 is 0.9 μm; d2 is 1.0 μm; and d3 is 1.1 μm.

[0115] In the first embodiment of the present invention, Figure 5 As shown, the unit cell grooves 201 and the outermost unit cell grooves 201a are strip-shaped and arranged in parallel. In other embodiments, the unit cell grooves 201 and the outermost unit cell grooves 201a can also adopt other suitable shapes and arrangement structures in the prior art, such as square and two-dimensional arrangement.

[0116] In the first embodiment of the present invention, the unit cell trench 201, the outermost unit cell trench 201a and the first annular terminal trench 201b are formed simultaneously using the same trench process.

[0117] The first implantation region 210 is the trench bottom implantation region. In some embodiments, the first implantation region 210 is implanted into the trench bottom after the trench etching is complete, while the hard mask layer remains. In some embodiments, the first implantation region 210 can also be formed by performing a blanket ion implantation after the trench etching is complete and the hard mask is stripped. The impurities implanted into the mesa between the trenches can serve as part of the subsequent channel region.

[0118] The materials of the primary cell source conductive material layer 208 a and the terminal source conductive material layer 208 b are both polysilicon and are formed simultaneously using the same process.

[0119] The primary source dielectric layer 209 a and the terminal source dielectric layer 209 b are both formed of oxide layers and are formed simultaneously using the same process, for example, a thermal oxidation process or a thermal oxidation process plus a CVD deposition process.

[0120] The gate conductive material layer adopts a polysilicon gate, and the gate dielectric layer adopts a gate oxide layer.

[0121] In the first embodiment of the present invention, the half-SGT MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. Alternatively, the half-SGT MOSFET device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0122] In the first embodiment of the present invention, a plurality of first annular terminal grooves 201b are provided in the terminal structure, a terminal source conductive material layer 208b is formed in the first annular terminal groove 201b, a first injection region 210 doped with the second conductive type is formed in the outermost unit cell groove 201a and the first epitaxial layer 203 at the bottom of the first annular terminal groove 201b, and no first injection region 210 is formed in the first epitaxial layer 203 inside the outermost unit cell groove 201a. The plurality of terminal source conductive material layers 208b can realize the lateral widening of the depletion region of the second epitaxial layer 204 with a higher doping concentration in the terminal region 202b, and the first injection region 210 can increase the longitudinal depletion of the first epitaxial layer 203 at the bottom on the basis of the depletion region formed by the laterally widened second epitaxial layer 204, so that the terminal The depletion region of the first epitaxial layer 203 in region 202b can also be widened laterally and vertically. Therefore, the terminal source conductive material layer 208b formed in the first annular terminal groove 201b and the setting of the first injection region 210 in the first embodiment of the present invention can realize the expansion of the depletion region of the terminal region 202b under reverse bias. After the depletion region of the terminal region 202b is expanded, the breakdown voltage of the device can be increased, that is, the withstand voltage of the device can be increased. The first embodiment of the present invention can also meet the withstand voltage requirements of the device by setting the first width w1 between the inner side surface of the innermost first annular terminal groove 201b and the outer side surface of the outermost first annular terminal groove 201b. Therefore, the first embodiment of the present invention can expand the size of the depletion region of the terminal region 202b, thereby increasing the breakdown voltage of the device and making the withstand voltage of the device meet the requirements.

[0123] like Figure 7 FIG. 1 is a schematic cross-sectional structural diagram of a semi-SGT MOSFET device according to a second embodiment of the present invention. The difference between the semi-SGT MOSFET device according to the second embodiment of the present invention and the semi-SGT MOSFET device according to the second embodiment of the present invention is that the terminal structure of the semi-SGT MOSFET device according to the second embodiment of the present invention further includes:

[0124] One or more second annular terminal grooves 201c are formed around the outermost first annular terminal groove 201b and the surrounding radius increases successively. Figure 7FIG2 shows a second annular terminal groove 201c. In other embodiments, there may be two or more second annular terminal grooves 201c. When there are three or more second annular terminal grooves 201c, the spacing between the second annular terminal grooves 201c may include two or more spacing regions. From the active area 202a to the terminal area 202b, the spacing between the second annular terminal grooves 201c may remain constant or increase in sequence.

[0125] A second terminal conductive material layer 208c is formed in each second annular terminal groove 201c, and a second terminal dielectric layer 209c is spaced between the second terminal conductive material layer 208c and the inner surface of the second annular terminal groove 201c.

[0126] The second terminal conductive material layer 208c is a floating structure not connected to the electrode.

[0127] Each second annular terminal trench 201 c vertically passes through the second epitaxial layer 204 ; a first implantation region 210 is also formed in the first epitaxial layer 203 at the bottom of each second annular terminal trench 201 c .

[0128] In the second embodiment of the present invention, the second annular terminal trench 201c and the first annular terminal trench 201b are formed simultaneously using the same process; the second terminal conductive material layer 208c and the terminal source conductive material layer 208b are formed simultaneously using the same process; and the terminal source dielectric layer 209b and the second terminal dielectric layer 209 are formed simultaneously using the same process. The only difference between the second terminal conductive material layer 208c and the terminal source conductive material layer 208b is that the terminal source conductive material layer 208b is connected to the source electrode, while the second terminal conductive material layer 208c is not connected to any electrode.

[0129] like Figure 8 FIG. 1 is a schematic cross-sectional view of a semi-SGT MOSFET device according to a third embodiment of the present invention. The difference between the semi-SGT MOSFET device according to the third embodiment of the present invention and the semi-SGT MOSFET device according to the second embodiment of the present invention is that the terminal structure of the semi-SGT MOSFET device according to the third embodiment of the present invention further includes:

[0130] A third annular terminal groove 201d surrounds the outermost second annular terminal groove 201c.

[0131] A third terminal conductive material layer 208d is formed in each third annular terminal trench 201d, and a third terminal dielectric layer 209d is spaced between the third terminal conductive material layer 208d and the inner surface of the third annular terminal trench 201d.

[0132] The top of the third terminal conductive material layer 208d and the top of the second epitaxial layer 204 outside the third annular terminal groove are connected to the first connection layer 207a composed of the front metal layer 207 through the contact hole 206. The first connection layer 207a is connected to the drain. Figure 8 In the figure, the first connection layer 207a is composed of a portion of the patterned front metal layer 207, and is therefore marked separately with a mark 207a.

[0133] Each third ring-shaped terminal trench 201d vertically passes through the second epitaxial layer 204; a first implantation region 210 is also formed in the first epitaxial layer 203 at the bottom of each third ring-shaped terminal trench 201d.

[0134] In the third embodiment of the present invention, the third annular terminal trench 201d and the first annular terminal trench 201b are formed simultaneously using the same process; the third terminal conductive material layer 208d and the terminal source conductive material layer 208b are formed simultaneously using the same process; and the terminal source dielectric layer 209b and the third terminal dielectric layer 209d are formed simultaneously using the same process. The only difference between the third annular terminal trench 201d and the terminal source conductive material layer 208b is that the terminal source conductive material layer 208b is connected to the source electrode, while the third terminal conductive material layer 208d is ultimately connected to the drain electrode. The provision of the third terminal conductive material layer 208d connected to the drain electrode provides better isolation of the device from the outside world.

[0135] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A semi-SGT MOSFET device, characterized in that: A first epitaxial layer doped with a first conductivity type is formed on a semiconductor substrate, and a second epitaxial layer doped with the first conductivity type is formed on a surface of the first epitaxial layer; the doping concentration of the first epitaxial layer is lower than the doping concentration of the second epitaxial layer; The semi-SGT MOSFET device is divided into an active region and a terminal region, wherein the terminal region surrounds the active region; In the active area, a channel region doped with the second conductivity type is formed on the surface of the second epitaxial layer, and a source region heavily doped with the first conductivity type is formed on the surface of the channel region; An outermost unit cell groove is further included outside the channel region, wherein the inner surface of the outermost unit cell groove contacts the outer surface of the channel region, and the outer surface of the outermost unit cell groove enters the terminal region; A unit cell source conductive material layer is formed in the outermost unit cell groove, and a unit cell source dielectric layer is interposed between the unit cell source conductive material layer and the inner surface of the outermost unit cell groove; A terminal structure is provided in the terminal area, and the terminal structure includes: Two or more first annular terminal grooves surrounding the active area with successively increasing surrounding radius; A terminal source conductive material layer is formed in each of the first annular terminal grooves, and a terminal source dielectric layer is spaced between the terminal source conductive material layer and the inner surface of the first annular terminal groove; The outermost unit cell trench and each of the first annular terminal trenches both vertically penetrate the second epitaxial layer; a first implantation region doped with a second conductivity type is formed in the first epitaxial layer at the bottom of the outermost unit cell trench and the bottom of each of the first annular terminal trenches, and the first implantation region is not formed in the first epitaxial layer inside the outermost unit cell trench; The source region, the channel region, the primary cell source conductive material layer and the terminal source conductive material layer are all connected to the source electrode composed of the front metal layer through corresponding contact holes on the top; A first width is defined between an inner side surface of the innermost first annular terminal groove and an outer side surface of the outermost first annular terminal groove; Each of the terminal source conductive material layers is used to laterally deplete the second epitaxial layer in the terminal region and laterally widen the depletion region of the second epitaxial layer when reverse biased. The first injection region is used to increase the longitudinal depletion of the first epitaxial layer in the terminal region and widen the depletion region of the first epitaxial layer at the bottom of the depletion region of the second epitaxial layer when reverse biased. When reverse biased, the first width ensures that the depletion region size of the terminal region meets the withstand voltage requirement of the half-SGT MOSFET device. The first epitaxial layer has a first thickness, and the second epitaxial layer has a second thickness; When reverse biased, the maximum longitudinal dimension of the depletion region of the active region is the sum of the first thickness and the second thickness, and the sum of the first thickness and the second thickness meets the withstand voltage requirement of the semi-SGT MOSFET device; The first width is greater than twice the first thickness.

2. The semi-SGT MOSFET device according to claim 1, wherein: The first width is greater than or equal to three times the first thickness.

3. The semi-SGT MOSFET device according to claim 1, wherein: The implantation dose of the first implantation region is 1e12 cm -2 ~6e12cm -2 , the injection energy is 40keV~120keV.

4. The semi-SGT MOSFET device according to claim 1, wherein: In a direction from the inside to the outside of the active area to the terminal area, the spacing between the first annular terminal grooves remains unchanged or increases sequentially.

5. The semi-SGT MOSFET device according to claim 4, wherein: A plurality of parallel device units are formed in the active area; Each of the device units includes a gate structure and a source field plate structure; The gate structure is a trench gate, comprising: a gate conductive material layer formed in a cell trench and a gate dielectric layer isolated between the gate conductive material layer and the inner surface of the cell trench; The source field plate structure includes a source conductive material layer and a source dielectric layer; In the same device unit, the cell source conductive material layer and the gate conductive material layer are formed in the same cell trench, the cell source conductive material layer and the inner surface of the cell trench are separated by the cell source dielectric layer; and the cell source conductive material layer and the gate conductive material layer are separated by an inter-gate dielectric layer; Alternatively, in the same device unit, the cell trench is divided into a cell gate trench and a cell source trench, the gate conductive material layer is formed in the cell gate trench, and the gate conductive material layer and the inner surface of the cell gate trench are separated by the gate dielectric layer; the cell source conductive material layer is formed in the cell source trench, and the cell source conductive material layer and the inner surface of the cell source trench are separated by the cell source dielectric layer.

6. The semi-SGT MOSFET device according to claim 4, wherein: A plurality of parallel device units are formed in the active area; Each of the device units includes a gate structure and a source field plate structure; The gate structure is a planar gate, comprising: a gate dielectric layer and a gate conductive material layer formed on the surface of the gate dielectric layer; the gate dielectric layer covers the surface of the channel region and extends to the surface of the second epitaxial layer outside the channel region; The source field plate structure includes a source cell conductive material layer and a source cell dielectric layer; the source cell conductive material layer is formed in the source cell trench, and the source cell dielectric layer is separated from the inner surface of the source cell trench by the source cell conductive material layer.

7. The semi-SGT MOSFET device according to claim 5 or 6, wherein: The minimum spacing between the first annular terminal grooves is a first spacing, and the unit cell grooves where the unit cell source conductive material layer is located in the active area have a second spacing; The first spacing is smaller than the second spacing.

8. The semi-SGT MOSFET device according to claim 7, wherein: The first spacing is 50% to 90% of the second spacing.

9. The semi-SGT MOSFET device according to claim 5, wherein: When the primitive cell source conductive material layer and the gate conductive material layer are formed in the same primitive cell trench, the gate structure is an upper and lower structure, and the gate conductive material layer is located on the top of the primitive cell source conductive material layer; or, the gate structure is a left and right structure, and the gate conductive material layer is located on the left and right sides of the top area of ​​the primitive cell source conductive material layer.

10. The semi-SGT MOSFET device according to claim 5 or 6, wherein: The unit cell grooves and the outermost unit cell grooves are both strip-shaped and arranged in parallel.

11. The semi-SGT MOSFET device according to claim 1, wherein: The terminal structure further includes: One or more second annular terminal grooves surrounding the outermost side of the first annular terminal groove and having increasing surrounding radius; A second terminal conductive material layer is formed in each of the second annular terminal grooves, and a second terminal dielectric layer is spaced between the second terminal conductive material layer and the inner surface of the second annular terminal groove; The second terminal conductive material layer is a floating structure not connected to the electrode; Each of the second annular terminal trenches passes through the second epitaxial layer longitudinally; and a first implantation region is also formed in the first epitaxial layer at the bottom of each of the second annular terminal trenches.

12. The semi-SGT MOSFET device according to claim 11, wherein: In a direction from the inside to the outside of the active area to the terminal area, the spacing between the second annular terminal grooves remains unchanged or increases sequentially.

13. The semi-SGT MOSFET device according to claim 11, wherein: The terminal structure further includes: a third annular terminal groove surrounding the outermost side of the second annular terminal groove; A third terminal conductive material layer is formed in each of the third annular terminal grooves, and a third terminal dielectric layer is spaced between the third terminal conductive material layer and the inner surface of the third annular terminal groove; The top of the third terminal conductive material layer and the top of the second epitaxial layer outside the third annular terminal trench are connected to a first connection layer composed of a front metal layer through contact holes, and the first connection layer is connected to the drain; Each of the third annular terminal trenches passes through the second epitaxial layer longitudinally; and the first implantation region is also formed in the first epitaxial layer at the bottom of each of the third annular terminal trenches.

14. The semi-SGT MOSFET device according to claim 13, wherein: The outermost unit cell groove, the first annular terminal groove, the second annular terminal groove and the third annular terminal groove are formed simultaneously using the same process; The materials of the original cell source conductive material layer, the terminal source conductive material layer, the second terminal conductive material layer and the third terminal conductive material layer are all made of polysilicon and are formed simultaneously using the same process; The original cell source dielectric layer, the terminal source dielectric layer, the second terminal dielectric layer and the third terminal dielectric layer are all formed using oxide layers and are formed simultaneously using the same process.

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