Field effect transistor and method for manufacturing the same

Abstract

The present application discloses a field effect transistor and a preparation method thereof, wherein the field effect transistor comprises: a substrate, a drift layer, a silicon substrate region and a gate structure, wherein the drift layer and the substrate have the same doping type, and the drift layer has a first surface on the side facing away from the substrate; a plurality of silicon substrate regions are located on both sides of the drift layer, and the surface of the silicon substrate region on the side facing away from the substrate is located in the first surface, or located on the side of the drift layer facing away from the substrate, the silicon substrate region is in contact with a gate oxide layer, and the silicon substrate region has a second doping type; the gate structure is at least partially located on the side of the drift layer facing away from the substrate, the gate structure comprises a gate oxide layer, and the gate oxide layer is in contact with a plurality of silicon substrate regions. The interface state density between the silicon substrate region and the gate oxide layer is small, the electron mobility is high, and the resistance of electrons flowing through the channel is very small, thereby reducing the on-resistance and conduction loss of the silicon carbide MOSFET.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular, to a field effect transistor and a method for preparing the same. Background Art

[0002] Silicon carbide field effect transistors (MOSFET, Metal-Oxide-Semiconductor Field-EffectTransistor) are widely used in automobiles, power grids, photovoltaic power generation and other fields due to their high withstand voltage, high thermal conductivity, and high reliability. Due to material and process reasons, the gate oxide interface channel of silicon carbide MOSFET has more interface states, and the carrier mobility in the channel is very small. Therefore, the channel resistance of silicon carbide MOSFET is large, which is the most important component of the device's on-state resistance. How to improve electron mobility and reduce channel resistance has always been the focus of research on silicon carbide-based MOSFETs. Summary of the invention

[0003] The present application provides a field effect transistor and a method for preparing the same, so as to solve the problem of low electron mobility of silicon carbide-based field effect transistors in the related art.

[0004] According to one aspect of the present application, a field effect transistor is provided, comprising: a substrate having a first doping type; a drift layer located on one side of the substrate, the drift layer having a first surface on a side facing away from the substrate, and the drift layer having the first doping type; a gate structure at least partially located on a side of the drift layer facing away from the substrate, the gate structure comprising a gate oxide layer; a plurality of silicon substrate regions located in the drift layer, the surfaces of the silicon substrate regions facing away from the substrate being located in the first surface, or being located on a side of the drift layer facing away from the substrate, the silicon substrate regions being in contact with the gate oxide layer, and the silicon substrate regions having a second doping type.

[0005] Optionally, the field effect transistor further includes a plurality of first body regions, wherein the first body regions are located on a side of the silicon base region close to the substrate, and the first body regions have a second doping type.

[0006] Optionally, the field effect transistor further includes a body region isolation dielectric layer, and at least a portion of the body region isolation dielectric layer is located between the silicon substrate region and the first body region.

[0007] Optionally, the field effect transistor further comprises a plurality of conductive layers, wherein the conductive layers are respectively in contact with the drift layer, the silicon substrate region, the body region isolation dielectric layer and the gate oxide layer.

[0008] Optionally, the gate structure is located on a side of the drift layer away from the substrate, or a portion of the gate structure is located in the drift layer, and another portion of the gate structure is located on a side of the drift layer away from the substrate.

[0009] Optionally, the field effect transistor comprises a first doping region and a second doping region, the first doping region is located between the conductive layer and the second doping region, the first doping region has a first doping type, and the second doping region has a second doping type.

[0010] Optionally, the field effect transistor comprises a first doping region and a second doping region, the first doping region is located between the gate oxide layer and the second doping region, the first doping region has a first doping type, and the second doping region has a second doping type.

[0011] According to another aspect of the present application, a method for preparing a field effect transistor is provided, comprising: providing a substrate, the substrate having a first doping type; forming a drift layer on one side of the substrate, the drift layer having a first surface, and the drift layer having the first doping type; forming a plurality of silicon substrate regions in the drift layer, and a surface of the silicon substrate region facing away from the substrate is located in the first surface, or a plurality of silicon substrate regions are formed on a side of the drift layer facing away from the substrate, the silicon substrate regions are in contact with the gate oxide layer, and the silicon substrate regions have a second doping type; forming a gate structure at least on a side of the drift layer facing away from the substrate, the gate structure comprising a gate oxide layer, and the gate oxide layer is in contact with the plurality of silicon substrate regions.

[0012] Optionally, before the silicon base region is formed on the side of the drift layer facing away from the substrate, the preparation method also includes: forming a first body region in the preliminary drift layer, the first body region having a second doping type; forming a preliminary body region isolation dielectric layer on the first body region, etching the preliminary body region isolation dielectric layer and the preliminary drift layer to obtain a body region isolation dielectric layer and a first groove, a portion of the first groove being located in the preliminary drift layer; and forming a preliminary conductive layer in the first groove.

[0013] Optionally, the step of forming the silicon substrate region includes: forming a silicon-based preliminary region on the preliminary conductive layer; forming a first doped preliminary region and a second doped preliminary region in the silicon-based preliminary region, and etching the silicon-based preliminary region, the first doped preliminary region, the preliminary conductive layer and the preliminary drift layer to obtain the silicon substrate region.

[0014] Optionally, before the step of forming multiple silicon substrate regions on both sides of the drift layer, the preparation method also includes: forming a first preliminary body region in the preliminary drift layer, the first preliminary body region having a second doping type, and a surface of the first preliminary body region facing away from the substrate is located in the first surface; etching the first preliminary body region to obtain a second groove and a first body region, and forming a preliminary body region isolation dielectric layer in the second groove.

[0015] Optionally, the step of forming the silicon substrate region includes: forming a silicon-based preliminary region on the preliminary region isolation dielectric layer, and forming a first doping region and a second doping region in the silicon-based preliminary region to obtain the silicon substrate region.

[0016] A field effect transistor provided by the present application includes a substrate, a drift layer, a silicon substrate region and a gate structure, wherein the drift layer and the substrate have the same doping type, and the side of the drift layer facing away from the substrate has a first surface; multiple silicon substrate regions are located on both sides of the drift layer, or on the side of the drift layer facing away from the substrate, and the silicon substrate region has a second doping type; the gate structure is at least partially located on the side of the drift layer facing away from the substrate, and the gate structure includes a gate oxide layer, and the gate oxide layer is in contact with multiple silicon substrate regions. The interface state density between the silicon substrate region and the gate oxide layer is small, the electron mobility is high, and the resistance of electrons flowing through the channel is very small, thereby reducing the on-resistance and conduction loss of the silicon carbide MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 is a cross-sectional schematic diagram of a field effect transistor provided according to an embodiment of the present application;

[0019] Figure 2 is a cross-sectional schematic diagram of another field effect transistor provided according to an embodiment of the present application;

[0020] Figure 3 It is a schematic flow chart of a method for preparing a field effect transistor provided in an embodiment of the present application;

[0021] Figure 4 It is a cross-sectional schematic diagram of a base body after providing a substrate in a method for preparing a field effect transistor provided in an embodiment of the present application;

[0022] Figure 5 is Figure 4 A schematic cross-sectional view of a substrate after a preliminary drift layer is formed on the substrate provided in the embodiment;

[0023] Figure 6 is Figure 8 A schematic cross-sectional view of a substrate after forming a first body region in a preliminary drift layer formed in the process and forming a preliminary body region isolation dielectric layer on the preliminary drift layer;

[0024] Figure 7 is Figure 6 A schematic cross-sectional view of the substrate after a preliminary body region isolation dielectric layer is formed in the preliminary body region and a preliminary conductive layer is formed in the preliminary drift layer;

[0025] Figure 8 is Figure 7 A schematic cross-sectional view of the substrate after a preliminary silicon substrate region is formed on the preliminary conductive layer formed in the process;

[0026] Fig. 9 is Figure 8 A schematic cross-sectional view of the substrate after a first doping preparation region and a second doping preparation region are formed in the prepared silicon substrate region formed in the process;

[0027] Fig.10 Yes Fig. 9 The first doped preparation area and the preparation drift layer formed in the substrate are etched to obtain a cross-sectional schematic diagram of the substrate after the second groove is obtained;

[0028] Fig.11 Yes Fig.10 A schematic cross-sectional view of the substrate after a gate structure and an insulating layer are formed in the second groove formed in the substrate;

[0029] Fig.12 is Figure 5 A schematic cross-sectional view of a substrate after a first preliminary body region is formed in a preliminary drift layer formed in the substrate;

[0030] Fig.13 is Fig.12 A schematic cross-sectional view of the substrate after the first preliminary body region formed in the process is etched to form a first body region;

[0031] Fig.14 is Fig.13 A schematic cross-sectional view of the substrate after a preliminary body region isolation dielectric layer is formed on the first body region formed in the process;

[0032] Fig.15 is Fig.14 A schematic cross-sectional view of a substrate after a silicon-based preliminary body region is formed on a preliminary body region isolation dielectric layer;

[0033] Fig.16 is Fig.15 A schematic cross-sectional view of a substrate after a first doping region and a second doping region are formed in a silicon-based preparatory region;

[0034] Fig.17 is Fig.16A schematic cross-sectional view of the substrate after a fourth groove is formed in the isolation dielectric layer in the middle preparation region;

[0035] Fig.18 is Fig.17 A schematic cross-sectional view of the substrate after a conductive layer is formed in a fourth groove;

[0036] Fig.19 is Fig.18 A schematic cross-sectional view of the substrate after a gate structure and an insulating layer are formed on the substrate formed in FIG.

[0037] The above drawings include the following reference numerals:

[0038] 10. substrate; 20. drift layer; 201. preliminary drift layer; 30. silicon base region; 301. silicon base preliminary region; 40. gate structure; 41. gate oxide layer; 42. gate; 50. first body region; 501. first preliminary region; 60. body region isolation dielectric layer; 601. preliminary body region isolation dielectric layer; 70. conductive layer; 701. preliminary conductive layer; 80. first doped region; 801. first doped preliminary region; 90. second doped region; 110. insulating layer; 120. source; 130. drain. DETAILED DESCRIPTION

[0039] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0040] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0041] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0042] As mentioned in the background technology, in the prior art, there are many gate-oxide interface channel interface states in silicon carbide MOSFETs, and the carrier mobility in the channel is very small. Therefore, the channel resistance of silicon carbide MOSFETs is large, which is the most important component of the device on-resistance, and it is difficult to improve the electron mobility. To this end, the present application proposes a field effect transistor and a method for preparing the same.

[0043] In order to solve the above technical problem, according to an embodiment of the present application, a field effect transistor is provided. Figure 1 and Figure 2 is a cross-sectional schematic diagram of a field effect transistor according to an embodiment of the present application. Figure 1 and Figure 2 As shown, the field effect transistor includes: a substrate 10 having a first doping type; a drift layer 20 located on one side of the substrate 10, the side of the drift layer 20 facing away from the substrate 10 having a first surface, and the drift layer 20 having the first doping type; a gate structure 40, at least partially located on the side of the drift layer 20 facing away from the substrate 10, the gate structure 40 including a gate oxide layer 41; a plurality of silicon substrate regions 30 located in the drift layer 20, the surface of the silicon substrate region 30 facing away from the substrate 10 being located in the first surface, or being located on the side of the drift layer 20 facing away from the substrate 10, the silicon substrate region 30 being in contact with the gate oxide layer 41, and the silicon substrate region 30 having a second doping type.

[0044] By setting a silicon substrate region in the drift layer of the above-mentioned field effect transistor or on one side of the drift layer, the silicon substrate region replaces the silicon carbide substrate region in the silicon carbide MOSFET and contacts the gate oxide layer. The interface state density between the silicon substrate region and the gate oxide layer is small, the electron mobility is high, and the resistance of electrons flowing through the channel is very small, thereby reducing the on-resistance and conduction loss of the silicon carbide MOSFET.

[0045] In the above embodiment, if Figure 1 and Figure 2As shown, the doping type of the substrate 10 and the drift layer 20 is the same, and the doping concentration of the drift layer 20 is lower than the doping concentration of the substrate 10. The doping concentration of the drift layer 20 is two orders of magnitude lower than the doping concentration of the substrate 10. The silicon substrate region 30 is of the second doping type, such as the drift layer 20 is of N type and the silicon substrate region 30 is of P type. The thickness of the silicon substrate region 30 is 0.5 μm to 1 μm. The thickness of the gate oxide layer 41 is 0.04 μm to 0.12 μm, such as 0.06 μm, 0.1 μm and 0.11 μm; the gate structure 40 also includes a gate 42, and the thickness of the gate 42 is 0.5 μm to 0.9 μm, such as 0.6 μm, 0.7 μm and 0.8 μm. The material of the gate oxide layer 41 can be any one or more of silicon oxide and silicon nitride, and can also be other insulating dielectric materials. The material of the gate 42 can be polysilicon, which is not specifically limited in this application. The drift layer 20 and the silicon substrate region 30 are both prepared by epitaxial growth process.

[0046] The internal structure of the transistor in the present application may be a symmetrical structure, and the internal structure of the device may also be an asymmetrical structure, such as a half-enclosed structure.

[0047] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the field effect transistor further includes a plurality of first body regions 50, the first body regions 50 are located on a side of the silicon base region 30 close to the substrate 10, and the first body regions 50 have a second doping type. The specific doping concentration and thickness of the first body regions 50 can be reasonably defined by those skilled in the art according to the use scenario and conditions of the transistor.

[0048] In the above optional implementation, if Figure 1 and Figure 2 As shown, the first body region 50 is a silicon carbide substrate region in the silicon carbide MOSFET, having a second doping type, which is the same as the doping type of the silicon substrate region 30, and a thickness of the first body region 50 is 0.4 μm to 0.6 μm. When the MOSFET is in a blocking state, the drift layer 20 and the first body region 50 will deplete each other to form a reverse withstand voltage PN junction, thereby bearing the blocking voltage.

[0049] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the field effect transistor further includes a body region isolation dielectric layer 60 , and at least a portion of the body region isolation dielectric layer 60 is located between the silicon substrate region 30 and the first body region 50 .

[0050] In the above optional implementation, if Figure 1 and Figure 2As shown, the body region isolation dielectric layer 60 isolates the silicon substrate region 30 and the first body region 50. The carrier mobility between the silicon substrate region 30 and the gate oxide layer 41 is high, and a heterojunction structure can be formed between the silicon substrate region 30 and the first body region 50. If current flows between the two, lattice mismatch is likely to occur, affecting the overall current flow of the device. The present application uses the body region isolation dielectric layer 60 to block the silicon substrate region 30 and the first body region 50 to avoid the above problems. The thickness of the body region isolation dielectric layer 60 can be 0.4μm~0.6μm, and the material of the body region isolation dielectric layer 60 can be silicon oxide. The projections of the body region isolation dielectric layer 60 and the first body region 50 on the substrate 10 may not completely overlap, that is, from Figure 1 and Figure 2 In the embodiment, the width of the body region isolation dielectric layer 60 can be consistent with that of the first body region 50, or the body region isolation dielectric layer 60 can be greater than that of the first body region 50. The width relationship between the body region isolation dielectric layer 60 and the first body region 50 is not limited to Figure 1 and Figure 2 The above are illustrated in the figure, and can be reasonably limited by those skilled in the art.

[0051] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the field effect transistor further includes a plurality of conductive layers 70 , and the conductive layers 70 are in contact with the drift layer 20 , the silicon substrate region 30 , the body region isolation dielectric layer 60 and the gate oxide layer 41 , respectively.

[0052] In the above optional implementation, if Figure 1 and Figure 2 As shown, the conductive layer 70 can be composed of any one or more of titanium, copper, aluminum and silver. The conductive layer 70 avoids the low mobility effect of the heterojunction between the silicon substrate region 30 and the first body region 50, and can reduce the on-resistance and conduction loss of the silicon carbide MOSFET. The thickness of the conductive layer 70 is 0.12μm~0.16μm, and the width is 0.4μm~0.6μm. The existence of the conductive layer 70 connection structure avoids the effect of the low mobility of the heterojunction between the first body region 50 and the silicon substrate region 30 on the device.

[0053] In some optional embodiments, such as Figure 1 and Figure 2 As shown, the gate structure 40 is located on the side of the drift layer 20 away from the substrate 10 , or a portion of the gate structure 40 is located in the drift layer 20 , and another portion of the gate structure 40 is located on the side of the drift layer 20 away from the substrate 10 .

[0054] In the above optional implementation, if Figure 1As shown, when the MOSFET is a planar type, the gate structure 40 is located on the drift layer. Figure 2 As shown, when the MOSFET is a trench type, the gate structure 40 is partially located in the drift layer 20 and partially protrudes from the drift layer 20 .

[0055] In the above optional implementation, if Figure 1 and Figure 2 As shown, the field effect transistor further includes an insulating layer 110 and a source 120 on the side of the gate structure 40 away from the substrate 10 , and further includes a drain 130 on the side of the substrate 10 away from the drift layer 20 . The insulating layer 110 may be made of silicon oxide or silicon nitride.

[0056] In some optional embodiments, such as Figure 1 As shown, the field effect transistor includes a first doping region 80 and a second doping region 90. The first doping region 80 is located between the conductive layer 70 and the second doping region 90. The first doping region 80 has a first doping type, and the second doping region 90 has a second doping type.

[0057] In the above optional implementation, if Figure 1 As shown, in the case of a planar MOSFET, the first doping region 80 is between the conductive layer 70 and the second doping region 90, and there is also a portion of the silicon substrate region 30 between the first doping region 80 and the conductive layer 70, and the portion of the silicon substrate region 30 is in contact with the gate oxide layer 41. Since the resistivity of the conductive layer 70 is small and the electron mobility between the silicon substrate region 30 and the gate oxide layer 41 is high, the mobility of the carriers is improved. The doping type of the first doping region 80 is opposite to that of the second doping region 90, for example, the first doping region 80 is N-type and the second doping region 90 is P-type. The second doping region 90 is in ohmic contact with the source.

[0058] In some optional embodiments, such as Figure 2 As shown, the field effect transistor includes a first doping region 80 and a second doping region 90 . The first doping region 80 is located between the gate oxide layer 41 and the second doping region 90 . The first doping region 80 has a first doping type, and the second doping region 90 has a second doping type.

[0059] In the above optional implementation, if Figure 2 As shown, in the case where the MOSFET is a trench type, the first doping region 80 is between the gate oxide layer 41 and the second doping region 90 .

[0060] The field effect transistor may be composed of an array of one or more field effect transistors. The silicon substrate region in the field effect transistor in contact with the gate oxide layer may form a channel with high mobility, thereby reducing the channel resistance, and reducing the overall on-resistance and conduction loss of the MOSFET.

[0061] According to another aspect of the present application, a method for preparing a field effect transistor is provided, such as Figure 3 As shown, including:

[0062] Step S100: providing a substrate, wherein the substrate has a first doping type;

[0063] Step S200: forming a drift layer on one side of the substrate, wherein the drift layer has a first surface and has the first doping type;

[0064] Step S300: forming a plurality of silicon substrate regions in the drift layer, wherein the surface of the silicon substrate region facing away from the substrate is located in the first surface, or forming a plurality of silicon substrate regions on the side of the drift layer facing away from the substrate, wherein the silicon substrate regions are in contact with the gate oxide layer, and the silicon substrate regions have a second doping type;

[0065] Step S400: forming a gate structure on a side of the drift layer away from the substrate, or in the drift layer, wherein the gate structure comprises a gate oxide layer, and the gate oxide layer is in contact with the plurality of silicon substrate regions.

[0066] The field effect transistor prepared by the preparation method comprises a substrate, a drift layer, a silicon substrate region and a gate structure. A silicon substrate region is arranged on the side of the drift layer away from the substrate, or in the drift layer, so that the silicon substrate region replaces the silicon carbide substrate region in the silicon carbide MOSFET and contacts the gate oxide layer. The interface state density between the silicon substrate region and the gate oxide layer is small, the electron mobility is high, and the resistance of electrons flowing through the channel is very small, thereby reducing the on-resistance and conduction loss of the silicon carbide MOSFET.

[0067] The exemplary embodiments of the method for preparing a field effect transistor provided according to the present invention will be described in more detail below in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should not be construed as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0068] According to an embodiment of the present application, the method for preparing a trench field effect transistor of the present application may include the following steps:

[0069] First, if Figure 4As shown, step S100 is performed: providing a substrate 10, wherein the substrate has a first doping type.

[0070] Specifically, a substrate 10 having a first doping type is provided, wherein the substrate 10 may be silicon carbide.

[0071] After the step of providing a substrate, as Figures 5 to 10 As shown, step S200 is performed: a drift layer 20 is formed on one side of the substrate 10 , wherein the drift layer 20 has a first surface and has the first doping type.

[0072] Specifically, Figure 5 As shown, a preliminary drift layer 201 is formed on one side surface of the substrate 10 . The preliminary drift layer 201 has the same doping type as the substrate 10 , and the doping concentration of the preliminary drift layer 201 is two orders of magnitude lower than the doping concentration of the substrate 10 .

[0073] In some optional embodiments, such as Figure 6 and Figure 7 As shown, the preparation method also includes: forming a first body region 50 in the preliminary drift layer 201, the first body region 50 having a second doping type; forming a preliminary body region isolation dielectric layer 601 on the first body region 50, etching the preliminary body region isolation dielectric layer 601 and the preliminary drift layer 201 to obtain the body region isolation dielectric layer 60 and a first groove, a portion of the first groove being located in the preliminary drift layer 201; and forming a preliminary conductive layer 701 in the first groove.

[0074] In the above optional implementation, if Figure 6 As shown, a first body region 50 is formed in the preliminary drift layer 201 by an ion implantation process. The doping type of the first body region 50 is opposite to that of the preliminary drift layer 201. The first body region 50 may be of P type. The thickness of the first body region 50 is 0.4 μm to 0.6 μm (the thickness may be reasonably limited according to the application of the device, but is not limited thereto). A preliminary body region isolation dielectric layer 601 is formed on the first body region 50. The thickness of the preliminary body region isolation dielectric layer 601 may be 0.4 μm to 0.6 μm. The material of the preliminary body region isolation dielectric layer 601 may be silicon oxide, or other insulating dielectric materials, such as Figure 7 As shown, the prepared body region isolation dielectric layer and the prepared drift layer 201 are etched to form the body region isolation dielectric layer 60 and a first groove is formed in the prepared drift layer 201, and a conductive material is deposited in the first groove to form a prepared conductive layer 701. The prepared conductive layer 701 has a thickness of 0.12 μm to 0.16 μm and a width of 0.4 μm to 0.6 μm.

[0075] like Figures 8 to 10As shown, step S300 is performed: a plurality of silicon substrate regions 30 are formed on a side of the drift layer 20 away from the substrate 10 , wherein the silicon substrate regions 30 are in contact with the gate oxide layer 41 , and have a second doping type.

[0076] Specifically, the interface state between the silicon substrate region 30 and the gate oxide layer 41 is smaller than the interface state between the first body region 50 and the gate oxide layer 41. The field effect transistor uses the silicon substrate region 30 to contact the gate oxide layer 41 to form a high mobility channel, thereby reducing the channel resistance and reducing the overall on-resistance of the MOSFET.

[0077] In some optional embodiments, such as Figure 8 and Fig.10 As shown, the steps of forming the above-mentioned silicon substrate area 30 include: forming a silicon-based preliminary area 301 on the above-mentioned preliminary conductive layer 701; forming a first doped preliminary area 801 and a second doped area 90 in the above-mentioned silicon-based preliminary area 301, and etching the above-mentioned silicon-based preliminary area 301, the above-mentioned first doped preliminary area 801, the preliminary conductive layer 701 and the above-mentioned preliminary drift layer 201 to obtain the above-mentioned silicon substrate area 30.

[0078] In the above optional implementation, if Figure 8 As shown, a silicon-based preliminary body region 301 is formed on the preliminary conductive layer 701 and the body region isolation dielectric layer 60, as shown in FIG. Fig. 9 As shown, an ion implantation process is used to form a first doping preparation region 801 and a second doping region 90 in the silicon-based preparation region 301. The first doping preparation region 801 is located between the two second doping regions 90. Fig.10 As shown, the silicon-based preliminary region, the first doped preliminary region, the preliminary conductive layer and the preliminary drift layer are etched to form a third groove in the silicon-based preliminary region, the first doped preliminary region, the preliminary conductive layer and the preliminary drift layer to form a drift layer 20, a first doped region 80, a conductive layer 70 and a silicon-based region 30.

[0079] After the step of forming a plurality of silicon substrate regions, as Fig.11 As shown, step S400 is performed: a gate structure 40 is formed at least on one side of the drift layer 20 away from the substrate 10 , wherein the gate structure 40 includes a gate oxide layer 41 , and the gate oxide layer 41 is in contact with the plurality of silicon base regions 30 .

[0080] Specifically, a gate oxide layer 41 is formed in the third groove, and the thickness of the gate oxide layer 41 is 0.04 μm to 0.12 μm, such as 0.06 μm, 0.1 μm and 0.11 μm; the gate structure 40 also includes a gate 42, and the gate 42 is formed on the side of the gate oxide layer 41 away from the drift layer 20, a part of the gate 42 is located in the second groove, and another part of the gate 42 is located on the side of the third groove away from the drift layer 20. The material of the gate oxide layer 41 can be silicon oxide, and can also be other insulating dielectric materials, and the material of the gate 42 can be polysilicon.

[0081] In the above optional implementation, if Fig.11 and Figure 2 As shown, the manufacturing method further includes: forming an insulating layer 110 and a source 120 on the gate 42 , and forming a drain 130 on a side of the substrate 10 away from the drift layer 20 .

[0082] According to an embodiment of the present application, a method for preparing a planar field effect transistor may include the following steps:

[0083] First, if Figure 4 As shown, step S100 is performed: providing a substrate 10, wherein the substrate has a first doping type.

[0084] Specifically, a substrate 10 having a first doping type is provided, which may be an N-type.

[0085] After the step of providing a substrate, as Figure 5 and Figures 12 to 15 As shown, step S200 is performed: a drift layer 20 is formed on one side of the substrate 10 , wherein the drift layer 20 has a first surface and has the first doping type.

[0086] Specifically, Figure 5 As shown, a preliminary drift layer 201 is formed on one side surface of the substrate 10 . The preliminary drift layer 201 has the same doping type as the substrate 10 , and the doping concentration of the preliminary drift layer 201 is two orders of magnitude lower than the doping concentration of the substrate 10 .

[0087] In some optional embodiments, such as Figure 12 to Figure 14 As shown, the preparation method also includes: forming a first preliminary body region 501 in the preliminary drift layer, the first preliminary body region 501 having a second doping type, and a surface of the first preliminary body region 501 facing away from the substrate 10 is located in the first surface; etching the first preliminary body region to obtain a second groove and the first body region 50, and forming a preliminary body region isolation dielectric layer 601 in the second groove.

[0088] In the above optional implementation, if Fig.12As shown, a first preliminary body region 501 is formed in the preliminary drift layer, and the preliminary drift layer having the first preliminary body region 501 forms the drift layer 20, and the first preliminary body region 501 has the second doping type. Fig.13 As shown, the first preparation region is etched to form a first body region 50 in the first preparation region, and a second groove is formed in the first body region 50, as shown in FIG. Fig.14 As shown, a preliminary body region isolation dielectric layer 601 is formed on the first body region 50 .

[0089] like Figure 15 to Figure 16 As shown, step S300 is performed: a plurality of silicon substrate regions 30 are formed on both sides of the drift layer 20, and the surface of the silicon substrate region 30 facing away from the substrate 10 is located in the first surface, the silicon substrate region 30 is in contact with the gate oxide layer, and the silicon substrate region 30 has a second doping type.

[0090] In some optional embodiments, such as Figure 15 to Figure 16 As shown, the step of forming the silicon substrate region 30 includes: forming a silicon-based preliminary region 301 on the preliminary region isolation dielectric layer 601 , and forming a first doping region 80 and a second doping region 90 in the silicon-based preliminary region 301 to obtain the silicon substrate region 30 .

[0091] In the above optional implementation, if Fig.15 As shown, a silicon-based preliminary region 301 is formed on the preliminary region isolation dielectric layer 601. Fig.16 As shown, the first doping region 80 and the second doping region 90 are formed in the silicon-based preparation region by using an ion implantation process, and the silicon-based region 30 is formed at the same time.

[0092] In the above optional implementation manner, after forming the silicon substrate region, the preparation method further comprises: Fig.17 As shown, a fourth groove is formed in the prepared body region isolation dielectric layer by etching to obtain a body region isolation dielectric layer 60, as shown in FIG. Fig.18 As shown, a conductive layer 70 is formed in the fourth groove. Fig.19 As shown, a gate structure 40 and an insulating layer 110 are formed on the drift layer 20, and the gate structure 40 includes a gate oxide layer 41 and a gate 42. Figure 1 As shown, a source 120 is formed on the insulating layer 110 , and a drain 130 is formed on a side of the substrate 10 away from the drift layer 20 .

[0093] In the above optional implementation, the thickness of the first body region is 0.4μm~0.6μm, and the thickness and doping concentration of the first body region can be reasonably selected by those skilled in the art according to parameters such as breakdown voltage, but are not limited thereto. The thickness of the body region isolation dielectric layer can be 0.4μm~0.6μm, and the material of the body region isolation dielectric layer can be a dielectric layer, and the specific material can be silicon oxide and silicon nitride. The thickness of the conductive layer is 0.12μm~0.16μm. The thickness of the gate oxide layer in the gate structure is 0.04μm~0.12μm, such as 0.06μm, 0.1μm and 0.11μm; the gate structure also includes a gate, and the thickness of the gate is 0.5μm~0.9μm, such as 0.6μm, 0.7μm and 0.8μm. The material of the gate oxide layer can be any one or more of silicon oxide and silicon nitride, and the material of the gate can be polysilicon.

[0094] Example 1

[0095] The present application proposes a planar field effect transistor, such as Figure 1 As shown, it includes: a substrate 10, a drift layer 20, a gate structure 40, a silicon base region 30, a first body region 50, a body region isolation dielectric layer 60, a conductive layer 70, a first doped region 80, a second doped region 90, an insulating layer 110, a source 120 and a drain 130.

[0096] Wherein: the substrate 10 is N-type; the drift layer 20 is N-type and is located on one side of the substrate 10; the P-type silicon substrate region 30 is located on both sides of the drift layer 20, and the surface of the silicon substrate region 30 facing away from the substrate 10 is located in the first surface; the P-type silicon carbide-based first body region 50 is located on the side of the silicon substrate region 30 close to the substrate 10; a part of the body region isolation dielectric layer 60 is located between the silicon substrate region 30 and the first body region 50, and another part of the body region isolation dielectric layer 60 is located between the silicon substrate region 30 and the drift layer 20, and the body region isolation dielectric layer 60 is made of silicon oxide; the gate structure 40 includes a gate oxide layer 41 and a gate 42, and the gate oxide layer 41 is located on the side of the drift layer 20 facing away from the substrate 10 The gate 42 is located on the side of the gate oxide layer 41 away from the drift layer 20, the insulating layer 110 wraps the exposed part of the gate structure 40, the material of the gate oxide layer 41 is silicon oxide, the material of the gate 42 is polysilicon, and the material of the insulating layer 110 is silicon nitride; the conductive layer 70 is in contact with the above-mentioned drift layer 20, the above-mentioned silicon substrate region 30, the above-mentioned body region isolation dielectric layer 60 and the above-mentioned gate oxide layer 41, and the material of the conductive layer 70 is titanium; the P-type second doping region 90 is located in the silicon substrate region 30, and the N-type first doping region 80 is located between the above-mentioned conductive layer 70 and the above-mentioned second doping region 90; the source 120 is located on the side of the insulating layer 110 away from the substrate 10, and covers the first doping region 80 and the second doping region 90; the drain 130 is located on the side of the substrate 10 away from the drift layer 20, and the source 120 and the drain 130 are made of silver.

[0097] The present application proposes a method for preparing a planar field effect transistor, comprising:

[0098] like Figure 4 As shown, an N-type doped silicon carbide substrate 10 is provided, such as Figure 5 As shown, a preliminary drift layer 201 of N-type doped silicon carbide is formed on a silicon carbide substrate 10, as shown in FIG. Fig.12 As shown, an ion implantation process is performed in the preliminary drift layer 201 to form a first preliminary region 501 of P-type doped silicon carbide, as shown in FIG. Fig.13 As shown, the first preparation body region is etched to form a second groove, and the first preparation body region having the second groove is the first body region 50. Fig.14 As shown, a preliminary body region isolation dielectric layer 601 is formed in the second groove (on the first body region 50 and on both sides of the drift layer 20), and the material of the preliminary body region isolation dielectric layer 601 is silicon oxide, such as Fig.15 As shown, a P-type silicon-based preliminary region 301 is formed on the preliminary region isolation dielectric layer 601, as shown in FIG. Fig.16 As shown, an N-type first doping region 80 and a P-type second doping region 90 are formed in the silicon-based preparation region by an ion implantation process, and a silicon-based region 30 is obtained at the same time. Fig.17 As shown, a fourth groove is formed in the prepared body region isolation dielectric layer by etching to obtain a body region isolation dielectric layer 60, as shown in FIG. Fig.18 As shown, a conductive layer 70 is formed in the fourth groove, and the conductive layer 70 is made of titanium. Fig.19 As shown, a gate structure 40 and an insulating layer 110 are formed on the drift layer 20. The gate structure 40 includes a gate oxide layer 41 and a gate 42. The material of the gate oxide layer 41 is silicon oxide, the material of the gate 42 is polysilicon, and the material of the insulating layer 110 is silicon nitride. Figure 1 As shown, a source electrode 120 is formed on the insulating layer 110 , and a drain electrode 130 is formed on a side of the substrate 10 away from the drift layer 20 . The material of the source electrode 120 and the drain electrode 130 is silver.

[0099] Example 2

[0100] The present application proposes a trench field effect transistor, such as Figure 2 As shown, it includes: a substrate 10, a drift layer 20, a gate structure 40, a silicon base region 30, a first body region 50, a body region isolation dielectric layer 60, a conductive layer 70, a first doped region 80, a second doped region 90, an insulating layer 110, a source 120 and a drain 130.

[0101] Wherein: the substrate 10 is N-type; the drift layer 20 is N-type and is located on one side of the substrate 10; the P-type silicon substrate region 30 is located on the side of the drift layer 20 away from the substrate 10; the P-type silicon carbide-based first body region 50 is located on the side of the silicon substrate region 30 close to the substrate 10; at least part of the body region isolation dielectric layer 60 is located between the silicon substrate region 30 and the first body region 50, and the body region isolation dielectric layer 60 is made of silicon oxide; the gate structure 40 includes a gate oxide layer 41 and a gate 42, and there are grooves in the drift layer 20, the conductive layer 70, the silicon substrate region 30 and the first doped region 80, the gate oxide layer 41 covers the inner wall of the groove, the gate 42 covers the gate oxide layer 41, and the gate oxide layer The material of the gate electrode 41 is silicon oxide, the material of the gate electrode 42 is polysilicon, and the material of the insulating layer 110 is silicon nitride; the conductive layer 70 is in contact with the drift layer 20, the silicon substrate region 30, the body region isolation dielectric layer 60 and the gate oxide layer 41 respectively, and the material of the conductive layer 70 is titanium; the P-type second doping region 90 is located on the side of the silicon substrate region 30 away from the drift layer 20, and the N-type first doping region 80 is located between the gate oxide layer 41 and the second doping region 90; the insulating layer 110 covers the gate structure 40 and part of the first doping region 80; the source 120 is located on the side of the insulating layer 110 away from the substrate 10, and covers the first doping region 80 and the second doping region 90; the drain 130 is located on the side of the substrate 10 away from the drift layer 20, and the materials of the source 120 and the drain 130 are silver.

[0102] A method for preparing a trench field effect transistor proposed in the present application comprises:

[0103] like Figure 4 As shown, an N-type doped silicon carbide substrate 10 is provided, such as Figure 5 As shown, a preliminary drift layer 201 of N-type doped silicon carbide is formed on the silicon carbide substrate 10, as shown in FIG. Figure 6 As shown, a P-type silicon carbide-based first body region 50 is formed in the preliminary drift layer 201 by an ion implantation process, and a preliminary body region isolation dielectric layer 601 is formed on the first body region 50. The material of the preliminary body region isolation dielectric layer 601 is silicon oxide. Figure 7 As shown, the above-mentioned prepared body region isolation dielectric layer and the above-mentioned prepared drift layer 201 are etched to obtain the body region isolation dielectric layer 60 and the first groove (not shown in the figure), and a prepared conductive layer 701 is formed in the above-mentioned first groove. The material of the prepared conductive layer 701 is titanium. Figure 8 As shown, a P-type silicon-based preliminary body region 301 is formed on the preliminary conductive layer 701 and the body region isolation dielectric layer 60, as shown in FIG. Fig. 9 As shown, an ion implantation process is used to form a first doping preparation region 801 and a second doping region 90 in the silicon-based preparation region 301. The first doping preparation region 801 is located between the two second doping regions 90. The first doping preparation region 801 is N-type, and the second doping region 90 is P-type. Fig.10 As shown, the silicon-based preliminary region, the first doped preliminary region, the preliminary conductive layer and the preliminary drift layer are etched to form grooves in the silicon-based preliminary region, the first doped preliminary region, the preliminary conductive layer and the preliminary drift layer, thereby forming the drift layer 20, the first doped region 80, the conductive layer 70 and the silicon-based region 30. Fig.11 As shown, a gate oxide layer 41 and a gate 42 are formed in the groove, the gate oxide layer 41 and the gate 42 form a gate structure 40, and an insulating layer 110 is formed on the gate structure 40. The material of the gate oxide layer 41 is silicon oxide, the material of the gate 42 is polysilicon, and the material of the insulating layer 110 is silicon oxide. Figure 2 As shown, a source 120 is formed on the side of the insulating layer 110, the first doping region 80 and the second doping region 90 away from the drift layer 20, and a drain 130 is formed on the side of the substrate 10 away from the drift layer 20. The source 120 and the drain 130 are composed of metal layers of titanium, nickel and silver.

[0104] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0105] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0106] An embodiment of the present application provides a field effect transistor in which a silicon substrate region is arranged in a drift layer or on one side of the drift layer, so that the silicon substrate region replaces the silicon carbide substrate region in the silicon carbide MOSFET in contact with the gate oxide layer. The interface state density between the silicon substrate region and the gate oxide layer is small, the electron mobility is high, and the resistance of electrons flowing through the channel is very small, thereby reducing the on-resistance and conduction loss of the silicon carbide MOSFET.

[0107] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A field effect transistor, characterized in that: include: a substrate having a first doping type; A drift layer is located on one side of the substrate, wherein a side of the drift layer facing away from the substrate has a first surface, and the drift layer has the first doping type; a gate structure, at least partially located on a side of the drift layer away from the substrate, the gate structure comprising a gate oxide layer; A plurality of silicon substrate regions are located in the drift layer, and a surface of the silicon substrate region facing away from the substrate is located in the first surface, or is located on a side of the drift layer facing away from the substrate, the silicon substrate region is in contact with the gate oxide layer, and the silicon substrate region has a second doping type; A plurality of first body regions, wherein the first body regions are located on a side of the silicon base region close to the substrate, and the first body regions have a second doping type; A body region isolation dielectric layer, at least a portion of which is located between the silicon substrate region and the first body region; A plurality of conductive layers are respectively in contact with the drift layer, the silicon substrate region, the body region isolation dielectric layer and the gate oxide layer.

2. The field effect transistor according to claim 1, characterized in that The gate structure is located on a side of the drift layer away from the substrate, or a portion of the gate structure is located in the drift layer, and another portion of the gate structure is located on a side of the drift layer away from the substrate.

3. The field effect transistor according to claim 2, characterized in that: The field effect transistor comprises a first doping region and a second doping region, wherein the first doping region is located between the conductive layer and the second doping region, the first doping region has a first doping type, and the second doping region has a second doping type.

4. The field effect transistor according to claim 2, characterized in that: The field effect transistor comprises a first doping region and a second doping region, wherein the first doping region is located between the gate oxide layer and the second doping region, the first doping region has a first doping type, and the second doping region has a second doping type.

5. A method for preparing a field effect transistor, characterized in that: Used to prepare a field effect transistor according to any one of claims 1 to 4, the preparation method comprising: providing a substrate, the substrate having a first doping type; forming a drift layer on one side of the substrate, the drift layer having a first surface and the drift layer having the first doping type; A plurality of silicon substrate regions are formed in the drift layer, and a surface of the silicon substrate region facing away from the substrate is located in the first surface, or a plurality of silicon substrate regions are formed on a side of the drift layer facing away from the substrate, the silicon substrate regions are in contact with the gate oxide layer, and the silicon substrate regions have a second doping type; A gate structure is formed at least on one side of the drift layer away from the substrate, wherein the gate structure comprises a gate oxide layer, and the gate oxide layer is in contact with the plurality of silicon base regions.

6. The preparation method according to claim 5, characterized in that: Before forming the silicon base region on the side of the drift layer facing away from the substrate, the preparation method further includes: forming a first body region in the preliminary drift layer, the first body region having a second doping type; forming a preliminary body region isolation dielectric layer on the first body region, and etching the preliminary body region isolation dielectric layer and the preliminary drift layer to obtain the body region isolation dielectric layer and a first groove, wherein a portion of the first groove is located in the preliminary drift layer; A preliminary conductive layer is formed in the first groove.

7. The preparation method according to claim 6, characterized in that: The step of forming the silicon substrate region comprises: forming a silicon-based preliminary body region on the preliminary conductive layer; A first doping preparation region and a second doping preparation region are formed in the silicon-based preparation region, and the silicon-based preparation region, the first doping preparation region, the preparation conductive layer and the preparation drift layer are etched to obtain the silicon-based region.

8. The preparation method according to claim 5, characterized in that: Before the step of forming a plurality of silicon substrate regions on both sides of the drift layer, the preparation method further comprises: forming a first preliminary body region in the preliminary drift layer, wherein the first preliminary body region has a second doping type, and a surface of the first preliminary body region facing away from the substrate is located in the first surface; The first preliminary body region is etched to obtain a second groove and a first body region, and a preliminary body region isolation dielectric layer is formed in the second groove.

9. The preparation method according to claim 8, characterized in that: The step of forming the silicon substrate region comprises: A silicon-based preliminary region is formed on the preliminary region isolation dielectric layer, and a first doping region and a second doping region are formed in the silicon-based preliminary region to obtain the silicon-based region.

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