Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises MOS transistors which are formed on the surface of a substrate and are provided with metal gates, and at least one MOS transistor with a metal gate comprises a gate dielectric layer between the metal gate and the substrate. The gate dielectric layer comprises a high dielectric constant layer and a threshold voltage adjusting layer between the substrate and the high dielectric constant layer, and the threshold voltage adjusting layer comprises a dipole used for adjusting the work function of the substrate in a channel region so as to reduce the threshold voltage of the corresponding MOS transistor. Therefore, the corresponding MOS transistor can meet the threshold voltage requirement, the flexibility of adjusting the threshold voltage is improved, and the adjusting difficulty of the threshold voltage can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the development of CMOS integrated circuit manufacturing technology and the reduction of key dimensions, in order to avoid the increase of leakage current caused by the thinning of the silicon oxide gate dielectric layer, and in order to avoid the depletion effect and boron penetration effect of the polysilicon gate, the HKMG (high k metal gate) process using a gate dielectric layer containing a high dielectric constant (high k) material and a metal gate has become the mainstream in advanced processes.

[0003] In order to reduce the threshold voltage, a p-type work function regulating layer is usually provided in the gate structure of a PMOS transistor to adjust the gate work function, and an n-type work function regulating layer is provided in the gate structure of an NMOS transistor to adjust the gate work function.

[0004] However, the gate structure including the work function adjustment layer is relatively complex. As the technology develops, the process window is reduced, which increases the difficulty of adjusting the threshold voltage by only providing the work function adjustment layer in the gate structure. Summary of the invention

[0005] In order to make the corresponding MOS transistor meet the threshold voltage requirement and reduce the difficulty of adjusting the threshold voltage, the present invention provides a semiconductor device and a method for manufacturing the semiconductor device.

[0006] In one aspect, the present invention provides a semiconductor device, comprising:

[0007] substrate; and

[0008] A MOS transistor with a metal gate is formed on the surface of the substrate, at least one of the MOS transistors with a metal gate includes a gate dielectric layer between the metal gate and the substrate, and the gate dielectric layer includes a high dielectric constant layer and a threshold voltage adjustment layer between the substrate and the high dielectric constant layer, and the threshold voltage adjustment layer includes a dipole for adjusting the work function of the substrate in the channel region to reduce the threshold voltage of the corresponding MOS transistor.

[0009] Optionally, the substrate has a first active area, the semiconductor device includes a PMOS transistor formed in the first active area, the PMOS transistor includes a first metal gate and a first gate dielectric layer located between the first metal gate and the first active area, the first gate dielectric layer includes a first interface dielectric layer, a first threshold voltage adjustment layer and a first high dielectric constant layer stacked in sequence on the surface of the first active area, and the first threshold voltage adjustment layer includes a dipole with a dipole moment direction pointing to the outside of the first active area.

[0010] Optionally, the PMOS transistor further includes a first bottom barrier layer and / or a first sidewall barrier layer located between the first metal gate and the first high dielectric constant layer.

[0011] Optionally, the first threshold voltage adjustment layer includes at least one of an aluminum alloy and an aluminum-containing compound.

[0012] Optionally, the substrate has a second active area, the semiconductor device includes an NMOS transistor formed in the second active area, the NMOS transistor includes a second metal gate and a second gate dielectric layer located between the second metal gate and the second active area, the second gate dielectric layer includes a second interface dielectric layer, a second threshold voltage adjustment layer and a second high dielectric constant layer stacked in sequence on the surface of the second active area, and the second threshold voltage adjustment layer includes a dipole with a dipole moment direction pointing to the second active area.

[0013] Optionally, the NMOS transistor further includes a second bottom barrier layer and / or a second sidewall barrier layer located between the first metal gate and the second high dielectric constant layer.

[0014] Optionally, the second threshold voltage adjustment layer includes at least one of the rare earth elements La, Ru and Ta.

[0015] On the other hand, the present invention also provides a method for manufacturing a semiconductor device, which can be used to manufacture the above-mentioned semiconductor device. The method for manufacturing a semiconductor device comprises:

[0016] A MOS transistor with a metal gate is formed on a surface of a substrate, wherein at least one of the MOS transistors with a metal gate includes a gate dielectric layer formed between the metal gate and the substrate, the gate dielectric layer includes a high dielectric constant layer and a threshold voltage adjustment layer between the substrate and the high dielectric constant layer, and the threshold voltage adjustment layer includes a dipole for adjusting the work function of the substrate in a channel region to reduce the threshold voltage of the corresponding MOS transistor.

[0017] Optionally, the substrate has a first active region for forming a PMOS transistor and a second active region for forming an NMOS transistor, and forming a MOS transistor having a metal gate on the surface of the substrate includes:

[0018] forming a first stack on the substrate, the first stack comprising a first interface dielectric layer, a first threshold voltage adjustment layer, a first high dielectric constant layer and a first bottom barrier layer stacked in sequence on the surface of the substrate, wherein the first threshold voltage adjustment layer comprises a dipole with a dipole moment direction pointing to the outside of the first active region;

[0019] Forming a patterned hard mask layer on the substrate, using the hard mask layer to protect the first active area, and etching away the first stacked layer located in the second active area;

[0020] forming a second stack on the substrate, the second stack comprising a second interface dielectric layer, a second threshold voltage adjustment layer, a second high dielectric constant layer, and a second bottom barrier layer sequentially stacked on the surface of the second active region and the surface of the hard mask layer, wherein the second threshold voltage adjustment layer comprises a dipole whose dipole moment direction points to the second active region;

[0021] removing the mask layer and the second stacked layer on the mask layer;

[0022] Forming a first dummy gate and a second dummy gate in the first active area and the second active area respectively, forming sidewalls on both sides of the first dummy gate and the second dummy gate, and filling an interlayer dielectric layer in the groove outside the sidewalls;

[0023] removing the first dummy gate and the second dummy gate, forming a first groove on the first active area, and forming a second groove on the second active area;

[0024] forming a sidewall barrier layer conformally on the substrate, and filling the first groove and the second groove with a conductive material; and

[0025] A planarization process is performed to expose the upper surface of the interlayer dielectric layer, and the conductive material remaining in the first groove forms a first metal gate, and the conductive material remaining in the second groove forms a second metal gate.

[0026] Optionally, the substrate has a first active region for forming a PMOS transistor and a second active region for forming an NMOS transistor, and forming a MOS transistor having a metal gate on the surface of the substrate includes:

[0027] Forming a first dummy gate and a second dummy gate in the first active area and the second active area respectively, forming sidewalls on both sides of the first dummy gate and the second dummy gate, and filling an interlayer dielectric layer in the groove outside the sidewalls;

[0028] removing the first dummy gate and forming a first groove on the first active area;

[0029] A first interface dielectric layer, a first threshold voltage adjustment layer, a first high dielectric constant layer, a first bottom barrier layer and a first sidewall barrier layer are sequentially formed on the inner wall of the first groove and filled with a conductive material, wherein the first threshold voltage adjustment layer includes a dipole whose dipole moment direction points to the outside of the first active region;

[0030] Performing a planarization process to expose the upper surface of the interlayer dielectric layer, and the remaining conductive material in the first groove forms the first metal gate;

[0031] removing the second dummy gate and forming a second groove on the second active area;

[0032] A second interface dielectric layer, a second threshold voltage adjustment layer, a second high dielectric constant layer, a second bottom barrier layer and a second sidewall barrier layer are sequentially formed on the inner wall of the first groove and filled with a conductive material, wherein the second threshold voltage adjustment layer includes a dipole whose dipole moment direction points to the second active region; and

[0033] A planarization process is performed to expose the upper surface of the interlayer dielectric layer, and the remaining conductive material in the second groove forms the second metal gate.

[0034] Optionally, the first threshold voltage adjustment layer includes at least one of an aluminum alloy and an aluminum-containing compound; and / or the second threshold voltage adjustment layer includes at least one of rare earth elements La, Ru and Ta.

[0035] In the semiconductor device provided by the present invention, in at least one of the MOS transistors with a metal gate, a threshold voltage adjustment layer is arranged between the substrate and the high dielectric constant layer, and the threshold voltage adjustment layer includes a dipole for adjusting the work function of the substrate in the channel region to reduce the threshold voltage of the corresponding MOS transistor, which helps to make the corresponding MOS transistor meet the threshold voltage requirements, improves the flexibility of adjusting the threshold voltage, and can reduce the difficulty of adjusting the threshold voltage.

[0036] The method for manufacturing a semiconductor device provided by the present invention can form the above-mentioned semiconductor device, and has similar advantages to the above-mentioned semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figures 1A to 1GIt is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0038] FIG. 2A to FIG. 2F It is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0039] The semiconductor device and the method for making the same of the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not the only order for performing these steps, some of the steps described may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation in addition to the orientation of the device described in the figure. For example, if the structure in the accompanying drawings is inverted or positioned in other different ways (such as rotation), the exemplary term "on..." may also include "under..." and other orientation relationships.

[0040] The threshold voltage (Threshold Voltage, usually expressed as Vth) of a MOS transistor is related to the work function difference between the gate and the channel (the work function difference refers to the difference between the gate work function and the channel work function, which is a positive value). Generally speaking, reducing the work function difference can reduce the threshold voltage of the corresponding MOS transistor. For CMOS devices using HKMG technology, in order to reduce the threshold voltage, although a work function adjustment layer can be set in the gate structure to adjust the gate work function, this method has the problem that the process window is reduced as the technology develops, and the difficulty of adjustment increases. In the embodiment of the present invention, the work function difference between the gate and the channel is reduced mainly from the perspective of adjusting the substrate work function of the channel region. The threshold voltage of the corresponding MOS transistor can be reduced when the gate work function remains unchanged, which makes it easier for the corresponding MOS transistor to meet the threshold voltage requirements, improves the flexibility of adjusting the threshold voltage, and can reduce the adjustment requirements for the gate work function. For example, when the process window is small, the gate work function adjustment layer may not be set or the adjustment range and thickness requirements of the gate work function adjustment layer may be reduced, so that the difficulty of adjusting the threshold voltage is reduced.

[0041] The interface state charge formed in the metal and semiconductor interface region has an impact on the interface band structure. In this embodiment, a dipole is introduced between the metal gate and the substrate to adjust the work function of the substrate channel region, thereby reducing the threshold voltage. Specifically, for a PMOS transistor, when the gate voltage is less than the source voltage (the source voltage is usually equal to the substrate voltage), a conductive channel is formed, and the threshold voltage is a negative voltage. A suitable dipole is used to reduce the work function of the substrate in the PMOS transistor formation region in the channel region, so that the work function difference between the gate and the channel is reduced, thereby reducing the threshold voltage; for an NMOS transistor, when the gate voltage is greater than the source voltage (the source voltage is the substrate voltage), a conductive channel is formed, and the threshold voltage is a positive voltage. A suitable dipole is used to increase the work function of the substrate in the NMOS transistor formation region in the channel region, so that the work function difference between the gate and the channel is reduced, thereby reducing the threshold voltage.

[0042] In the method for manufacturing a semiconductor device of an embodiment of the present invention, a MOS transistor with a metal gate is formed on the surface of a substrate, wherein at least one of the MOS transistors with a metal gate includes a gate dielectric layer formed between the metal gate and the substrate, the gate dielectric layer includes a high dielectric constant layer and a threshold voltage adjustment layer between the substrate and the high dielectric constant layer, and the threshold voltage adjustment layer includes a dipole for adjusting the work function of the substrate in the channel region to reduce the threshold voltage of the corresponding MOS transistor. As an example, the method for manufacturing a semiconductor device of an embodiment of the present invention is described in Embodiment 1 and Embodiment 2 respectively. In addition, the semiconductor device of an embodiment of the present invention is described in Embodiment 3.

[0043] It should be noted that in the first and second embodiments, a PMOS transistor is formed corresponding to the first active area of ​​the substrate, and an NMOS transistor is formed corresponding to the second active area, and corresponding threshold voltage adjustment layers are formed in the PMOS transistor and the NMOS transistor, respectively, to reduce the threshold voltage of the corresponding transistor. However, the present invention is not limited thereto, and according to the requirements of the threshold voltage and the process window, in some embodiments, the corresponding threshold voltage adjustment layer may be formed only in the PMOS transistor, or only in the NMOS transistor.

[0044] It should be understood that the description of multiple embodiments is only for the purpose of more clearly explaining the connotation of the present invention, but the technical features in each embodiment are not unique to the embodiment, and all the features of each embodiment can also be regarded as the features of a general embodiment. It should be understood that each embodiment is only an exemplary specific implementation method for manufacturing and applying the embodiment, and does not constitute a scope limitation when manufacturing and applying the present invention.

[0045] Embodiment 1

[0046] Reference Figure 1A In the method for manufacturing a semiconductor device of this embodiment, first, a substrate 100 is provided. The substrate 100 may have a first active region 110 for forming a PMOS transistor and a second active region 120 for forming an NMOS transistor.

[0047] The substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon on insulator (SOI) substrate, a germanium on insulator substrate, a silicon germanium on insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), or may be other substrates known to those skilled in the art for carrying semiconductor components. In the following description, the substrate 100 is, for example, a silicon substrate. Certain doping ions may be implanted into the substrate 100 according to design requirements to adjust electrical parameters, and an isolation structure (e.g., shallow trench isolation, STI) may be formed in the substrate 100 to define and isolate the first active region 110, the second active region 120, and / or other active regions.

[0048] The method for manufacturing the semiconductor device of this embodiment may include the following processes.

[0049] Reference Figure 1A First, a first stack S1 is formed on a substrate 100, and the first stack S1 includes a first interfacial dielectric layer 101 (interfacial layer, IL), a first threshold voltage adjustment layer 102, a first high dielectric constant layer 103 (high-k) and a first bottom barrier layer 104 (bottom barrier material, BBM) stacked sequentially on the surface of the substrate 100.

[0050] In the first stack S1, the first interface dielectric layer 101 is, for example, a silicon oxide layer. The first high dielectric constant layer 103 may include various high dielectric constant dielectric materials (dielectric constant is, for example, greater than 4) such as rare earth metal oxides or lanthanide metal oxides. The first bottom barrier layer 104 is formed on the surface of the high dielectric constant dielectric layer 103. The first bottom barrier layer 104 may be used as an etching stop layer for subsequent processes. The material of the first bottom barrier layer 104 may include elements such as high temperature transition metals, precious metals, rare earth metals, and their carbides, nitrides, silicides, aluminum nitrides, or nitride silicon, such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), tantalum nitride silicon (TaSiN), and molybdenum aluminum nitride (MoAlN). As an example, the material of the first bottom barrier layer 104 is titanium nitride. In some embodiments, the first bottom barrier layer 104 may also be omitted. Each layer of material in the first stack S1 can be formed by using a suitable known process (such as thermal oxidation, chemical vapor deposition, physical vapor deposition or atomic layer deposition, etc.), and the thickness of each layer of material can be set according to the performance requirements of the device.

[0051] In this embodiment, a first threshold voltage adjustment layer 102 is further formed between the first interface dielectric layer 101 and the first high dielectric constant layer 103. The first threshold voltage adjustment layer 102 is used to adjust the work function of the first active region 110 in the channel region to reduce the threshold voltage of the PMOS transistor. The first threshold voltage adjustment layer 102 includes a dipole (i.e., a negative dipole) with a dipole moment direction (i.e., a direction in which negative charges point to positive charges) pointing to the outside of the first active region 110. As an example, the first threshold voltage adjustment layer 102 includes, for example, an aluminum alloy or an aluminum-containing compound (such as aluminum oxide). Further, the first threshold voltage adjustment layer 102 is, for example, an aluminum alloy layer.

[0052] Reference Figure 1B Then, a patterned hard mask layer HM is formed on the substrate 100, and the first active region 110 is protected by the hard mask layer HM, and the first stacked layer S1 located in the second active region 120 is removed by etching. The hard mask layer HM may include oxide, nitride and / or oxynitride.

[0053] Reference Figure 1C Then, a second stack S2 is formed on the substrate 100. The second stack S2 includes, for example, a second interface dielectric layer 105, a second threshold voltage adjustment layer 106, a second high dielectric constant layer 107, and a second bottom barrier layer 108, which are sequentially stacked on the second active region 120 and the surface of the hard mask layer HM. As an example, the second interface dielectric layer 105 can be formed using the same material and process as the first interface dielectric layer 101, the second high dielectric constant layer 107 can be formed using the same material and process as the first high dielectric constant layer 103, and the second bottom barrier layer 108 can be formed using the same material and process as the first bottom barrier layer 104.

[0054] In this embodiment, a second threshold voltage adjustment layer 106 is further formed between the second interface dielectric layer 105 and the second high dielectric constant layer 107. The second threshold voltage adjustment layer 106 is used to adjust the work function of the second active region 120 in the channel region to increase so as to reduce the threshold voltage of the NMOS transistor to be formed in the second active region 120. The second threshold voltage adjustment layer 106 includes a dipole (i.e., a positive dipole) whose dipole moment direction (i.e., the direction in which negative charges point to positive charges) points to the second active region 120. As an example, the second threshold voltage adjustment layer 106 includes at least one of rare earth elements such as La, Ru, and Ta. Further, the first threshold voltage adjustment layer 102 includes, for example, La oxide.

[0055] Reference Figure 1D Then, the hard mask layer HM and the second stacked layer S2 on the surface of the hard mask layer HM are removed. The first stacked layer S1 and the second stacked layer S2 are formed on the surfaces of the first active region 110 and the second active region 120, respectively.

[0056] Reference Figure 1E Then, a first dummy gate DG1 and a second dummy gate DG2 are formed in the first active area 110 and the second active area 120 respectively, and sidewalls SP are formed on both sides of the first dummy gate DG1 and the second dummy gate DG2, and an interlayer dielectric layer 130 is filled in the trench outside the sidewalls SP.

[0057] As an example, forming the first dummy gate DG1, the second dummy gate DG2 and the spacer SP may include the following process:

[0058] First, a polysilicon layer is formed on a substrate, and then the polysilicon layer and the first stack S1 and the second stack S2 thereunder are etched, so as to form a first dummy gate DG1 in a first active region 110 and a first stack S1 between the first dummy gate DG1 and the first active region 110, wherein a first interface dielectric layer 101, a first threshold voltage adjustment layer 102 and a first high dielectric constant layer 103 form a first gate dielectric layer, and a second dummy gate DG2 and a second stack S2 between the second dummy gate DG2 and the second active region 120 are formed in a second active region 120, wherein a second interface dielectric layer 105, a second threshold voltage adjustment layer 106 and a second high dielectric constant layer 107 form a second gate dielectric layer, and the polysilicon layer may be made of materials such as undoped polysilicon, doped polysilicon, and amorphous silicon;

[0059] Next, a first spacer is formed on the side of the first dummy gate DG1 and the first gate dielectric layer and on the side of the second dummy gate DG2 and the second gate dielectric layer by using a spacer process;

[0060] Afterwards, lightly doped source and drain regions (LDD) are formed in the first active region 110 and the second active region 120, and then a second sidewall is formed outside the first sidewall. The first sidewall and the second sidewall form a sidewall SP, and the sidewall SP may include silicon oxide, silicon nitride or silicon nitride, etc.

[0061] like Figure 1EAs shown, after forming the sidewall SP, source and drain ion implantation may be performed to form source and drain regions (such as source region S and drain region D) in the first active region 110 and the second active region 120, and then a metal silicide process may be used to form a metal silicide layer 109 on the surface of the source and drain regions. Then, a contact hole etch stop layer (CESL) and an interlayer dielectric layer 130 (ILD) may be sequentially formed on the substrate 100, wherein the contact hole etch stop layer, for example, conformally covers the surface of the substrate 100, and the interlayer dielectric layer 130 covers the contact hole etch stop layer and fills the trench outside the sidewall SP. The interlayer dielectric layer 130, for example, includes silicon oxide, and a planarization process may be performed to make the upper surface of the interlayer dielectric layer 130 flush with the upper surface of the first dummy gate DG1 and the second dummy gate DG2.

[0062] Reference Figure 1F After that, wet etching or dry etching can be selected to remove the first dummy gate DG1 and the second dummy gate DG2, and a first groove T1 is formed on the first active area 110, and a second groove T2 is formed on the second active area 110. The bottom surfaces of the first groove T1 and the second groove T2 expose the first bottom barrier layer 104 and the second bottom barrier layer 108, respectively.

[0063] Reference Figure 1G Then, a sidewall barrier layer 111 is formed on the inner walls of the first groove T1 and the second groove T2 and filled with a conductive material to form a first metal gate MG1 in the first groove T1 and a second metal gate MG2 in the second groove T2.

[0064] For example, the material of the sidewall barrier layer 111 may be first deposited on the interlayer dielectric layer 130 and cover the inner surface of the first groove T1 and the second groove T2 (but not fill the first groove T1 and the second groove T2). As an example, tantalum nitride may be selected as the material of the sidewall barrier layer 111. In some embodiments, according to the need to adjust the work function, if the process window allows, a p-type work function adjustment layer may be formed on the inner wall of the first groove T1 and / or an n-type work function adjustment layer may be formed on the inner wall of the second groove T2 to adjust the gate work function. Compared with the prior art, since the first threshold voltage adjustment layer 102 and the second threshold voltage adjustment layer 106 are used to adjust the work function of the channel region in this embodiment, the adjustment requirements of the p-type work function adjustment layer and the n-type work function adjustment layer on the gate work function are lower. For example, the p-type work function adjustment layer and / or the n-type work function adjustment layer may not be provided, or the p-type work function adjustment layer and / or the n-type work function adjustment layer that meet the process window may be provided. The p-type work function adjustment layer may be, for example, titanium nitride, and the n-type work function adjustment layer may be, for example, TiAl.

[0065] The conductive material filled in the first groove T1 and the second groove T2 is preferably a conductive material with low resistance, such as aluminum, titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper, titanium nitride, titanium carbide, tantalum nitride, titanium tungsten (Ti / W) or a composite metal layer formed by titanium and titanium nitride (Ti / TiN), etc. As an example, the conductive material filled in the first groove T1 and the second groove T2 includes a titanium nitride layer, a titanium layer and an aluminum layer formed in sequence. After filling the conductive material, the upper surface of the interlayer dielectric layer 130 can be exposed by a planarization process (such as CMP), and the remaining conductive material in the first groove T1 forms a first metal gate MG1, which is the gate of the PMOS transistor, and the remaining conductive material in the second groove T2 forms a second metal gate MG2 of the NMOS transistor, which is the gate of the NMOS transistor.

[0066] Furthermore, the method for manufacturing the semiconductor device of this embodiment may also include processes such as forming a dielectric layer, a metal plug and a metal interconnect structure on the substrate 100 to form the input and output terminals of the PMOS transistor and the NMOS transistor, which will not be repeated here.

[0067] In the method for manufacturing a semiconductor device of this embodiment, a first threshold voltage adjustment layer 102 is formed between the first interface dielectric layer 101 and the first high dielectric constant layer 103, and a dipole in the first threshold voltage adjustment layer 102 can change the work function of the channel region of the first active region 110 below, so that the threshold voltage of the PMOS transistor is reduced. A second threshold voltage adjustment layer 106 is formed between the second interface dielectric layer 105 and the second high dielectric constant layer 107, and a dipole in the second threshold voltage adjustment layer 106 can change the work function of the channel region of the second active region 120 below, so that the threshold voltage of the NMOS transistor is reduced. The thickness and dipole concentration of the first threshold voltage adjustment layer 102 and the second threshold voltage adjustment layer 106 can be adjusted as needed, which helps to make the corresponding MOS transistor meet the threshold voltage requirements, improves the flexibility of threshold voltage adjustment, and reduces the difficulty of threshold voltage adjustment.

[0068] In addition, in the manufacturing method of the above-mentioned semiconductor device, a mask is used only when forming a patterned hard mask layer HM. Compared with the existing process of using two mask processes to form a gate structure including a p-type work function adjustment layer on one side of the PMOS transistor and a gate structure including an n-type work function adjustment layer on one side of the NMOS transistor, one mask can be saved, which helps to save costs.

[0069] Embodiment 2

[0070] The present embodiment relates to a method for manufacturing a semiconductor device. The main difference between the present embodiment and the method for manufacturing a semiconductor device described in the first embodiment is that the manufacturing method of the first embodiment adopts a gate last process and a high-k first process, while the manufacturing method of the second embodiment adopts a gate last process and a high-k last process. It should be noted that the following description focuses on the differences between the present embodiment and the first embodiment, and the description of some of the same functional materials and processes can refer to the description of the first embodiment.

[0071] Reference Figure 2A In the method for manufacturing a semiconductor device of this embodiment, first, a substrate 200 is provided, and the substrate 200 has a first active region 210 for forming a PMOS transistor and a second active region 220 for forming an NMOS transistor.

[0072] Reference Figure 2B Then, a first dummy gate DG1 and a second dummy gate DG2 are formed in the first active region 210 and the second active region 220, respectively. For example, an oxide layer 201 is formed between the first dummy gate DG1 and the first active region 210 and between the second dummy gate DG2 and the second active region 220. In addition, sidewalls SP are formed on both sides of the first dummy gate DG1 and the second dummy gate DG2, and an interlayer dielectric layer 230 is filled in the trench outside the sidewalls SP. In addition, lightly doped source and drain regions LDD and source and drain regions (such as source region S and drain region D) are formed in the first active region 110 and the second active region 120. A metal silicide layer may be formed on the surface of the source and drain regions. In addition, before forming the interlayer dielectric layer 230, a contact etch stop layer (CESL) may be formed on the substrate 100. The process of forming the first dummy gate DG1, the second dummy gate DG2, the lightly doped source and drain regions LDD, the source and drain regions, the metal silicide layer, the contact etch stop layer (CESL) and the interlayer dielectric layer 230 may refer to the description in the first embodiment.

[0073] Reference Figure 2C Then, a patterned first mask layer (not shown, the first mask layer may include a hard mask layer and / or a photoresist layer) is formed on the substrate 200, the first mask layer is used to protect the second active area 220, the first dummy gate DG1 is removed by etching (the oxide layer 201 under the first dummy gate DG1 is also removed, for example), and a first groove T3 is formed on the first active area 210. The first mask layer may be removed afterwards.

[0074] Reference Figure 2DThen, a first interface dielectric layer 202 is formed on the surface of the first active region 210 exposed by the first groove T3, and a first threshold voltage adjustment layer 203, a first high dielectric constant layer 204, a first bottom barrier layer 205 and a first sidewall barrier layer 206 are sequentially formed conformally on the surface of the substrate 100, and a conductive material is deposited, the conductive material fills the first groove T3 and covers the surface of the substrate 200 outside the first groove T3. The first interface dielectric layer 202 is, for example, a silicon oxide layer. The first threshold voltage adjustment layer 203 includes a dipole (i.e., a negative dipole) with a dipole moment direction (i.e., a direction in which negative charges point to positive charges) pointing to the outside of the first active region 210, and the first threshold voltage adjustment layer 203 may include at least one of an aluminum alloy and an aluminum-containing compound (such as aluminum oxide). The first bottom barrier layer 205 is, for example, titanium nitride. The first sidewall barrier layer 206 is, for example, tantalum nitride. Afterwards, a planarization process (such as CMP) is used to expose the upper surface of the interlayer dielectric layer 230, and the remaining conductive material is located in the first groove T3 to form a first metal gate MG1. The first interface dielectric layer 202, the first threshold voltage adjustment layer 203 and the first high dielectric constant layer 204 located between the first metal gate MG1 and the first active area 210 form a first gate dielectric layer.

[0075] Reference Figure 2E Next, a patterned second mask layer (not shown, the second mask layer may include a hard mask layer and / or a photoresist layer) is formed on the substrate 100, the second mask layer is used to protect the first active area 210, the second dummy gate DG2 is removed by etching (the oxide layer 201 under the second dummy gate DG2 is also removed, for example), and a second groove T4 is formed on the second active area 120. The second mask layer may be removed afterwards.

[0076] Reference Figure 2FThen, a second interface dielectric layer 207 is formed on the surface of the second active region 220 exposed by the second groove T4, and a second threshold voltage adjustment layer 208, a second high dielectric constant layer 209, a second bottom barrier layer 211 and a second sidewall barrier layer 213 are sequentially formed conformally on the surface of the substrate 100, and a conductive material is deposited, the conductive material fills the second groove T4 and covers the surface of the substrate 200 outside the second groove T4. The second interface dielectric layer 207 is, for example, a silicon oxide layer. The second threshold voltage adjustment layer 208 includes a dipole (i.e., a positive dipole) whose dipole moment direction (i.e., the direction in which negative charges point to positive charges) points to the second active region 220. The second threshold voltage adjustment layer 208 includes, for example, at least one of rare earth elements such as rare earth elements La, Ru and Ta. The second bottom barrier layer 211 is, for example, titanium nitride. The second sidewall barrier layer 213 is, for example, tantalum nitride. Afterwards, a planarization process (such as CMP) is used to expose the upper surface of the interlayer dielectric layer 230, and the conductive material deposited on the second sidewall barrier layer 213 is located in the second groove T4 to form a second metal gate MG2. The second interface dielectric layer 207, the second threshold voltage adjustment layer 208 and the second high dielectric constant layer 209 located between the second metal gate MG2 and the second active area 220 form a second gate dielectric layer.

[0077] By using the method for manufacturing a semiconductor device of the present embodiment, a first threshold voltage adjustment layer 203 is formed between the first interface dielectric layer 202 and the first high dielectric constant layer 204, and the dipole in the first threshold voltage adjustment layer 203 can change the work function of the channel region of the first active region 110 below, so that the threshold voltage of the PMOS transistor is reduced. A second threshold voltage adjustment layer 208 is formed between the second interface dielectric layer 207 and the second high dielectric constant layer 209, and the dipole in the second threshold voltage adjustment layer 208 can change the work function of the channel region of the second active region 120 below, so that the threshold voltage of the NMOS transistor is reduced. The thickness and dipole concentration of the first threshold voltage adjustment layer 203 and the second threshold voltage adjustment layer 208 can be adjusted as needed, which helps to make the corresponding MOS transistor meet the threshold voltage requirements, and makes the threshold voltage adjustment flexibility high, thereby reducing the difficulty of threshold voltage adjustment.

[0078] Embodiment 3

[0079] The present embodiment relates to a semiconductor device. The semiconductor device includes a substrate and a MOS transistor formed on the surface of the substrate and having a metal gate, wherein at least one of the MOS transistors having a metal gate includes a gate dielectric layer between the metal gate and the substrate, and the gate dielectric layer includes a high dielectric constant layer and a threshold voltage adjustment layer between the substrate and the high dielectric constant layer, and the threshold voltage adjustment layer includes a dipole for adjusting the work function of the substrate in the channel region to reduce the threshold voltage of the corresponding MOS transistor. According to an embodiment of the present invention, the semiconductor device may include at least one PMOS transistor with a metal gate and / or at least one NMOS transistor with a metal gate, and wherein at least one MOS transistor with a metal gate (which may be a PMOS transistor and / or an NMOS transistor) has a corresponding threshold voltage adjustment layer, and the threshold voltage adjustment layer includes a dipole for adjusting the work function of the substrate in the corresponding channel region to reduce the threshold voltage of the corresponding MOS transistor.

[0080] The semiconductor device can be formed by using the above-mentioned method for manufacturing the semiconductor device. Figure 1G and Figure 2F As an example, the semiconductor device includes a substrate (such as Figure 1G The substrate 100 or Figure 2F The substrate 200 shown in FIG. 1 has a first active region (eg, Figure 1G The first active region 110 or Figure 2F The first active region 210 shown) and / or the second active region (such as Figure 1G The second active region 120 or Figure 2F The first active region 220 is shown.

[0081] The semiconductor device may include a PMOS transistor formed in the first active region. The PMOS transistor includes a first metal gate MG1 and a first gate dielectric layer located between the first metal gate MG1 and the first active region, wherein the first gate dielectric layer includes a first interface dielectric layer (such as Figure 1G The first interface dielectric layer 101 or Figure 2F The first interface dielectric layer 202 shown in FIG. 1 ), the first threshold voltage adjustment layer (such as Figure 1G The first threshold voltage adjustment layer 102 or Figure 2F The first threshold voltage adjustment layer 203 shown in FIG. Figure 1G The first high dielectric constant layer 103 and Figure 2F The first high dielectric constant layer 204 is shown).

[0082] The semiconductor device may include an NMOS transistor formed in the second active region. The NMOS transistor includes a second metal gate MG2 and a second gate dielectric layer located between the second metal gate MG2 and the second active region, wherein the second gate dielectric layer includes a second interface dielectric layer (such as Figure 1G The second interface dielectric layer 105 or Figure 2F The second interface dielectric layer 207 shown in FIG. 1 ), the second threshold voltage adjustment layer (such as Figure 1G The second threshold voltage adjustment layer 106 or Figure 2F The second threshold voltage adjustment layer 208 shown in FIG. Figure 1G The second high dielectric constant layer 107 or Figure 2F The second high dielectric constant layer 209 is shown).

[0083] Optionally, the first threshold voltage adjustment layer includes at least one of aluminum alloy and aluminum-containing compound. Optionally, the second threshold voltage adjustment layer includes at least one of rare earth elements such as La, Ru and Ta.

[0084] In some embodiments, the PMOS transistor may further include a first bottom barrier layer (eg, Figure 1G The first bottom barrier layer 104 or Figure 2F The first bottom barrier layer 205 shown in FIG. 1 and / or the first sidewall barrier layer (such as the first bottom barrier layer 205 shown in FIG. 1 ) located on the side and bottom of the first metal gate MG1 Figure 1G The side wall barrier layer 111 or Figure 2F The first sidewall barrier layer 206 is shown.

[0085] In some embodiments, the NMOS transistor may further include a second bottom barrier layer (eg, Figure 1G The second bottom barrier layer 108 or Figure 2F The second bottom barrier layer 211 shown in FIG. 1 and / or the second sidewall barrier layer (such as the second bottom barrier layer 211 shown in FIG. 1 ) located on the side and bottom of the second metal gate MG2 Figure 1G The side wall barrier layer 111 or Figure 2F The second sidewall barrier layer 213 is shown).

[0086] The first metal gate MG1 and the second metal gate MG2 may each include a stacked structure of a titanium nitride layer, a titanium layer, and an aluminum layer. The first bottom barrier layer and the second bottom barrier layer may include titanium nitride. The first sidewall barrier layer and the second sidewall barrier layer may include titanium nitride.

[0087] like Figure 1G and Figure 2FAs shown, the semiconductor device may further include an interlayer dielectric layer (such as Figure 1G The interlayer dielectric layer 130 or Figure 2F The interlayer dielectric layer 230 is shown, and the upper surfaces of the first metal gate MG1 and the second metal gate MG2 are flush with the upper surface of the interlayer dielectric layer.

[0088] In the semiconductor device described in the embodiment of the present invention, the first gate dielectric layer in the PMOS transistor includes a first threshold voltage adjustment layer, and the second gate dielectric layer in the NMOS transistor includes a second threshold voltage adjustment layer. The dipoles in the first threshold voltage adjustment layer and the second threshold voltage adjustment layer can adjust the threshold voltage of the corresponding MOS transistor. The thickness and dipole concentration of the first threshold voltage adjustment layer and the second threshold voltage adjustment layer can be adjusted as needed, which helps to make the corresponding MOS transistor meet the threshold voltage requirements, improves the flexibility of adjusting the threshold voltage, and reduces the difficulty of adjusting the threshold voltage.

[0089] It should be noted that the contents of the embodiments in this specification are described in a progressive manner, and the parts described later focus on the differences from the parts described previously, and the same and similar parts between the various parts can be referenced to each other.

[0090] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; as well as A MOS transistor with a metal gate is formed on the surface of the substrate, at least one of the MOS transistors with a metal gate includes a gate dielectric layer between the metal gate and the substrate, and the gate dielectric layer includes a high dielectric constant layer and a threshold voltage adjustment layer between the substrate and the high dielectric constant layer, and the threshold voltage adjustment layer includes a dipole for adjusting the work function of the substrate in the channel region to reduce the threshold voltage of the corresponding MOS transistor.

2. The semiconductor device according to claim 1, wherein The substrate has a first active area, the semiconductor device includes a PMOS transistor formed in the first active area, the PMOS transistor includes a first metal gate and a first gate dielectric layer located between the first metal gate and the first active area, the first gate dielectric layer includes a first interface dielectric layer, a first threshold voltage adjustment layer and a first high dielectric constant layer stacked in sequence on the surface of the first active area, and the first threshold voltage adjustment layer includes a dipole with a dipole moment direction pointing to the outside of the first active area.

3. The semiconductor device according to claim 2, wherein: The PMOS transistor further includes a first bottom barrier layer and / or a first sidewall barrier layer located between the first metal gate and the first high dielectric constant layer.

4. The semiconductor device according to claim 2, wherein: The first threshold voltage adjustment layer includes at least one of an aluminum alloy and an aluminum-containing compound.

5. The semiconductor device according to claim 1, wherein: The substrate has a second active area, the semiconductor device includes an NMOS transistor formed in the second active area, the NMOS transistor includes a second metal gate and a second gate dielectric layer located between the second metal gate and the second active area, the second gate dielectric layer includes a second interface dielectric layer, a second threshold voltage adjustment layer and a second high dielectric constant layer stacked in sequence on the surface of the second active area, and the second threshold voltage adjustment layer includes a dipole with a dipole moment direction pointing to the second active area.

6. The semiconductor device according to claim 5, characterized in that The NMOS transistor further includes a second bottom barrier layer and / or a second sidewall barrier layer located between the first metal gate and the second high dielectric constant layer.

7. The semiconductor device according to claim 5, characterized in that The second threshold voltage adjustment layer includes at least one of the rare earth elements La, Ru and Ta.

8. A method for manufacturing a semiconductor device, characterized in that: include: A MOS transistor with a metal gate is formed on a surface of a substrate, wherein at least one of the MOS transistors with a metal gate includes a gate dielectric layer formed between the metal gate and the substrate, the gate dielectric layer includes a high dielectric constant layer and a threshold voltage adjustment layer between the substrate and the high dielectric constant layer, and the threshold voltage adjustment layer includes a dipole for adjusting the work function of the substrate in a channel region to reduce the threshold voltage of the corresponding MOS transistor.

9. The method of claim 8, wherein: The substrate has a first active area for forming a PMOS transistor and a second active area for forming an NMOS transistor, and forming a MOS transistor with a metal gate on the surface of the substrate includes: forming a first stack on the substrate, the first stack comprising a first interface dielectric layer, a first threshold voltage adjustment layer, a first high dielectric constant layer and a first bottom barrier layer stacked in sequence on the surface of the substrate, wherein the first threshold voltage adjustment layer comprises a dipole with a dipole moment direction pointing to the outside of the first active region; Forming a patterned hard mask layer on the substrate, using the hard mask layer to protect the first active area, and etching away the first stacked layer located in the second active area; forming a second stack on the substrate, the second stack comprising a second interface dielectric layer, a second threshold voltage adjustment layer, a second high dielectric constant layer, and a second bottom barrier layer sequentially stacked on the surface of the second active region and the surface of the hard mask layer, wherein the second threshold voltage adjustment layer comprises a dipole whose dipole moment direction points to the second active region; removing the mask layer and the second stacked layer on the mask layer; Forming a first dummy gate and a second dummy gate in the first active area and the second active area respectively, forming sidewalls on both sides of the first dummy gate and the second dummy gate, and filling an interlayer dielectric layer in the groove outside the sidewalls; removing the first dummy gate and the second dummy gate, forming a first groove on the first active area, and forming a second groove on the second active area; forming a sidewall barrier layer conformally on the substrate, and filling the first groove and the second groove with a conductive material; and A planarization process is performed to expose the upper surface of the interlayer dielectric layer, and the conductive material remaining in the first groove forms a first metal gate, and the conductive material remaining in the second groove forms a second metal gate.

10. The method according to claim 8, characterized in that: The substrate has a first active area for forming a PMOS transistor and a second active area for forming an NMOS transistor, and forming a MOS transistor with a metal gate on the surface of the substrate includes: Forming a first dummy gate and a second dummy gate in the first active area and the second active area respectively, forming sidewalls on both sides of the first dummy gate and the second dummy gate, and filling an interlayer dielectric layer in the groove outside the sidewalls; removing the first dummy gate and forming a first groove on the first active area; A first interface dielectric layer, a first threshold voltage adjustment layer, a first high dielectric constant layer, a first bottom barrier layer and a first sidewall barrier layer are sequentially formed on the inner wall of the first groove and filled with a conductive material, wherein the first threshold voltage adjustment layer includes a dipole whose dipole moment direction points to the outside of the first active region; Performing a planarization process to expose the upper surface of the interlayer dielectric layer, and the remaining conductive material in the first groove forms the first metal gate; removing the second dummy gate and forming a second groove on the second active area; A second interface dielectric layer, a second threshold voltage adjustment layer, a second high dielectric constant layer, a second bottom barrier layer and a second sidewall barrier layer are sequentially formed on the inner wall of the first groove and filled with a conductive material, wherein the second threshold voltage adjustment layer includes a dipole with a dipole moment direction pointing to the second active region; and A planarization process is performed to expose the upper surface of the interlayer dielectric layer, and the remaining conductive material in the second groove forms the second metal gate.

11. The production method according to claim 9 or 10, characterized in that: The first threshold voltage adjustment layer includes at least one of an aluminum alloy and an aluminum-containing compound; and / or the second threshold voltage adjustment layer includes at least one of rare earth elements La, Ru and Ta.

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