Method for producing diode

Abstract

The present disclosure relates to a method for producing an electronic component. At least one bipolar transistor and at least one variable capacitance diode are commonly produced on a common substrate by the method.

Description

[0001] Description of the case

[0002] This application is a divisional application of the Chinese invention patent application with application number 202010591265.9 and name “Method for Producing a Diode” filed on June 24, 2020.

[0003] Priority claim

[0004] This application claims the benefit of priority from French patent application No. 1907149, filed on June 28, 2019, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0005] The present disclosure relates generally to methods for producing electronic components, and more particularly, to methods for producing variable capacitance diodes (also known as varicap diodes or varactors). Background Art

[0006] A varactor is an electronic dipole having two terminals between which a pn junction is formed.

[0007] When the varactor is directly polarized, it has an operation similar to that of a conventional diode, in other words, when a certain voltage threshold is exceeded, the varactor conducts.

[0008] If, on the other hand, a voltage of opposite polarization is applied across the terminals of a varactor, the varactor differs from a conventional diode in the off state in that, in theory, it does not behave like an open circuit, but rather like a capacitor. In practice, a similar capacitance phenomenon also occurs for a reverse-biased conventional diode, but to a lesser extent.

[0009] Whereas in the case of conventional diodes efforts are made to avoid such capacitive phenomena, in the case of varactor diodes such capacitive phenomena are encouraged as much as possible.

[0010] There is a need in the art to increase the capacitance of current varactors. There is a further need for improved methods by which varactors can be produced. Summary of the invention

[0011] One embodiment addresses all or some of the disadvantages of known varactors and known methods of producing these varactors.

[0012] One embodiment provides a method for jointly producing at least one bipolar transistor and at least one variable capacitance diode on the same (ie, common or shared) substrate.

[0013] According to one embodiment, the diode comprises a pn-junction constituted by: a first region having a first conductivity type; and a second region having a second conductivity type; the first region and the extrinsic base of the transistor being manufactured during the same step.

[0014] According to one embodiment, the first region is made flush with an extrinsic collector region constituting the second region.

[0015] According to one embodiment, the first region is produced by epitaxy.

[0016] According to one embodiment, the section of the second region is doped by ion implantation.

[0017] According to one embodiment, the first conductivity type is p and the second conductivity type is n.

[0018] According to one embodiment, the first conductivity type is n and the second conductivity type is p.

[0019] According to one embodiment, the diode comprises a varactor having a hyperabrupt pn junction.

[0020] One embodiment provides a method as described, having the following steps: providing a substrate, within which a first extrinsic collector region laterally bounded by a first deep isolation trench and by a second deep isolation trench has a first sink, the first sink being inserted between the first deep isolation trench and the first shallow isolation trench, and within which a third deep isolation trench and the second extrinsic collector region laterally bounded by the first deep isolation trench have a second sink and a third sink, the second sink being inserted between the third deep isolation trench and the second shallow isolation trench, the third sink being inserted between the first deep isolation trench and the third shallow isolation trench; forming a stack formed of the following layers on a surface of the substrate: a first layer, a first layer covering the first layer; a second layer covering the second layer, a third layer covering the second layer, a fourth layer covering the third layer, a fifth layer covering the fourth layer, and a sixth layer covering the fifth layer; a through opening is formed in the stack and is flush with a portion of the surface of the substrate, the first non-intrinsic collector region is flush at a portion of the surface, and the through opening separates the stack into a first stack consisting of a first region of the layer and a second stack consisting of a second region of the layer; a first deposit and a second deposit are generated in the first opening, and the second deposit completely covers the first deposit; two spacers are generated in the first opening, each spacer having a first portion and a second portion, and the first portion of each spacer is composed of a portion covering the The invention relates to a method for depositing a first link in contact with the second layer, wherein the first region of the sixth layer is a horizontal portion of an upper surface of the second deposit, and a vertical portion flush with an upper surface of the first region of the sixth layer or an upper surface of the second region of the sixth layer; removing the first region of the sixth layer, the second region of the sixth layer, the vertical portion of the first portion of the spacer, and the second portion of the spacer; producing a third deposit above the following portions: the second deposit, the horizontal portion of the first portion of the spacer, a portion of the first region of the fifth layer, and a portion of the second region of the fifth layer; removing the first region of the fifth layer except for the portion of the first region of the fifth layer, and removing the second region of the fifth layer except for the portion of the second region of the fifth layer; depositing a seventh layer, the seventh layer covering an upper surface of the third deposit, a side surface of the third deposit, a side surface of a portion of the first region of the fifth layer, and a side surface of a portion of the second region of the fifth layer; removing all of the first region of the fourth layer and all of the second region of the fourth layer; producing a first link contacting the second layer below the portion of the first region of the fifth layer and the vertical portion of the seventh layer, and producing a second link contacting the second layer below the portion of the second region of the fifth layer and the vertical portion of the seventh layer;A second opening is formed, penetrating through the first regions of the first, second and third layers and flush with a portion of the surface of the substrate having the second extrinsic collector region, a portion of the second shallow isolation trench and a portion of the third shallow isolation trench, wherein these first regions are flush with a portion of the surface of the substrate, and the second opening separates the first region of the first layer into a first portion and a second portion, separates the first region of the second layer into a first portion and a second portion, and separates the first region of the third layer into a first portion and a second portion. ;

[0021] One embodiment provides the described method, further having the following steps: removing all of the first portion of the first area of ​​the third layer, removing the second portion of the first area of ​​the third layer except for the first element located flush with the first link, and removing the second area of ​​the third layer except for the second element located flush with the second link; generating an eighth layer, wherein the first area of ​​the eighth layer covers a portion of the surface of the second area of ​​the second layer not covered by the second element, the second area of ​​the eighth layer completely covers the first portion of the first area of ​​the second layer, the third area of ​​the eighth layer covers a portion of the surface of the second portion of the first area of ​​the second layer not covered by the first element, and the fourth area of ​​the eighth layer constitutes the first area; depositing a sacrificial layer, wherein the first portion of the sacrificial layer covers the first area, and the second portion of the sacrificial layer covers the seventh layer, the first path and the second link, and the second portion of the sacrificial layer extends laterally above the first element of the third area of ​​the eighth layer and above the second element of the first area of ​​the eighth layer; removing the areas and portions of the eighth layer and the second layer that are not covered by the first and second portions of the sacrificial layer part; completely remove the first part of the first area of ​​the first layer, remove the second part of the first area of ​​the first layer except the fifth element covered by the third element, and remove the second area of ​​the first layer except the sixth element covered by the fourth element; generate a second spacer on either side of the first area, generate a third spacer on either side of the first deposit, and generate a fourth spacer on either side of the second deposit; generate a first contact reaction element on the second groove, generate a second contact reaction element on the third groove, generate a third contact reaction element on the first area, generate a fourth contact reaction element on the first host, generate a fifth contact reaction element on the first element of the third area of ​​the eighth layer, generate a sixth contact reaction element on the second element of the first area of ​​the eighth layer, and generate a seventh contact reaction element on the third deposit, the first, second and third contact reaction elements constitute the terminals of the variable capacitance diode, the fourth contact reaction element constitutes the collector terminal of the bipolar transistor, the fifth and seventh contact reaction elements constitute the base terminal of the bipolar transistor, and the eighth contact reaction element constitutes the emitter terminal of the bipolar transistor.

[0022] One embodiment provides an electronic circuit comprising at least one of a varactor and at least one bipolar transistor obtained using the method described. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The foregoing features and advantages, as well as other features and advantages, will be described in detail below in the description of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0024] Figures 1 to 17 The steps of one embodiment of a method for producing a varactor and a bipolar transistor are schematically shown in cross-section; and

[0025] Fig.18 The variation curves of characteristic properties of a varactor diode obtained using an embodiment of the described method are shown. DETAILED DESCRIPTION

[0026] In the various drawings, similar features have been denoted by similar reference numerals. In particular, common structural and / or functional features between the various embodiments may have the same reference numerals and may be provided with the same structure, dimensions, and material properties.

[0027] For the sake of clarity, only operations and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, the method of preparing the substrate is not described in detail.

[0028] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors; and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0029] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers (such as terms "front", "back", "top", "bottom", "left", "right", etc.) or relative position qualifiers (such as terms "above", "below", "higher", "lower", etc.) or directional qualifiers (such as "horizontal", "vertical", etc.), reference is made to the orientation shown in the figure.

[0030] Unless otherwise specified, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, and preferably within 5%.

[0031] the following Figures 1 to 17 The following is a diagram of the steps of a method for producing a varactor 100 or a variable capacitance diode 100 or a varactor 100. According to this embodiment, the varactor 100 is co-integrated with a heterojunction bipolar transistor (HBT) 300, here of the BiCMOS (bipolar CMOS) type. In other words, the described embodiment makes it possible to produce the bipolar transistor 300 and the varactor 100 on the same (ie common or shared) substrate and jointly. Figures 2 to 9More particularly, the steps dedicated to producing the bipolar transistor 300 are shown. Figures 10 to 12 More particularly, the steps specific to producing the varactor 100 are shown again.

[0032] For the sake of simplicity, the following Figures 1 to 17 The disclosure uses the example of a method of jointly manufacturing a single variable capacitance diode 100 and a single bipolar transistor 300. However, it should be understood that the method can be extended to jointly and on the same substrate produce any number of bipolar transistors 300 and any number of variable capacitance diodes 100, which numbers may be different.

[0033] Figure 1 The steps of an embodiment of a method for producing a varactor and a bipolar transistor are schematically shown in cross section.

[0034] According to this embodiment, a substrate 500, for example composed of a single crystal silicon wafer, is provided. Figure 1 In the embodiment, the substrate 500 has a first isolation substrate (DTI) 510, 512 and 514, for example a deep trench isolation (DTI) substrate. These deep isolation trenches 510, 512 and 514 extend vertically from the upper surface 501 of the substrate 500. Therefore, the trenches 510, 512 and 514 define two positions laterally in the substrate 500: a first position (HA-varactor, for hyperabrupt varactor), included between the trenches 510 and the trenches 512, at which the variable capacitance diode 100 needs to be produced, and thus this position is hereinafter referred to as the "diode position" ( Figure 1 and a second location (HBT, for heterojunction bipolar transistor), included between trench 512 and trench 514, where it is desired to produce a bipolar transistor 300, which is therefore hereinafter referred to by the expression "transistor location" ( Figure 1 on the right side of the image).

[0035] exist Figure 1 Deep isolation trenches 510, 512 and 514 in the substrate 500 separate two extrinsic collector regions 520, 525 (implanted collectors). Regions 520 and 525 emerge while extending vertically toward the upper surface 501 of the substrate 500 from a lower depth than the trenches 510, 512 and 514. More specifically, the first extrinsic collector region 520 located at the transistor position is inserted between the deep isolation trenches 512 and the deep isolation trenches 514; and the second extrinsic collector region 525 located at the diode position is inserted between the deep isolation trenches 510 and the deep isolation trenches 512.

[0036] Therefore, in Figure 1In the case of the trench 512 being approached, the non-intrinsic collector regions 520 and 525 are separated from each other by a common isolation trench. These non-intrinsic collector regions 520 and 525 are obtained, for example, by ion implantation of a dopant element (e.g., phosphorus or arsenic) having a first conductivity type (e.g., n-type) below the upper surface 501 of the substrate 500. When one of the regions 520 and 525 moves away from the upper surface 501 of the substrate 500, these regions have a gradually increasing concentration of the dopant element.

[0037] The substrate 500 also includes second isolation structures 530, 532, and 534 (SSTI), for example, which are super shallow trench isolations (SSTI). These trenches 530, 532, and 534 extend vertically from the upper surface 501 of the substrate 500 to a smaller depth than the regions 520 and 525. The depth of the shallow isolation trenches 530, 532, and 534 is between about 50 nm and about 100 nm, preferably between 50 nm and 100 nm.

[0038] A first sink 540 (N sink) located in a transistor position is inserted between the trench 512 and the trench 534. The first sink 540 has a first conductivity type, in this example, n-type.

[0039] Two second sinks 545 and 547 (NS / D sinks) located in diode positions are respectively inserted between: for sink 545, between deep isolation trench 510 and shallow isolation trench 530; and for sink 547, between shallow isolation trench 532 and deep isolation trench 512.

[0040] These second sinks 545 and 547 have a first conductivity type, which is n-type in this example.

[0041] The first sink 540 and the second sink 545, 547 extend vertically from the upper surface 501 of the substrate 500 inside the first and second extrinsic collector regions 520, 525, respectively. In other words, the sinks 540, 545 and 547 make it possible to contact the extrinsic collector regions 520 and 525, respectively, from the upper surface 501 of the substrate 500.

[0042] exist Figure 1 In the embodiment, either side of the extrinsic collector region 520 (at Figure 1 The sink 540 is located on the left and right sides of the region 520, respectively, and is adjacent to the deep isolation trenches 512 and 514. Figure 1 The shallow isolation trench 534 is beside the sink 540, that is, on the side of the sink 540 that does not contact the deep isolation trench 512 ( Figure 1The portion of the extrinsic collector region 520 between the shallow isolation trench 534 and the deep isolation trench 514 is flush with the surface 501 of the substrate 500 .

[0043] exist Figure 1 In the case of a non-intrinsic collector region 525, either side (in Figure 1 The sink 545 is located on the left and right sides of the region 525, respectively, and is adjacent to the deep isolation trenches 510 and 512. The sink 545 is located next to the deep isolation trench 510 (at Figure 1 The shallow isolation trench 530 is beside the sink 545, that is, on the side of the sink 545 that does not contact the deep isolation trench 510 ( Figure 1 The sink 547 is next to the deep isolation trench 512 ( Figure 1 The shallow isolation trench 532 is next to the sink 547, that is, on the side where the sink 547 does not contact the deep isolation trench 512 ( Figure 1 The portion of the extrinsic collector region 525 between the shallow isolation trench 530 and the shallow isolation trench 532 is flush with the surface 501 of the substrate 500 .

[0044] In the rest of the description, Figures 2 to 17 The described method embodiments consist primarily of operations performed above the upper surface 501 of the substrate 500. Unless otherwise mentioned, Figures 2 to 17 The substrate 500 is thus maintained as with respect to Figure 1 The disclosed substrate 500 is the same. For the sake of simplicity, the substrate 500 will therefore not be described in detail in the following figures.

[0045] Figure 2 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Figure 1 The disclosed structure is made. Figure 2 The disclosed steps are more particularly dedicated to producing a portion of a future bipolar transistor 300 .

[0046] During this step, a stack 700 composed of successive layers placed one above the other is deposited over the entire upper surface 501 of the substrate 500 .

[0047] like Figure 2As illustrated in , the stack 700 more specifically includes: a first layer 701, which is composed of an oxide such as silicon oxide, and the first layer completely covers the upper surface 501 of the substrate 500; a second layer 703, which is preferably composed of polysilicon having a second conductivity type (p-type in this example), and the second layer completely covers the upper surface of the first layer 701; a third layer 705, which is composed of an oxide (for example, an oxide that is the same as the oxide that constitutes the first layer 701), and the third layer completely covers the upper surface of the second layer 703; a fourth layer 707, which is composed of a nitride such as silicon nitride, and the fourth layer completely covers the upper surface of the third layer 705; a fifth layer 709, which is composed of an oxide (for example, an oxide that is the same as the oxide that constitutes the first layer 701), and the fifth layer completely covers the upper surface of the fourth layer 707; and a sixth layer 711, which is composed of a nitride (for example, a nitride that is the same as the nitride that constitutes the fourth layer 707), and the sixth layer completely covers the upper surface of the fifth layer 709.

[0048] The thickness of the first layer 701 is about 50 nm, preferably equal to 50 nm. The thickness of the second layer 703 is about 40 nm, preferably equal to 40 nm. The thickness of the third layer 705 is about 5 nm, preferably equal to 5 nm. The thickness of the fourth layer 707 is about 40 nm, preferably equal to 40 nm. The thickness of the fifth layer 709 is about 30 nm, preferably equal to 30 nm. The thickness of the sixth layer is about 40 nm, preferably equal to 40 nm.

[0049] Figure 3 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Figure 2 The disclosed structure is made. Figure 3 The disclosed steps are more particularly dedicated to producing a portion of a future bipolar transistor 300 .

[0050] During this step, stack 700 ( Figure 2 ) is locally etched over its entire thickness to a depth flush with a portion of the upper surface 501 of the substrate 500, with which the extrinsic collector region 520 located in the transistor position is flush. This amounts to the formation of a vertical opening 720 that passes through the six layers 701, 703, 705, 707, 709 and 711 of the stack 700.

[0051] Therefore, in Figure 3 , the opening 720 separates two separate stacks: the first stack 7001 ( Figure 3701, 703, 705, 707, 709, and 711, respectively; and a second stack 7002 ( Figure 3 7052, 7072, 7092 and 7112 of the layers 701, 703, 705, 707, 709 and 711, respectively.

[0052] Therefore, in Figure 3 In the embodiment of the present invention, a portion of the extrinsic collector region 520 inserted between the shallow isolation trench 534 and the deep isolation trench 514 is stripped.

[0053] Next, within the entire width of the opening 720 and above the portion of the upper surface 501 of the substrate 500 that is not covered by the stacks 7001 and 7002, there are produced: a first deposit 721 of a doping material having a first conductivity type (n-type in this example); and a second deposit 723 of a doping material having a second conductivity type (p-type in this example), which covers the entire upper surface of the deposit 721.

[0054] The first and second deposits 721 and 723 are preferably made by epitaxy. This makes it possible to obtain a very sharp interface between these deposits 721 and 723, so that the pn junction is characterized by a very sharp change in the dopant distribution near the interface. This is then called a "mutated" pn junction.

[0055] The thickness of the first deposit 721 is substantially equal to the cumulative thickness of the second region 7012 of the first layer 701 and the second region 7032 of the second layer 703, preferably equal to the cumulative thickness of the second regions 7012 and 7032. Therefore, the thickness of the first deposit is about 90 nm, preferably equal to 90 nm. The thickness of the second deposit 723 is about 25 nm, preferably equal to 25 nm.

[0056] According to this embodiment, the first deposit 721 constitutes the intrinsic collector of the transistor 300. The second deposit 723 constitutes the intrinsic base of the transistor 300.

[0057] Figure 4 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Figure 3 The disclosed structure is made. Figure 4 The disclosed steps are more particularly dedicated to producing a portion of a future bipolar transistor 300 .

[0058] During this step, two spacers 730 are created inside the opening 720. The two spacers 730 are each placed on the upper surface of a portion of the second deposit 723 and completely abut against the sidewalls of the opening 720. The two spacers 730 are not connected, in other words, they do not completely cover the upper surface of the deposit 723. Figure 4 In the embodiment, the spacers 730 each abut against a portion of the side surfaces of the first and second regions 7091 , 7092 of the fifth layer 709 and against the entire side surfaces of the first and second regions 7111 , 7112 of the sixth layer 711 within the opening 720 .

[0059] exist Figure 4 In the example of FIG. 7 , each spacer 730 has an L-shaped first portion 731. Each L-shaped first portion 731 is composed of a vertical portion 731V corresponding to the vertical branch of the L, and a horizontal portion 731H corresponding to the horizontal branch of the L. The first portion 731 of the spacer 730 is made of silicon oxide, for example.

[0060] The vertical portion 731V of the first portion 731 of the spacer 730 partially covers the side surfaces of the first and second regions 7091, 7092 of the fifth layer 709 and the entire side surfaces of the first and second regions 7111, 7112 of the sixth layer 711. The vertical portion 731V is flush with the upper surfaces of the first and second regions 7111, 7112 of the sixth layer 711.

[0061] The horizontal portion 731H partially covers the upper surface of the deposit 723 .

[0062] Each spacer 730 also includes a second portion 732. The second portion 732 is obtained by depositing a nitride on the horizontal portion 731H of the first portion 731. For example, the same as that used to constitute the fourth layer 707 ( Figure 2 ) The deposition is followed by a selective etching step which imparts a D-shape to the second portion 732 of the spacer 730.

[0063] Figure 5 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Figure 4 The disclosed structure is made. Figure 5 The disclosed steps are more particularly dedicated to producing a portion of a future bipolar transistor 300 .

[0064] During this step, the Figure 4The nitride on the surface of the described structure is selectively etched, thereby removing: all first and second regions 7111 , 7112 of the sixth layer 711 ; the vertical portion 731V of the first portion 731 of the spacer 730 ; and the second portion 732 of the spacer 730 .

[0065] Therefore, only the horizontal portions 731H of the first portion 731 of the spacer 730 remain, which partially cover the upper surface of the second deposit 723. These horizontal portions 731H remain in contact with the first and second regions 7091, 7092 of the fifth layer 709.

[0066] Figure 6 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Figure 5 The disclosed structure is made. Figure 6 The disclosed steps are more particularly dedicated to producing a portion of a future bipolar transistor 300 .

[0067] During this step, a third deposition 725 is completed on top of the second deposition 723 forming the intrinsic base of the transistor 300. The third deposition 725 covers the following: the entire free upper surface of the second deposition 723; the entire upper surface of each horizontal portion 731H of the first portion 731 of the spacer 730; a portion 70911 ( Figure 6 in the left side of the second deposit 723); and a portion 70921 of the second region 7092 of the layer 709 ( Figure 6 on the right side of the second deposit 723).

[0068] The third deposit 725 is made of a doping material having a first conductivity type (n-type in this example). The third deposit 725 constitutes an intrinsic emitter of the transistor 300 .

[0069] The third deposit 725 is preferably made by epitaxy. This makes it possible to obtain a very sharp interface between these deposits 725 and the deposit 723, so that the pn junction is characterized by a very sharp change in the dopant profile near this interface ("abrupt" pn junction).

[0070] The thickness of the third deposit 725 is approximately 100 nm, preferably equal to 100 nm.

[0071] Next, the first and second regions 7091 , 7092 of the fifth layer 709 are etched so that only portions 70911 , 70921 located below the third deposit 725 remain. Figure 6The structure obtained after the step for etching the first and second regions 7091 and 7092 of the layer 709 is shown. Figure 6 The reason why only parts 70911 and 70921 are visible.

[0072] Figure 7 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Figure 6 The disclosed structure is made. Figure 7 The disclosed steps are more particularly dedicated to producing a portion of a future bipolar transistor 300 .

[0073] During this step, transistor 300 is covered by seventh layer 713. Figure 7 In the embodiment, the seventh layer 713 covers the following: the upper surface and the side surfaces of the third deposit 725; and the free side surfaces of the portions 70911 and 70921.

[0074] The seventh layer 713 is made of oxide, for example, the same as the first layer 701 ( Figure 2 )'s oxide is composed of the same oxide.

[0075] Figure 8 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Figure 7 The disclosed structure is made. Figure 8 The disclosed steps are more particularly dedicated to producing a portion of a future bipolar transistor 300 .

[0076] During this step, the first and second regions 7071, 7072 of the fourth layer 707 are completely etched, so that Figure 8 In other words, the regions 7071 and 7072 are completely removed from the fourth layer 707. Thus, the etching forms two notches 740 between: on the one hand, the first and second regions 7051, 7052 of the third layer 705; and on the other hand, the portions 70911, 70921 and the lower part of the seventh layer 713.

[0077] Therefore, at least part of the side surface of the second deposit 723 constituting the intrinsic base of the transistor 300 is lifted off.

[0078] Fig. 9 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Figure 8The disclosed structure is made. Fig. 9 The disclosed steps are more particularly dedicated to producing a portion of a future bipolar transistor 300 .

[0079] During this step, the notch 740 ( Figure 8 ) are links 7231 and 7232 (respectively located at Fig. 9 The left and right sides of the second deposit 723 in are completely filled.

[0080] These links 7231 and 7232 are made by depositing a doped material of the second conductivity type (p-type in this example). Preferably, the same material is used as that constituting the second deposit 723. This then amounts to extending the second deposit 723 constituting the intrinsic base of the transistor 300 until it is flush with the outer side surface of the seventh layer 713 covering the third deposit 725.

[0081] Fig.10 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Fig. 9 The disclosed structure is made. Fig.10 The disclosed steps are more particularly dedicated to producing a portion of a future varactor 100 .

[0082] During this step, the first regions 7011, 7031 and 7051 of the layers 701, 703 and 705 are locally etched over their entire thickness. The etching is performed so as to be flush with the portion of the upper surface 501 of the substrate 500, at which the extrinsic collector region 525 located in the diode position is flush. This is equivalent to forming a vertical opening 750 that passes through the first regions 7011, 7031 and 7051 of the layers 701, 703 and 705. As a result, the portion of the extrinsic collector region 525 inserted between the shallow isolation trench 530 and the shallow isolation trench 532 is stripped. Fig.10 In the embodiment, during etching, portions of the upper surfaces of these shallow isolation trenches 530 and 532 are also exposed.

[0083] Therefore, in Fig.10 , the opening 750 separates the first regions 7011, 7031 and first portions 7013, 7033 and 7053 of the layers 701, 703 and 705, respectively. Fig.10 and second portions 7014, 7034 and 7054 of first regions 7011, 7031 and 7051 of layers 701, 703 and 705 ( Fig.10 is located on the right side of opening 750).

[0084] According to a preferred embodiment, ion implantation of a doping element of the first conductivity type (n-type in this example) is further performed below the portion of the upper surface 501 flush with the non-intrinsic collector region 525. Thus, a segment 527 with increased doping relative to the initial doping (i.e., before the implantation) is formed in the same position of the substrate 500. This implantation operation, forming the segment 527, makes it possible to modify the dopant profile of the region 525 of the non-intrinsic collector near the upper surface 501 of the substrate 500.

[0085] It is assumed in the following that the substrate 500 now comprises the section 527 as previously described.

[0086] Fig.11 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Fig.10 The disclosed structure is made. Fig.11 The disclosed steps are more particularly dedicated to producing a portion of a future varactor 100 .

[0087] During this step, a deoxidation operation is performed to remove most of the second region 7052 of the third layer 705 and most of the first and second parts 7053, 7054 of the first region 7051 of the third layer 705. Only the following remain in the transistor position: the first element 70541 of the second part 7054, which is positioned flush with the first link 7231; and the second element 70521 of the second part 7052, which is positioned flush with the second link 7232.

[0088] Fig.12 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Fig.11 The disclosed structure is made. Fig.12 The disclosed steps are more particularly dedicated to producing a portion of a future varactor 100 .

[0089] During this step, a selective deposition of the eighth layer 715 is performed on the surface of the remaining part of the second layer 703 and on the surface of the second extrinsic collector region 525 .

[0090] More specifically, the eighth layer 715 is composed of four regions: a first region 7152, which covers the entire free upper surface of the second region 7032 of the second layer 703; a second region 7153, which covers the entire free upper surface of the first portion 7033 of the first region 7031 of the second layer 703; a third region 7154, which covers the entire free upper surface of the second portion 7034 of the first region 7031 of the second layer 703; and a fourth region 7155, which covers the upper surface of the segment 527, at Fig.12 In the example shown, the section 527 has been formed below the surface 501 of the substrate 500 .

[0091] The regions 7152 to 7155 of the eighth layer 715 are formed, for example, by epitaxial growth. Figure 2 ) of the same material. This then amounts to: increasing the thickness of the region 7032 and the remaining portions 7033, 7034 of the second layer 703 by a value denoted h, which is equal to the thickness of the regions 7152 to 7154; and forming a region 7154 flush with the segment 527.

[0092] The thickness h is checked so that regions 7154 and 7152 are in contact with links 7231 and 7232, respectively, located in the transistor position. Thus, regions 7154 and 7152 are placed in contact with the intrinsic base 723 of transistor 300 through links 7231 and 7232. Subsequently, regions 7154 and 7152 of the eighth layer 715 form the extrinsic base of transistor 300.

[0093] In this example, the region 7155 is of p-type. Therefore, in this example, the region 7155 still forms a pn junction with the n-type sector 527. In other words, the region 7155 forms a doped region 7155 of the diode 100 having a second conductivity type (here, p-type).

[0094] In the case where substrate 500 does not have section 527 in its extrinsic collector region 525 , region 7155 and region 525 together form the pn junction of diode 100 .

[0095] Fig.13 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Fig.12 The disclosed structure is made.

[0096] During this step, the diode 100 and the transistor 300 are protected by the sacrificial layer 790 for the subsequent steps. Thus, in the diode position, the region 7155 is covered by the first portion 7901 of the layer 790. Fig.13In the figure, the side portions of portion 7901 also partially cover the shallow isolation trenches 530 and 532.

[0097] In the transistor position, the structure with the second part 7903 of the layer 790 forming the future transistor 300 is also covered. Fig.13 In the embodiment, the portion 7903 of the layer 790 specifically covers the following: the top surface and the side surfaces of the seventh layer 713; and the free sides of the links 7231 and 7232.

[0098] The portion 7903 formed in the transistor location also extends over: a portion 71541 of the region 7154 located near the first link 7231; and a region 7152 located near the second link 7232 (in Fig.13 Part 71521 not visible in the figure.

[0099] For example, these protections are performed by a first operation in which a layer 790 made, for example, of a photolithographic photoresist is deposited, a second operation in which this photoresist layer 790 is exposed through a mask, and a third operation in which the portions of the photoresist layer 790 thus exposed are removed.

[0100] Subsequently, a mask is designed to leave only the unexposed portions of the photoresist layer 790 after removal of the exposed photoresist, in this example the first and second portions 7901 and 7903 of the layer 790 .

[0101] Fig.14 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Fig.13 The disclosed structure is made.

[0102] During this step, an etching operation is performed, for example by a dry etching method, such as plasma etching, to remove all areas of the unprotected areas of the layers 703 and 715 .

[0103] More specifically, the following items are removed: the entire first portion 7033 of the first region 7031 of the second layer 703; the entire second region 7153 of the eighth layer 715; the portion of the second portion 7034 of the first region 7031 of the second layer 703 that is not flush with the second portion 7903 of the protective layer 790; the portion of the third region 7154 of the layer 715 that is not covered by the second portion 7903 of the protective layer 790; the second region 7032 of the second layer 703 (in Fig.14 a portion of the first region 7152 of the layer 715 that is not covered by the second portion 7903 of the protective layer 790 (not visible in the figure), which is not positioned flush with the second portion 7903 of the protective layer 790; and a portion of the first region 7152 of the layer 715 that is not covered by the second portion 7903 of the protective layer 790.

[0104] Next, portions 7901 and 7903 from sacrificial protective layer 790 are removed (due to portions 7901 and 7903 being removed at the end of the step of removing the unprotected areas listed above). Fig.14 (not visible in the image).

[0105] like Fig.14 As shown in the figure, what is retained is: the entire fourth area 7155; a portion 71541 of the third area 7154 of the layer 715; a portion 71521 of the first area 7152 of the layer 715; an element 70341 of the second portion 7034 of the first area 7031 of the second layer 703, the element 70341 being positioned flush with the portion 71541 and located below the partial element 70541; and an element 70321 of the second area 7032 of the second layer 703, the element 70321 being positioned flush with the portion 71521 and located below the partial element 70521.

[0106] Fig.15 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section is schematically shown. Fig.14 The disclosed structure is made.

[0107] During this step, uncovered portions of the first layer 701 and the entire seventh layer 713 are removed. To this end, the second region 7012 of the first layer 701 and the first portion 7013 and the second portion 7014 of the first region 7011 of the first layer 701 are subjected to an etching operation, for example a wet etching.

[0108] More specifically, the etching operation results in the removal of the following: the entire seventh layer 713; the entire first portion 7013 of the first region 7011 of the first layer 701; removal of the portion of the second portion 7014 of the first region 7011 of the first layer 701 that is not covered by the element 70341; and removal of the portion of the second region 7012 of the first layer 701 that is not covered by the element 70321.

[0109] Thus, the following items are retained: element 70141 of the second portion 7014 of the first area 7011 of the first layer 701, which is positioned flush with element 70341 and element 70541; element 70121 of the second area 7012 of the first layer 701, which is positioned flush with element 70321 and element 70521.

[0110] Fig.16 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Fig.15 The disclosed structure is made.

[0111] During this step, in combination with Fig.15 The structure described has MOS spacers formed at right angles. Specifically, the following items are produced: two first MOS spacers 830 and 831; two second MOS spacers 832 and 833 ( Fig.16 Only the second MOS spacer 832 is shown; and two third MOS spacers 834 and 835.

[0112] First MOS spacers 830 and 831 are located on either side of region 7155 and partially cover shallow isolation trenches 530 and 532, respectively.

[0113] Fig.16 The second MOS spacer 832 shown in FIG. 8 covers the following: the free side of the element 70341 ; the free side of the element 70141 ; the free surface of the shallow isolation trench 534 ; and a portion of the free surface of the sink 540 .

[0114] The second MOS spacer 833 is formed symmetrically with respect to the intrinsic collector 721 of the transistor 300 ( Fig.16 not shown).

[0115] The third MOS spacers 834 and 835 cover the following: a portion of the side surfaces of portions 70911 and 70921, respectively; a portion of one or more free surfaces in links 7231 and 7232, respectively; and a portion of the upper surfaces of elements 70541 and 71521, respectively.

[0116] Fig.17 A further step of an embodiment of a method for producing a varactor and a bipolar transistor by combining as shown in cross section Fig.16 The disclosed structure is made.

[0117] During this step, first contact-reactive elements 741 , 742 and 743 of the varactor 100 and second contact-reactive elements 745 , 746 , 747 and 748 of the transistor 300 are produced.

[0118] More specifically, for the varactor 100 : the contact reaction element 741 is formed on the entire upper surface of the sink 545 ; the contact reaction element 742 is formed on the entire upper surface of the sink 547 ; and the contact reaction element 743 is formed on the entire upper surface of the region 7155 .

[0119] Contact reactive elements 741 and 742 are thus connected to power grid 527, whereas contact reactive element 743 is connected to region 7155. Power grid 527 is doped to a first type, in this example n-type. Region 7155 is doped to a second type, in this example p-type.

[0120] In this example, elements 741 and 742 constitute the cathode contact or terminal of varactor 100. Also in this example, element 743 constitutes the anode contact or terminal of varactor 100.

[0121] More specifically, for transistor 300: a contact reaction element 745 is formed on the entire upper surface of the host 540; a contact reaction element 746 is formed on the upper surface of portion 71541 that is not covered by the MOS spacer 734; a contact reaction element 747 is formed on the upper surface of portion 71521 that is not covered by the MOS spacer 735; and a contact reaction element 748 is formed on the entire upper surface of the third deposit 725.

[0122] Therefore, the contact reaction element 745 is connected to the first deposition 721 (intrinsic collector). The contact reaction elements 746 and 747 are connected to the second deposition 723 (intrinsic base). The contact reaction element 748 is connected to the third deposition 725 (intrinsic emitter).

[0123] The first deposit 721 is doped to a first type, in this example, n-type. The second deposit 723 is doped to a second type, in this example, p-type. The third deposit 725 is doped to a first type, in this example, n-type.

[0124] Contact responsive element 745 constitutes a collector contact or terminal of transistor 300. Contact responsive elements 746 and 747 constitute a base contact or terminal of transistor 300. Contact responsive element 748 constitutes an emitter contact or terminal of transistor 300.

[0125] Combination Figures 1 to 17 The embodiment of the method whose sequential steps have been described has the advantage of enabling the simultaneous production of the variable capacitance diode 100 and the bipolar transistor 300. This therefore reduces the number of manufacturing steps for the diode 100 and the transistor 300 relative to a method in which the diode 100 and the transistor 300 are produced separately.

[0126] Another advantage of the above described embodiment is the fact that the region 7155 is preferably formed by epitaxial growth. Thus, in this example, this allows the region 7155 and the power grid 527 to form a pn junction with a very sharp interface, in other words, near which the dopant profile varies greatly. Thus, a varactor 100 with a "hyperabrupt" pn junction is obtained, in other words, a variable capacitance diode is obtained with an abrupt dopant profile provided near the interface of its pn junction.

[0127] Fig.18 The variation curves of characteristic properties of a varactor diode obtained using an embodiment of the described method are shown.

[0128] Fig.18 reflects the capacitance (C) of the variable capacitance diode 100 according to the anode ( Fig.17 Terminal 743) and cathode ( Fig.17 The change in the voltage (V) with reverse polarization applied between terminals 741 and 742 in the circuit.

[0129] More specifically: a first curve 91 in solid line illustrates the capacitance variation of a diode 100 having no region 525 within its extrinsic collector region 525 ; and a second curve 92 in dashed line illustrates the capacitance variation of a diode 100 having region 525 within its extrinsic collector region 525 .

[0130] For zero polarization voltage V, the diode without region 525 has a capacitance indicated as C0_1 which is lower than the capacitance indicated as C0_2 of the diode with region 525. In general, the presence of region 525 makes it possible to increase the capacitance of variable capacitance diode 100.

[0131] Various embodiments and implementations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined, and those skilled in the art will readily recognize other variations.

[0132] Finally, actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art, based on the functional description provided above.

Claims

1. An integrated circuit, comprising: substrate; A first collector region in the substrate is doped with a first conductivity type; A second collector region in the substrate is also doped with the first conductivity type; wherein the first collector region is isolated from the second collector region by deep trench isolation in the substrate; wherein a portion of the first collector region at the upper surface of the substrate is defined by shallow trench isolation; a doped region having the first conductivity type in the portion of the first collector region; an intrinsic collector epitaxial region having the first conductivity type, above the second collector region; an intrinsic base epitaxial region having a second conductivity type, above the intrinsic collector epitaxial region; an emitter region having the first conductivity type, above the intrinsic base epitaxial region; an extrinsic base region of the second conductivity type contacting the intrinsic base region and extending laterally from the intrinsic base region; an epitaxial layer having a second conductivity type, comprising a first layer portion on the doped region and a second layer portion in contact with the extrinsic base region; a doped layer having the second conductivity type, over the substrate and laterally isolated from the intrinsic collector epitaxial region, and wherein the second layer portion is in contact with the doped layer; wherein the doped region and the first layer portion form a hyperabrupt PN junction for a variable capacitance diode; and The intrinsic collector epitaxial region, the intrinsic base epitaxial region and the emitter region form a bipolar transistor. 2 . The integrated circuit of claim 1 , wherein the epitaxial layer is epitaxially grown from the doped region and the doped layer to form the first layer portion and the second layer portion, respectively.

3. The integrated circuit of claim 1, wherein the doped layer is formed of doped polysilicon. 4 . The integrated circuit of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type. 5 . The integrated circuit of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.

6. An integrated circuit comprising: substrate; A first collector region in the substrate is doped with a first conductivity type; A second collector region in the substrate is also doped with the first conductivity type; wherein the first collector region is isolated from the second collector region by deep trench isolation in the substrate; wherein a portion of the first collector region on the upper surface of the substrate is defined by shallow trench isolation; a doped region having the first conductivity type in the portion of the first collector region; an intrinsic collector epitaxial region having the first conductivity type, above the second collector region; an intrinsic base epitaxial region having a second conductivity type, above the intrinsic collector epitaxial region; an emitter region having the first conductivity type, above the intrinsic base epitaxial region; an extrinsic base region of the second conductivity type contacting the intrinsic base region and extending laterally from the intrinsic base region; an epitaxial layer having the second conductivity type, comprising a first layer portion on the doped region and a second layer portion in contact with the extrinsic base region; an insulating layer on the upper surface of the substrate, wherein the insulating layer includes a first opening over a portion of the first collector region in which the first layer portion is formed and a second opening over the second collector region in which the intrinsic collector epitaxial region is formed; wherein the doped region and the first layer portion form a hyperabrupt PN junction for a varactor diode; and The intrinsic collector epitaxial region, the intrinsic base epitaxial region and the emitter region form a bipolar transistor.

7. The integrated circuit of claim 6, further comprising a doped layer of the second conductivity type on top of the insulating layer, and wherein the second layer portion is in contact with the doped layer.

8. The integrated circuit of claim 7, wherein the epitaxial layer is epitaxially grown from the doped region and the doped layer to form the first layer portion and the second layer portion, respectively.

9. The integrated circuit of claim 7, wherein the doped layer is formed of doped polysilicon.

10. An integrated circuit comprising: substrate; A first collector region in the substrate is doped with a first conductivity type; A second collector region in the substrate is also doped with the first conductivity type; wherein the first collector region is isolated from the second collector region by deep trench isolation in the substrate; wherein a portion of the first collector region on the upper surface of the substrate is defined by shallow trench isolation; an intrinsic collector epitaxial region having a first conductivity type, above the second collector region; an intrinsic base epitaxial region having a second conductivity type, above the intrinsic collector epitaxial region; an emitter region having the first conductivity type, above the intrinsic base epitaxial region; an extrinsic base region of the second conductivity type contacting the intrinsic base region and extending laterally from the intrinsic base region; an epitaxial layer having the second conductivity type, comprising a first layer portion on the portion of the first collector region and a second layer portion in contact with the extrinsic base region; a doped layer having a second conductivity type on the substrate and laterally isolated from the intrinsic collector epitaxial region, and wherein the second layer portion is in contact with the doped layer; wherein the portion of the first collector region and the first layer portion form a hyperabrupt PN junction for a variable capacitance diode; and The intrinsic collector epitaxial region, the intrinsic base epitaxial region and the emitter region form a bipolar transistor.

11. The integrated circuit of claim 10, wherein the epitaxial layer is epitaxially grown from the portion of the first collector region and the doped layer to form the first layer portion and the second layer portion, respectively.

12. The integrated circuit of claim 10, wherein the doped layer is formed of doped polysilicon.

13. The integrated circuit of claim 10, wherein the first conductivity type is p-type and the second conductivity type is n-type.

14. The integrated circuit of claim 10, wherein the first conductivity type is n-type and the second conductivity type is p-type.

15. An integrated circuit comprising: substrate; A first collector region in the substrate is doped with a first conductivity type; A second collector region in the substrate is also doped with the first conductivity type; wherein the first collector region is isolated from the second collector region by deep trench isolation in the substrate; wherein a portion of the first collector region on the upper surface of the substrate is defined by shallow trench isolation; an intrinsic collector epitaxial region having a first conductivity type, above the second collector region; an intrinsic base epitaxial region having a second conductivity type, above the intrinsic collector epitaxial region; an emitter region having the first conductivity type, above the intrinsic base epitaxial region; an extrinsic base region of the second conductivity type contacting the intrinsic base region and extending laterally from the intrinsic base region; an epitaxial layer having a second conductivity type, comprising a first layer portion on the portion of the first collector region and a second layer portion in contact with the extrinsic base region; an insulating layer on the upper surface of the substrate, wherein the insulating layer includes a first opening over a portion of the first collector region in which the first layer portion is formed and a second opening over the second collector region in which the intrinsic collector epitaxial region is formed; wherein the portion of the first collector region and the first layer portion form a hyperabrupt PN junction of a variable capacitance diode; and The intrinsic collector epitaxial region, the intrinsic base epitaxial region and the emitter region form a bipolar transistor.

16. The integrated circuit of claim 15, further comprising a doped layer of the second conductivity type on top of the insulating layer, and wherein the second layer portion is in contact with the doped layer.

17. The integrated circuit of claim 16, wherein the epitaxial layer is epitaxially grown from the doped region and the doped layer to form a first layer portion and a second layer portion, respectively.

18. The integrated circuit of claim 16, wherein the doped layer is formed of doped polysilicon.

19. A method of jointly producing a bipolar transistor and a variable capacitance diode on a substrate, comprising: a) depositing a first layer, a second layer, a third layer, a fourth layer, a fifth layer and a sixth layer over the upper surface of the substrate; b) forming a first opening through the first layer to the sixth layer, aligned with a first region of the first conductivity type in the substrate forming a first extrinsic collector of the bipolar transistor; c) providing an intrinsic collector and an intrinsic base of the bipolar transistor in the first opening, wherein the intrinsic base completely covers the intrinsic collector; d) forming two first spacers in the first opening over the upper surface of the intrinsic base; e) removing the sixth layer and the two first spacers except for horizontal portions of the two first spacers partially covering the upper surface of the intrinsic base; f) forming a first deposit on top of the intrinsic base, the horizontal portions of the two first spacers and a portion of the fifth layer, and removing the fifth layer except for the portion of the fifth layer; g) depositing a seventh layer covering the upper surface and sides of the first deposit and sides of the portion of the fifth layer, and removing the fourth layer; h) forming a first link and a second link contacting the intrinsic base; i) forming a second opening through the first layer, the second layer and the third layer to reach a second extrinsic collector electrode of the first conductivity type in the substrate; j) removing the third layer except for a first element and a second element which are in line with the first link and the second link respectively; k) selectively depositing an eighth layer on the remaining portion of the surface of the second layer and on the surface of the second extrinsic collector, wherein the selective deposition of the surface of the eighth layer in the second extrinsic collector region forms a first region of a second conductivity type of a PN junction of the variable capacitance diode; L) protecting the variable capacitance diode and the bipolar transistor with the first and second portions of the sacrificial layer, and removing all unprotected areas of the second layer and the eighth layer; as well as m) removing the first portion and the second portion of the sacrificial layer, removing portions not covered by the first layer and removing the seventh layer.

20. The method according to claim 19, further comprising, after step m), forming: a first spacer on each side of the first region of the PN junction of the variable capacitance diode; and A second spacer on each side of the intrinsic collector of the bipolar transistor.

21. The method of claim 19, wherein the first region of the PN junction of the variable capacitance diode and the extrinsic base of the bipolar transistor are manufactured using the same step k).

22. The method of claim 19, wherein the first region of the PN junction of the variable capacitance diode is produced by epitaxy.

23. The method of claim 19, wherein sectors of the second region are doped by ion implantation.

24. The method of claim 19, wherein the first conductivity type is P and the second conductivity type is N.

25. The method of claim 19, wherein the first conductivity type is N and the second conductivity type is P.

26. The method of claim 19, wherein the variable capacitance diode is a hyperabrupt PN junction varactor.

27. The method of claim 19, further comprising, after step m), forming spacers on either side of the intrinsic collector and forming spacers on either side of the intrinsic base.

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